Process corner extraction method and device, electronic equipment and storage medium

Abstract

The invention provides a process corner extraction method and device, electronic equipment and a storage medium, and relates to the technical field of semiconductors. The process corner extraction method of the metal interconnection line comprises the steps that in response to an input initial RC process corner file of a chip circuit, a process corner extraction model is configured, a target RC process corner is output through the process corner extraction model, and the process allowance of the target RC process corner is smaller than the process allowance in the initial RC process corner file; wherein simulation operation of circuit performance is executed on the chip circuit based on the initial RC process corner file, so that the process corner extraction model is configured based on a result of the simulation operation. Through the technical scheme of the invention, the target RC process corner parameter with smaller allowance and higher precision can be obtained, so that the influence of parasitic resistance and capacitance on the performance of a device can be reduced when the back-end process of a chip is guided based on the target RC process corner parameter.

Description

Background Art

[0002] The integrated circuit process flow of the wafer includes the front-end manufacturing process and the back-end manufacturing process. The front-end manufacturing process includes the manufacturing process of devices such as transistors, and the back-end manufacturing process includes the interconnection process of wiring the designed logic circuit in a device layer and multiple metal layers. With the development of semiconductor technology, the wafer size is getting smaller and smaller, which results in that in the back-end interconnection process, the parasitic resistance and capacitance have an increasingly greater impact on the performance of the devices in the wafer.

[0003] The process corner file output by the currently used process corner model needs to cover the metal layer of the wafer, so a large margin is given to the process parameters in the process corner file, resulting in a waste of design space for the process parameters. Therefore, the actual circuit performance will deviate from the expected circuit performance.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a method for extracting a process angle of a metal interconnection line, a device for extracting a process angle of a metal interconnection line, and a computer-readable storage medium, which at least to a certain extent overcome the problem that the process parameters output by the process angle model in the related art waste design space.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for extracting a process corner of a metal interconnect line is provided, comprising: in response to an initial RC process corner file of an input chip circuit, configuring a process corner extraction model so that the process corner extraction model outputs a target RC process corner, and a process margin of the target RC process corner is smaller than a process margin in the initial RC process corner file; wherein a circuit performance simulation operation is performed on the chip circuit based on the initial RC process corner file so as to configure the process corner extraction model based on a result of the simulation operation.

[0008] In one embodiment of the present disclosure, the circuit performance simulation operation performed on the chip circuit based on the initial RC process corner file includes: obtaining an interconnect structure matching a preset process layout in the initial RC process corner file, adding interconnect line parasitic parameters to the process layout based on the interconnect structure, and generating an electrical layout; extracting an RC sensitivity netlist from the electrical layout, the RC sensitivity netlist including sensitivity information of the interconnect line parasitic parameters under a typical RC process corner; and performing a circuit performance simulation operation on the chip circuit based on the RC sensitivity netlist.

[0009] In one embodiment of the present disclosure, the circuit performance simulation operation is performed on the chip circuit based on the RC sensitivity netlist, including: determining the parameter range of the interconnect parasitic parameters based on the sensitivity information in the RC sensitivity netlist; randomly generating multiple groups of process parameter values ​​within the parameter range; performing multiple Monte Carlo simulation operations on the circuit performance based on the multiple groups of process parameter values ​​to obtain performance data of the circuit performance; wherein the multiple groups of process parameter values ​​and the corresponding performance data are results of the simulation operation.

[0010] In one embodiment of the present disclosure, the target RC process corner is outputted by the process corner extraction model, including: estimating a target value of the circuit performance based on the performance data, the target value corresponding to the process margin of the target RC process corner; outputting a plurality of alternative RC process corners that meet the target value by the process corner extraction model; and selecting the target RC process corner from the plurality of alternative RC process corners.

[0011] In one embodiment of the present disclosure, selecting the target RC process corner from the multiple candidate RC process corners includes: calculating the joint probability density of each of the candidate RC process corners respectively; and determining the candidate RC process corner with the largest joint probability density as the target RC process corner.

[0012] In one embodiment of the present disclosure, the configuration of the process corner extraction model includes: obtaining a response surface model, the response surface model is used to represent the response of the circuit performance to the change of the process parameters, the response surface model is of M order, and M is greater than or equal to 2; based on the relationship between the multiple groups of process parameter values ​​and the corresponding performance data, the model coefficients of the response surface model are determined as the process corner extraction model, and the number of the model coefficients is determined based on the number of the process parameters and M.

[0013] In one embodiment of the present disclosure, the method further includes: performing a circuit performance verification operation based on the target RC process corner.

[0014] In one embodiment of the present disclosure, the circuit performance verification operation based on the target RC process corner includes: formatting the target RC process corner to generate a target RC process corner file; performing a circuit performance verification operation based on the target RC process corner file to obtain a verification value of the circuit performance; detecting whether the deviation rate of the verification value relative to the target value is less than a ratio threshold; if the deviation rate is less than the ratio threshold, determining that the target RC process corner verification has passed.

[0015] In one embodiment of the present disclosure, it also includes: if the deviation rate is greater than or equal to the ratio threshold, reconstructing the process corner extraction model, and optimizing the target RC process corner based on the reconstructed process corner extraction model until the optimized target RC process corner passes performance verification.

[0016] In one embodiment of the present disclosure, the reconstructing the process angle extraction model includes: reconstructing the response surface model to N order, N is greater than M; redetermining the model coefficients based on the relationship between the multiple groups of process parameter values ​​and the corresponding performance data to reconstruct the process angle extraction model, and the number of the model coefficients is determined based on the number of the process parameters and N.

[0017] In one embodiment of the present disclosure, estimating the target value of the circuit performance based on the performance data includes: estimating the expected value and standard deviation of the performance data distribution; and determining the target value of the circuit performance based on the expected value, the standard deviation and the number of process parameters.

[0018] According to one aspect of the present disclosure, a process corner extraction device for metal interconnect lines is provided, comprising: an extraction module, configured to respond to an initial RC process corner file of an input chip circuit, and configure a process corner extraction model so that a target RC process corner is output by the process corner extraction model, wherein a process margin of the target RC process corner is smaller than a process margin in the initial RC process corner file; wherein a circuit performance simulation operation is performed on the chip circuit based on the initial RC process corner file, so as to configure the process corner extraction model based on a result of the simulation operation.

[0019] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; the processor is configured to execute the process angle extraction method of the metal interconnection line of the first aspect by executing the executable instructions.

[0020] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the method for extracting process corners of metal interconnects is implemented.

[0021] The process corner extraction scheme for metal interconnection lines provided in the embodiments of the present disclosure configures a process corner extraction model that can simulate the circuit performance of a chip. When an initial RC process corner file is provided by a foundry, the initial RC process corner file is directly input into the process corner extraction model. Based on the process corner extraction model, relevant parameters in the initial RC process corner file are extracted, and circuit performance simulation is performed. Thus, the parameters in the initial RC process corner file can be optimized based on the simulation results to obtain target RC process corner parameters with smaller margin and higher accuracy. The back-end process of the chip is guided based on the target RC process corner parameters, so that the simulation results are closer to the actual operation results of the chip, which is beneficial to reduce the influence of parasitic resistance and capacitance on device performance.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0024] Figure 1 A partial schematic diagram showing a chip back-end metal interconnection structure in an embodiment of the present disclosure;

[0025] Figure 2 A schematic block diagram showing a method for extracting a process angle of a metal interconnect line in an embodiment of the present disclosure;

[0026] Figure 3 A schematic diagram showing the flow of another device for extracting process angles of metal interconnects according to an embodiment of the present disclosure;

[0027] Figure 4 A schematic diagram showing the flow of another device for extracting process angles of metal interconnects according to an embodiment of the present disclosure is shown;

[0028] Figure 5 A schematic diagram showing a process flow of another device for extracting a process angle of a metal interconnect line according to an embodiment of the present disclosure is shown;

[0029] Figure 6 A schematic diagram showing a process flow of another device for extracting a process angle of a metal interconnect line according to an embodiment of the present disclosure is shown;

[0030] Figure 7 A schematic diagram showing a process flow of another device for extracting a process angle of a metal interconnect line according to an embodiment of the present disclosure is shown;

[0031] Figure 8 A schematic diagram showing a process flow of another device for extracting a process angle of a metal interconnect line according to an embodiment of the present disclosure is shown;

[0032] Fig. 9 A structural block diagram of an electronic device in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0033] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0034] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0035] For semiconductor chips, since different processes, voltages and temperatures will affect the performance of the chip, it is necessary to optimize the parameters in the chip's integrated circuit process flow so that the prepared chip can meet the use requirements in different environments as much as possible. Among them, environmental factors include parasitic parameter RC value, which can reflect the corresponding delay size of the circuit. In the back-end interconnection process of the chip, Figure 1 The figure shows the back-end metal interconnect structure of the chip, including the Mn-1th layer, the Mnth layer and the Mn+1th layer. The various process parameters of the interconnect lines include the width W of the metal line, the thickness T of the metal line, the thickness H of the dielectric layer between the metal layers (i.e., H1+H2+T), and the distance S between adjacent metal lines, etc., where S is determined by W.

[0036] When preparing semiconductor chips, it is usually required that the semiconductor chips prepared using different process parameters can meet the needs of different usage environments. However, the current process angle extraction scheme usually has a large configured process margin, resulting in the extraction result being unable to meet the above requirements. Figure 2 A flow chart of a method for extracting process corners of metal interconnects in an embodiment of the present disclosure is shown.

[0037] like Figure 2As shown, a method for extracting a process angle of a metal interconnection line according to an embodiment of the present disclosure includes:

[0038] Step S202, in response to the input initial RC process corner file of the chip circuit, configure a process corner extraction model so that the process corner extraction model outputs a target RC process corner, and the process margin of the target RC process corner is smaller than the process margin in the initial RC process corner file, wherein a simulation operation of the circuit performance is performed on the chip circuit based on the initial RC process corner file to configure the process corner extraction model based on the result of the simulation operation.

[0039] Among them, the RC process corner is used to model the deviation of the chip's interconnection lines. Exemplarily, the initial RC process corner file is the RC process corner file provided by the wafer foundry. Those skilled in the art can understand that the process parameters in the initial RC process corner file have a large redundancy. Therefore, if production is directly based on these process parameters, it will result in a larger parasitic resistance and capacitance, thereby increasing the impact of the parasitic resistance and capacitance on the circuit performance of the chip.

[0040] In addition, simulating the circuit performance of the chip based on the process parameters in the initial RC process corner file can be understood as a machine learning process. A process corner extraction model is generated through machine learning, and the process parameters in the initial RC process corner file are optimized based on the process corner extraction model to obtain a target RC process corner with a process margin smaller than the initial RC process corner.

[0041] Circuit performance includes but is not limited to dynamic power consumption, static power consumption, gate delay, saturation current and leakage current.

[0042] In addition, in response to the input initial RC process angle file of the chip circuit, a process angle extraction application can be loaded by loading the metal interconnect line, and the initial process angle file can be imported into the application interface to display the corresponding target RC process angle based on the calculation of the process angle extraction model, so as to guide the back-end process of the chip based on the target RC process angle.

[0043] In this embodiment, by configuring a process corner extraction model that can simulate the circuit performance of the chip, when the initial RC process corner file is provided by the foundry, the initial RC process corner file is directly input into the process corner extraction model, and the relevant process parameters and parasitic RC parameters in the initial RC process corner file are extracted based on the process corner extraction model, and the circuit performance simulation is performed, so that the parameters in the initial RC process corner file can be optimized based on the simulation results, and the target RC process corner parameters with smaller margin and higher accuracy can be obtained. The back-end process of the chip is guided based on the target RC process corner parameters, so that the simulation results are closer to the actual operation results of the chip, which is beneficial to reduce the influence of parasitic resistance and capacitance on device performance.

[0044] like Figure 3 As shown, in one embodiment of the present disclosure, in step S202, an implementation method of performing a circuit performance simulation operation on a chip circuit based on an initial RC process corner file includes:

[0045] Step S302 , obtaining an interconnection structure matching a preset process layout in the initial RC process corner file, adding interconnection line parasitic parameters to the process layout based on the interconnection structure, and generating an electrical layout.

[0046] Exemplarily, the initial RC process corner file generally includes a suffix identifier such as nxtgrd. By identifying the suffix, the input initial RC process corner is obtained, and the process layout generation function is integrated into the process corner extraction application of the metal interconnect line. For example, multiple process layouts are preset. After the initial RC process corner file is obtained and the process layout is generated, the process layout that matches the initial RC process corner file is determined, and the interconnect line parasitic parameters are added to the matching process layout based on the parameters in the initial RC process corner file to obtain the electrical layout.

[0047] The interconnect parasitic parameters include electrical parameters of the interconnect and related linear parameters of the dielectric layer ILD between metal layers.

[0048] Step S304: extracting an RC sensitivity netlist from the electrical layout, wherein the RC sensitivity netlist includes sensitivity information of parasitic parameters of interconnect lines under a typical RC process corner.

[0049] Among them, RC netlist refers to the description of the RC connection relationship between circuit elements during the circuit design process, and RC sensitivity refers to the sensitivity of parasitic resistance and capacitance elements to process changes. By incorporating RC sensitivity into the RC sensitivity netlist, it is beneficial to perform circuit performance simulation operations on chip circuits.

[0050] Exemplarily, the process corner extraction application of metal interconnect lines also integrates an RC extraction module and a sensitivity extraction module. The RC extraction module extracts RC data from the electrical layout to generate an RC netlist. Furthermore, the sensitivity extraction module extracts the RC sensitivity under typical process corners from the RC netlist, specifically including separately calculating the sensitivity of the conductive layer and / or the conductive layer group in the interconnect structure of the chip, so as to add these sensitivities to the RC netlist and generate an RC sensitivity netlist.

[0051] In addition, the RC sensitivity netlist can be in the file format of xxx.spf for use as input to a circuit simulation tool.

[0052] Step S306 , performing circuit performance simulation operation on the chip circuit based on the RC sensitivity netlist.

[0053] Among them, the process corner extraction application of metal interconnect lines is also integrated with a simulation module. Based on the simulation module, the circuit performance simulation operation is performed using the parameters in the randomly generated RC sensitivity netlist, including but not limited to the process corner and the corresponding process parameters, to generate simulation parameters, and the circuit performance simulation operation is performed based on the simulation parameters to obtain the simulation results, that is, the circuit performance data obtained by simulation, so as to further extract the target RC process corner.

[0054] In this embodiment, the interconnect structure describes several graphics of the chip, the electrical layout includes the process parameters and electrical parameters of the back-end interconnect layer, and the RC sensitivity netlist further includes the sensitivity information of the parasitic parameters of the interconnect structure. The sensitivity netlist can be used to simulate the impact of changes in semiconductor processes on circuit performance. By generating the electrical layout and extracting the RC sensitivity netlist from the electrical layout, circuit performance simulation operations can be performed based on the parameters in the RC sensitivity netlist, which helps to ensure the reliability of the simulation operation.

[0055] like Figure 4 As shown, in one embodiment of the present disclosure, in step S306, a specific implementation method of performing a circuit performance simulation operation on a chip circuit based on an RC sensitivity netlist includes:

[0056] Step S402 : determining a parameter range of interconnect parasitic parameters based on sensitivity information in the RC sensitivity netlist.

[0057] The parameter range of the interconnect parasitic parameters refers to the range of parameters such as W, T, and H recorded in the RC sensitivity netlist.

[0058] Step S404, randomly generating multiple sets of process parameter values ​​within the parameter range.

[0059] The process parameter value is specifically a combination of multiple W, T and H.

[0060] Step S406, performing multiple Monte Carlo simulation operations on the circuit performance based on the multiple sets of process parameter values ​​to obtain performance data of the circuit performance, wherein the multiple sets of process parameter values ​​and the corresponding performance data are results of the simulation operations.

[0061] Among them, the Monte Carlo method, also known as the computer random simulation method, is mainly used to analyze the circuit performance deviation caused by device dispersion and the probability of a certain range of deviations. It uses a probability model to study a large number of randomly generated numbers to find the target solution for the process parameters.

[0062] Exemplarily, the process of Monte Carlo simulation includes:

[0063] Firstly, a probability model that can correctly describe the simulation process is constructed; secondly, since various probability models can be regarded as composed of various probability distributions, multiple groups of process parameter values ​​are randomly generated within the parameter range of interconnect parasitic parameters based on the probability model, wherein the multiple groups of process parameter values ​​can specifically be multiple groups of process parameter values ​​with a certain uniform distribution; finally, an estimate of circuit performance is generated based on the probability model to obtain the target RC process angle.

[0064] In this embodiment, a Monte Carlo simulation operation is used to obtain performance data of circuit performance corresponding to multiple sets of process parameter values, so that a target performance value can be extracted from the performance data to further determine a target RC process corner determined by the target performance value. By simulating actual circuit performance such as gate delay and crosstalk based on Monte Carlo simulation, the simulation results are made to be more in line with the performance of the actual circuit design, thereby achieving optimization operation on the RC process corner.

[0065] like Figure 5 As shown, in one embodiment of the present disclosure, in step S202, a specific implementation method of outputting a target RC process angle by the process angle extraction model includes:

[0066] Step S502 , estimating a target value of circuit performance based on the performance data, where the target value corresponds to a process margin of a target RC process corner.

[0067] In one embodiment of the present disclosure, estimating a target value of circuit performance based on performance data includes:

[0068] Estimate the expected value and standard deviation of the performance data distribution, and determine the target value of circuit performance based on the expected value, standard deviation, and number of process parameters.

[0069] Among them, the circuit performance includes at least one of dynamic power consumption, static power consumption, gate delay, saturation current, and leakage current. Taking gate delay as an example, the expected value and standard deviation of the estimated performance data distribution are specifically the expected value and standard deviation of the estimated gate delay data distribution.

[0070] Because the performance distribution obtained based on the Monte Carlo model can satisfy a certain distribution, such as Gaussian distribution, Beta distribution, Cauchy distribution and Chi-square distribution.

[0071] Exemplarily, taking the Gaussian distribution as an example, the expected value and standard deviation of the performance data distribution are estimated based on the Gaussian distribution of the performance data. The target value at the new corner of the circuit performance can be estimated to be μ+n*σ, where μ is the expected value, σ is the standard deviation, and n is the multiple of σ when the circuit performance is close to 0.

[0072] Step S504: the process corner extraction model outputs a plurality of candidate RC process corners that meet the target value.

[0073] Among them, the combination of (W, T, H) is calculated for the target value Y=μ+n*σ. Since there are many groups of (W, T, H) combinations that satisfy this n-σ formula, multiple alternative RC process angles can be output.

[0074] Step S506 , selecting a target RC process corner from a plurality of candidate RC process corners.

[0075] In this embodiment, based on multiple Monte Carlo simulation operations, multiple groups of performance data of the circuit performance are obtained, so as to further estimate the target value of the circuit performance based on the multiple groups of performance data. The target value is used as an input parameter, and the process corner extraction model outputs multiple alternative RC process corners that meet the target value, so as to screen out the target RC process corner from the alternative RC process corners. Based on multiple Monte Carlo simulation operations, a specific circuit design is made to correspond to a specific target value, which prevents the margin of the process corner parameter from being too large and ensures the reliability of the screening of the target RC process corner.

[0076] In one embodiment of the present disclosure, a specific implementation method of selecting a target RC process corner from a plurality of candidate RC process corners includes:

[0077] The joint probability density of each candidate RC process corner is calculated respectively; and the candidate RC process corner with the largest joint probability density is determined as the target RC process corner.

[0078] Among them, probability density refers to the probability of an event occurring randomly, and the joint probability includes multiple conditions and the probability that multiple conditions are met at the same time.

[0079] For a random variable (W, T, H), there exists a distribution function F(W, T, H) if there exists any non-negative function f(w, t, h) such that for (W, T, H), there exists Then f(w,t,h) is the joint probability density function of the random variables (W,T,H).

[0080] In this embodiment, by configuring the joint probability density function, a combination of random variables (W, T, H) that satisfies the maximum joint probability density is selected, that is, the process parameter combination with the highest probability of occurrence, which can also be understood as the parameters closest to the actual circuit design, is used as the target RC process angle to obtain an interconnect line process angle model that is close to the actual process results.

[0081] In one embodiment of the present disclosure, a specific implementation of configuring a process corner extraction model includes:

[0082] A response surface model is obtained. The response surface model is used to represent the response of circuit performance to changes in process parameters. The response surface model is of M order, where M is greater than or equal to 2.

[0083] Among them, the response surface method (RSM) model refers to replacing the real surface with a regression fitting analysis to approximately express the functional function as an explicit random variable to process the conversion relationship between the input target value of the circuit performance and the output process parameters (W, T, H), thereby predicting the impact of different conditions on the response value.

[0084] The model coefficients of the response surface model are determined based on the relationship between the multiple sets of process parameter values ​​and the corresponding performance data to determine the response surface model with the determined model coefficients as the process corner extraction model, and the number of the model coefficients is determined based on the number of process parameters and M.

[0085] Among them, when determining the response surface model based on the performance data of the circuit performance and multiple groups of parameter values ​​(W, T, H), the parameter values ​​are used as input values ​​and the performance data are used as output values. The determination of the response surface model depends on the approximate function. The approximate function can be linear, second-order polynomial or multi-order polynomial (i.e., the value of M). For the second-order polynomial, it can also be divided into a form without cross terms and a form with cross terms. As a specific construction method of the response surface model, in the present disclosure, the response surface model is constructed based on the form without cross terms, as shown in the following formula:

[0086] Y=a0+a1W+a2W 2 +a3T+a4T 2 +a5H1+a6H1 2 +a7H2+a8H2 2

[0087] Further, model coefficients a0 to a8 of the response surface model are determined based on the relationship between the multiple sets of process parameter values ​​and the corresponding performance data to obtain a process angle extraction model.

[0088] As another way to construct the response surface model, a BP (Back Propagation) neural network can also be used as a response surface approximation function, which is beneficial to improving the accuracy of the response surface model. Specifically, based on the above-mentioned Monte Carlo simulation, multiple sets of process parameter values ​​and corresponding circuit performance data are generated as sample data. Before establishing the neural network model, the topological structure of the neural network is determined, and then the numerical value of the neural network is optimized and sampled based on the sample data. The neural network response surface is established to fit the real limit state, and finally the target value of the circuit performance is calculated using reliability.

[0089] As another way to construct the response surface model, the response surface model can also be determined based on a global fuzzy neural network.

[0090] In this embodiment, by adopting the response method to construct a process corner extraction model, the response surface model can more accurately fit the fitting relationship between multiple groups of process parameter values ​​and corresponding performance data. Therefore, when the target value of the circuit performance is obtained, the effectiveness of the obtained alternative RC process corners based on the output of the process corner extraction model can be guaranteed.

[0091] In one embodiment of the present disclosure, the method further includes: performing a circuit performance verification operation based on a target RC process corner.

[0092] like Figure 6 As shown, in one embodiment of the present disclosure, a specific implementation method of performing a circuit performance verification operation based on a target RC process corner includes:

[0093] Step S602, formatting the target RC process angle to generate a target RC process angle file.

[0094] Among them, by performing formatting processing, a target RC process corner file having the same format as the initial RC process corner file is obtained to serve as an input file for simulation verification. The formatting processing is specifically converted into a file in nxtgrd format.

[0095] Step S604 , performing a circuit performance verification operation based on the target RC process corner file to obtain a circuit performance verification value.

[0096] Step S606, detecting whether the deviation rate of the verification value relative to the target value is less than a ratio threshold.

[0097] Step S608: If the deviation rate is less than the ratio threshold, it is determined that the target RC process angle verification has passed.

[0098] In one embodiment of the present disclosure, it also includes:

[0099] Step S610 : if the deviation rate is greater than or equal to the ratio threshold, reconstruct the process corner extraction model.

[0100] Step S612: Optimize the target RC process corner based on the reconstructed process corner extraction model until the optimized target RC process corner passes the performance verification.

[0101] In this embodiment, after determining the target RC process angle, in order to verify the reliability of the target RC process angle, it is necessary to use the newly extracted target RC process angle for circuit simulation to verify the target circuit performance. In order to perform circuit simulation, it is necessary to convert the target RC process angle into a format and input it into a circuit simulation module, and output a verification value of the circuit performance to detect whether it meets the application requirements based on the verification value. If the deviation rate of the target value is less than the ratio threshold, it is determined that the application requirements are met. If the deviation rate is greater than or equal to the ratio threshold, it is determined that the application requirements are not met. It is necessary to reconstruct the response surface model to establish a more accurate process angle extraction model.

[0102] For example, taking the circuit delay as the circuit performance to be verified, the ratio threshold is set to 10%. After obtaining the target RC process angle, the verification value D of the circuit performance of the delay can be obtained. Compared with the target value n, if the difference is within 10%, it is considered that the verification is successful. If the result is not satisfied, it returns to establish a more accurate response surface model formula.

[0103] In one embodiment of the present disclosure, a process corner extraction model is reconstructed, including: reconstructing a response surface model into N order, where N is greater than M; redetermining model coefficients based on the relationship between multiple groups of process parameter values ​​and corresponding performance data to reconstruct the process corner extraction model, wherein the number of model coefficients is determined based on the number of process parameters and N.

[0104] In this embodiment, a higher-order response surface model is constructed to obtain a more accurate process angle extraction model.

[0105] like Figure 7 As shown, a method for extracting a process angle of a metal interconnection line according to another embodiment of the present disclosure includes:

[0106] Step S702, in response to the input initial RC process corner file of the chip circuit, obtain the interconnection structure matching the preset process layout in the initial RC process corner file, add interconnection line parasitic parameters to the process layout based on the interconnection structure, and generate an electrical layout.

[0107] Step S704: extracting an RC sensitivity netlist from the electrical layout, wherein the RC sensitivity netlist includes sensitivity information of parasitic parameters of interconnect lines under a typical RC process corner.

[0108] Step S706 , determining a parameter range of interconnect parasitic parameters based on the sensitivity information in the RC sensitivity netlist, and randomly generating multiple sets of process parameter values ​​within the parameter range.

[0109] Step S708 , performing multiple Monte Carlo simulation operations on the circuit performance based on multiple sets of process parameter values ​​to obtain performance data of the circuit performance.

[0110] Step S710 , determining model coefficients of a response surface model based on the relationship between the multiple groups of process parameter values ​​and the corresponding performance data, so as to determine the response surface model with the determined model coefficients as a process angle extraction model.

[0111] Step S712: estimating a target value of circuit performance based on the performance data.

[0112] Step S714: the process corner extraction model outputs a plurality of candidate RC process corners that meet the target value.

[0113] Step S716: determine the candidate RC process corner with the maximum joint probability density as the target RC process corner.

[0114] Step S718, performing circuit performance verification operation based on the target RC process corner.

[0115] Step S720: If the circuit performance verification fails, reconstruct the process corner extraction model, and optimize the target RC process corner based on the reconstructed process corner extraction model until the optimized target RC process corner passes the performance verification.

[0116] In this embodiment, parasitic parameters including sensitivity information are extracted from the electrical layout, and Monte Carlo simulation is performed according to the actual variation range to obtain performance data of the circuit performance, wherein the circuit performance includes but is not limited to dynamic power consumption, static power consumption, gate delay, saturation current, leakage current, etc. A surface response model is established based on Monte Carlo statistical data of circuit performance and process parameters, and a new process parameter angle file, namely, a target RC process angle, is produced based on the surface model and circuit specifications, namely, the target value of circuit performance, and the circuit simulation is re-performed based on the target RC process angle to verify the performance.

[0117] Based on the above-mentioned process corner extraction solution, it is not necessary to perform Monte Carlo simulation of the entire circuit to find the optimal circuit performance specifications. There are specific corner target values ​​for specific circuit designs, which prevents "over-design" and verifies the new target RC process corner to reduce the probability of defects in circuit performance design. In addition, since the back-end metal layers below the 40nm technology node can be as many as 10 layers, the new corner target can optimize the delay by about 20% relative to the original Corner angle.

[0118] It should be noted that the above figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0119] It will be appreciated by those skilled in the art that various aspects of the present invention may be implemented as a system, method or program product. Therefore, various aspects of the present invention may be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to herein as a "circuit", "module" or "system".

[0120] Refer to the following Figure 8 A process angle extraction apparatus 800 for a metal interconnection line according to an embodiment of the present invention will be described. Figure 8 The process angle extraction device 800 for metal interconnection lines shown is only an example and shall not bring any limitation to the functions and application scope of the embodiments of the present invention.

[0121] The process corner extraction device 800 for metal interconnection lines is presented in the form of a hardware module. The components of the process corner extraction device 800 for metal interconnection lines may include but are not limited to: an extraction module 802, configured to respond to an input initial RC process corner file of a chip circuit, configure a process corner extraction model, so that the process corner extraction model outputs a target RC process corner, and the process margin of the target RC process corner is less than the process margin in the initial RC process corner file; wherein a circuit performance simulation operation is performed on the chip circuit based on the initial RC process corner file, so that the process corner extraction model is configured based on the result of the simulation operation.

[0122] It will be appreciated by those skilled in the art that various aspects of the present invention may be implemented as a system, method or program product. Therefore, various aspects of the present invention may be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to herein as a "circuit", "module" or "system".

[0123] Refer to the following Fig. 9 An electronic device 900 according to this embodiment of the present invention will be described. Fig. 9 The electronic device 900 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0124] like Fig. 9 As shown, the electronic device 900 is in the form of a general computing device. The components of the electronic device 900 may include but are not limited to: at least one processing unit 910, at least one storage unit 920, and a bus 930 connecting different system components (including the storage unit 920 and the processing unit 910).

[0125] The storage unit stores program codes, which can be executed by the processing unit 910, so that the processing unit 910 performs the steps according to various exemplary embodiments of the present invention described in the above “Exemplary Method” section of this specification. For example, the processing unit 910 can perform the following steps: Figure 2 The scheme described in step S202 shown in .

[0126] The storage unit 920 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 9201 and / or a cache storage unit 9202 , and may further include a read-only storage unit (ROM) 9203 .

[0127] The storage unit 920 may also include a program / utility 9204 having a set (at least one) of program modules 9205, such program modules 9205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0128] Bus 930 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0129] The electronic device 900 may also communicate with one or more external devices 970 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 900, and / or communicate with any device that enables the electronic device 900 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface 950. Furthermore, the electronic device 900 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter 960. As shown, the network adapter 960 communicates with other modules of the electronic device 900 via a bus 930. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 900, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0130] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0131] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the above method of the present specification is stored. In some possible implementations, various aspects of the present invention may also be implemented in the form of a program product, which includes a program code, and when the program product is run on an electronic device, the program code is used to enable the electronic device to perform the steps according to various exemplary implementations of the present invention described in the above "Exemplary Method" section of the present specification.

[0132] The program product for implementing the above method according to an embodiment of the present invention may adopt a portable compact disk read-only memory (CD-ROM) and include program code, and may be run on an electronic device, such as a personal computer. However, the program product of the present invention is not limited thereto, and in this document, a readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, apparatus, or device.

[0133] The program product may use any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0134] Computer readable signal media may include data signals propagated in baseband or as part of a carrier wave, in which readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Readable signal media may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0135] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

[0136] Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0137] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0138] In addition, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0139] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0140] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for extracting process angles of metal interconnects, characterized in that: include: In response to an input initial RC process corner file of a chip circuit, a process corner extraction model is configured to output a target RC process corner by the process corner extraction model, wherein a process margin of the target RC process corner is smaller than a process margin in the initial RC process corner file; Wherein, a circuit performance simulation operation is performed on the chip circuit based on the initial RC process corner file, so as to configure the process corner extraction model based on the result of the simulation operation.

2. The method for extracting process angle of metal interconnection line according to claim 1, characterized in that: The performing of a circuit performance simulation operation on the chip circuit based on the initial RC process corner file includes: Acquire an interconnection structure matching a preset process layout in the initial RC process corner file, add interconnection line parasitic parameters to the process layout based on the interconnection structure, and generate an electrical layout; Extracting an RC sensitivity netlist from the electrical layout, wherein the RC sensitivity netlist includes sensitivity information of parasitic parameters of the interconnection lines under a typical RC process corner; A circuit performance simulation operation is performed on the chip circuit based on the RC sensitivity netlist.

3. The method for extracting process angle of metal interconnection line according to claim 2, characterized in that: The performing a circuit performance simulation operation on the chip circuit based on the RC sensitivity netlist includes: Determining a parameter range of the interconnect parasitic parameter based on the sensitivity information in the RC sensitivity netlist; Randomly generate multiple sets of process parameter values ​​within the parameter range; Performing a plurality of Monte Carlo simulation operations on the circuit performance based on the plurality of sets of process parameter values ​​to obtain performance data of the circuit performance; The multiple sets of process parameter values ​​and the corresponding performance data are results of the simulation operation.

4. The method for extracting process angle of metal interconnection line according to claim 3, characterized in that: Outputting a target RC process angle from the process angle extraction model includes: estimating a target value of the circuit performance based on the performance data, the target value corresponding to a process margin of the target RC process corner; Outputting a plurality of candidate RC process angles satisfying the target value by the process angle extraction model; The target RC process corner is selected from the plurality of candidate RC process corners.

5. The method for extracting process angle of metal interconnection line according to claim 4, characterized in that: The step of selecting the target RC process corner from the plurality of candidate RC process corners includes: Calculating the joint probability density of each of the candidate RC process corners respectively; The candidate RC process corner having the maximum joint probability density is determined as the target RC process corner.

6. The method for extracting process angle of metal interconnection line according to claim 4, characterized in that: The configuration process corner extraction model includes: Obtaining a response surface model, wherein the response surface model is used to represent the response of the circuit performance to the change of the process parameter, wherein the response surface model is of M order, and M is greater than or equal to 2; The model coefficients of the response surface model are determined based on the relationship between the multiple sets of process parameter values ​​and the corresponding performance data, so as to determine the response surface model that determines the model coefficients as the process corner extraction model, and the number of the model coefficients is determined based on the number of the process parameters and M.

7. The method for extracting process angle of metal interconnection line according to claim 6, characterized in that: Also includes: A circuit performance verification operation is performed based on the target RC process corner.

8. The method for extracting process angle of metal interconnection line according to claim 7, characterized in that: The circuit performance verification operation based on the target RC process angle includes: Formatting the target RC process angle to generate a target RC process angle file; Performing a circuit performance verification operation based on the target RC process corner file to obtain a verification value of the circuit performance; Detecting whether the deviation rate of the verification value relative to the target value is less than a ratio threshold; If the deviation rate is less than the ratio threshold, it is determined that the target RC process angle verification has passed.

9. The method for extracting process angle of metal interconnection line according to claim 8, characterized in that: Also includes: If the deviation rate is greater than or equal to the ratio threshold, reconstructing the process angle extraction model; The target RC process angle is optimized based on the reconstructed process angle extraction model until the optimized target RC process angle passes performance verification.

10. The method for extracting process angle of metal interconnection line according to claim 9, characterized in that: The reconstructing the process corner extraction model comprises: Reconstructing the response surface model into N-order, where N is greater than M; The model coefficients are re-determined based on the relationship between the plurality of sets of process parameter values ​​and the corresponding performance data to reconstruct the process corner extraction model, and the number of the model coefficients is determined based on the number of the process parameters and N.

11. The method for extracting process angles of metal interconnection lines according to any one of claims 4 to 10, characterized in that: The estimating a target value of the circuit performance based on the performance data includes: estimating the expected value and standard deviation of the performance data distribution; A target value for the circuit performance is determined based on the expected value, the standard deviation, and the number of process parameters.

12. A process angle extraction device for metal interconnection lines, characterized in that: include: an extraction module, configured to configure a process corner extraction model in response to an input initial RC process corner file of a chip circuit, so that the process corner extraction model outputs a target RC process corner, wherein a process margin of the target RC process corner is smaller than a process margin in the initial RC process corner file; Wherein, a circuit performance simulation operation is performed on the chip circuit based on the initial RC process corner file, so as to configure the process corner extraction model based on the result of the simulation operation.

13. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to execute the method for extracting a process corner of a metal interconnection line according to any one of claims 1 to 11 by executing the executable instructions.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for extracting process corners of metal interconnection lines according to any one of claims 1 to 11 is implemented.

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