Driving circuit for suppressing bridge arm crosstalk

Abstract

The invention provides a drive circuit for suppressing bridge arm crosstalk, which comprises a full-bridge PWM (Pulse Width Modulation) controller and two single-bridge arm drive circuits, namely a first bridge arm crosstalk suppression drive circuit and a second bridge arm crosstalk suppression drive circuit. The first bridge arm crosstalk suppression driving circuit comprises a single bridge arm driving circuit, a single bridge arm magnetic isolation high-frequency signal transmitter, a peak reduction ground bounce suppression circuit, an oscillation suppression discharge clamping circuit, a high-frequency switching device upper tube (QM1) and a high-frequency switching device lower tube (QM2); the second bridge arm crosstalk suppression drive circuit and the first bridge arm crosstalk suppression drive circuit are the same in structure, and each of the second bridge arm crosstalk suppression drive circuit and the first bridge arm crosstalk suppression drive circuit comprises an upper tube drive and a lower tube drive to form a four-way switch tube drive circuit. According to the drive circuit, forward drive pulse peak reduction and reverse ground bounce voltage oscillation suppression can be realized.

Description

Technical Field

[0001] The invention relates to a driving circuit for suppressing bridge arm crosstalk, in particular to a full-bridge driving circuit for suppressing high-frequency crosstalk of upper and lower switch tubes of a bridge arm with a high voltage conversion rate, and belongs to the technical field of switching power supply conversion. Background Art

[0002] In order to realize the design of compact high-power power supply, high frequency is an important research direction. With the upgrading of power electronic components, new high-frequency power devices with lower on-resistance, faster switching speed and higher voltage resistance have been increasingly used. The use of new high-frequency power devices in full-bridge soft switching topology can give full play to the high-frequency performance of switching devices. While achieving high-power output, it can significantly reduce the weight and volume of power devices such as magnetic components and energy storage capacitors, thereby improving the power density of the power converter. However, the new high-frequency power devices are characterized by low conduction threshold voltage, small circuit impedance, and switching speed reaching ns level. The application of such devices can indeed reduce the conduction loss of the switching power supply circuit, but in the bridge circuit composed of the new high-frequency power devices, the Vgs voltage of the upper tube is suspended on the lower tube Vds that is continuously turned on and off. The Vds voltage can complete the jump from zero volts to thousands of volts within a few nanoseconds. The high voltage superimposed on the high frequency significantly increases the high-order harmonic components in the drive circuit. The differential mode voltage of the drive circuit Vgs generally ranges from a few volts (gallium nitride) to more than ten volts (silicon carbide), and it will be significantly affected by the common-mode interference brought to it by the high-order harmonic components of Vds.

[0003] Conversely, the Vgs differential voltage of the lower tube will also be affected by the common-mode interference caused by the Vds voltage jump of the upper tube, which is the main source of bridge arm crosstalk. During the transient switching process of high-frequency power devices, the extremely high dv / dt of the device drain-source will cause strong interference to the drive circuit through the drain-gate capacitance of the device, which not only seriously affects the accuracy of signal acquisition and the reliability of feedback signals, but also causes the destruction of the device in severe cases. High-frequency operation further increases the impact of adverse factors. If appropriate suppression measures are not taken and traditional silicon-based device drive circuits are still used, the failure rate of switching devices will be greatly increased.

[0004] In order to solve the bridge arm crosstalk problem of the above-mentioned new switching device, many scholars have proposed many effective solutions. For example, [A resonant gate drive circuit and drive method with crosstalk suppression, CN202111427442.0, valid] The invention patent discusses a digital isolation resonant drive circuit with negative voltage shutdown. The digital isolation circuit requires a signal amplification circuit, which is relatively complicated to implement and has no similarity with the present invention; [An improved gate drive circuit for suppressing SiC-MOSFET bridge arm crosstalk, CN202111113427.9, valid] The invention patent uses an RCD absorption network to achieve bridge arm crosstalk suppression. The circuit is relatively simple, but does not have forward oscillation suppression and reverse ground bounce suppression circuits; [A silicon carbide MOSFET drive circuit, CN201911366027.1, valid] The invention patent uses two clamping diodes to achieve forward and negative drive spike suppression, and uses a capacitor in series with a transistor to achieve a negative discharge function, but does not have spike reduction and ground bounce suppression functions. Summary of the invention

[0005] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide a driving circuit for suppressing bridge arm crosstalk, to achieve forward driving pulse peak reduction, and to suppress reverse ground bounce voltage oscillation.

[0006] The technical solution of the present invention is:

[0007] A driving circuit for suppressing bridge arm crosstalk, comprising: a full-bridge PWM controller, a first bridge arm crosstalk suppression driving circuit and a second bridge arm crosstalk suppression driving circuit;

[0008] The first bridge arm crosstalk suppression driving circuit includes a single bridge arm driving circuit, a single bridge arm magnetic isolation high-frequency signal transmitter, a spike reduction ground bounce suppression circuit, an oscillation suppression discharge clamp circuit, a high-frequency switch device upper tube, and a high-frequency switch device lower tube; the structure of the second bridge arm crosstalk suppression driving circuit is the same as that of the first bridge arm crosstalk suppression driving circuit, and both include an upper tube driving part and a lower tube driving part, forming a total of four switch tube driving circuits;

[0009] The full-bridge PWM controller generates four drive signals: PWMA, PWMB, PWMC, and PWMD; after the drive capability of PWMA and PWMB is enhanced by the first single-bridge arm drive circuit, the first and second reference grounds are isolated from each other and the phase difference is 180°, and two complementary drive signals are generated through the first 1:1:1 single-bridge arm magnetic isolation high-frequency signal transmitter, wherein the first drive signal passes through the first spike reduction ground bounce suppression circuit and the first oscillation suppression discharge clamp circuit, reaches the gate of the upper tube of the first high-frequency switch device, and drives the upper tube of the high-frequency switch device to turn on and off at high frequency; the second drive signal passes through the second spike reduction ground bounce suppression circuit and the second oscillation suppression discharge clamp circuit, reaches the gate of the lower tube of the second high-frequency switch device, and drives the lower tube of the high-frequency switch device to turn on and off at high frequency;

[0010] After the driving capability of PWMC and PWMD is enhanced by the second single-bridge-arm driving circuit, the third and fourth reference grounds are isolated from each other and two complementary signals with a phase difference of 180° are generated through the second 1:1:1 single-bridge-arm magnetic isolation high-frequency signal transmitter, wherein the third driving signal passes through the third spike reduction ground bounce suppression circuit and the third oscillation suppression discharge clamp circuit to reach the gate of the upper tube of the third high-frequency switching device and drive the device to be turned on and off at high frequency; the fourth driving signal passes through the fourth spike reduction ground bounce suppression circuit and the fourth oscillation suppression discharge clamp circuit to reach the gate of the lower tube of the fourth high-frequency switching device and drive the device to be turned on and off at high frequency.

[0011] Furthermore, PWMA and PWMB are a first group of complementary signals with a maximum duty cycle of 48% and a phase difference of 180°, and PWMC and PWMD are a second group of complementary driving signals with a maximum duty cycle of 48% and a phase difference of 180°.

[0012] Further, the first single bridge arm driving circuit includes resistors R9, R10, and clamping diodes D5, D6, which transmit the two driving signals PWMA and PWMB to the single bridge arm magnetic isolation high frequency signal transmitter TD1;

[0013] One end of the resistor R9 is connected to the high-frequency drive pulse signal PWMA, and the other end is connected to the primary positive input pin of the magnetic isolation high-frequency signal transmitter TD1. At the same time, the other end of the resistor R9 is also connected to the primary drive ground DGND through the clamping diode D5;

[0014] One end of the resistor R10 is connected to the high-frequency drive pulse signal PWMB, and the other end is connected to the primary negative input pin of the magnetic isolation high-frequency signal transmitter TD1. At the same time, the other end of the resistor R10 is also connected to the primary drive ground DGND through the clamping diode D6;

[0015] The primary positive input pin, the secondary upper tube positive output pin, and the secondary lower tube positive output pin of the magnetic isolation high-frequency signal transmitter TD1 are the same-name terminals, wherein the secondary upper tube positive output pin is connected to resistor R11, the secondary upper tube negative output pin is connected to resistor R12 and the cathode of diode D7, the secondary lower tube negative output pin is connected to resistor R17, and the secondary lower tube positive output pin is connected to resistor R18 and the cathode of diode D10.

[0016] Furthermore, the first spike reduction ground bounce suppression circuit and the second spike reduction ground bounce suppression circuit have the same structure, and the first spike reduction ground bounce suppression circuit includes: a capacitor C1, a resistor R11, and a voltage regulator DZ1;

[0017] The first spike reduction ground bounce suppression circuit is used to reduce the spike burrs on the rising edge of the driving signal PWMA and charge the C1 capacitor. The capacitor C1 is connected in parallel with the voltage regulator DZ1, and the voltage difference between the two ends of C1 is the DZ1 voltage drop; one end of the resistor R11 is connected to the positive output pin of the secondary side upper tube TD1, and the other end is connected to the drain of the field effect tube Q1, the base of the transistor Q3, and the anode intersection of the diode D8 through DZ1.

[0018] Furthermore, the first oscillation suppression and discharge clamp circuit and the second oscillation suppression and discharge clamp circuit have the same structure, the first oscillation suppression and discharge clamp circuit includes a first oscillation suppression circuit and a first discharge clamp circuit, and the second oscillation suppression and discharge clamp circuit includes a second oscillation suppression circuit and a second discharge clamp circuit;

[0019] The first oscillation suppression circuit includes a diode D8, resistors R14-16, a PNP transistor Q3, and a transient absorption diode TVS3; TVS3 is used to suppress the oscillation of the gate drive signal of the switch tube QM1, wherein the anode of D8 is connected to the anode of DZ1, the base of Q3, and the intersection of the drain of Q1, the cathode of D8 is connected to one end of R14, the other end of R14 is connected to the emitter of Q3, one end of TVS3, one end of R15, and the intersection of the gate of QM1, the collector of Q3 is connected to one end of the resistor R16, and the other end of R16, the other end of TVS3, the source of QM1, and the other end of R15 are all connected to the floating ground of the midpoint of the first bridge arm;

[0020] The first discharge clamp circuit includes a field effect transistor Q1, resistors R12, R13, a capacitor C2, and a Schottky diode D7; one end of the resistor R12 is connected to the cathode of the diode D7, and the other end is connected to the intersection of one end of the resistor R13, one end of the capacitor C2, and the gate of the field effect transistor Q1, the resistor R13 is connected in parallel with the capacitor C2, and the anode of the diode D7, the other end of the resistor R13, the other end of the capacitor C2, and the source of the field effect transistor Q1 are all connected to the floating ground at the midpoint of the first bridge arm.

[0021] When the switch tube QM1 is turned on, Q1 is turned off, and the base of Q3 is clamped at a high level, so that Q3 cannot be turned on. When the switch tube QM1 is turned off, the negative output pin of the secondary tube of the magnetic isolation high-frequency signal transmitter TD1 becomes a high level, Q1 is turned on, and the PNP transistor Q3 is turned on, which quickly drains the gate charge of the switch tube QM1 and accelerates the shutdown of the switch tube QM1. At this time, the positive output pin of the secondary tube of TD1 becomes a low level, and the charge stored in the energy storage capacitor C1 cannot be released immediately. The voltage across C1 is 0V on one side and a negative voltage lower than 0V on the other side. The amplitude of the negative voltage depends on the DZ1 voltage regulator value.

[0022] Furthermore, PWMA and PWMB are driving signals for the upper and lower switches of the first bridge arm, QM1 and QM2 are the two switches of the first bridge arm, and the connection point between the two switches is the floating ground of the midpoint of the first bridge arm; when the PWMA signal is high and the PWMB signal is low, the switch tube QM1 is turned on and the switch tube QM2 is turned off; when the PWMA signal is low and the PWMB signal is high, the switch tube QM1 is turned off and the switch tube QM2 is turned on.

[0023] Further, PWMC and PWMD are driving signals of the upper and lower switches of the second bridge arm, wherein QM3 is the third switch, QM4 is the fourth switch, and the middle connection point between the two switches is the floating ground of the middle point of the second bridge arm;

[0024] The second single-bridge arm driving circuit includes resistors R23, R24, clamping diodes D11, D12, and is used to transmit two driving signals PWMC and PWMD to the second single-bridge arm magnetic isolation high-frequency signal transmitter TD2; wherein one end of the resistor R23 is connected to the PWMC driving signal, and the other end is connected to the primary positive input pin of TD2 and the cathode of D11; one end of the resistor R24 ​​is connected to the PWMD driving signal, and the other end is connected to the primary negative input pin of TD2 and the cathode of the diode D12; the anodes of the diodes D11 and D12 are both connected to the primary driving ground DGND;

[0025] The primary positive input pin, the secondary upper tube positive output pin, and the secondary lower tube positive output pin of TD2 are the same-name terminals, wherein the secondary upper tube positive output pin is connected to the resistor R25, the secondary upper tube negative output pin is connected to the resistor R26 and the cathode of the diode D13, the secondary lower tube negative output pin is connected to the resistor R31, and the secondary lower tube positive output pin is connected to the resistor R32 and the cathode of the diode D16;

[0026] When the PWMC signal is at a high level and the PWMD signal is at a low level, the switch tube QM3 is turned on and the switch tube QM4 is turned off; when the PWMC signal is at a low level and the PWMD signal is at a high level, the switch tube QM3 is turned off and the switch tube QM4 is turned on;

[0027] Furthermore, the third spike reduction ground bounce suppression circuit has the same structure as the fourth spike reduction ground bounce suppression circuit, and the third spike reduction ground bounce suppression circuit includes: a capacitor C5, a resistor R25, and a voltage regulator DZ3;

[0028] The third spike reduction ground bounce suppression circuit is used to reduce the spike burrs on the rising edge of the driving signal PWMC and charge the C5 capacitor. The capacitor C5 is connected in parallel with the voltage regulator DZ3, and the voltage difference across C5 is the DZ3 voltage drop; one end of the resistor R25 is connected to the positive output pin of the secondary side upper tube TD2, and the other end is connected to the drain of the field effect tube Q5, the base of the transistor Q7, and the anode intersection of the diode D14 through DZ3.

[0029] Further, the third oscillation suppression and discharge clamp circuit and the fourth oscillation suppression and discharge clamp circuit have the same structure, the third oscillation suppression and discharge clamp circuit includes a third oscillation suppression circuit and a third discharge clamp circuit, and the fourth oscillation suppression and discharge clamp circuit includes a fourth oscillation suppression circuit and a fourth discharge clamp circuit;

[0030] The third oscillation suppression circuit includes a diode D14, resistors R28-R30, a PNP transistor Q7, and a transient absorption diode TVS5, wherein TVS5 is used to suppress the oscillation of the gate drive signal of the switch tube QM3; wherein the anode of D14 is connected to the anode of DZ3, the base of Q7, and the intersection of the drain of Q5, the cathode of D14 is connected to one end of R28, the other end of R28 is connected to the emitter of Q7, one end of TVS5, one end of R29, and the intersection of the gate of QM3, the collector of Q7 is connected to one end of R30, and the other side of R30, the other end of TVS5, the source of QM3, and the other end of R29 are all connected to the floating ground of the midpoint of the second bridge arm.

[0031] Further, the third discharge clamp circuit includes a field effect transistor Q5, resistors R26, R27, a capacitor C6, and a Schottky diode D13;

[0032] One end of R26 is connected to the cathode of D13 and the negative output pin of the secondary tube of TD2, and the other end is connected to the intersection of one end of R27, one end of C6, and the gate of Q5. R27 is connected in parallel with C6, and the anode of D13, the other end of R27, the other end of C6, and the source of Q5 are all connected to the floating ground at the midpoint of the second bridge arm.

[0033] When the third switch tube QM3 is turned on, Q5 is turned off, and the base of Q7 is clamped at a high level, so that Q7 cannot be turned on. When the third switch tube QM3 is turned off, the negative output pin of the secondary tube of the second single-arm magnetic isolation high-frequency signal transmitter TD2 becomes a high level, Q5 is turned on, and the PNP transistor Q7 is turned on, which quickly drains the gate charge of the third switch tube QM3 and accelerates the shutdown of the third switch tube; at this time, the positive output pin of the secondary tube of TD2 becomes a low level, and the charge stored in the energy storage capacitor C5 cannot be released immediately, that is, one side of the voltage across C5 is 0V, and the other side is a negative voltage lower than 0V, and the amplitude of the negative voltage depends on the DZ3 voltage regulator value.

[0034] The beneficial effects of the present invention compared with the prior art are:

[0035] (1) The present invention realizes forward drive pulse peak reduction and reverse ground bounce voltage oscillation suppression, thereby improving the reliability of the operation of the new high-frequency switch device. At the same time, it has a reverse negative voltage clamp, which can prevent the crosstalk voltage from causing the switch tube to be erroneously turned on during the shutdown period of the switch device.

[0036] (2) The driving circuit of the present invention does not require high-power consumption devices, and can realize low-cost and compact driving circuit design, which is conducive to realizing miniaturized design of power supply module.

[0037] (3) The conduction peak reduction circuit of the present invention realizes the reduction of the forward driving signal peak voltage by connecting the voltage regulator tube and the energy storage capacitor in parallel, and at the same time provides a negative voltage when the new switch tube is turned off;

[0038] (4) The shutdown ground bounce suppression circuit of the present invention provides a fast clamping of the driving level when the switch tube is turned off through a controllable low-voltage MOSFET circuit, thereby preventing the switch tube from being mistakenly turned on due to a ground bounce signal;

[0039] (5) The forward oscillation suppression circuit of the present invention further absorbs forward level jitter and spike glitches by placing a TVS diode between the gate and source of the switch tube, ensuring that the forward drive level is within a safe range;

[0040] (6) The reverse discharge clamp circuit of the present invention provides a reverse discharge channel through a Schottky diode and a fast transistor, thereby accelerating the shutdown of the switch tube and thus improving the shutdown speed of the switch tube.

[0041] (7) The present invention improves the reliability of the new high-speed switching device driving circuit through suppression measures, enhances the anti-interference ability of the full-bridge power circuit, and is conducive to achieving high frequency and miniaturization of the power converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 The working principle diagram of the driving circuit for suppressing bridge arm crosstalk of the present invention;

[0043] Figure 2Isolate the drive circuit for traditional single-arm power devices;

[0044] Figure 3 This is the full-bridge soft switch drive waveform timing diagram;

[0045] Figure 4 is a schematic diagram of a crosstalk suppression driving circuit for the first bridge arm;

[0046] Figure 5 Schematic diagram of the crosstalk suppression driving circuit of the second bridge arm. DETAILED DESCRIPTION

[0047] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0048] like Figure 1 As shown, a driving circuit for suppressing bridge arm crosstalk proposed by the present invention includes: a full-bridge PWM controller and two single bridge arm driving circuits, namely a first bridge arm crosstalk suppression driving circuit and a second bridge arm crosstalk suppression driving circuit. The first bridge arm crosstalk suppression driving circuit includes a single bridge arm driving circuit, a single bridge arm magnetic isolation high-frequency signal transmitter, a peak reduction ground bounce suppression circuit, an oscillation suppression discharge clamp circuit, a high-frequency switching device upper tube (QM1), and a high-frequency switching device lower tube (QM2); the structure of the second bridge arm crosstalk suppression driving circuit is the same as that of the first bridge arm crosstalk suppression driving circuit, both of which include an upper tube drive and a lower tube drive, forming a total of four switch tube drive circuits.

[0049] Specifically, the full-bridge PWM controller generates four drive signals: PWMA, PWMB and PWMC, PWMD, PWMA, PWMB are the first group of complementary signals with a maximum duty cycle of 48% and a phase difference of 180°. After the driving capability of the two groups of drive signals is enhanced by the first single-bridge arm drive chip, the first 1:1:1 single-bridge arm magnetic isolation high-frequency signal transmitter generates a first and a second reference ground isolated from each other, and two complementary signals with a phase difference of 180°, wherein the first drive signal passes through the first peak reduction ground bounce suppression circuit and the first oscillation suppression discharge clamp circuit, reaches the gate of the first high-frequency switching device (upper tube), and drives the device to be turned on and off at high frequency; the second drive signal passes through the second peak reduction ground bounce suppression circuit and the second oscillation suppression discharge clamp circuit, reaches the gate of the second high-frequency switching device (lower tube), and drives the device to be turned on and off at high frequency.

[0050] PWMC and PWMD are the second group of complementary signals with a maximum duty cycle of 48% and a phase difference of 180°. After the driving capability of the two groups of drive signals is enhanced by the second single-bridge arm drive chip, the third and fourth reference grounds are isolated from each other and the phase difference is 180°. The third drive signal passes through the third peak reduction ground bounce suppression circuit and the third oscillation suppression discharge clamp circuit to reach the gate of the third high-frequency switching device (upper tube) and drive the device to be turned on and off at high frequency; the fourth drive signal passes through the fourth peak reduction ground bounce suppression circuit and the fourth oscillation suppression discharge clamp circuit to reach the gate of the fourth high-frequency switching device (lower tube) and drive the device to be turned on and off at high frequency.

[0051] Pin 1 of the 1:1:1 single-arm magnetically isolated high-frequency signal transmitter is the primary positive input pin, and pin 2 is the primary negative input pin; pin 3 is the secondary upper tube positive output pin, and pin 4 is the secondary upper tube negative output pin; pin 5 is the secondary lower tube negative output pin; and pin 6 is the secondary lower tube positive output pin.

[0052] Traditional single-arm power device isolation drive circuit such as Figure 2 shown.

[0053] A pair of complementary drive signals PWMA and PWMB are transmitted to the isolation transformer T1 via the current limiting resistors R1 and R2. T1 consists of three windings with a turn ratio of 1:1:1, where 1, 3, and 6 are the same-name terminals. When PWMA is high, PWMB is low, the positive output pin of the secondary upper tube and the positive output pin of the secondary lower tube of T1 are high, the switch tube QS1 is turned on, and the switch tube QS2 is turned off. TVS1 prevents the gate from generating a spike voltage when QS1 is turned on; when PWMB is high, PWMA is low. The negative input pin of the primary side of T1, the negative output pin of the upper tube on the secondary side, and the negative output pin of the lower tube on the secondary side are at a high level. The switch tube QS2 is turned on, and the switch tube QS1 is turned off. TVS2 prevents the gate from generating a spike voltage when QS2 is turned on. When QS1 is turned off, the charge when the gate is turned on is quickly discharged through the low impedance circuit R3 and D3, and R4 clamps the gate-source voltage of QS1 at a low level. When QS2 is turned off, the charge when the gate is turned on is quickly discharged through the low impedance circuit R6 and D4, and R7 clamps the gate-source voltage of QS2 at a low level. Figure 2 It can be seen that the traditional single-arm power device isolation drive circuit only has the gate voltage spike suppression function, which is suitable for silicon-based semiconductor switching devices and lacks effective suppression function for the bridge arm crosstalk generated by new high-speed semiconductors.

[0054] Typical full-bridge soft switch drive waveform timing diagram is as follows: Figure 3As shown, it can be seen that at t0 and t1, PWMC and PWMD will be affected by the rising and falling edges of PWMA and PWMB, and spikes will be generated at the horizon and peaks of PWMC and PWMD at the corresponding moments, thereby exceeding the maximum threshold voltage of the gate of the switching device or mis-turning on, damaging the switching device; similarly, PWMA and PWMB will also be affected by the crosstalk at the switching moments of PWMC and PWMD.

[0055] The first bridge arm crosstalk suppression driving circuit in the full-bridge driving circuit for suppressing bridge arm crosstalk proposed by the present invention is as follows Figure 4 shown.

[0056] PWMA and PWMB are the driving signals of the upper and lower switches of the first bridge arm, among which QM1 and QM2 are the two switches of the first bridge arm, and the connection point between the two tubes is the floating ground of the midpoint of the first bridge arm. When the PWMA signal is high and the PWMB signal is low, the switch tube QM1 is turned on and the switch tube QM2 is turned off; when the PWMA signal is low and the PWMB signal is high, the switch tube QM1 is turned off and the switch tube QM2 is turned on.

[0057] like Figure 4 As shown, resistor R9, resistor R10, clamping diode D5, and clamping diode D6 form a first bridge arm primary drive signal circuit (single bridge arm drive circuit), which is responsible for transmitting the two drive signals PWMA and PWMB enhanced by the drive chip to the single bridge arm magnetic isolation high frequency signal transmitter TD1, wherein one end of the resistor R9 is connected to the high frequency drive pulse signal PWMA, and the other end is connected to the primary positive input pin of the magnetic isolation high frequency signal transmitter TD1 and the cathode of the diode D5, one end of the resistor R10 is connected to the high frequency drive pulse signal PWMB, and the other end is connected to the primary negative input pin of the magnetic isolation high frequency signal transmitter TD1 and the cathode of the diode D6, and the anodes of the diodes D5 and D6 are both connected to the primary drive ground DGND. The primary positive input pin of TD1, the positive output pin of the secondary upper tube, and the positive output pin of the secondary lower tube are the same-named terminals, wherein the positive output pin of the secondary upper tube is connected to one end of the resistor R11, the negative output pin of the secondary upper tube is connected to one end of the resistor R12 and the cathode of the diode D7, the negative output pin of the secondary lower tube is connected to one end of the resistor R17, and the positive output pin of the secondary lower tube is connected to one end of the resistor R18 and the cathode of the diode D10.

[0058] like Figure 4As shown, capacitor C1, resistor R11, and voltage regulator DZ1 form a first peak reduction circuit, which mainly reduces the peak burrs on the rising edge of the driving signal and charges the capacitor C1. The left end of C1 is high and the right end is low, and the voltage difference is the DZ1 voltage drop; one end of the resistor R11 is connected to the positive output pin of the secondary side upper tube TD1, and the other end is connected to DZ1. The voltage regulator DZ1 is connected in parallel with the two ends of the capacitor C1, and the other end of the parallel connection is connected to the drain of the field effect tube Q1, the base of the transistor Q3, and the intersection of the anode of the diode D8.

[0059] like Figure 4 As shown, diode D8, resistor R14, PNP transistor Q3, resistor R16, transient absorption diode TVS3, and resistor R15 form the first oscillation suppression circuit, and TVS3 bidirectional transient absorption diode suppresses the oscillation of the gate drive signal of switch tube QM1. Among them, the anode of D8 is connected to the anode of DZ1, the base of Q3, and the intersection of the drain of Q1, the cathode of D8 is connected to one end of R14, and the other end of R14 is connected to the emitter of Q3, the upper end of TVS3, the upper end of R15, and the intersection of the gate of QM1. The collector of Q3 is connected to the right side of resistor R16, and the left side of R16, the lower end of TVS3, the source of QM1, and the lower end of R15 are all connected to the floating ground of the midpoint of the first bridge arm.

[0060] like Figure 4 As shown, field effect tube Q1, resistor R12, resistor R13, capacitor C2, and Schottky diode D7 form the first discharge clamping circuit. When the switch tube QM1 is turned on, Q1 is turned off, and the base of Q3 is clamped at a high level, so that Q3 cannot be turned on. When the switch tube QM1 is turned off, the negative output pin of the secondary tube of the magnetic isolation high-frequency signal transmitter TD1 becomes a high level, Q1 is turned on, and the PNP transistor Q3 is turned on, which quickly drains the gate charge of the switch tube QM1 and accelerates the shutdown of the switch tube QM1. ; Since the positive output pin of the secondary tube of TD1 becomes low level (0V) at this time, the charge stored in the energy storage capacitor C1 cannot be released immediately, that is, the voltage across C1 is still high on the left and low on the right. Since the left side is 0V, a negative voltage lower than 0V appears on the right side. The magnitude of the negative voltage depends on the DZ1 voltage regulator value. The selection of the DZ1 voltage regulator value is related to the driving voltage required by the high-frequency power switch tube QM1, which is generally 2 to 4V. The capacitance of C1 is related to the turn-off holding time of the switch tube QM1. Among them, one end of the resistor R12 is connected to the cathode of the diode D7, and the other end is connected to the intersection of the upper end of the resistor R13, the upper end of the capacitor C2, and the gate of the field effect tube Q1. The resistor R13 is connected in parallel with the capacitor C2. The anode of the diode D7, the lower end of the resistor R13, the lower end of the capacitor C2, and the source of the field effect tube Q1 are all connected to the floating ground of the midpoint of the first bridge arm.

[0061] like Figure 4As shown, the resistor R17, the voltage regulator tube DZ2, and the third energy storage capacitor C3 form the second peak reduction circuit, which mainly reduces the peak burrs on the rising edge of the driving signal and charges the C3 capacitor. The left end of C3 is high and the right end is low, and the voltage difference is the DZ2 voltage drop. The left side of R17 is connected to the negative output pin of the secondary lower tube of TD1, and the right side is connected to the cathode of DZ2. DZ2 is connected in parallel with C3, and the other end of the parallel connection is connected to the drain of the field effect tube Q2, the base of the triode Q4, and the anode intersection of the diode D9.

[0062] like Figure 4 As shown, diode D9, resistor R20, PNP transistor Q4, resistor R22, transient absorption diode TVS4, and resistor R21 form a second oscillation suppression circuit, and TVS4 bidirectional transient absorption diode suppresses the oscillation of the gate drive signal of switch tube QM2. Among them, the cathode of D9 is connected to one end of R20, and the other end of R20 is connected to the emitter of Q4, the upper end of TVS4, the upper end of R21, and the intersection of the gate of QM2. The collector of Q4 is connected to the other end of R22, and one end of R22, the lower end of TVS4, the lower end of R21, and the source of QM2 are all connected to the reference ground GND of the power circuit.

[0063] like Figure 4 As shown, field effect tube Q2, resistor R18, resistor R19, capacitor C4, and Schottky diode D10 form a second discharge clamping circuit. When the switch tube QM2 is turned on, Q2 is turned off, and the base of Q4 is clamped at a high level, and Q4 cannot be turned on. When the switch tube QM2 is turned off, the positive output pin of the secondary lower tube of the magnetic isolation high-frequency signal transmitter TD1 becomes a high level, Q2 is turned on, and the PNP transistor Q4 is turned on, which quickly drains the gate charge of the switch tube QM2 and accelerates the switch tube QM2. Shutdown; since the negative output pin of the secondary lower tube of TD1 becomes a low level (0V) at this time, the charge stored in the energy storage capacitor C3 cannot be released immediately, that is, the voltage across C3 is still high on the left and low on the right, the left side is 0V, and a negative voltage below 0V appears on the right. The magnitude of the negative voltage depends on the voltage regulation value of DZ2. The selection of the voltage regulation value of DZ2 is related to the driving voltage required by the high-frequency power switch tube QM2, which is generally 2 to 4V. The capacitance value of C3 is related to the shutdown holding time of the switch tube QM2. The left side of the resistor R18 is connected to the positive output pin of the secondary lower tube of TD1 and the cathode intersection of the diode D10, and the right side of the resistor R18 is connected to the resistor R19, the upper end of the capacitor C4, and the gate intersection of the field effect tube Q2. The resistor R19 and the capacitor C4 are connected in parallel, and the anode of the diode D10, the lower end of the resistor R19, the lower end of the capacitor C4, and the source of the field effect tube Q2 are all connected to the reference ground GND of the power circuit.

[0064] like Figure 5As shown, PWMC and PWMD are the driving signals of the upper and lower switches of the second bridge arm, among which QM3 is the third switch, QM4 is the fourth switch, and the middle connection point between the two tubes is the floating ground of the middle point of the second bridge arm. Resistor R23, resistor R24, clamping diode D11 and clamping diode D12 form the primary driving signal circuit of the second bridge arm, which is responsible for transmitting the two driving signals PWMC and PWMD enhanced by the driver chip to the second single bridge arm magnetic isolation high-frequency signal transmitter TD2. When the PWMC signal is high and the PWMD signal is low, the switch tube QM3 is turned on and the switch tube QM4 is turned off; when the PWMC signal is low and the PWMD signal is high, the switch tube QM3 is turned off and the switch tube QM4 is turned on. One end of the resistor R23 is connected to the PWMC drive signal, and the other end is connected to the primary positive input pin of TD2 and the cathode of D11; one end of the resistor R24 ​​is connected to the PWMD drive signal, and the other end is connected to the primary negative input pin of TD2 and the cathode of diode D12; the anodes of diodes D11 and D12 are both connected to the primary drive ground DGND. The primary positive input pin, the secondary upper tube positive output pin, and the secondary lower tube positive output pin of the magnetic isolation transmitter TD2 are the same-name terminals, wherein the secondary upper tube positive output pin is connected to one end of the resistor R25, the secondary upper tube negative output pin is connected to one end of the resistor R26 and the cathode of diode D13, the secondary lower tube negative output pin is connected to one end of the resistor R31, and the secondary lower tube positive output pin is connected to one end of the resistor R32 and the cathode of diode D16.

[0065] like Figure 5 As shown, resistor R25, voltage regulator DZ3, and capacitor C5 form the third peak reduction circuit, which mainly reduces the peak burrs on the rising edge of the driving signal and charges the C5 capacitor. The left end of C5 is high and the right end is low, and the voltage difference is the DZ3 voltage drop. One end of the resistor R25 is connected to the positive output pin of the secondary side upper tube of TD2, and the other end is connected to DZ3. The voltage regulator DZ3 is connected in parallel with the two ends of the capacitor C5, and the other end of the parallel connection is connected to the drain of the field effect tube Q5, the base of the transistor Q7, and the anode intersection of the diode D14.

[0066] like Figure 5 As shown, diode D14, resistor R28, PNP transistor Q7, resistor R30, transient absorption diode TVS5, and resistor R29 form a third oscillation suppression circuit, wherein the TVS5 bidirectional transient absorption diode suppresses the oscillation of the gate drive signal of the switch tube QM3; wherein the anode of D14 is connected to the anode of DZ3, the base of Q7, and the intersection of the drain of Q5, the cathode of D14 is connected to one end of R28, the other end of R28 is connected to the emitter of Q7, the upper end of TVS5, the upper end of R29, and the intersection of the gate of QM3, the collector of Q7 is connected to the right side of R30, and the left side of R30, the other end of TVS5, the source of QM3, and the lower end of R29 are all connected to the floating ground of the midpoint of the second bridge arm.

[0067] like Figure 5 As shown, field effect tube Q5, resistor R26, resistor R27, capacitor C6, and Schottky diode D13 form a third discharge clamping circuit. When the third switch tube QM3 is turned on, Q5 is turned off, and the base of Q7 is clamped at a high level, and Q7 cannot be turned on. When the third switch tube QM3 is turned off, the negative output pin of the secondary upper tube of the second single-arm magnetic isolation high-frequency signal transmitter TD2 becomes a high level, Q5 is turned on, and the PNP transistor Q7 is turned on, and the gate charge of the third switch tube QM3 is quickly emptied. Accelerate the shutdown of the third switch tube; since the positive output pin of the secondary tube of TD2 becomes a low level (0V) at this time, the charge stored in the energy storage capacitor C5 cannot be released immediately, that is, the voltage across C5 is still high on the left and low on the right. Since the left side is 0V, a negative voltage lower than 0V appears on the right side. The magnitude of the negative voltage depends on the DZ3 voltage regulator value. The selection of the DZ3 voltage regulator value is related to the driving voltage required by the high-frequency power switch tube QM3, which is generally 2 to 4V. The capacitance of C5 depends on the QM3 shutdown holding time. Among them, one end of R26 is connected to the cathode of D13 and the negative output pin of the secondary tube of TD2, and the other end is connected to the intersection of the upper end of R27, the upper end of C6, and the gate of Q5. R27 is connected in parallel with C6, and the anode of D13, the lower end of R27, the lower end of C6, and the source of Q5 are all connected to the floating ground of the midpoint of the second bridge arm.

[0068] like Figure 5 As shown, the resistor R31, the voltage regulator DZ4, and the capacitor C7 form the fourth peak reduction circuit, which mainly reduces the peak burrs on the rising edge of the driving signal and charges the capacitor C7. The left end of C7 is high and the right end is low, and the voltage difference is the voltage drop of DZ4. One end of the resistor R31 is connected to the negative output pin of the secondary lower tube of TD2, and the other end is connected to DZ4. The voltage regulator DZ4 is connected in parallel with the two ends of the capacitor C7, and the other end of the parallel connection is connected to the drain of the field effect tube Q6, the base of the transistor Q8, and the anode intersection of the diode D15.

[0069] like Figure 5 As shown, diode D15, resistor R34, PNP transistor Q8, resistor R36, transient absorption diode TVS6, and resistor R35 form a second oscillation suppression circuit, in which TVS6 bidirectional transient absorption diode suppresses the oscillation of the gate drive signal of switch tube QM4. The anode of D15 is connected to the anode of DZ4, the base of Q8, and the intersection of the drain of Q6, the cathode of D15 is connected to one end of R34, and the other end of R34 is connected to the emitter of Q8, the upper end of TVS6, the upper end of R35, and the intersection of the gate of QM4. The collector of Q8 is connected to the right side of resistor R36, and the left side of R36, the lower end of TVS6, the source of QM4, and the lower end of R29 are all connected to the second bridge arm power reference ground GND.

[0070] like Figure 5As shown, field effect tube Q6, resistor R32, resistor R33, capacitor C8, and Schottky diode D16 form a second discharge clamping circuit. When the switch tube QM4 is turned on, Q6 is turned off, and the base of Q8 is clamped at a high level, and Q8 cannot be turned on. When the fourth switch tube QM4 is turned off, the positive output pin of the secondary lower tube of the second single-arm magnetic isolation high-frequency signal transmitter TD2 becomes a high level, Q6 is turned on, and the PNP transistor Q8 is turned on, and the gate charge of the second switch tube QM4 is quickly emptied, and the gate charge of the second switch tube QM4 is increased. The fourth switch tube is turned off quickly; since the negative output pin of the secondary lower tube of TD2 becomes a low level (0V) at this time, the charge stored in the energy storage capacitor C7 cannot be released immediately, that is, the voltage across C7 is still high on the left and low on the right. Since the left side is 0V, a negative voltage lower than 0V appears on the right. The magnitude of the negative voltage depends on the DZ4 voltage regulation value. The selection of the DZ4 voltage regulation value is related to the driving voltage required by the high-frequency power switch tube QM4, which is generally 2 to 4V. The capacitance of C7 depends on the QM4 shutdown holding time. Among them, one end of R32 is connected to the cathode of D16 and the positive output pin of the secondary lower tube of TD2, and the other end is connected to the upper end of R33, the upper end of C8, and the intersection of the gate of Q6. R33 is connected in parallel with C8, and the anode of D16, the lower end of R33, the lower end of C8, and the source of Q6 are all connected to the second bridge arm power reference ground GND.

[0071] Phase-shifted full-bridge PWM control chip and peripheral circuits, single-bridge arm drive chip and peripheral circuits, high-frequency power device drain-source RC absorption circuit, etc., are all involved in existing inventions or existing products and can be used as components or parts of the present invention.

[0072] Parts of the present invention that are not described in detail belong to common knowledge among those skilled in the art.

Claims

1. A driving circuit for suppressing bridge arm crosstalk, characterized in that include: A full-bridge PWM controller, a first bridge arm crosstalk suppression driving circuit, and a second bridge arm crosstalk suppression driving circuit; The first bridge arm crosstalk suppression driving circuit includes a single bridge arm driving circuit, a single bridge arm magnetic isolation high-frequency signal transmitter, a spike reduction ground bounce suppression circuit, an oscillation suppression discharge clamp circuit, a high-frequency switch device upper tube, and a high-frequency switch device lower tube; the structure of the second bridge arm crosstalk suppression driving circuit is the same as that of the first bridge arm crosstalk suppression driving circuit, and both include an upper tube driving part and a lower tube driving part, forming a total of four switch tube driving circuits; The full-bridge PWM controller generates four drive signals: PWMA, PWMB, PWMC, and PWMD. After the drive capability of PWMA and PWMB is enhanced by the first single-bridge arm drive circuit, the first 1:1:1 single-bridge arm magnetic isolation high-frequency signal transmitter generates two complementary drive signals, the first and second reference grounds are isolated from each other and the phase difference is 180°, wherein the first drive signal passes through the first peak reduction ground bounce suppression circuit and the first oscillation suppression discharge clamp circuit, reaches the gate of the upper tube of the first high-frequency switch device, and drives the upper tube of the high-frequency switch device to turn on and off at high frequency; The second driving signal passes through the second peak reduction ground bounce suppression circuit and the second oscillation suppression discharge clamp circuit, reaches the gate of the lower tube of the second high-frequency switching device, and drives the lower tube of the high-frequency switching device to turn on and off at high frequency; After the driving capability of PWMC and PWMD is enhanced by the second single-bridge arm driving circuit, the third and fourth reference grounds are isolated from each other and the phase difference is 180°. The third driving signal passes through the third peak reduction ground bounce suppression circuit and the third oscillation suppression discharge clamp circuit, reaches the gate of the upper tube of the third high-frequency switching device, and drives the device to turn on and off at high frequency; The fourth driving signal passes through the fourth peak reduction ground bounce suppression circuit and the fourth oscillation suppression discharge clamp circuit, reaches the gate of the lower tube of the fourth high-frequency switching device, and drives the device to turn on and off at high frequency.

2. A driving circuit for suppressing bridge arm crosstalk according to claim 1, characterized in that: PWMA and PWMB are a first group of complementary signals with a maximum duty cycle of 48% and a phase difference of 180°, and PWMC and PWMD are a second group of complementary driving signals with a maximum duty cycle of 48% and a phase difference of 180°.

3. A driving circuit for suppressing bridge arm crosstalk according to claim 1 or 2, characterized in that: The first single bridge arm driving circuit includes resistors R9, R10, clamping diodes D5, D6, and transmits two driving signals PWMA and PWMB to the single bridge arm magnetic isolation high frequency signal transmitter TD1; One end of the resistor R9 is connected to the high-frequency drive pulse signal PWMA, and the other end is connected to the primary positive input pin of the magnetic isolation high-frequency signal transmitter TD1. At the same time, the other end of the resistor R9 is also connected to the primary drive ground DGND through the clamping diode D5; One end of the resistor R10 is connected to the high-frequency drive pulse signal PWMB, and the other end is connected to the primary negative input pin of the magnetic isolation high-frequency signal transmitter TD1. At the same time, the other end of the resistor R10 is also connected to the primary drive ground DGND through the clamping diode D6; The primary positive input pin, the secondary upper tube positive output pin, and the secondary lower tube positive output pin of the magnetic isolation high-frequency signal transmitter TD1 are the same-name terminals, wherein the secondary upper tube positive output pin is connected to resistor R11, the secondary upper tube negative output pin is connected to resistor R12 and the cathode of diode D7, the secondary lower tube negative output pin is connected to resistor R17, and the secondary lower tube positive output pin is connected to resistor R18 and the cathode of diode D10.

4. A driving circuit for suppressing bridge arm crosstalk according to claim 3, characterized in that: The first spike reduction ground bounce suppression circuit has the same structure as the second spike reduction ground bounce suppression circuit. The first spike reduction ground bounce suppression circuit includes: a capacitor C1, a resistor R11, and a voltage regulator DZ1; The first spike reduction ground bounce suppression circuit is used to reduce the spike burrs on the rising edge of the driving signal PWMA and charge the C1 capacitor. The capacitor C1 is connected in parallel with the voltage regulator DZ1, and the voltage difference between the two ends of C1 is the DZ1 voltage drop; one end of the resistor R11 is connected to the positive output pin of the secondary side upper tube TD1, and the other end is connected to the drain of the field effect tube Q1, the base of the transistor Q3, and the anode intersection of the diode D8 through DZ1.

5. A driving circuit for suppressing bridge arm crosstalk according to claim 4, characterized in that: The first oscillation suppression and discharge clamp circuit and the second oscillation suppression and discharge clamp circuit have the same structure, the first oscillation suppression and discharge clamp circuit includes a first oscillation suppression circuit and a first discharge clamp circuit, and the second oscillation suppression and discharge clamp circuit includes a second oscillation suppression circuit and a second discharge clamp circuit; The first oscillation suppression circuit includes a diode D8, resistors R14-16, a PNP transistor Q3, and a transient absorption diode TVS3; TVS3 is used to suppress the oscillation of the gate drive signal of the switch tube QM1, wherein the anode of D8 is connected to the anode of DZ1, the base of Q3, and the intersection of the drain of Q1, the cathode of D8 is connected to one end of R14, the other end of R14 is connected to the emitter of Q3, one end of TVS3, one end of R15, and the intersection of the gate of QM1, the collector of Q3 is connected to one end of the resistor R16, and the other end of R16, the other end of TVS3, the source of QM1, and the other end of R15 are all connected to the floating ground of the midpoint of the first bridge arm; The first discharge clamp circuit includes a field effect transistor Q1, resistors R12, R13, a capacitor C2, and a Schottky diode D7; one end of the resistor R12 is connected to the cathode of the diode D7, and the other end is connected to the intersection of one end of the resistor R13, one end of the capacitor C2, and the gate of the field effect transistor Q1, the resistor R13 is connected in parallel with the capacitor C2, and the anode of the diode D7, the other end of the resistor R13, the other end of the capacitor C2, and the source of the field effect transistor Q1 are all connected to the floating ground at the midpoint of the first bridge arm. When the switch tube QM1 is turned on, Q1 is turned off, and the base of Q3 is clamped at a high level, so that Q3 cannot be turned on. When the switch tube QM1 is turned off, the negative output pin of the secondary tube of the magnetic isolation high-frequency signal transmitter TD1 becomes a high level, Q1 is turned on, and the PNP transistor Q3 is turned on, which quickly drains the gate charge of the switch tube QM1 and accelerates the shutdown of the switch tube QM1. At this time, the positive output pin of the secondary tube of TD1 becomes a low level, and the charge stored in the energy storage capacitor C1 cannot be released immediately. The voltage across C1 is 0V on one side and a negative voltage lower than 0V on the other side. The amplitude of the negative voltage depends on the DZ1 voltage regulator value.

6. A driving circuit for suppressing bridge arm crosstalk according to claim 5, characterized in that: PWMA and PWMB are the driving signals of the upper and lower switches of the first bridge arm, QM1 and QM2 are the two switches of the first bridge arm, and the connection point between the two switches is the floating ground of the midpoint of the first bridge arm; when the PWMA signal is high and the PWMB signal is low, the switch tube QM1 is turned on and the switch tube QM2 is turned off; when the PWMA signal is low and the PWMB signal is high, the switch tube QM1 is turned off and the switch tube QM2 is turned on.

7. A driving circuit for suppressing bridge arm crosstalk according to claim 1 or 2, characterized in that: PWMC and PWMD are driving signals for the upper and lower switches of the second bridge arm, where QM3 is the third switch, QM4 is the fourth switch, and the middle connection point between the two is the floating ground of the middle point of the second bridge arm; The second single-bridge arm driving circuit includes resistors R23, R24, clamping diodes D11, D12, and is used to transmit two driving signals PWMC and PWMD to the second single-bridge arm magnetic isolation high-frequency signal transmitter TD2; wherein one end of the resistor R23 is connected to the PWMC driving signal, and the other end is connected to the primary positive input pin of TD2 and the cathode of D11; one end of the resistor R24 ​​is connected to the PWMD driving signal, and the other end is connected to the primary negative input pin of TD2 and the cathode of the diode D12; the anodes of the diodes D11 and D12 are both connected to the primary driving ground DGND; The primary positive input pin, the secondary upper tube positive output pin, and the secondary lower tube positive output pin of TD2 are the same-name terminals, wherein the secondary upper tube positive output pin is connected to the resistor R25, the secondary upper tube negative output pin is connected to the resistor R26 and the cathode of the diode D13, the secondary lower tube negative output pin is connected to the resistor R31, and the secondary lower tube positive output pin is connected to the resistor R32 and the cathode of the diode D16; When the PWMC signal is at a high level and the PWMD signal is at a low level, the switch tube QM3 is turned on and the switch tube QM4 is turned off; when the PWMC signal is at a low level and the PWMD signal is at a high level, the switch tube QM3 is turned off and the switch tube QM4 is turned on.

8. The driving circuit for suppressing bridge arm crosstalk according to claim 7, characterized in that: The third spike reduction ground bounce suppression circuit has the same structure as the fourth spike reduction ground bounce suppression circuit. The third spike reduction ground bounce suppression circuit includes: a capacitor C5, a resistor R25, and a voltage regulator DZ3; The third spike reduction ground bounce suppression circuit is used to reduce the spike burrs on the rising edge of the driving signal PWMC and charge the C5 capacitor. The capacitor C5 is connected in parallel with the voltage regulator DZ3, and the voltage difference across C5 is the DZ3 voltage drop; one end of the resistor R25 is connected to the positive output pin of the secondary side upper tube TD2, and the other end is connected to the drain of the field effect tube Q5, the base of the transistor Q7, and the anode intersection of the diode D14 through DZ3.

9. The driving circuit for suppressing bridge arm crosstalk according to claim 8, characterized in that: The third oscillation suppression and discharge clamp circuit and the fourth oscillation suppression and discharge clamp circuit have the same structure. The third oscillation suppression and discharge clamp circuit includes a third oscillation suppression circuit and a third discharge clamp circuit. The fourth oscillation suppression and discharge clamp circuit includes a fourth oscillation suppression circuit and a fourth discharge clamp circuit. The third oscillation suppression circuit includes a diode D14, resistors R28-R30, a PNP transistor Q7, and a transient absorption diode TVS5, wherein TVS5 is used to suppress the oscillation of the gate drive signal of the switch tube QM3; wherein the anode of D14 is connected to the anode of DZ3, the base of Q7, and the intersection of the drain of Q5, the cathode of D14 is connected to one end of R28, the other end of R28 is connected to the emitter of Q7, one end of TVS5, one end of R29, and the intersection of the gate of QM3, the collector of Q7 is connected to one end of R30, and the other side of R30, the other end of TVS5, the source of QM3, and the other end of R29 are all connected to the floating ground of the midpoint of the second bridge arm.

10. The driving circuit for suppressing bridge arm crosstalk according to claim 9, characterized in that: The third discharge clamp circuit includes a field effect transistor Q5, resistors R26, R27, a capacitor C6, and a Schottky diode D13; One end of R26 is connected to the cathode of D13 and the negative output pin of the secondary tube of TD2, and the other end is connected to the intersection of one end of R27, one end of C6, and the gate of Q5. R27 is connected in parallel with C6, and the anode of D13, the other end of R27, the other end of C6, and the source of Q5 are all connected to the floating ground at the midpoint of the second bridge arm. When the third switch tube QM3 is turned on, Q5 is turned off, and the base of Q7 is clamped at a high level, so that Q7 cannot be turned on. When the third switch tube QM3 is turned off, the negative output pin of the secondary tube of the second single-arm magnetic isolation high-frequency signal transmitter TD2 becomes a high level, Q5 is turned on, and the PNP transistor Q7 is turned on, which quickly drains the gate charge of the third switch tube QM3 and accelerates the shutdown of the third switch tube; at this time, the positive output pin of the secondary tube of TD2 becomes a low level, and the charge stored in the energy storage capacitor C5 cannot be released immediately, that is, one side of the voltage across C5 is 0V, and the other side is a negative voltage lower than 0V, and the amplitude of the negative voltage depends on the DZ3 voltage regulator value.

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