MOSFET structure and manufacturing method thereof

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a method for manufacturing the MOSFET structure. The structure comprises a substrate; the drift region is positioned on the upper surface of the substrate and consists of a single-layer or multi-layer epitaxial layer; the drift region is provided with a plurality of first groove structures located in the active region and a plurality of second groove structures located in the terminal region, and the side walls of the second groove structures are zigzag; the first bottom oxidation layer is located in the first groove structure, and the second bottom oxidation layer is located in the second groove structure; the first bottom oxide layer and the second bottom oxide layer are of groove structures, and the thickness of the first bottom oxide layer is smaller than that of the second bottom oxide layer. The zigzag side wall is formed when the second groove structure is etched, so that the thickness of the second bottom oxide layer can be increased while the first bottom oxide layer is not increased, the withstand voltage of the terminal structure is ensured, the very small primitive cell unit size and the lower on-resistance are obtained, and the source-drain breakdown voltage is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a separated gate trench MOSFET structure and a method for manufacturing the separated gate trench MOSFET structure. Background Art

[0002] Power metal oxide semiconductor field effect transistors (Power MOSFET) are widely used in low power supply systems due to their high input impedance, high switching speed, and low switching power consumption. Split Gate Trench MOSFET (SGT MOS) achieves high source-drain breakdown voltage while obtaining low drift region resistance by setting a charge compensation structure in the drift region.

[0003] In the prior art, an epitaxial process is usually used to form a drift region in the SGT MOS that bears a high source-drain voltage, so that the electric field distribution in the drift region between trenches and at the bottom of the trench is optimized, and high blocking voltage and low on-resistance can be achieved simultaneously.

[0004] However, the existing technology makes the terminal structure have the highest electric field strength in the outermost trench, which is also most prone to breakdown. In order to avoid the terminal structure from being broken down in the outermost trench and meet the breakdown voltage requirements, it is usually necessary to set a thicker trench bottom oxide layer and a wider terminal structure, which increases the size of the MOSFET unit cell, causing the chip on-resistance to increase or the chip area to increase, making it difficult to meet the requirements of low on-resistance or small chip area. Summary of the invention

[0005] The purpose of the present invention is to solve the technical problem that the existing SGT MOS terminal structure breaks down in the outermost trench too early, and a thicker trench bottom oxide layer and a wider terminal structure are set to meet the breakdown voltage requirement, so that the size of the MOSFET primitive unit cell is increased, which will cause the chip on-resistance to increase or the chip area to increase, making it difficult to meet the requirements of low on-resistance or small chip area, and to provide a MOSFET structure and a manufacturing method thereof.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is:

[0007] A MOSFET structure, which is special in that it includes:

[0008] substrate;

[0009] A drift region located on the upper surface of the substrate and composed of a single layer or multiple epitaxial layers; a plurality of first trench structures located in the active region and a plurality of second trench structures located in the terminal region are arranged on the drift region, and the sidewalls of the second trench structures are sawtooth-shaped;

[0010] A first bottom oxide layer located in the first trench structure, and a second bottom oxide layer located in the second trench structure; the first bottom oxide layer and the second bottom oxide layer are both groove structures, and the thickness of the first bottom oxide layer is less than the thickness of the second bottom oxide layer;

[0011] An active region original cell polycrystalline structure located in the first bottom oxide layer groove structure, and a terminal region original cell polycrystalline structure located in the second bottom oxide layer groove structure;

[0012] An intermediate oxide layer located on the active region primitive cell polycrystalline structure;

[0013] A gate oxide layer located on the sidewall of the first trench structure above the intermediate oxide layer;

[0014] A gate polycrystalline structure located on the upper portion of the intermediate oxide layer and on the surface of the gate oxide layer;

[0015] A shielding oxide layer located on the upper side of the drift region, the gate polycrystalline structure and the original cell polycrystalline structure of the terminal region;

[0016] a base region between the drift region and the shielding oxide layer;

[0017] A source region located outside the first trench structure and on the upper surface of the base region outside the outermost second trench structure;

[0018] a dielectric oxide layer located on the surface of the shielding oxide layer;

[0019] A source electrode and a gate electrode are located on the dielectric oxide layer; the source electrode passes through the source region and is connected to the corresponding base region;

[0020] a passivation structure located on the source electrode and the gate electrode;

[0021] A drain electrode is located on the lower surface of the substrate.

[0022] Furthermore, the sawtooth shape of the sidewall of the second trench structure is a trapezoid, a triangle, a sine wave or a rectangle.

[0023] Furthermore, the saw teeth of the sidewall of the second groove structure are arranged alternately on the top mesas and the bottom mesas at the same depth position.

[0024] Furthermore, the sawtooth shape of the sidewall of the second groove structure is a trapezoid, the top terrace width of the trapezoid is 0.1μm to 0.5μm, the height of the trapezoid is 0.3μm to 1.0μm, the bottom terrace width of the trapezoid is 0.05μm to 0.2μm, and the angle between the trapezoidal slope and the width direction of the second groove structure is 45° to 85°.

[0025] Furthermore, the depths of the first trench structure and the second trench structure are both 3mm to 7mm, and the widths are both 0.5mm to 2.0mm; the thickness of the first bottom oxide layer is 0.3mm to 0.9mm, and the thickness of the second bottom oxide layer is 0.4mm to 1.3mm; the thickness of the middle oxide layer is 0.3mm to 0.6mm; the thickness of the gate oxide layer is 0.04mm to 0.09mm; the thickness of the shielding oxide layer is 0.05mm to 0.1mm; and the thickness of the dielectric oxide layer is 1.0mm to 1.5mm.

[0026] Furthermore, the substrate is an N+ type silicon substrate; the drift region is an N- type drift region; the base region is a P base region; and the source region is an N+ type source region.

[0027] At the same time, the present invention also provides a method for manufacturing a MOSFET structure, which is special in that it includes the following steps:

[0028] Step 1, selecting a substrate, and depositing a single or multiple epitaxial layers on the upper surface of the substrate to form a drift region, and using photolithography and etching processes on the drift region to form a first trench structure in the active region, and a second trench structure with a sawtooth sidewall in the terminal region;

[0029] Step 2, forming a first bottom oxide layer and a second bottom oxide layer in the first trench structure and the second trench structure, respectively, and the thickness of the second bottom oxide layer is greater than the thickness of the first bottom oxide layer;

[0030] Step 3, forming an active region unit cell polycrystalline structure and a terminal region unit cell polycrystalline structure on the surfaces of the first bottom oxide layer and the second bottom oxide layer respectively;

[0031] Step 4, forming an intermediate oxide layer on the active area original cell polycrystalline structure;

[0032] Step 5, forming a gate oxide layer on the sidewall of the first trench structure; then forming a gate polycrystalline structure on the upper part of the intermediate oxide layer and on the surface of the gate oxide layer; finally forming a shielding oxide layer on the upper surface of the drift region, the gate polycrystalline structure and the original cell polycrystalline structure of the terminal region;

[0033] Step 6: forming a source region on the upper surface of the base region formed at the upper end of the drift region and located outside the first trench structure and outside the outermost second trench structure;

[0034] Step 7, depositing a dielectric oxide layer on the entire upper surface of the drift region, and then forming a source electrode and a gate electrode on the upper surface of the dielectric oxide layer; the source electrode passes through the source region and is connected to the corresponding base region;

[0035] Step 8: Form a passivation structure on the source electrode and the gate electrode; form a drain electrode on the lower surface of the substrate to complete the preparation of the separated gate trench MOSFET structure.

[0036] The beneficial effects of the present invention are:

[0037] 1. The present invention defines the photolithography pattern and forms a serrated sidewall when etching the second trench structure, thereby increasing the thickness of the second bottom oxide layer without increasing the second bottom oxide layer, thereby ensuring the voltage resistance of the terminal structure, obtaining a very small primitive cell size and lower on-resistance, and improving the source-drain breakdown voltage.

[0038] 2. When the present invention etches a groove on the drift region, a photolithography pattern is defined to form a second groove structure with a sawtooth sidewall during the groove etching. When the drift region of the etched groove is subjected to thermal oxidation, due to the special sawtooth structure of the groove sidewall, the gap between adjacent protruding parts of the sawtooth morphology is filled with SiO2 due to the expansion of the oxide layer during the thermal oxidation of silicon, and the bottom of the protruding part of the sawtooth morphology is completely oxidized due to the overlap of the oxide layer under the Si surface at the bottom of the sawtooth gap. After the oxide layer deposition process, the thickness of the second bottom oxide layer on the sidewall of the second groove structure in the terminal region is greater than the thickness of the first bottom oxide layer in the first groove structure in the active region, so that the outermost terminal groove structure can withstand a higher electric field strength and improve the source-drain breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a schematic diagram of the structural principle of step 1 in an embodiment of a method for manufacturing a MOSFET structure of the present invention;

[0040] Figure 2 This is a schematic diagram of the structural principle of step 2 in an embodiment of a method for manufacturing a MOSFET structure of the present invention;

[0041] Figure 3 This is a schematic diagram of the structural principle of step 3 in an embodiment of a method for manufacturing a MOSFET structure of the present invention;

[0042] Figure 4 This is a schematic diagram of the structural principle of step 4 in an embodiment of a method for manufacturing a MOSFET structure of the present invention;

[0043] Figure 5 This is a schematic diagram of the structural principle of step 5 in an embodiment of a method for manufacturing a MOSFET structure of the present invention;

[0044] Figure 6 It is a schematic diagram of the structural principle of step 6 in an embodiment of a method for manufacturing a MOSFET structure of the present invention;

[0045] Figure 7 Schematic diagram of the structure principle of step 7 in an embodiment of a method for manufacturing a MOSFET structure of the present invention;

[0046] Figure 8This is a schematic diagram of the structural principle of step 8 in an embodiment of a method for manufacturing a MOSFET structure of the present invention;

[0047] Fig. 9 It is a structural schematic diagram of a MOSFET structural embodiment of the present invention;

[0048] Fig.10 It is a schematic diagram of sawtooth sidewall etching in a MOSFET structure embodiment of the present invention;

[0049] Fig.11 It is a schematic diagram of a process for forming a first bottom oxide layer and a second bottom oxide layer in a MOSFET structure embodiment of the present invention;

[0050] In the figure: 1-substrate, 2-drift region, 31-first trench structure, 32-second trench structure, 41-first bottom oxide layer, 42-second bottom oxide layer, 5-active region original cell polycrystalline structure, 6-terminal region original cell polycrystalline structure, 7-intermediate oxide layer, 8-gate oxide layer, 9-gate polycrystalline structure, 10-shielding oxide layer, 11-base region, 12-source region, 13-source electrode, 14-gate electrode, 15-passivation structure, 16-drain electrode. DETAILED DESCRIPTION

[0051] In order to make the purpose, advantages and features of the present invention more clear, the following is a further detailed description of a MOSFET structure and a manufacturing method thereof proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will be more clear according to the following specific embodiments.

[0052] A method for manufacturing a MOSFET structure in this embodiment specifically includes the following steps:

[0053] Step 1] See Figure 1 , select an N+ type silicon substrate 1, and sequentially deposit a first N-type epitaxial layer, a second N-type epitaxial layer and a third N-type epitaxial layer on the N+ type silicon substrate 1 as an N-type drift region 2, and perform photolithography and etching processes on the N-type drift region 2 to form a trench structure with a depth of 3mm to 7mm and a width of 0.5mm to 2.0mm, wherein a first trench structure 31 with a conventional straight edge sidewall is formed in the active region by defining a photolithography pattern, and a second trench structure 32 with a sawtooth sidewall is formed in the terminal region.

[0054] Step 2] See Figure 2 A first bottom oxide layer 41 with a thickness of 0.3 mm to 0.9 mm and a second bottom oxide layer 42 with a thickness of 0.4 mm to 1.3 mm are formed in the first trench structure 31 and the second trench structure 32 through thermal growth and deposition processes respectively, and the thickness of the second bottom oxide layer 42 is greater than the thickness of the first bottom oxide layer 41.

[0055] Step 3] See Figure 3 , polysilicon is deposited on the surface of the wafer where the first bottom oxide layer 41 and the second bottom oxide layer 42 are formed to fill the trench structure, and the polysilicon in the first trench structure 31 is subjected to photolithography and etching processes to form an active area unit cell polycrystalline structure 5 and a terminal area unit cell polycrystalline structure 6 respectively; and the upper surface of the active area unit cell polycrystalline structure 5 is lower than the upper surface of the first bottom oxide layer 41.

[0056] Step 4] See Figure 4 , the first trench structure 31 is filled again by an oxide layer deposition process, the excess oxide layer on the silicon surface is removed, and the deposited oxide layer in the first trench structure 31 is subjected to photolithography and etching processes to form an intermediate oxide layer 7 with a thickness of 0.3 mm to 0.6 mm on the active area original cell polycrystalline structure 5, and the upper surface of the intermediate oxide layer 7 is lower than the upper surface of the drift region 2.

[0057] Step 5] See Figure 5 , a dry oxygen oxidation process is used to thermally grow an oxide layer on the side wall of the first trench structure 31 to form a gate oxide layer 8 with a thickness of 0.04mm to 0.09mm; then the first trench structure 31 is filled with a polysilicon deposition process to form a gate polycrystalline structure 9 on the upper part of the intermediate oxide layer 7 and on the surface of the gate oxide layer 8; dry oxygen oxidation is performed again to form a shielding oxide layer 10 with a thickness of 0.05mm to 0.1mm on the top of the gate polycrystalline structure 9.

[0058] Step 6] See Figure 6 , the silicon surface is globally implanted with an implantation energy of 60KeV to 150KeV and an implantation dose of 0.6E13 to 1.5E13 to form a P base region 11 located at the upper end of the drift region. After the ion implantation of the P base region 11 is completed, the base region is annealed at a temperature of 1000°C to 1150°C for 30min to 120min. Arsenic ions are implanted into the upper surface of the outer base region 11 of the outer side of the first trench structure 31 and the outermost second trench structure 32. After the arsenic ion implantation, annealing is performed at a temperature of 950°C to 1000°C for 90min to 120min to form an N+ type source region 12.

[0059] Step 7] See Figure 7, a dielectric oxide layer with a thickness of 1.0 mm to 1.5 mm is deposited on the wafer forming the N+ type source region 12, and then a metal electrode contact hole is formed on the dielectric oxide layer by a photolithography process; a BF2 injection process is performed in the source electrode contact region through the metal electrode contact hole, and annealing is performed after the injection, wherein the injection energy is 60 KeV to 80 KeV, the injection dose is 3E14 to 5E14, the annealing temperature is 900° C. to 1000° C., and the annealing time is 20 min to 30 min; and then an AlSiCu metal layer with a thickness of 4 μm to 6 μm is deposited on the upper surface of the dielectric oxide layer wafer forming the electrode contact hole, and a source electrode 13 and a gate electrode 14 are formed by performing a photolithography and etching process on the AlSiCu metal layer, wherein the source electrode 13 passes through the source region 12 and is connected to the corresponding base region 11.

[0060] Step 8] See Figure 8 , deposit a passivation layer on the source electrode 13 and the gate electrode 14, and form a passivation structure 15 by photolithography and etching processes; evaporate a Ti / Ni / Ag metal layer on the lower surface of the silicon substrate 1 to form a drain electrode 16, and then manufacture a device such as Fig. 9 The split-gate trench MOSFET structure shown.

[0061] In this embodiment, when the first trench structure 31 and the second trench structure 32 are photolithographically processed and etched, the sidewall of the second trench structure 32 is formed by defining the photolithographic pattern characteristics. Fig.10 The serrated groove structure shown:

[0062] Fig.10 In the figure, A, B, and G are points selected in the groove, and A', B', and G' are corresponding points after A, B, and G are cut along the length direction of the groove.

[0063] First, when the sawtooth shape of the sidewall of the second trench structure is a trapezoid, the width of the terrace D / E (D' / E') at the top (large end) of the trapezoid is 0.1 μm to 0.5 μm, and the height h of the trapezoid is T The width of the terrace C / F (C' / F') at the bottom (small end) of the trapezoid is 0.3 μm to 1.0 μm, the width of the terrace C / F (C' / F') at the bottom (small end) of the trapezoid is 0.05 μm to 0.2 μm, and the angle θ between the trapezoidal slope and the width direction of the second groove structure is 45° to 85°.

[0064] Second, the trapezoidal top terrace D / E (D' / E') and the bottom terrace C / F (C' / F') are alternately arranged on the side walls of the second groove structure 32 at the same depth position. Fig.10At position HH' of the second trench structure 32, the left sidewall is a trapezoidal top terrace D / E (D' / E') or a trapezoidal bottom terrace C / F (C' / F'), and the corresponding right sidewall is a trapezoidal bottom terrace C / F (C' / F') or a trapezoidal top terrace D / E (D' / E'); the trapezoidal top terrace D / E (D' / E') and the trapezoidal bottom terrace C / F (C' / F') are staggered on both sides of the sidewalls at the same depth position of the second trench structure 32, so that the source polysilicon filled in the second trench structure 32 and the second trench structure 32 have the same spacing width, thereby obtaining a terminal structure with consistent structural dimensions and ensuring the breakdown voltage of the device terminal.

[0065] Third, due to the presence of the sawtooth sidewalls in the second trench structure 32, the gaps between adjacent sawtooth protruding parts are filled with SiO2 due to the expansion of the oxide layer during the thermal oxidation of silicon. Fig.11 The area shown in Ⅰ in the middle; the bottom of the protruding part of the sawtooth morphology is completely oxidized due to the overlap of the oxide layer under the Si surface at the bottom of the sawtooth gap, as shown in Fig.11 After the oxide layer deposition process, the thickness T2 of the second bottom oxide layer 42 on the sidewall of the second trench structure 32 is greater than the thickness T1 of the first bottom oxide layer 41 on the first trench structure 31 without the sawtooth sidewall.

[0066] It should be noted that the trapezoidal sawtooth shape of the second groove side wall is only a specific embodiment of the present invention. In other embodiments of the present invention, the tooth shape can also be processed into a triangle, a sine wave, or a rectangle to achieve the same purpose of the invention.

Claims

1. A MOSFET structure, characterized in that: include: Substrate (1); A drift region (2) located on the upper surface of a substrate (1) and composed of a single layer or multiple layers of epitaxial layers; a plurality of first trench structures (31) located in an active region and a plurality of second trench structures (32) located in a terminal region are arranged on the drift region (2); the side walls of the second trench structures (32) are sawtooth-shaped; A first bottom oxide layer (41) located in the first trench structure (31), and a second bottom oxide layer (42) located in the second trench structure (32); the first bottom oxide layer (41) and the second bottom oxide layer (42) are both groove structures, and the thickness of the first bottom oxide layer (41) is less than the thickness of the second bottom oxide layer (42); An active region original cell polycrystalline structure (5) located in a groove structure of a first bottom oxide layer (41), and a terminal region original cell polycrystalline structure (6) located in a groove structure of a second bottom oxide layer (42); An intermediate oxide layer (7) located on the active region unit cell polycrystalline structure (5); A gate oxide layer (8) located on the side wall of the first trench structure (31) above the intermediate oxide layer (7); A gate polycrystalline structure (9) located on the upper part of the intermediate oxide layer (7) and on the surface of the gate oxide layer (8); A shielding oxide layer (10) located on the upper side of the drift region (2), the gate polycrystalline structure (9) and the terminal region original cell polycrystalline structure (6); A base region (11) located between the drift region (2) and the shielding oxide layer (10); A source region (12) located outside the first trench structure (31) and on the upper surface of the base region (11) outside the outermost second trench structure (32); A dielectric oxide layer located on the surface of the shielding oxide layer (10); A source electrode (13) and a gate electrode (14) are located on the dielectric oxide layer; the source electrode (13) passes through the source region (12) and is connected to the corresponding base region (11); a passivation structure (15) located on the source electrode (13) and the gate electrode (14); A drain electrode (16) is located on the lower surface of the substrate (1).

2. A MOSFET structure according to claim 1, characterized in that: The sawtooth shape of the side wall of the second groove structure (32) is a trapezoid, a triangle, a sine wave or a rectangle.

3. A MOSFET structure according to claim 1 or 2, characterized in that: The saw teeth of the side wall of the second groove structure (32) are arranged alternately on the top mesas and the bottom mesas at the same depth.

4. A MOSFET structure according to claim 3, characterized in that: The sawtooth shape of the side wall of the second groove structure (32) is a trapezoid, the width of the top terrace of the trapezoid is 0.1 μm to 0.5 μm, the height of the trapezoid is 0.3 μm to 1.0 μm, the width of the bottom terrace of the trapezoid is 0.05 μm to 0.2 μm, and the angle between the trapezoidal slope and the width direction of the second groove structure (32) is 45° to 85°.

5. A MOSFET structure according to claim 4, characterized in that: The first groove structure (31) and the second groove structure (32) both have a depth of 3 mm to 7 mm and a width of 0.5 mm to 2.0 mm; The thickness of the first bottom oxide layer (41) is 0.3 mm to 0.9 mm, and the thickness of the second bottom oxide layer (42) is 0.4 mm to 1.3 mm; The thickness of the intermediate oxide layer (7) is 0.3 mm to 0.6 mm; The thickness of the gate oxide layer (8) is 0.04 mm to 0.09 mm; The thickness of the shielding oxide layer (10) is 0.05 mm to 0.1 mm; The thickness of the dielectric oxide layer is 1.0 mm to 1.5 mm.

6. A MOSFET structure according to claim 5, characterized in that: The substrate (1) is an N+ type silicon substrate; The drift region (2) is an N-type drift region; The base region (11) is a P base region; The source region (12) is an N+ type source region.

7. A method for manufacturing a MOSFET structure according to any one of claims 1 to 6, characterized in that: The following steps are involved: Step 1, selecting a substrate (1), and depositing a single layer or multiple layers of epitaxial layers on the upper surface of the substrate (1) to form a drift region (2), and using photolithography and etching processes to form a first trench structure (31) in the active region, and forming a second trench structure (32) with a sawtooth sidewall in the terminal region; Step 2, forming a first bottom oxide layer (41) and a second bottom oxide layer (42) in the first trench structure (31) and the second trench structure (32), respectively, and the thickness of the second bottom oxide layer (42) is greater than the thickness of the first bottom oxide layer (41); Step 3, forming an active region unit cell polycrystalline structure (5) and a terminal region unit cell polycrystalline structure (6) on the surfaces of the first bottom oxide layer (41) and the second bottom oxide layer (42), respectively; Step 4, forming an intermediate oxide layer (7) on the active region original cell polycrystalline structure (5); Step 5, forming a gate oxide layer (8) on the side wall of the first trench structure (31); then forming a gate polycrystalline structure (9) on the upper part of the intermediate oxide layer (7) and on the surface of the gate oxide layer (8); finally forming a shielding oxide layer (10) on the upper surface of the drift region (2), the gate polycrystalline structure (9) and the terminal region original cell polycrystalline structure (6); Step 6: forming a source region (12) on the upper surface of the base region (11) formed at the upper end of the drift region (2) and located outside the first trench structure (31) and outside the outermost second trench structure (32); Step 7, depositing a dielectric oxide layer on the entire upper surface of the drift region (2), and then forming a source electrode (13) and a gate electrode (14) on the upper surface of the dielectric oxide layer; the source electrode (13) passes through the source region (12) and is connected to the corresponding base region (11); Step 8: forming a passivation structure (15) on the source electrode (13) and the gate electrode (14); forming a drain electrode (16) on the lower surface of the substrate (1), thereby completing the preparation of the split-gate trench MOSFET structure.

8. The method for manufacturing a MOSFET structure according to claim 7, characterized in that: The sawtooth shape of the side wall of the second groove structure (32) is a trapezoid, a triangle, a sine wave or a rectangle.

9. A method for manufacturing a MOSFET structure according to claim 7 or 8, characterized in that: The saw teeth of the side wall of the second groove structure (32) are arranged alternately on the top mesas and the bottom mesas at the same depth.

10. The method for manufacturing a MOSFET structure according to claim 9, characterized in that: The sawtooth shape of the side wall of the second groove structure (32) is a trapezoid, the width of the top terrace of the trapezoid is 0.1 μm to 0.5 μm, the height of the trapezoid is 0.3 μm to 1.0 μm, the width of the bottom terrace of the trapezoid is 0.05 μm to 0.2 μm, and the angle between the trapezoidal slope and the width direction of the second groove structure (32) is 45° to 85°; In step 1, the first groove structure (31) and the second groove structure (32) have a depth of 3 mm to 7 mm and a width of 0.5 mm to 2.0 mm; In step 2, the thickness of the first bottom oxide layer (41) is 0.3 mm to 0.9 mm, and the thickness of the second bottom oxide layer (42) is 0.4 mm to 1.3 mm; In step 4, the thickness of the intermediate oxide layer (7) is 0.3 mm to 0.6 mm; In step 5, the thickness of the gate oxide layer (8) is 0.04 mm to 0.09 mm; The thickness of the shielding oxide layer (10) is 0.05 mm to 0.1 mm; In step 7, the thickness of the dielectric oxide layer is 1.0 mm to 1.5 mm.

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