Shield gate trench MOSFET device structure and manufacturing method thereof

Abstract

The invention relates to a shield gate trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device structure and a manufacturing method thereof. The structure comprises a substrate and an epitaxial layer, the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer which are sequentially grown on the substrate; at least one MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device unit is arranged in the epitaxial layer; the MOSFET device unit comprises two groups of first grooves and a second groove positioned between the two groups of first grooves; a shield gate structure is arranged in the first groove, and an active polycrystalline silicon structure grows in the second groove; body regions are doped on the two sides of the first groove and between the first groove and the second groove. Under the requirement of the same breakdown voltage, the doping concentration of the second epitaxial layer can be increased, so that the resistivity is reduced, the on-resistance Ron is reduced, and the power loss of the MOSFET device can be reduced.

Description

Technical Field

[0001] The invention relates to an integrated circuit, and in particular to a shielded gate trench MOSFET device structure and a manufacturing method. Background Art

[0002] Shielded Gate Trench MOSFET (SGT-MOSFET) is an advanced discrete device MOSFET structure with high breakdown voltage, low on-resistance and fast switching speed. The structure of shielded gate trench MOSFET is generally that the polysilicon filled in the trench is divided into two parts: the polysilicon located in the lower part of the trench forms the shielded gate polysilicon, which is short-circuited with the source of the device; the polysilicon located in the upper part of the trench constitutes the polysilicon gate, and the two layers of polysilicon are separated by a silicon oxide film layer.

[0003] With the development of technology, shielded gate trench MOSFET requires a larger current density, that is, a smaller internal resistance per unit area, which can also reduce the power loss of MOSFET. Generally speaking, this can be achieved by increasing the doping concentration of the epitaxial layer. However, if the doping concentration is simply increased, the breakdown voltage of the MOSFET cannot be maintained and the breakdown voltage will decrease. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention discloses a shielded gate trench MOSFET device structure and a manufacturing method.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A shielded gate trench MOSFET device structure comprises a substrate and an epitaxial layer; the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer sequentially grown on the substrate; at least one MOSFET device unit is arranged in the epitaxial layer;

[0007] The MOSFET device unit includes two groups of first trenches and a second trench located between the two groups of the first trenches; a shielding gate structure is arranged in the first trench, and an active polysilicon structure is grown in the second trench; both sides of the first trench and between the first trench and the second trench are doped into a body region.

[0008] Its further technical features are that the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; and the doping type of the second epitaxial layer and the first epitaxial layer is the same.

[0009] Its further technical feature is that, in a MOSFET device unit, the distance between two of the first trenches is 0.6 μm to 1.0 μm, and the distance between the first trench and the second trench is 0.2 to 0.4 μm.

[0010] Its further technical features are that the shielding gate structure includes gate polysilicon and source polysilicon; a field oxide layer is formed between the source polysilicon and the inner wall of the first trench, and a gate oxide layer is formed between the gate polysilicon and the inner wall of the first trench; an IPO oxide layer is formed between the source polysilicon and the gate polysilicon; the source polysilicon structure includes the source polysilicon in the trench and the field oxide layer between the source polysilicon and the inner wall of the second trench.

[0011] Its further technical feature is that the MOSFET device unit also includes a source region formed on the body region on both sides of the first trench; the source region is electrically connected to the source polysilicon.

[0012] A method for manufacturing a shielded gate trench MOSFET device structure comprises the following steps:

[0013] Growing an epitaxial layer on a substrate; the epitaxial layer includes a first epitaxial layer grown on the substrate and a second epitaxial layer grown on the basis of the first epitaxial layer;

[0014] Forming trenches on the epitaxial layer, the trenches comprising two groups of first trenches and a second trench located between the two groups of first trenches; and forming a dielectric layer as a field oxide layer at the bottom and sidewalls of the trenches;

[0015] A shielding gate structure is formed in the first trench, and a source polysilicon structure is formed in the second trench; and body regions are doped on both sides of the first trench and between the first trench and the second trench, and active regions are doped on the body regions on both sides of the first trench.

[0016] Its further technical features are that the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; and the doping type of the second epitaxial layer and the first epitaxial layer is the same.

[0017] Its further technical feature is that the body region is formed on both sides of the first trench and between the first trench and the second trench.

[0018] Its further technical feature is that the steps of forming the shield gate structure and the source polysilicon structure specifically include:

[0019] backfilling the trench; depositing source polysilicon in the trench and backfilling the trench, thereby forming a source polysilicon structure in the second trench;

[0020] Etching the source polysilicon; etching the target thickness of the source polysilicon in the first trench by photolithography and etching, wherein the thickness of the etched source polysilicon is less than the depth of the first trench;

[0021] Depositing a dielectric layer; depositing a dielectric layer in the first trench, backfilling the first trench, and then performing photolithography and etching to etch away the dielectric layer of a target thickness to form an IPO oxide layer;

[0022] A gate oxide layer and gate polysilicon are grown; a gate oxide layer is grown in the first trench, gate polysilicon is deposited, and the first trench is backfilled, thereby forming a shielding gate structure in the first trench.

[0023] Its further technical feature is that it also includes the steps of forming contact holes and depositing metal: depositing a contact hole dielectric layer of target thickness, followed by photolithography and etching to form contact holes, and depositing contact hole metal; then depositing source metal.

[0024] The beneficial effects of the present invention are as follows:

[0025] The MOSFET device unit of the present invention is made in the second epitaxial layer, a second trench is arranged between two groups of first trenches, and a body region is doped between the first trench and the second trench. Compared with the prior art, after the second trench is arranged and the body region is diffused to fill the space between the first trench and the second trench, it is equivalent to reducing the distance between the two first trenches in the prior art. Under the requirement of the same breakdown voltage, the doping concentration of the second epitaxial layer can be increased, so that the resistivity becomes lower, the on-resistance Ron is reduced, and the power loss of the MOSFET device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 4 is a schematic diagram of a step of forming a groove in an embodiment of the present invention.

[0027] Figure 2 Schematic diagram of the step of backfilling the trench in an embodiment of the present invention.

[0028] Figure 3 Schematic diagram of the step of etching source polysilicon in an embodiment of the present invention.

[0029] Figure 4 Schematic diagram of the step of depositing a dielectric layer in an embodiment of the present invention.

[0030] Figure 5 Schematic diagram of the steps of growing a gate oxide layer and gate polysilicon in an embodiment of the present invention.

[0031] Figure 6 Schematic diagram of the steps of forming body regions and source regions in an embodiment of the present invention.

[0032] Figure 7 FIG. 4 is a schematic diagram of a step of forming a contact hole in an embodiment of the present invention.

[0033] Figure 8 Schematic diagram of the metal deposition step in an embodiment of the present invention.

[0034] In the figure: 100, substrate; 101, first epitaxial layer; 102, second epitaxial layer; 103, trench; 104, dielectric layer; 105, source polysilicon; 106, gate polysilicon; 107, body region; 108, source region; 109, contact hole metal; 110, source metal. DETAILED DESCRIPTION

[0035] The specific implementation of the present invention will be described below in conjunction with the accompanying drawings.

[0036] Figure 8 is a schematic diagram of a metal deposition step in an embodiment of the present invention, and at the same time, Figure 8 It also comprehensively shows the shielded gate trench MOSFET device structure in this embodiment. Figure 8 As shown, the shielded gate trench MOSFET device structure includes a substrate 100 and an epitaxial layer grown on the substrate 100. The epitaxial layer includes a first epitaxial layer 101 and a second epitaxial layer 102 grown on the substrate 100 in sequence.

[0037] At least one MOSFET device unit is arranged in the epitaxial layer 102. The MOSFET device unit includes a groove 103. Generally, the MOSFET device unit is mainly grown in the second epitaxial layer 102, and the thickness of the second epitaxial layer 102 is slightly smaller than the depth of the groove 103 of the MOSFET device unit. The groove 103 includes two groups of first grooves and a second groove located between the two groups of first grooves.

[0038] A shielding gate structure is provided in the first trench. Specifically, the shielding gate structure includes gate polysilicon 106 and source polysilicon 105. A field oxide layer is formed between the source polysilicon 105 and the inner wall of the first trench, a gate oxide layer is formed between the gate polysilicon 106 and the inner wall of the first trench, and an IPO oxide layer is formed between the source polysilicon 105 and the gate polysilicon 106.

[0039] An active polysilicon structure is grown in the second trench. Specifically, the source polysilicon structure includes a source polysilicon 105 in the second trench and a field oxide layer between the source polysilicon 105 and an inner wall of the second trench.

[0040] Both sides of the first trench and between the first trench and the second trench are doped into body regions 107, and active regions 108 are grown on the body regions 107 on both sides of the first trench. The source region 108 serves as the source of the device and is short-circuited with the source metal 110 through the contact hole metal 109. The source region 108 is also short-circuited with the source polysilicon 105 inside the MOSFET device.

[0041] The doping concentration of the second epitaxial layer 102 is greater than that of the first epitaxial layer 101. The second epitaxial layer 102 and the first epitaxial layer 101 have the same doping type. The specific doping concentration and doping type can be determined by those skilled in the art according to the functional parameters and models of the device. For example, for a device with a maximum operating voltage of 30V, the doping concentration of the first epitaxial layer 101 can be 7×10 15 atoms / cm 3 , the doping concentration of the second epitaxial layer 102 may be 8×10 15 atoms / cm 3 , the first epitaxial layer 101 and the second epitaxial layer 102 are both N-type.

[0042] Preferably, the distance between the two first grooves is 0.55 μm to 0.65 μm, for example, 0.6 μm, and the distance between the first groove and the second groove is 0.15 μm to 0.25 μm, for example, 0.2 μm.

[0043] Compared with the prior art, such a MOSFET device structure is equivalent to reducing the distance between the two first trenches in the prior design. Under the same breakdown voltage requirement, the doping concentration of the second epitaxial layer can be increased, thereby lowering the resistivity and reducing the on-resistance Ron, thereby reducing the power loss of the MOSFET device.

[0044] This embodiment also discloses a method for manufacturing the shielded gate trench MOSFET device structure described above. The MOSFET device structure includes at least one MOSFET device unit. The steps for manufacturing a MOSFET device unit are shown below, specifically including:

[0045] Step 1: Forming a groove. Figure 1 FIG. 1 is a schematic diagram of a step of forming a groove in an embodiment of the present invention. Figure 1 As shown, an epitaxial layer is grown on a substrate 100. Specifically, a first epitaxial layer 101 with a target thickness and a target doping concentration is formed on the substrate 100, and a second epitaxial layer 102 with a target thickness and a target doping concentration is formed on the basis of the first epitaxial layer 101. The doping concentration of the second epitaxial layer 102 is greater than that of the first epitaxial layer 101. The second epitaxial layer 102 and the first epitaxial layer 101 have the same doping type.

[0046] The grooves 103 are formed by a first photolithography, etching and other processes. The grooves 103 include two groups of first grooves and a second groove located between the two groups of first grooves.

[0047] A dielectric layer 104 of a target thickness is formed on the bottom and sidewalls of the trench 103 by, but not limited to, thermal oxidation, CVD deposition, etc., as a field oxide layer.

[0048] The target thickness and target doping concentration in this step and subsequent steps are determined according to the device model and functional parameters, and can be specifically adjusted by those skilled in the art according to known techniques.

[0049] Step 2: Backfill the trench. Figure 2 FIG. 1 is a schematic diagram of the step of backfilling the trench in an embodiment of the present invention. Figure 2 As shown, source polysilicon 105 is deposited in the trench 103, the trench 103 is backfilled, and the surface of the trench 103 is planarized by CMP. At this time, a source polysilicon structure is formed in the second trench.

[0050] Step 3: Etching the source polysilicon. Figure 3 FIG. 1 is a schematic diagram of the step of etching source polysilicon in an embodiment of the present invention. Figure 3 As shown, through the second photolithography and etching, the target thickness of the source polysilicon 105 is etched away in the first trench, and the thickness of the etched source polysilicon 105 is smaller than the depth of the first trench.

[0051] Step 4: Deposit a dielectric layer. Figure 4 Schematic diagram of the step of depositing a dielectric layer in an embodiment of the present invention. A silicon oxide dielectric layer of target thickness is deposited in the first trench, the first trench is backfilled, and the silicon surface is planarized by CMP, and then a third photolithography and etching are performed to etch away the dielectric layer of target thickness as an IPO oxide layer, so that the final Figure 4 shown.

[0052] Step 5: growing a gate oxide layer and gate polysilicon. Figure 5 FIG. 1 is a schematic diagram of the steps of growing a gate oxide layer and gate polysilicon in an embodiment of the present invention. Figure 5 As shown, after cleaning, a gate oxide layer of target thickness is grown in the first trench, and gate polysilicon 106 of target thickness is deposited, the first trench is backfilled, and the surface is planarized by CMP, at which time a shielding gate structure is formed in the first trench.

[0053] Step 6: Form body region and source region. Figure 6 FIG. 1 is a schematic diagram of the steps of forming the body region and the source region in an embodiment of the present invention. Figure 6 As shown, impurities are injected, annealed, and a body region 107 is formed. Then, after a fourth photolithography process, impurities are injected to form a device source region 108. Specifically, the body region 107 is formed on both sides of the first trench and between the first trench and the second trench. In this embodiment, the body region 107 is injected with P-type impurities, and the source region 108 is injected with N-type impurities. The source region 108 is electrically connected to the source polysilicon 105.

[0054] Step 7: forming contact holes. Figure 7 FIG. 1 is a schematic diagram of the step of forming a contact hole in an embodiment of the present invention. Figure 7As shown, a contact hole dielectric layer of target thickness is deposited, followed by a fifth photolithography process, etching to form a contact hole, and depositing a contact hole metal 109.

[0055] Step 8: Deposit metal. Figure 8 Schematic diagram of the metal deposition step in an embodiment of the present invention. Figure 8 As shown, a source metal 110 is deposited. A contact metal 109 electrically connects the source region 108 to the source metal 110 .

[0056] Then, the sixth photolithography process is performed to perform metal etching and deposit a protective dielectric layer. The seventh photolithography process is performed to etch the protective dielectric layer to form a MOSFET device protection layer.

[0057] Through the above MOSFET manufacturing process, a Figure 8 The MOSFET device structure shown in FIG. 1 is shown in FIG. 1 . Under the same breakdown voltage requirement, the on-resistance Ron of the device is reduced, thereby reducing the power loss of the MOSFET device.

[0058] In this embodiment, the specific process parameters of steps 1 to 8 are adjusted and selected by technicians in this field based on general process knowledge and device parameter requirements of integrated circuits. The specific process parameters are not the content to be protected by this application and will not be repeated in this article.

[0059] The above description is an explanation of the present invention, not a limitation of the present invention. The scope of the present invention is defined in the claims. The present invention may be modified in any form without violating the basic structure of the present invention.

Claims

1. A shielded gate trench MOSFET device structure, characterized in that: It comprises a substrate and an epitaxial layer; the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer sequentially grown on the substrate; at least one MOSFET device unit is arranged in the epitaxial layer; The MOSFET device unit includes two groups of first trenches and a second trench located between the two groups of the first trenches; a shielding gate structure is arranged in the first trench, and an active polysilicon structure is grown in the second trench; both sides of the first trench and between the first trench and the second trench are doped into a body region.

2. The shielded gate trench MOSFET device structure according to claim 1, characterized in that: The doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; and the second epitaxial layer and the first epitaxial layer have the same doping type.

3. The shielded gate trench MOSFET device structure according to claim 1, characterized in that: In a MOSFET device unit, the distance between two of the first trenches is 0.6 μm to 1.0 μm, and the distance between the first trench and the second trench is 0.2 to 0.4 μm.

4. The shielded gate trench MOSFET device structure according to claim 1, characterized in that: The shielding gate structure includes gate polysilicon and source polysilicon; a field oxide layer is formed between the source polysilicon and the inner wall of the first trench, and a gate oxide layer is formed between the gate polysilicon and the inner wall of the first trench; an IPO oxide layer is formed between the source polysilicon and the gate polysilicon; the source polysilicon structure includes the source polysilicon in the trench and the field oxide layer between the source polysilicon and the inner wall of the second trench.

5. The shielded gate trench MOSFET device structure according to claim 1, characterized in that: The MOSFET device unit further includes a source region formed on the body region at both sides of the first trench; the source region is electrically connected to the source polysilicon.

6. A method for manufacturing a shielded gate trench MOSFET device structure, characterized in that: The following steps are involved: Growing an epitaxial layer on a substrate; the epitaxial layer includes a first epitaxial layer grown on the substrate and a second epitaxial layer grown on the basis of the first epitaxial layer; Forming trenches on the epitaxial layer, the trenches comprising two groups of first trenches and a second trench located between the two groups of first trenches; and forming a dielectric layer as a field oxide layer at the bottom and sidewalls of the trench; A shielding gate structure is formed in the first trench, and a source polysilicon structure is formed in the second trench; and body regions are doped on both sides of the first trench and between the first trench and the second trench, and active regions are doped on the body regions on both sides of the first trench.

7. The method for manufacturing a shielded gate trench MOSFET device structure according to claim 6, characterized in that: The doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; and the second epitaxial layer and the first epitaxial layer have the same doping type.

8. The method for manufacturing a shielded gate trench MOSFET device structure according to claim 6, characterized in that: The body region is formed on both sides of the first trench and between the first trench and the second trench.

9. The method for manufacturing a shielded gate trench MOSFET device structure according to claim 6, characterized in that: The steps of forming the shield gate structure and the source polysilicon structure specifically include: backfilling the trench; depositing source polysilicon in the trench and backfilling the trench, thereby forming a source polysilicon structure in the second trench; Etching the source polysilicon; etching the target thickness of the source polysilicon in the first trench by photolithography and etching, wherein the thickness of the etched source polysilicon is less than the depth of the first trench; Depositing a dielectric layer; depositing a dielectric layer in the first trench, backfilling the first trench, and then performing photolithography and etching to etch away the dielectric layer of a target thickness to form an IPO oxide layer; A gate oxide layer and gate polysilicon are grown; a gate oxide layer is grown in the first trench, gate polysilicon is deposited, and the first trench is backfilled, thereby forming a shielding gate structure in the first trench.

10. The method for manufacturing a shielded gate trench MOSFET device structure according to claim 6, characterized in that: The method also includes the steps of forming contact holes and depositing metal: depositing a contact hole dielectric layer of target thickness, then performing photolithography and etching to form contact holes, and depositing contact hole metal; and then depositing source metal.

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