Preparation method of gate structure and pHEMT device
By forming a trapezoidal trench and a T-shaped window structure during the gate production of the pHEMT device, combined with the protection of the dielectric layer, the problems of metal debris fall and photoresistance in the prior art are solved, and the performance and reliability of the device are improved.
Patent Information
- Application Number
- CN202411950211.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-03-04
AI Technical Summary
During the gate production process, existing pHEMT devices are easily affected by metal debris drop, metal peeling and photoresist residue caused by unstable photoresist morphology, resulting in larger leakage of the device and reduced breakdown voltage.
A first photoresist layer with a first opening is formed on the substrate, and a trapezoidal groove is formed along the first opening. Then, a first metal layer and a dielectric layer are formed, which covers part of the bottom wall of the trapezoidal trench and the dielectric layer covers the area not covered by the metal layer. Next, a second photoresist layer is formed to form a T-shaped window, and a second metal layer is formed in the window, and the second metal layer and the first metal layer together form a gate structure.
The exposed substrate is protected by depositing a dielectric layer, avoiding oxidation on the substrate surface and metal debris fall, reducing damage to the etching groove by the subsequent cleaning process, reducing power loss and improving device performance.
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Figure CN119562579A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a gate structure and a pHEMT device. Background Art
[0002] Pseudo-matched high electron mobility transistor (pHEMT) is a technology widely used in the design and manufacture of monolithic microwave integrated circuits. It is favored for its excellent broadband performance characteristics, including low noise figure and high output third-order intermodulation (OIP3) and excellent reliability. These characteristics make pHEMT the first choice for electronics manufacturers to produce many monolithic microwave integrated circuits (MMIC) building blocks, in which the pHEMT gate fabrication plays a crucial role.
[0003] In the existing process of forming the pHEMT gate, the etching groove is easily affected by the falling of metal debris caused by unstable photoresist morphology, the falling of metal debris during metal stripping, or the residual photoresist, which leads to increased device leakage and reduced breakdown voltage. Summary of the invention
[0004] The object of the present invention is to provide a method for preparing a gate structure and a pHEMT device to solve one or more problems existing in the prior art.
[0005] In order to solve the above problems, the present invention provides a method for preparing a gate structure, comprising:
[0006] Forming a first photoresist layer on a substrate, and patterning the first photoresist layer so that the first photoresist layer has a first opening;
[0007] Etching the substrate along the first opening to form a trapezoidal groove, wherein the bottom width of the trapezoidal groove is greater than the width of the first opening;
[0008] forming a first metal layer and a dielectric layer, wherein the first metal layer covers a portion of the bottom wall of the trapezoidal groove directly below the first opening, and the dielectric layer covers the area of the trapezoidal groove not covered by the first metal layer and the sidewall of the first opening; forming a second photoresist layer, and patterning the second photoresist layer so that the second photoresist layer has a second opening, the second photoresist layer is located on the first photoresist layer, and the second opening is connected to the first opening to form a T-shaped window; and,
[0009] A second metal layer is formed in the T-shaped window, and the second metal layer and the first metal layer together constitute the gate structure.
[0010] Optionally, in the method for preparing the gate structure, the first metal layer is formed first and then the dielectric layer is formed, and the step of forming the dielectric layer includes:
[0011] forming an initial dielectric layer, the initial dielectric layer covering the first metal layer and extending to cover the surface exposed by the trapezoidal groove; and,
[0012] The initial dielectric layer on the surface of the first metal layer is removed by etching, and the portion of the initial dielectric layer that is not removed by etching constitutes the dielectric layer.
[0013] Optionally, in the method for preparing the gate structure, an anisotropic etching process is used to etch away the initial dielectric layer.
[0014] Optionally, in the method for preparing the gate structure, the first metal layer is formed by a metal evaporation process.
[0015] Optionally, in the method for preparing the gate structure, the first metal layer also covers the surface of the first photoresist layer;
[0016] After forming the gate structure, the preparation method further includes:
[0017] removing the second photoresist layer;
[0018] removing the first metal layer on the surface of the first photoresist layer; and,
[0019] The first photoresist layer is removed.
[0020] Optionally, in the method for preparing the gate structure, the second metal layer is formed by a metal evaporation process.
[0021] Optionally, in the method for preparing the gate structure, the second opening is in a trapezoidal shape.
[0022] Optionally, in the method for preparing the gate structure, the material of the dielectric layer includes silicon nitride.
[0023] Optionally, in the method for preparing the gate structure, the substrate is etched using a wet etching process to form the trapezoidal trench.
[0024] The present invention also provides a pHEMT device, comprising:
[0025] The gate structure is prepared using the preparation method as described in any of the preceding items.
[0026] In summary, the preparation method of the gate structure and the pHEMT device provided by the present invention include: forming a first photoresist layer with a first opening on a substrate; etching the substrate along the first opening to form a trapezoidal groove with a bottom width greater than the width of the first opening; forming a first metal layer and a dielectric layer, the first metal layer covers part of the bottom wall of the trapezoidal groove directly below the first opening, and the dielectric layer covers the area of the trapezoidal groove not covered by the first metal layer; forming a second photoresist layer with a second opening, the second opening and the first opening are connected to form a T-shaped window; and forming a second metal layer in the T-shaped window, the second metal layer and the first metal layer together constitute a gate structure. That is, in the preparation method of the gate structure provided by the present invention, before removing the photoresist layer, a dielectric layer is deposited to protect the exposed substrate, so that the following beneficial effects exist:
[0027] (1) Avoid oxidation of the exposed substrate surface;
[0028] (2) There will be no metal debris falling onto the substrate surface causing leakage or short circuit problems in the device;
[0029] (3) Reduce the damage to the etching groove caused by subsequent cleaning processes;
[0030] (4) Reduce power loss and improve device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 A flow chart of the steps of a method for preparing a gate structure provided by an embodiment of the present invention;
[0032] Figure 2 to Figure 9 for Figure 1 Schematic diagram of device structure corresponding to each step in the figure;
[0033] The descriptions of the reference numerals are as follows:
[0034] 10-substrate; 20-first photoresist layer; 30-first metal layer; 40'-initial dielectric layer; 40-dielectric layer; 50-second photoresist layer; 60-second metal layer;
[0035] 100 - trapezoidal groove; 200 - first opening; 300 - second opening. DETAILED DESCRIPTION
[0036] The following is a further detailed description of the preparation method of the gate structure and the pHEMT device provided by the present invention in conjunction with the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis required to be shown in each drawing is different, and sometimes different proportions are used. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, for example, an element described as "above" another element will now be below the element. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0037] like Figure 1 As shown, an embodiment of the present invention provides a method for preparing a gate structure, comprising:
[0038] S1, forming a first photoresist layer on a substrate, and patterning the first photoresist layer so that the first photoresist layer has a first opening;
[0039] S2, etching the substrate along the first opening to form a trapezoidal groove, wherein the bottom width of the trapezoidal groove is greater than the width of the first opening;
[0040] S3, forming a first metal layer and a dielectric layer, wherein the first metal layer covers a portion of the bottom wall of the trapezoidal trench directly below the first opening, and the dielectric layer covers the area of the trapezoidal trench not covered by the first metal layer and the sidewalls of the first opening;
[0041] S4, forming a second photoresist layer, and patterning the second photoresist layer so that the second photoresist layer has a second opening, the second photoresist layer is located on the first photoresist layer, and the second opening is connected to the first opening to form a T-shaped window; and,
[0042] S5, forming a second metal layer in the T-shaped window, wherein the second metal layer and the first metal layer together constitute the gate structure.
[0043] The method for preparing the gate structure provided in an embodiment of the present invention deposits a dielectric layer to protect the exposed substrate before removing the photoresist layer. In this way, oxidation of the exposed substrate surface can be avoided, and no metal debris will fall on the substrate surface to cause leakage or short circuit problems in the device. The damage to the etching groove caused by the subsequent cleaning process can also be reduced, reducing power loss and improving device performance.
[0044] The following is combined with Figures 2 to 8 The method for preparing the gate structure provided in this embodiment is further described.
[0045] First, execute step S1, see Figure 2 , a first photoresist layer 20 is formed on a substrate 10 , and the first photoresist layer 20 is patterned so that the first photoresist layer 20 has a first opening 100 .
[0046] Specifically, the step of forming the patterned first photoresist layer 20 may include: coating a photoresist layer on the surface of the substrate 10, and then exposing, developing and photoresist reflowing the photoresist layer to form the patterned first photoresist layer 20. Optionally, the first photoresist layer 20 uses positive photoresist.
[0047] Next, execute step S2. Please refer to Figure 2 , the substrate 10 is etched along the first opening 100 to form a trapezoidal trench 200 , wherein a bottom width of the trapezoidal trench 200 is greater than a width of the first opening 100 .
[0048] Specifically, the substrate 10 may be etched by a wet etching process to form the trapezoidal groove 200. The wet etching process has the characteristic of isotropy, so the sidewalls of the groove formed by etching are inclined away from each other from top to bottom, so that the formed groove is trapezoidal. The trapezoidal groove 200 described in this step is the etching groove described above.
[0049] Then, execute step S3, see Figure 4 , forming a first metal layer 30 and a dielectric layer 40, wherein the first metal layer 30 is formed at the bottom of the trapezoidal groove 200 and is located directly below the first opening 100. Since the bottom width of the trapezoidal groove 200 is greater than the width of the first opening 100, the first metal layer 30 covers part of the bottom wall of the trapezoidal groove 200 and has a gap between the first metal layer 30 and the side wall of the trapezoidal groove 200. The dielectric layer 40 covers the area of the trapezoidal groove 200 not covered by the first metal layer 30 and the side wall of the first opening 100.
[0050] It can be understood that the first metal layer 30 is located directly below the first opening 100 , which means that the projection of the first metal layer 30 on the substrate 10 overlaps with the projection of the first opening 100 on the substrate 10 .
[0051] In this embodiment, the material of the dielectric layer 40 is silicon nitride. In some other embodiments, the material of the dielectric layer 40 may also be silicon oxide or the like.
[0052] In a preferred embodiment, the first metal layer 30 is formed first and then the dielectric layer 40 is formed. Figure 3 and Figure 4 The step of forming the dielectric layer 40 may specifically include: forming an initial dielectric layer 40', wherein the initial dielectric layer 40' covers the first metal layer 30 and extends to cover the surface exposed by the trapezoidal groove 200; and etching and removing the initial dielectric layer 40' on the surface of the first metal layer 30, wherein the portion of the initial dielectric layer 40' that is not etched and removed constitutes the dielectric layer 40.
[0053] In some other embodiments, the dielectric layer 40 may be formed first and then the first metal layer 30 may be formed. The specific steps include: after the initial dielectric layer 40' is formed, removing the initial dielectric layer 40' directly below the first opening 100 by etching, and then forming the first metal layer 30 at the corresponding position.
[0054] In comparison, forming the first metal layer 30 first and then forming the dielectric layer 40 can avoid trench damage when etching the initial dielectric layer 40 ′.
[0055] The formation process of the initial dielectric layer 40 ′ includes but is not limited to chemical vapor deposition, physical vapor deposition, etc. When the initial dielectric layer 40 ′ is formed by physical vapor deposition, chemical vapor deposition, etc., the initial dielectric layer 40 ′ will also cover the surface of the first photoresist layer 20 .
[0056] Specifically, the initial dielectric layer 40' can be etched by an anisotropic etching process, so that the portion of the initial dielectric layer 40' directly below the first opening 100 is removed, while the portion covering the bottom corner of the gate trench is retained. At the same time, the initial dielectric layer 40' located on the surface of the first photoresist layer 20 is also removed simultaneously.
[0057] Specifically, the first metal layer 30 may be formed by a metal evaporation process. When the first metal layer 30 is formed by a metal evaporation process, the first metal layer 30 also covers the surface of the first photoresist layer 20 .
[0058] Next, execute step S4, see Figure 5 , forming a second photoresist layer 50, and patterning the second photoresist layer 50 so that the second photoresist layer 50 has a second opening 300, the second photoresist layer 50 is located in the first photoresist layer 20, and the second opening 300 is connected to the first opening 100 to form a T-shaped window.
[0059] When the first metal layer 30 also covers the surface of the first photoresist layer 20 , the second photoresist layer 50 covers the surface of the first metal layer 30 located on the first photoresist layer 20 .
[0060] Similar to the formation of the first photoresist layer 20, the steps of forming the second photoresist layer 50 also include coating, exposure, development, etc. Preferably, the second photoresist layer 50 uses a negative photoresist, so that the width of the second opening 300 formed by patterning the second photoresist layer 50 gradually decreases from the top to the bottom, so that when the second metal layer is subsequently formed, it is prevented that the side wall of the second photoresist layer 50 is not easy to form a metal layer, which is conducive to accurately controlling the morphology of the second metal layer.
[0061] The width of the second opening 300 is greater than that of the first opening 100 , so that the second opening 300 is connected to the first opening 100 to form the T-shaped window.
[0062] Then, execute step S5, see Figure 6 A second metal layer 60 is formed in the T-shaped window, and the second metal layer 60 and the first metal layer 30 together constitute the gate structure.
[0063] Since the second metal layer 60 is formed in the T-shaped window and the first metal layer 30 is formed directly below the first opening 100 , the gate structure formed by the second metal layer 60 and the first metal layer 30 is also T-shaped.
[0064] See also Figure 7 to Figure 9 After step S5, the method for preparing the gate structure provided by the embodiment of the present invention may further include: a step of removing the photoresist layer. Since the first metal layer 30 also covers the surface of the first photoresist layer 20, after step S5, the following steps are further performed in sequence: Figure 7 As shown, the second photoresist layer 50 is removed; Figure 8 As shown, the first metal layer 30 on the surface of the first photoresist layer 20 is removed, and Fig. 9 As shown, the first photoresist layer 20 is removed.
[0065] Since the first photoresist layer 20 is removed only at this process stage, both the step of etching the dielectric layer 40 and the step of removing the first metal layer 30 on the surface of the first photoresist layer 20 can protect the substrate 10 without causing damage to the substrate 10, and no metal debris will fall off the surface of the substrate 10 to cause leakage or short circuit problems in the device.
[0066] An embodiment of the present invention further provides a pHEMT device, comprising: the gate structure prepared by the preparation method described in this embodiment.
[0067] Specifically, the pHEMT device further includes a substrate and an epitaxial structure formed on the substrate, the epitaxial structure includes a cap layer, and the cap layer may specifically be a GaAs layer. The trapezoidal groove is formed by etching the cap layer.
[0068] In summary, the method for preparing a gate structure provided by an embodiment of the present invention includes: forming a first photoresist layer having a first opening on a substrate; etching the substrate along the first opening to form a trapezoidal groove whose bottom width is greater than the width of the first opening; forming a first metal layer and a dielectric layer, wherein the first metal layer covers a portion of the bottom wall of the trapezoidal groove directly below the first opening, and the dielectric layer covers the area of the trapezoidal groove not covered by the first metal layer; forming a second photoresist layer having a second opening, wherein the second opening is connected to the first opening to form a T-shaped window; and forming a second metal layer in the T-shaped window, wherein the second metal layer and the first metal layer together constitute a gate structure. That is, before removing the photoresist layer, a dielectric layer is deposited to protect the exposed substrate, so that the following beneficial effects are achieved:
[0069] (1) Avoid oxidation of the exposed substrate surface;
[0070] (2) There will be no metal debris falling onto the substrate surface causing leakage or short circuit problems in the device;
[0071] (3) Reduce the damage to the etching groove caused by subsequent cleaning processes;
[0072] (4) Reduce power loss and improve device performance.
[0073] It should be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.
Claims
1. A method for preparing a gate structure, characterized in that: include: Forming a first photoresist layer on a substrate, and patterning the first photoresist layer so that the first photoresist layer has a first opening; Etching the substrate along the first opening to form a trapezoidal groove, wherein the bottom width of the trapezoidal groove is greater than the width of the first opening; forming a first metal layer and a dielectric layer, wherein the first metal layer covers a portion of the bottom wall of the trapezoidal trench directly below the first opening, and the dielectric layer covers the area of the trapezoidal trench not covered by the first metal layer and the sidewall of the first opening; forming a second photoresist layer, and patterning the second photoresist layer so that the second photoresist layer has a second opening, the second photoresist layer is located on the first photoresist layer, and the second opening is connected to the first opening to form a T-shaped window; as well as, A second metal layer is formed in the T-shaped window, and the second metal layer and the first metal layer together constitute the gate structure.
2. The method for preparing a gate structure according to claim 1, wherein: The first metal layer is formed first and then the dielectric layer is formed. The steps of forming the dielectric layer include: forming an initial dielectric layer, the initial dielectric layer covering the first metal layer and extending to cover the surface exposed by the trapezoidal groove; and, The initial dielectric layer on the surface of the first metal layer is removed by etching, and the portion of the initial dielectric layer that is not removed by etching constitutes the dielectric layer.
3. The method for preparing a gate structure according to claim 2, wherein: The initial dielectric layer is etched using an anisotropic etching process.
4. The method for preparing a gate structure according to claim 2, wherein: The first metal layer is formed by a metal evaporation process.
5. The method for preparing a gate structure according to claim 2, wherein: The first metal layer also covers the surface of the first photoresist layer; After forming the gate structure, the preparation method further includes: removing the second photoresist layer; removing the first metal layer on the surface of the first photoresist layer; and, The first photoresist layer is removed.
6. The method for preparing a gate structure according to claim 1, wherein: The second metal layer is formed by a metal evaporation process.
7. The method for preparing a gate structure according to claim 1, wherein: The width of the second opening gradually decreases from top to bottom.
8. The method for preparing a gate structure according to claim 1, wherein: The material of the dielectric layer includes silicon nitride.
9. The method for preparing a gate structure according to claim 1, wherein: The substrate is etched by a wet etching process to form the trapezoidal groove.
10. A pHEMT device, characterized in that: include: The gate structure is prepared by the preparation method according to any one of claims 1 to 9.
Citation Information
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