Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: an insulating layer; a first circuit pattern disposed on the insulating layer; and a first protective layer disposed on the insulating layer and including a first opening portion vertically overlapping the first circuit pattern, where the first protective layer includes a first region including the first opening portion and having a first thickness and a second region including the second opening portion and having a second thickness. And a second region having a second thickness greater than the first thickness without including the first opening portion, in which the first thickness of the first region is less than a third thickness of the first circuit pattern, an inner side surface of the first region constituting the first opening portion includes a first inner side surface in direct contact with an outer side surface of the first circuit pattern, and a second inner side surface spaced apart from the outer side surface of the first circuit pattern.

Description

Technical Field

[0001] Embodiments relate to a circuit board and a semiconductor package including the same. Background Art

[0002] The miniaturization, weight reduction and integration of electronic components are accelerating, and thus the circuit line width is becoming smaller. In particular, the design rules of semiconductor chips are being integrated at the nanometer level, and thus the circuit line width of a package substrate or circuit board on which a semiconductor chip is mounted is becoming smaller to less than several micrometers.

[0003] Various methods have been proposed to increase the circuit integration of a circuit board (i.e., to minimize the circuit line width). For example, a SAP (Semi-Additive Process) method and an MSAP (Modified Semi-Additive Process) method have been proposed to prevent the loss of circuit line width during an etching process for forming a pattern after copper plating.

[0004] Since then, the embedded trace substrate (ETS) method of embedding copper foil into an insulating layer has been used in the industry to achieve finer circuit patterns. The ETS method is a manufacturing method that embeds a copper circuit into an insulating layer, rather than protruding the copper circuit onto the surface of the insulating layer to form a copper circuit. Therefore, there is no circuit loss due to etching, which is conducive to minimizing the circuit pitch.

[0005] Meanwhile, the chip is mounted on the circuit board as described above, or the circuit board is combined with a main board of an external device to form a package substrate.

[0006] For this reason, a groove is formed in the outermost protective layer of the circuit board, and a solder ball for mounting a chip or a combined motherboard is arranged in the groove. In addition, a package substrate can be manufactured by mounting a chip on the solder ball or a combined motherboard and then forming a molding layer.

[0007] However, according to the prior art, when the solder ball is set on the circuit board, an intermetallic compound (IMC) is formed between the solder ball and the metal layer bonded to the solder ball. At this time, when the molding liquid for forming the molding layer is injected in the process of manufacturing the package substrate, there is a problem that the damage caused by the molding liquid injection pressure is transferred to the intermetallic compound (IMC), and thus cracks occur in the intermetallic compound (IMC). In addition, when cracks occur in the intermetallic compound (IMC), a reliability problem occurs that the chip or the main board is separated from the circuit board due to the separation of the intermetallic compound (IMC).

[0008] Therefore, there is a need for a structure that can minimize damage transmitted to the intermetallic compound (IMC) due to the molding liquid injection pressure. Summary of the invention

[0009] [Technical issues]

[0010] The embodiment provides a circuit board having a novel structure and a semiconductor package including the same.

[0011] In addition, the embodiment provides a circuit board capable of improving reliability of an intermetallic compound (IMC) and a semiconductor package including the same.

[0012] In addition, the embodiment provides a circuit board capable of increasing a contact area between a connection portion and a pad and a semiconductor package including the same.

[0013] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and those skilled in the art in the field to which the proposed embodiments belong can clearly understand other technical problems not mentioned from the following description.

[0014] [Technical solution]

[0015] According to an embodiment, a circuit board includes: an insulating layer; a first circuit pattern, which is arranged on the insulating layer; and a first protective layer, which is arranged on the insulating layer and includes a first opening portion vertically overlapping with the first circuit pattern, wherein the first protective layer includes a first area and a second area, the first area includes the first opening portion and has a first thickness, and the second area has a second thickness greater than the first thickness but does not include the first opening portion, wherein the first thickness of the first area is less than the third thickness of the first circuit pattern, wherein the inner surface of the first area constituting the first opening portion includes a first inner surface and a second inner surface, the first inner surface is in direct contact with the outer surface of the first circuit pattern, and the second inner surface is spaced apart from the outer surface of the first circuit pattern.

[0016] In addition, the second inner side surface of the first region is connected to the first inner side surface of the first region, and has a slope corresponding to the slope of the first inner side surface.

[0017] In addition, the second thickness of the second region is greater than the third thickness of the first circuit pattern.

[0018] In addition, the first circuit pattern includes a region whose width decreases toward an upper surface of the first circuit pattern, and the second inner side surface of the first region is spaced apart from an outer side surface of the region of the first circuit pattern where the width decreases.

[0019] In addition, the first thickness of the first region is within a range of 20% to 90% of the third thickness of the first circuit pattern.

[0020] In addition, the first circuit pattern includes a first portion and a second portion, the first portion is arranged on the upper surface of the insulating layer and has an outer surface that contacts the first inner surface of the first area, and the second portion is arranged on the first portion and has an outer surface that does not contact the first protective layer, wherein the second portion includes an area having a width smaller than a width of the first portion.

[0021] In addition, the width of the first opening portion corresponds to the width of the first portion.

[0022] In addition, the first portion has a fourth thickness within a range of 20% to 90% of the first thickness of the first region.

[0023] In addition, the outer side surface of the second portion has a linear slope that gradually decreases the width toward the upper surface of the second portion.

[0024] In addition, the outer side surface of the second portion includes a curved slope having a certain curvature that decreases the width toward the upper surface of the second portion.

[0025] In addition, a width of the second portion closest to the first portion is smaller than a width of the first portion closest to the second portion, and the first circuit pattern includes a step portion disposed between the first portion and the second portion.

[0026] In addition, the outer side surface of the second portion has a slope that reduces the width toward the upper surface of the second portion or a slope that does not change the width toward the upper surface of the second portion.

[0027] In addition, the second portion includes a first sub-portion and a second sub-portion, the outer surface of the first sub-portion having a first slope, and the outer surface of the second sub-portion having a second slope different from the first slope.

[0028] In addition, the first protective layer includes a recessed portion that is provided at a boundary between the first region and the second region and is recessed in an inward direction of the first protective layer.

[0029] Furthermore, the circuit board further includes a surface treatment layer provided on the first circuit pattern, and a lowermost end of the surface treatment layer is positioned lower than an upper surface of the first region.

[0030] In addition, at least a portion of the surface treatment layer is in contact with the second inner surface of the first region.

[0031] In addition, the surface roughness of the outer side surface of the first portion is different from the surface roughness of the outer side surface of the second portion.

[0032] Meanwhile, a semiconductor package according to an embodiment includes: an insulating layer; a first circuit pattern, which is disposed on the insulating layer; a first protective layer, which is disposed on the insulating layer and includes a first opening portion vertically overlapping with the first circuit pattern; a first connecting portion, which is disposed on the first circuit pattern and vertically overlaps with the first opening portion of the first protective layer; and a semiconductor device, which is mounted on the first connecting portion, wherein the first protective layer includes a first region and a second region, the first region includes the first opening portion and has a first thickness, the second region has a second thickness greater than the first thickness and does not include the first opening portion, the first thickness of the first region is less than a third thickness of the first circuit pattern, a crevice is formed between an inner side surface of the first region constituting the first opening portion and an outer side surface of the first circuit pattern, and at least a portion of the first connecting portion is disposed in the crevice.

[0033] In addition, the first protective layer includes a recessed portion provided at a boundary between the first region and the second region and formed in an inward direction of the first protective layer, and at least a portion of the first connection portion is provided in the recessed portion.

[0034] [Beneficial Effects]

[0035] The embodiment includes an insulating layer, a first circuit pattern disposed on the insulating layer, and a first protective layer disposed on the insulating layer, the first protective layer including a first opening portion vertically overlapping the first circuit pattern.

[0036] That is, the first protective layer includes a first region adjacent to and including the first opening portion. In addition, the first protective layer includes a second region adjacent to the first region. At this time, the height of the upper surface of the first region is lower than the height of the upper surface of the second region. Preferably, the height of the upper surface of the first region is lower than the height of the upper surface of the first circuit pattern. Therefore, in an embodiment, a first protective layer including a first region having a first opening portion and a second region may be arranged in an area where a protective layer is not provided due to the exposure resolution of the protective layer. In addition, the first region is provided around the first circuit pattern and includes a first opening portion having a width substantially the same as that of the first circuit pattern.

[0037] Therefore, the embodiment can stably protect the first circuit pattern from damage caused by various stresses. Therefore, the embodiment can improve the physical reliability and / or electrical reliability of the first circuit pattern.

[0038] At this time, a gap may be formed between the inner side surface of the first region of the first protection layer and the outer side surface of the first circuit pattern.

[0039] Specifically, the inner side surface of the first region includes a first inner side surface contacting the outer side surface of the first circuit pattern, and a second inner side surface spaced apart from the outer side surface of the first circuit pattern by a gap and not contacting the outer side surface of the first circuit pattern.

[0040] In addition, the embodiment allows the surface treatment layer and / or solder to be disposed in the gap. Therefore, the embodiment can increase the distance between the intermetallic compound formed by disposing the solder and the uppermost surface of the first protective layer. Therefore, the embodiment can greatly reduce the occurrence of cracks in the intermetallic compound, thereby improving the physical reliability and / or electrical reliability of the circuit board and the semiconductor package.

[0041] In addition, the embodiment can increase the distance by using the gap without increasing the thickness of the first protection layer. Therefore, the embodiment can achieve the thinning of the circuit board and the semiconductor package.

[0042] In addition, the outer side surface of the first circuit pattern includes a first outer side surface that contacts the outer side surface of the first region of the first protective layer and a second outer side surface that does not contact the first protective layer. In addition, the surface roughness of the second outer side surface may be greater than the surface roughness of the first outer side surface. Therefore, the embodiment can ensure the adhesion between the surface treatment layer disposed on the second outer side surface and the first circuit pattern, thereby improving the physical reliability and / or electrical reliability of the circuit board and the semiconductor package including the circuit board.

[0043] In addition, the embodiment allows a recessed portion to be formed inwardly at the boundary between the first region and the second region by controlling the thickness of the first region. In addition, in the process of joining solder, the recessed portion can be filled with a connecting portion such as solder. In addition, the connecting portion provided in the recessed portion can be used as an anchor, thereby improving the joining strength between the connecting portion and the first circuit pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a diagram showing a circuit board according to a comparative example.

[0045] Figure 2 It is used to explain Figure 1 Figure 2. Comparison of reliability issues of intermetallic compounds (IMC) in a control example.

[0046] Figure 3 is a cross-sectional view showing a circuit board according to an embodiment.

[0047] Figure 4 It shows that the setting Figure 3 A plan view of a first circuit pattern in a circuit board.

[0048] Figure 5is a cross-sectional view showing a first opening portion and a first circuit pattern of a first protective layer according to a first embodiment.

[0049] Figure 6 It shows that the surface treatment layer is provided on Figure 5 A cross-sectional view of a state on a first circuit pattern.

[0050] Figure 7 is a cross-sectional view illustrating a second opening portion of a first protective layer and a second circuit pattern according to an embodiment.

[0051] Figure 8 is a diagram showing a circuit board according to a second embodiment.

[0052] Fig. 9 is a diagram showing a circuit board according to a third embodiment.

[0053] Fig.10 is a diagram showing a circuit board according to a fourth embodiment.

[0054] Fig.11 is a diagram showing a circuit board according to a fifth embodiment.

[0055] Fig.12 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0056] Figures 13 to 18 are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment in process order. DETAILED DESCRIPTION

[0057] Hereinafter, the embodiments disclosed in this specification will be described in detail with reference to the accompanying drawings, but regardless of the figure numbers, the same or similar components are represented by the same figure numerals, and their repeated descriptions will be omitted. The component suffixes "module" and "part" used in the following description are given or mixed together only in consideration of the ease of creating the specification, and do not have meanings or functions that distinguish each other. In addition, when describing the embodiments disclosed in this specification, when it is determined that the detailed description of the relevant known technology unnecessarily makes the subject of the embodiments disclosed in this specification difficult to understand, its detailed description will be omitted. In addition, the drawings are only for the convenience of understanding the embodiments disclosed in this specification, and the technical scope disclosed in this specification is not limited by the drawings, and should be understood to include all modifications, equivalent transformations and alternatives that fall within the spirit and scope of the present invention.

[0058] It should be understood that although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0059] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (i.e., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0060] As used herein, the singular forms “a”, “an”, “said” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0061] It will be further understood that the terms “comprises,” “comprising,” “including,” and / or “having” when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0062] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0063] [Comparison example]

[0064] Before explaining the embodiment, a comparative example compared with the circuit board of the embodiment of the present invention will be described.

[0065] Figure 1 is a diagram showing a circuit board according to a comparative example, Figure 2 It is used to explain Figure 1 Figure 2. Comparison of reliability issues of intermetallic compounds (IMC) in a control example.

[0066] refer to Figure 1 , the circuit board according to the comparative example includes an insulating layer 10 , a circuit pattern layer 20 , a protective layer 30 , a surface treatment layer 40 and a solder 50 .

[0067] The circuit board of the comparative example has a structure in which solder 50 is provided on the circuit pattern layer 20 to attach a chip (not shown) or an external substrate (not shown).

[0068] The circuit board of the comparative example includes an insulating layer 10. In addition, the circuit board of the comparative example includes a circuit pattern layer 20 disposed on the insulating layer 10. The circuit pattern layer 20 includes a pad and a trace. The pad refers to an electrode pattern in the circuit pattern layer on which a solder 50 for bonding with a chip or an external substrate is disposed. The trace may refer to a thin signal line connecting a plurality of pads.

[0069] In addition, the circuit board of the comparative example includes a protection layer 30 disposed on the insulating layer 10 .

[0070] The protective layer 30 includes an opening. Specifically, the protective layer 30 partially exposes the upper surface of the pad on which the solder 50 is to be disposed in the circuit pattern layer 20. For example, the opening of the protective layer 30 provides a space for disposing the solder 50.

[0071] The surface treatment layer 40 is disposed in the opening of the protective layer 30. The surface treatment layer 40 is disposed on the circuit pattern layer 20 vertically overlapping the opening of the protective layer 30.

[0072] The surface treatment layer 40 may have a certain thickness.

[0073] Meanwhile, the solder 50 is disposed on the surface treatment layer 40 to fill the opening of the protective layer 30. At this time, the surface treatment layer 40 and the solder 50 are composed of different materials, and an intermetallic compound (IMC) is formed at the interface therebetween.

[0074] At this time, the upper surface of the protective layer 30 in the comparative example is located adjacent to the intermetallic compound (IMC). At this time, the protective layer 30 shrinks and expands due to the thermal stress in the use environment of the circuit board. In addition, the shrinkage and expansion are transmitted to the intermetallic compound (IMC) along the upper surface of the protective layer 30 and the inner wall of the opening.

[0075] In addition, the process of manufacturing the circuit board includes a process of bonding a chip or a main board of an external device on the solder 50 and a process of forming a molding layer (not shown) for molding the chip or the main board. At this time, the process of forming the molding layer is performed by injecting a molding liquid onto the protective layer 30. At this time, a certain pressure is applied during the process of forming the molding layer to inject the molding liquid, and the applied pressure is transmitted to the intermetallic compound (IMC) along the inner wall of the opening of the protective layer 30.

[0076] At this time, in the comparative example as described above, the upper surface of the protective layer 30 is located adjacent to the intermetallic compound (IMC), and thus, the generated stress or pressure is directly transferred to the intermetallic compound (IMC).

[0077] like Figure 2 As shown, when stress or pressure is transmitted to the intermetallic compound (IMC), cracks may occur in the intermetallic compound (IMC) due to the transmitted pressure. In addition, when cracks occur in the intermetallic compound (IMC), a physical reliability problem occurs in which the solder 50 is separated from the surface treatment layer 40.

[0078] In addition, when the solder 50 is separated from the surface finish layer 40 , the chip or main board connected to the solder 50 is also separated from the circuit board, which causes a problem of product reliability.

[0079] Furthermore, functions provided by semiconductor devices provided on a circuit board are increasing, and therefore, the number of semiconductor devices provided on the circuit board or the number of terminals provided in the semiconductor devices is increasing.

[0080] Therefore, it is necessary to miniaturize the circuit pattern layer to mount the semiconductor device. However, even if the circuit pattern layer is miniaturized, there is a limit to the size of the opening that can be formed in the protective layer 30. Therefore, the size of the opening is determined by the exposure resolution of the protective layer 30. At this time, the minimum size of the opening that can be formed is generally about 50 μm.

[0081] Therefore, the pad connected to the semiconductor device has a problem in that it is difficult to be miniaturized due to the limitation of the minimum size of the opening.

[0082] In addition, recently, in order to achieve miniaturization of pads, a protective layer is not provided on pads connected to semiconductor devices. However, in the area where the protective layer is not provided, the provided traces are not protected by the protective layer, so physical reliability and / or electrical reliability problems occur.

[0083] Therefore, the embodiment solves the physical reliability problem of the circuit board of the comparative example. Specifically, the embodiment increases the distance between the upper surface of the protective layer and the intermetallic compound (IMC) without increasing the thickness of the circuit board. Specifically, the embodiment increases the length of the inner wall of the protective layer opening connecting the upper surface of the protective layer and the intermetallic compound (IMC).

[0084] Thus, the embodiment stably protects the intermetallic compound (IMC) from the stress or pressure that occurs, thereby improving the physical reliability of the intermetallic compound (IMC). Thus, the embodiment improves the physical reliability of the intermetallic compound.

[0085] In addition, the embodiment forms a protective layer including an opening vertically overlapping with a pad while miniaturizing the pad connected to the semiconductor device. Thus, the embodiment can stably protect a pad or a trace disposed in a mounting area of ​​the semiconductor device.

[0086] [Electronic equipment]

[0087] Before describing the embodiment, an electronic device including a semiconductor package of the embodiment will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiment. Various semiconductor devices can be installed in the semiconductor package.

[0088] Semiconductor devices may include active devices and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs), in which hundreds to millions of devices are integrated into one chip. Semiconductor chips may be logic chips, memory chips, etc. Logic chips may be central processing units (CPUs), graphics processing units (GPUs), etc. For example, a logic chip may be an AP chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific IC (ASIC), or a chipset including a specific combination of the above.

[0089] The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a flash memory, or the like.

[0090] Meanwhile, the product group of the semiconductor package to which the embodiment is applied may be any one of CSP (chip scale package), FC-CSP (flip chip - chip scale package), FC-BGA (flip chip ball grid array), POP (stacked package) and SIP (system in package), but is not limited thereto.

[0091] In addition, the electronic device may be a smart phone, a personal digital assistant, a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, a car, etc. However, the embodiment is not limited thereto and may be any other electronic device that processes data.

[0092] [Circuit Board]

[0093] Hereinafter, a circuit board of the embodiment will be described.

[0094] The circuit board refers to a board before semiconductor devices or chips are mounted.

[0095] Figure 3 is a cross-sectional view showing a circuit board according to an embodiment, Figure 4 It shows that the setting Figure 3 a plan view of a first circuit pattern in a circuit board, Figure 5 is a cross-sectional view showing a first opening portion and a first circuit pattern of a first protective layer according to a first embodiment, Figure 6 It shows that the surface treatment layer is provided on Figure 5 A cross-sectional view of a state on a first circuit pattern, Figure 7 is a cross-sectional view illustrating a second opening portion of a first protective layer and a second circuit pattern according to an embodiment.

[0096] In the following, reference will be made to Figures 3 to 7A circuit board according to an embodiment is described.

[0097] The circuit board of the embodiment provides a mounting space in which at least one semiconductor device can be mounted.

[0098] For example, the circuit board of the first embodiment may provide a mounting space for mounting one semiconductor device, or alternatively, may provide a plurality of mounting spaces for mounting two or more semiconductor devices.

[0099] In addition, one logic chip may be mounted on the circuit board of the first embodiment. In addition, at least two different types of logic chips may be mounted on the circuit board of the first embodiment. In addition, at least one logic chip and at least one memory chip may be mounted on the circuit board of the first embodiment.

[0100] refer to Figure 3 , the circuit board 100 of the first embodiment includes an insulating layer 110. The insulating layer 110 may have one or more layers. The insulating layer 110 preferably has a multilayer structure. At this time, although the insulating layer 110 is shown as consisting of one layer in the figure, the embodiment is not limited thereto. For example, the insulating layer 110 may include a plurality of insulating layers having a structure stacked in a vertical direction.

[0101] Hereinafter, for convenience of explanation, the insulating layer 110 is illustrated and described as one layer.

[0102] The insulating layer 110 may be rigid or flexible.

[0103] As an example, the insulating layer 110 may include a prepreg. For example, the insulating layer 110 may be a prepreg in which glass fibers are impregnated into a resin. The resin may be an epoxy resin, but is not limited thereto.

[0104] In addition, the insulating layer 110 may include chemically strengthened / semi-strengthened glass, such as soda-lime glass or aluminosilicate glass. For example, the insulating layer 110 may include a reinforced or flexible plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer 110 may include sapphire. For example, the insulating layer 110 may include an optically isotropic film. For example, the insulating layer 110 may include COC (cyclic olefin copolymer), COP (cyclic olefin polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer 110 may be formed of a material including an inorganic filler and an insulating resin. For example, the insulating layer 110 may have a structure in which an inorganic filler of silicon dioxide or aluminum oxide is disposed in a thermosetting resin or a thermoplastic resin. For example, the insulating layer 110 may use ABF (Ajinomoto stacked film), FR-4, BT (bismaleimide triazine), PID (photoimaging dielectric resin), BT, etc. For example, the insulating layer 110 may include RCC (resin coated copper).

[0105] The insulating layer 110 may have a thickness in the range of 10 μm to 60 μm. For example, when the insulating layer 110 includes multiple layers, each of the multiple layers may have a thickness in the range of 10 μm to 60 μm. Preferably, the insulating layer 110 may have a thickness in the range of 15 μm to 55 μm. More preferably, the insulating layer 110 may have a thickness in the range of 18 μm to 52 μm.

[0106] The thickness of the insulating layer 110 may represent a vertical distance between a plurality of circuit pattern layers disposed adjacent to each other in a thickness direction. For example, the thickness of the insulating layer 110 may represent a vertical distance between the first circuit pattern layer 120 and the second circuit pattern layer 130. For example, the thickness of the insulating layer 110 may represent a vertical distance between a lower surface of the first circuit pattern layer 120 and an upper surface of the second circuit pattern layer 130.

[0107] If the thickness of the insulating layer 110 is less than 10 μm, the warpage characteristics of the circuit board 100 may be deteriorated. For example, if the thickness of the insulating layer 110 is less than 10 μm, the first circuit pattern layer 120 and the second circuit pattern layer 130 may not be stably disposed on the surface of the insulating layer 110, and thus electrical reliability and / or physical reliability problems may occur. In addition, if the thickness of the insulating layer 110 is less than 10 μm, process characteristics in the process of forming the first circuit pattern layer 120 or the second circuit pattern layer 130 on the insulating layer 110 may be deteriorated.

[0108] In addition, if the thickness of the insulating layer 110 exceeds 60 μm, the total thickness of the circuit board 100 may increase, and thus the thickness of the semiconductor package may increase. In addition, if the thickness of the insulating layer 110 exceeds 60 μm, it may be difficult to miniaturize the first circuit pattern layer 120 and / or the second circuit pattern layer 130. For example, if the thickness of the insulating layer 110 exceeds 60 μm, it may be difficult to form the width of the first circuit pattern layer 120 and / or the second circuit pattern layer 130 and the interval between adjacent patterns to be less than 12 μm, less than 10 μm, less than 8 μm, or less than 6 μm. In addition, if it is difficult to miniaturize the first circuit pattern layer 120 and / or the second circuit pattern layer 130, the circuit integration may be reduced, and therefore, due to the increase in signal transmission distance, the signal transmission loss may increase.

[0109] The circuit board 100 of the first embodiment includes a circuit pattern layer disposed on an insulating layer 110 .

[0110] For example, the circuit board 100 of the first embodiment includes the first circuit pattern layer 120 disposed on the upper surface of the insulating layer 110. In addition, the circuit board 100 includes the second circuit pattern layer 130 disposed on the lower surface of the insulating layer 110.

[0111] The first circuit pattern layer 120 may be divided into a plurality of circuit patterns according to positions or functions.

[0112] For example, the first circuit pattern layer 120 may include a first circuit pattern 120 - 1 and a second circuit pattern 120 - 2 . At least one of the first circuit pattern 120 - 1 and the second circuit pattern 120 - 2 may be disposed in a semiconductor device mounting region of the circuit board 100 .

[0113] For example, at least one of the first circuit pattern 120 - 1 and the second circuit pattern 120 - 2 may include a mounting pad connected to a terminal of the semiconductor device.

[0114] In addition, at least one of the first circuit pattern 120 - 1 and the second circuit pattern 120 - 2 may include a terminal pad coupled to an external substrate.

[0115] In addition, at least one of the first circuit pattern 120-1 and the second circuit pattern 120-2 may include a terminal pad coupled to an interposer or a mainboard of an electronic device. In this case, the interposer may be an active interposer including a semiconductor device function. Alternatively, the interposer may be a passive interposer that performs a signal relay function between multiple components.

[0116] Meanwhile, the first circuit pattern 120-1 and the second circuit pattern 120-2 may be distinguished from each other by their widths. For example, the first circuit pattern 120-1 may have a relatively smaller width than the second circuit pattern 120-2.

[0117] Preferably, the first circuit pattern 120-1 may include a mounting pad connected to a terminal of the semiconductor device. In addition, the second circuit pattern 120-2 may include a terminal pad connected to an external substrate, etc. Therefore, the first circuit pattern 120-1 may be a fine pattern corresponding to a terminal of the semiconductor device.

[0118] At this time, functions provided by semiconductor devices provided on the circuit board increase, and thus, the number of semiconductor devices provided on the circuit board or the number of terminals provided in the semiconductor devices increases.

[0119] Therefore, it is necessary to miniaturize the first circuit pattern 120-1 of the first circuit pattern layer 120. However, in the comparative example, due to the problem of size limitation of the opening portion of the protective layer, the problem of undercutting, and the problem of reliability of the intermetallic compound, there is a limit to the miniaturization of the first circuit pattern 120-1 of the first circuit pattern layer 120. That is, if the first circuit pattern 120-1 is miniaturized, there are problems such as that an opening portion having a size corresponding to the width of the first circuit pattern 120-1 cannot be formed, or a plurality of adjacent patterns are connected to each other by solder due to undercutting, or the reliability of the intermetallic compound is further reduced.

[0120] That is, if the intervals between the plurality of patterns of the first circuit pattern 120-1 are reduced, circuit integration can be improved. However, if the intervals between the plurality of patterns are reduced, a problem may occur that opening portions corresponding to the plurality of patterns cannot be formed in the first protective layer 150.

[0121] In addition, if the width of the first circuit pattern 120 - 1 is reduced or the interval between the plurality of patterns is reduced, the bonding area of ​​the intermetallic compound is reduced, and thus the physical reliability of the intermetallic compound may be further deteriorated.

[0122] Therefore, the embodiment allows the first protective layer 150 to include an opening portion, while the upper surface of the first protective layer 150 has a step structure. Thus, the embodiment maximizes the distance between the uppermost surface of the first protective layer 150 and the first circuit pattern 120-1. Specifically, the distance between the uppermost surface of the first protective layer 150 and the first circuit pattern 120-1 must be increased in order to improve the physical reliability of the intermetallic compound. To this end, the thickness of the first protective layer 150 can be increased. However, if the thickness of the first protective layer 150 increases, it may be difficult to form an opening portion having a size corresponding to the first circuit pattern 120-1 in the first protective layer 150. In addition, if the thickness of the first protective layer 150 increases, the thickness of the circuit board increases accordingly, and the total thickness of the semiconductor package increases accordingly.

[0123] Therefore, in the embodiment, the length of the inner wall of the opening portion of the first protective layer 150 disposed between the first protective layer 150 and the first circuit pattern 120 - 1 is increased without increasing the thickness of the first protective layer 150 .

[0124] This can be achieved by the shape of the opening portion of the first protective layer 150 described below and the shape of the first circuit pattern 120 - 1 vertically overlapping the opening portion. This will be described in more detail below.

[0125] Meanwhile, when the insulating layer 110 of the circuit board 100 includes multiple layers, the first circuit pattern layer 120 may be disposed on an upper surface of an uppermost insulating layer among the multiple layers of the insulating layer 110, and the second circuit pattern layer 130 may be disposed on a lower surface of a lowermost insulating layer among the multiple layers of the insulating layer 110. For example, the first circuit pattern layer 120 and the second circuit pattern layer 130 may be illustrated as outer circuit pattern layers, but are not limited thereto.

[0126] Meanwhile, when the insulating layer 110 includes a plurality of layers, an additional inner circuit pattern layer may be disposed between the plurality of layers.

[0127] refer to Figure 4 , the first circuit pattern 120-1 is disposed in a region where a semiconductor device such as a logic chip is mounted. Therefore, the first circuit pattern 120-1 may include a fine pattern. Figure 4 (a) is a plan view showing the first circuit pattern 120 - 1 in a state where the first protective layer 150 of the embodiment is removed, Figure 4 (b) is along Figure 4 (a) is a cross-sectional view taken along the AA' direction.

[0128] The first circuit pattern 120 - 1 includes a pad 120 - 11 corresponding to a terminal of a semiconductor device or a pad of an interposer and a trace 120 - 12 connected to the pad 120 - 11 .

[0129] The first circuit pattern 120-1 needs to be miniaturized. For example, the first circuit pattern 120-1 must be connected to all terminals of the semiconductor device or all pads of the interposer within a limited space, and traces connecting the pads must be provided. Therefore, the first circuit pattern 120-1 may include a fine pattern.

[0130] In addition, due to factors such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speed, the number of terminals in the first processor chip and the second processor chip is gradually increasing. Therefore, one semiconductor device may not be able to provide all functions, or the number of terminals set in one semiconductor device is increasing.

[0131] Therefore, the first circuit pattern 120 - 1 may be required to be ultra-fine.

[0132] The pads 120-11 of the first circuit pattern 120-1 correspond to the terminals of the semiconductor device to be mounted on the circuit board. Therefore, the number of the pads 120-11 corresponds to the number of the terminals of the semiconductor device.

[0133] The pad 120-11 may have different widths in a first horizontal direction and in a second horizontal direction perpendicular to the first horizontal direction. At this time, the width of the pad 120-11 in the separation direction of adjacent pads or traces may be smaller than the width in the direction perpendicular to the separation direction. In addition, the width of the pad 120-11 in the separation direction has a great influence on the circuit integration. The separation direction may represent the first horizontal direction.

[0134] That is, the pad 120-11 may have an elliptical shape whose width in the first horizontal direction is smaller than that in the second horizontal direction. However, the embodiment is not limited thereto. For example, the pad 120-11 may have a circular shape having a width in the first horizontal direction as a whole.

[0135] The width W1 of the pad 120 - 11 may be 3 μm to 30 μm. For example, the width W1 of the pad 120 - 11 may be 4 μm to 28 μm. For example, the width W1 of the pad 120 - 11 may be 5 μm to 25 μm.

[0136] If the width W1 of the pad 120-11 is less than 3 μm, it may be difficult to set the connection portion connected to the terminal of the semiconductor device. If the width W1 of the pad 120-11 is less than 3 μm, the connection reliability between the pad 120-11 and the semiconductor device may deteriorate. If the width W1 of the pad 120-11 is greater than 30 μm, it may be difficult to set all the pads connected to the semiconductor device in a limited space. If the width W1 of the pad 120-11 is greater than 30 μm, the size of the circuit board may increase. If the width W1 of the pad 120-11 is greater than 30 μm, the spacing between adjacent patterns is narrowed, and thus reliability problems such as circuit short circuits may occur.

[0137] In addition, the first circuit pattern 120-1 includes a trace 120-12 connected to the pad 120-11. The trace 120-12 may represent an elongated signal line connected to the pad 120-11. In addition, when two semiconductor devices are mounted on the first circuit pattern 120-1, the trace 120-12 may include a signal line connecting the two semiconductor devices.

[0138] Therefore, the trace 120-12 may include an ultra-fine pattern. For example, the line width W2 of the trace 120-12 may be in the range of 1 μm to 10 μm. For example, the line width W2 of the trace 120-12 may be in the range of 1.2 μm to 8 μm. For example, the line width W2 of the trace 120-12 may be in the range of 1.5 μm to 7 μm. If the line width W2 of the trace 120-12 is less than 1 μm, the resistance of the trace 120-12 increases, so normal communication with the semiconductor device may be difficult. In addition, if the line width W2 of the trace 120-12 is less than 1 μm, it may be difficult to apply a general circuit pattern manufacturing process. If the line width W2 of the trace 120-12 is less than 1 μm, a physical reliability problem may occur in which the trace 120-12 collapses due to stress caused by various factors. If the line width W2 of the trace 120-12 is greater than 10 μm, it may be difficult to arrange all signal lines connected to the terminals of the semiconductor device within a limited space. For example, if the line width W2 of the trace 120-12 is greater than 10 μm, it may be difficult to arrange all traces for connecting multiple processor chips within a limited space. For example, if the line width W2 of the trace 120-12 is greater than 10 μm, the circuit integration may be reduced.

[0139] Meanwhile, the first circuit patterns 120-1 may be spaced apart from each other by a certain interval W3. The interval W3 may represent the interval between the pads 120-11 of the first circuit pattern 120-1. In addition, the interval W3 may represent the interval between the traces of the first circuit pattern 120-1. In addition, the interval W3 may represent the interval between the pads 120-11 and the traces 120-12 of the first circuit pattern 120-1 that are adjacent to each other.

[0140] The interval W3 may have a range of 1 μm to 10 μm. The interval W3 may have a range of 1.2 μm to 8 μm. The interval W3 may have a range of 1.5 μm to 7 μm. If the interval W3 is less than 1 μm, there is a problem that traces or pads adjacent to each other are connected to each other, resulting in an electrical short circuit. For example, if the interval W3 is greater than 10 μm, it may be difficult to set all traces for connecting multiple processor chips within a limited space.

[0141] The circuit board 100 of the first embodiment may include a through electrode 140. The through electrode 140 may penetrate the insulating layer 110. Preferably, the through electrode 140 may penetrate the insulating layer 110 to electrically connect between the first circuit pattern layer 120 and the second circuit pattern layer 130. At this time, when the circuit board 100 has a multi-layer structure, the through electrode 140 may be spaced apart in a vertical direction and electrically connected between adjacent circuit pattern layers.

[0142] Meanwhile, the first circuit pattern layer 120 and the second circuit pattern layer 130 may be formed of a metal material having high conductivity as a wiring for transmitting electrical signals. To this end, the first circuit pattern layer 120 and the second circuit pattern layer 130 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the first circuit pattern layer 120 and the second circuit pattern layer 130 may be formed of a paste or solder paste including a metal material having excellent bonding strength selected from at least one of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first circuit pattern layer 120 and the second circuit pattern layer 130 may be formed of copper (Cu) having high conductivity and being relatively inexpensive.

[0143] The first circuit pattern layer 120 and the second circuit pattern layer 130 may be formed by a conventional printed circuit board manufacturing process, such as an additive process, a subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and a detailed description thereof will be omitted herein.

[0144] The thickness of the first circuit pattern layer 120 (T1, see Figure 5) may be in the range of 5 μm to 30 μm. Preferably, the thickness T1 of the first circuit pattern layer 120 may be in the range of 6 μm to 25 μm. More preferably, the thickness T1 of the first circuit pattern layer 120 may be in the range of 7 μm to 20 μm. The thickness T1 of the first circuit pattern layer 120 may represent a vertical distance from a lower surface to an upper surface of the first circuit pattern layer 120. In this case, when the upper surface or the lower surface of the first circuit pattern layer 120 has a step, the thickness T1 of the first circuit pattern layer 120 may represent a vertical distance from the lowermost end to the uppermost end of the first circuit pattern layer 120. However, the embodiment is not limited thereto. For example, the thickness T1 of the first circuit pattern layer 120 may represent an average thickness in the entire region of the first circuit pattern layer 120.

[0145] If the thickness T1 of the first circuit pattern layer 120 is less than 5 μm, the resistance of the circuit pattern may increase, and thus the signal transmission efficiency may decrease. For example, if the thickness T1 of the first circuit pattern layer 120 is less than 5 μm, the signal transmission loss may increase. For example, if the thickness T1 of the first circuit pattern layer 120 exceeds 30 μm, the line width of the first circuit pattern layer 120 may increase, and thus the circuit integration may decrease.

[0146] Meanwhile, the thickness of the second circuit pattern layer 130 may correspond to the thickness T1 of the first circuit pattern layer 120 .

[0147] The through electrode 140 may be formed by filling the inside of a through hole penetrating the insulating layer 110 with a conductive material.

[0148] The through hole may be formed by any of mechanical, laser, and chemical processing methods. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing may be used. In addition, when the through hole is formed by laser processing, a UV or CO2 laser method may be used. In addition, when the through hole is formed by chemical processing, chemical agents including aminosilane, ketone, etc. may be used.

[0149] Meanwhile, the circuit board 100 of the first embodiment may include a protection layer.

[0150] For example, the circuit board 100 may include a first protective layer 150 disposed above the insulating layer 110. For example, the circuit board 100 may include a second protective layer 160 disposed below the insulating layer 110.

[0151] The first protective layer 150 and the second protective layer 160 may be a resist layer. Preferably, the first protective layer 150 and the second protective layer 160 may be a solder resist layer including an organic polymer material. For example, the first protective layer 150 and the second protective layer 160 may include an epoxy acrylate resin. In detail, the first protective layer 150 and the second protective layer 160 may include a resin, a hardener, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc.

[0152] The thickness of each of the first protective layer 150 and the second protective layer 160 may be greater than the thickness of each of the first circuit pattern layer 120 and the second circuit pattern layer 130 .

[0153] That is, the thickness of the first protective layer 150 may be greater than the thickness of the first circuit pattern layer 120. In addition, the thickness of the second protective layer 160 may be greater than the thickness of the second circuit pattern layer 130.

[0154] The thickness of the first protective layer 150 may represent a vertical distance from a lower surface to an upper surface of the first protective layer 150 in a region excluding the opening portion of the first protective layer 150. For example, the thickness of the first protective layer 150 may represent a second region (R2, see Figure 5 ) in thickness (T4, see Figure 5 ).

[0155] The thickness T4 of the first protective layer 150 may be in the range of 6.7 μm to 35.0 μm. Preferably, the thickness T4 of the first protective layer 150 may be in the range of 7.3 μm to 32 μm. More preferably, the thickness T4 of the first protective layer 150 may be in the range of 8.0 μm to 30 μm.

[0156] If the thickness of the first protective layer 150 exceeds 30 μm, the thickness of the circuit board and the thickness of the semiconductor package may increase. In addition, if the thickness of the first protective layer 150 is less than 6.7 μm, the first circuit pattern layer may not be stably protected, and thus electrical reliability or physical reliability may deteriorate.

[0157] In addition, the second protective layer 160 may have a thickness corresponding to that of the first protective layer 150 , but is not limited thereto.

[0158] Meanwhile, the first protective layer 150 includes at least one opening portion. In addition, the second protective layer 160 includes at least one opening portion.

[0159] The first protective layer 150 may include a first opening portion OP1. For example, the first protective layer 150 may include the first opening portion OP1 vertically overlapping the first circuit pattern 120-1.

[0160] In addition, the first protective layer 150 may include a second opening portion OP2. For example, the first protective layer 150 may include a second opening portion OP2 vertically overlapping the second circuit pattern 120-2.

[0161] In addition, the second protective layer 160 may include at least one third opening portion vertically overlapping the second circuit pattern layer 130 .

[0162] In addition, the first protective layer 150 may be divided into a plurality of regions.

[0163] The first protective layer 150 may include a first region R1 having a first opening portion OP1. In addition, the first protective layer 150 may include a second region R2 adjacent to the first region R1 without including the first opening portion OP1.

[0164] In addition, the first protective layer 150 may include a third region R3 having the second opening portion OP2. In addition, the first protective layer 150 may include a fourth region R4 adjacent to the third region R3 without including the second opening portion OP2.

[0165] At this time, the second region R2 and the fourth region R4 are regions that do not include the first opening portion OP1 and the second opening portion OP2. In addition, the second region R2 and the fourth region R4 in the first protective layer 150 may form a single region connected to each other. Therefore, some regions of the first protective layer 150 may represent the second region R2 or the fourth region R4, or alternatively, may represent both the second region R2 and the fourth region R4.

[0166] Hereinafter, the shapes of the first and second circuit patterns 120 - 1 and 120 - 2 and the first and second opening portions OP1 and OP2 formed in the first protective layer 150 will be described in detail.

[0167] refer to Figure 5 , the first protection layer 150 includes a first opening portion OP1.

[0168] The first opening portion OP1 may correspond to the first circuit pattern 120 - 1. Specifically, the first protection layer 150 may include the first opening portion OP1 vertically overlapping the first circuit pattern 120 - 1.

[0169] The first opening portion OP1 may refer to a region exposing the upper surface of the first circuit pattern 120-1 in the first region R1 of the first protective layer 150. For example, the first opening portion OP1 may refer to a region vertically overlapping the first circuit pattern 120-1 in the first region R1 of the first protective layer 150.

[0170] At this time, the thickness T3 of the first region R1 of the first protection layer 150 is less than the thickness T1 of the first circuit pattern 120-1. Therefore, the first opening portion OP1 may indicate an area where the first protection layer 150 is not provided due to the first circuit pattern 120-1 in the area where the first circuit pattern 120-1 is provided.

[0171] Therefore, the width of the first opening portion OP1 of the first protection layer 150 may correspond to the width of the first circuit pattern 120-1. Here, the corresponding meaning may mean that the difference between the width of the first opening portion OP1 of the first protection layer 150 and the width of the first circuit pattern 120-1 is 2 μm or less, 1.5 μm or less, 1.0 μm or less, 0.8 μm or less, or 0.5 μm or less.

[0172] Preferably, the first protective layer 150 is formed by performing a process of thinning the first protective layer 150 to a thickness less than the first circuit pattern 120-1 in a state where the upper surface of the first circuit pattern 120-1 is covered. At this time, the thinned area may be referred to as the first area R1 of the first protective layer 150. In addition, the first opening portion OP1 may represent an area in which the first circuit pattern 120-1 is disposed (or an area vertically overlapped with the first circuit pattern) in the thinned first area R1 of the first protective layer 150. Therefore, the width of the first opening portion OP1 of the first protective layer 150 may be the same as the width of the first circuit pattern 120-1. Preferably, the width of the first opening portion OP1 of the first protective layer 150 may be the same as the width of the lower surface of the first circuit pattern 120-1. Therefore, the first protective layer 150 may be provided to cover a portion of the side surface of the first circuit pattern 120-1 while including the first opening portion OP1.

[0173] Specifically, the first protective layer 150 may be divided into a plurality of regions based on the position where the first opening portion OP1 is formed.

[0174] For example, the first protective layer 150 includes a first region R1 including and adjacent to the first opening portion OP1. In addition, the first protective layer 150 may include a second region R2 adjacent to and having a step with the first region R1.

[0175] The first region R1 of the first protective layer 150 includes a first opening portion OP1 vertically overlapping the first circuit pattern 120-1. Preferably, the first region R1 of the first protective layer 150 includes the first opening portion OP1 having the same width as the lower surface of the first circuit pattern 120-1.

[0176] The height of the upper surface of the first region R1 of the first protective layer 150 is different from the height of the upper surface of the second region R2. Preferably, the thickness T3 of the first region R1 of the first protective layer 150 is smaller than the thickness T4 of the second region R2 of the first protective layer 150.

[0177] The thickness T3 of the first region R1 of the first protective layer 150 may be determined based on the thickness T1 of the first circuit pattern 120-1. Preferably, the thickness T3 of the first region R1 of the first protective layer 150 is smaller than the thickness T1 of the first circuit pattern 120-1.

[0178] For example, the thickness T3 of the first region R1 of the first protective layer 150 may be in the range of 20% to 90% of the thickness T1 of the first circuit pattern 120-1. Preferably, the thickness T3 of the first region R1 of the first protective layer 150 may be in the range of 25% to 85% of the thickness T1 of the first circuit pattern 120-1. More preferably, the thickness T3 of the first region R1 of the first protective layer 150 may be in the range of 27% to 83% of the thickness T1 of the first circuit pattern 120-1.

[0179] If the thickness T3 of the first region R1 of the first protective layer 150 is less than 20% of the thickness T1 of the first circuit pattern 120-1, the physical reliability and / or electrical reliability of the first circuit pattern 120-1 may be deteriorated. Specifically, the first region R1 of the first protective layer 150 may have a function of supporting the pad 120-11 and / or the trace 120-12 of the first circuit pattern 120-1 as a fine pattern. In addition, if the thickness T3 of the first region R1 of the first protective layer 150 is less than 20% of the thickness T1 of the first circuit pattern 120-1, the effect of the supporting function may not be significant.

[0180] In addition, if the thickness T3 of the first region R1 of the first protective layer 150 exceeds 90% of the thickness T1 of the first circuit pattern 120-1, residual resin of the first protective layer 150 may exist on a portion of the upper surface of the first circuit pattern 120-1. In addition, if the residual resin of the first protective layer 150 exists on the upper surface of the first circuit pattern 120-1, the electrical reliability of the first circuit pattern 120-1 may be deteriorated.

[0181] At this time, the first region R1 of the first protective layer 150 is disposed to cover a portion of the side surface of the first circuit pattern 120 - 1 .

[0182] At this time, the first circuit pattern 120-1 may include a region whose width changes toward the upper surface of the first circuit pattern 120-1. Preferably, the first circuit pattern 120-1 may include a region whose width decreases toward the upper surface of the first circuit pattern 120-1. At this time, in the first circuit pattern 120-1, the position where the width starts to decrease may be positioned lower than the upper surface of the first region R1 of the first protective layer 150.

[0183] Therefore, at least a portion of the inner surface of the first region R1 of the first protective layer 150 (preferably, the side wall of the first opening portion OP1 formed in the first region R1) may not contact the side surface of the first circuit pattern 120-1. For example, a crevice may be formed between the inner surface of the first region R1 of the first protective layer 150 and the outer surface of the first circuit pattern 120-1. Specifically, the inner surface of the first region R1 of the first protective layer 150 may include a first inner surface adjacent to the lower surface of the first region R1 of the first protective layer 150 and in contact with the outer surface of the first circuit pattern 120-1. In addition, the inner surface of the first region R1 of the first protective layer 150 may include a second inner surface adjacent to the upper surface of the first region R1 of the first protective layer 150 and not in contact with or spaced apart from the outer surface of the first circuit pattern 120-1. In addition, the crevice may be provided between the outer surface of the first circuit pattern 120-1 and the second inner surface of the first region R1 of the first protective layer 150.

[0184] At this time, the gap may not be formed by the second inner surface of the first region R1 of the first protective layer 150, but may be formed by the outer surface of the first circuit pattern 120-1. For example, the gap may be provided by cutting inward at least a portion of the outer surface of the first circuit pattern 120-1. However, the embodiment is not limited thereto. For example, the gap may be formed by cutting inward the second inner surface of the first region R1 of the first protective layer 150, or may be formed by a combination of these.

[0185] However, the following description will assume that the slit is formed by cutting inwardly a portion of the outer side surface of the first circuit pattern 120 - 1 .

[0186] The first inner surface and the second inner surface of the first region R1 of the first protective layer 150 are connected to each other. At this time, the slope of the first inner surface of the first region R1 of the first protective layer 150 may correspond to the slope of the second inner surface. For example, the first inner surface and the second inner surface of the first region R1 of the first protective layer 150 may have a vertical slope relative to the lower surface of the first region R1 of the first protective layer 150.

[0187] The first circuit pattern 120-1 may be divided into a plurality of parts in the thickness direction. For example, the pad 120-11 and / or the trace 120-12 of the first circuit pattern 120-1 may be divided into a plurality of parts in the thickness direction.

[0188] The first circuit pattern 120-1 may include a first portion 120-1a adjacent to an upper surface of the insulating layer 110. The width of the upper surface of the first portion 120-1a of the first circuit pattern 120-1 may correspond to the width of the lower surface of the first portion 120-1a. Here, corresponding may mean that the width difference between the upper surface and the lower surface of the first portion 120-1a of the first circuit pattern 120-1 is 2 μm or less, 1.5 μm or less, 1.0 μm or less, 0.8 μm or less, or 0.5 μm or less.

[0189] The width of the first portion 120-1a of the first circuit pattern 120-1 may correspond to the width of the first opening portion OP1 formed in the first region R1 of the first protection layer 150. Preferably, the width of the first portion 120-1a of the first circuit pattern 120-1 may be the same as the width of the first opening portion OP1.

[0190] Therefore, the outer side surface 120-1as of the first portion 120-1a of the first circuit pattern 120-1 may directly contact the first protective layer 150. Preferably, the outer side surface 120-1as of the first portion 120-1a of the first circuit pattern 120-1 may directly contact the first inner side surface of the first region R1 of the first protective layer 150.

[0191] The outer surface 120-1as of the first portion 120-1a of the first circuit pattern 120-1 may have a slope corresponding to the slope of the first inner surface of the first region R1 of the first protection layer 150. For example, the outer surface of the first portion 120-1a of the first circuit pattern 120-1 may be perpendicular to the lower surface of the first circuit pattern 120-1, but is not limited thereto.

[0192] At this time, the uppermost end of the first portion 120-1a of the first circuit pattern 120-1 may be positioned lower than the upper surface of the first region R1 of the first protective layer 150. For example, the thickness T2 of the first portion 120-1a of the first circuit pattern 120-1 may be less than the thickness T3 of the first region R1 of the first protective layer 150.

[0193] At this time, the thickness T2 of the first portion 120 - 1 a of the first circuit pattern 120 - 1 may be determined by the thickness T3 of the first region R1 of the first protective layer 150 .

[0194] Specifically, the thickness T2 of the first portion 120-1a of the first circuit pattern 120-1 may be within 20% to 90% of the thickness T3 of the first region R1 of the first protective layer 150. Preferably, the thickness T2 of the first portion 120-1a of the first circuit pattern 120-1 may be within 25% to 85% of the thickness T3 of the first region R1 of the first protective layer 150. More preferably, the thickness T2 of the first portion 120-1a of the first circuit pattern 120-1 may be within 27% to 83% of the thickness T3 of the first region R1 of the first protective layer 150.

[0195] If the thickness T2 of the first portion 120-1a of the first circuit pattern 120-1 is less than 20% of the thickness T3 of the first region R1 of the first protective layer 150, the contact area between the outer surface of the first circuit pattern 120-1 and the inner surface of the first region R1 of the first protective layer 150 is reduced, and thus the physical reliability and / or electrical reliability of the first circuit pattern 120-1 may be deteriorated. In addition, if the thickness T2 of the first portion 120-1a of the first circuit pattern 120-1 is less than 20% of the thickness T3 of the first region R1 of the first protective layer 150, the depth of the gap increases, and thus the physical reliability of the connection portion provided on the first circuit pattern 120-1 may be deteriorated. For example, if the depth of the gap increases, the thickness deviation of the connection portion increases, and thus the mounting workability of the semiconductor device may be deteriorated. In addition, if the depth of the gap increases, the amount of the connection portion increases, and thus the rigidity of the connection portion may be deteriorated.

[0196] In addition, if the thickness T2 of the first portion 120-1a of the first circuit pattern 120-1 exceeds 90% of the thickness T3 of the first region R1 of the first protective layer 150, the depth of the gap may be reduced, and thus the effect provided by the gap may be insufficient. For example, the gap is formed to increase the thickness of the surface treatment layer (170, see Figure 6 ) and the upper surface of the second region R2 of the first protection layer 150. At this time, if the thickness T2 of the first portion 120-1a of the first circuit pattern 120-1 exceeds 90% of the thickness T3 of the first region R1 of the first protection layer 150, the distance increasing effect is insufficient, and thus, physical reliability problems such as cracks in the intermetallic compound formed by arranging the connection portion may occur.

[0197] Meanwhile, the first circuit pattern 120-1 includes a second portion 120-1b disposed on the first portion 120-1a. The upper surface of the second portion 120-1b is positioned higher than the upper surface of the first region R1 of the first protective layer 150. In addition, the lower surface of the second portion 120-1b is positioned lower than the upper surface of the first region R1 of the first protective layer 150.

[0198] The second portion 120 - 1 b of the first circuit pattern 120 - 1 includes a region where the width varies.

[0199] Specifically, the width of the second portion 120 - 1 b of the first circuit pattern 120 - 1 may decrease as it is away from the first portion 120 - 1 a .

[0200] For example, the second portion 120 - 1 b of the first circuit pattern 120 - 1 includes an outer side surface 120 - 1 bs connected to the outer side surface 120 - 1 as of the first portion 120 - 1 a .

[0201] The outer side surface 120-1bs of the second portion 120-1b has a slope different from that of the outer side surface 120-1as of the first portion 120-1a. For example, the outer side surface 120-1as of the first portion 120-1a may have a slope that does not vary in width.

[0202] In addition, the outer side surface 120 - 1bs of the second portion 120 - 1b may have a slope such that the width gradually decreases as it moves away from the first portion 120 - 1a .

[0203] For example, the outer side surface 120-1bs of the second portion 120-1b may be a straight line having a specific slope that gradually reduces the width of the second portion. Figure 5 , the outer surface 120-1bs of the second portion 120-1b is shown as a straight line having a specific slope, but is not limited thereto. For example, the outer surface 120-1bs of the second portion 120-1b may have a specific curvature that reduces the width of the second portion toward the upper surface of the second portion. In addition, the outer surface 120-1bs of the second portion 120-1b having a curvature may have a shape that is convex toward the first region R1 of the first protective layer 150, or may have a shape that is concave toward the inner side of the second portion 120-1b away from the first region R1 of the first protective layer 150.

[0204] The outer side surface 120-1bs of the second portion 120-1b does not contact the first protective layer 150. For example, the outer side surface 120-1bs of the second portion 120-1b does not contact the inner side surface of the first region R1 of the first protective layer 150. For example, the outer side surface 120-1bs of the second portion 120-1b is spaced apart from the inner side surface of the first region R1 of the first protective layer 150. For example, a gap is formed between the outer side surface 120-1bs of the second portion 120-1b and the inner side surface of the first region R1 of the first protective layer 150.

[0205] In addition, embodiments may improve physical reliability and / or electrical reliability of a circuit board and a semiconductor package including the same by using a gap formed between the first circuit pattern 120 - 1 and the first protective layer 150 .

[0206] For example, refer to Figure 6 The surface treatment layer 170 is disposed on the first circuit pattern 120 - 1 . The surface treatment layer 170 may be an organic solderability preservative (OSP).

[0207] At this time, the surface treatment layer 170 is disposed on the surface of the first circuit pattern 120-1. For example, the surface treatment layer 170 is disposed on the surface of the first circuit pattern 120-1 exposed by the first opening portion OP1 of the first protective layer 150. For example, the surface treatment layer 170 is disposed on the upper surface and the outer side surface 120-1bs of the second portion 120-1b of the first circuit pattern 120-1. Therefore, the lowermost end of the surface treatment layer 170 is located in the gap formed between the first circuit pattern 120-1 and the first region R1 of the first protective layer 150. Thus, the embodiment can increase the distance or length of the side wall of the first protective layer 150 between the upper surface of the second region R2 of the first protective layer 150 and the lowermost end of the surface treatment layer 170. Therefore, the embodiment can improve the physical reliability and / or electrical reliability of the intermetallic compound formed by providing a connection portion such as solder on the surface treatment layer 170.

[0208] Meanwhile, a gap may be formed by pre-processing a portion of the upper surface and the outer side surface of the first circuit pattern 120-1 during the process of forming the surface treatment layer 170. For example, during the pre-processing, the upper surface and the outer side surface 120-1bs of the second portion 120-1b of the first circuit pattern 120-1 may be etched. Therefore, due to the etching, a gap may be formed between the outer side surface 120-1bs of the second portion 120-1b and the inner side surface of the first region R1 of the first protective layer 150.

[0209] Therefore, the outer side surface of the first circuit pattern 120 - 1 may have a roughness that differs according to regions.

[0210] For example, the outer surface 120-1as of the first portion 120-1a of the first circuit pattern 120-1 may have a first surface roughness. At this time, the first surface roughness of the outer surface 120-1as of the first portion 120-1a may correspond to the surface roughness of the inner surface of the first region R1 of the first protective layer 150 that contacts the outer surface 120-1as of the first portion 120-1a.

[0211] Meanwhile, the outer surface 120-1bs of the second portion 120-1b of the first circuit pattern 120-1 may have a second surface roughness different from the first surface roughness. Preferably, the second surface roughness of the outer surface 120-1bs of the second portion 120-1b of the first circuit pattern 120-1 may be greater than the first surface roughness of the outer surface 120-1as of the first portion 120-1a.

[0212] Thus, embodiments may ensure adhesion between the surface finish layer 170 and the first circuit pattern 120 - 1 , thereby improving physical reliability and / or electrical reliability of a circuit board and a semiconductor package including the same.

[0213] Meanwhile, the first protective layer 150 may include a recessed portion 153. The recessed portion 153 may be formed at a boundary between the first region R1 and the second region R2 of the first protective layer 150. In the process of thinning the thickness T3 of the first region R1 of the first protective layer 150, the recessed portion 153 may be formed at the boundary. For example, because the first protective layer 150 is not completely cured, the recessed portion 153 may be formed at the boundary between the first region R1 and the second region R2. In addition, the embodiment may minimize the length of the recessed portion 153 in the horizontal direction by controlling the thickness T3 of the first region R1.

[0214] However, the embodiment allows the concave portion 153 having a certain length in the horizontal direction to be provided at the boundary by adjusting the thickness T3 of the first region R1. Then, the concave portion 153 may be filled with a connection portion such as solder in a subsequent solder bonding process. In addition, the connection portion provided in the concave portion 153 may serve as an anchor, thereby improving the bonding strength between the connection portion and the first circuit pattern 120-1.

[0215] At the same time, reference Figure 7 , the first protection layer 150 includes a second opening portion OP2. At this time, the second opening portion OP2 may have a shape different from that of the first opening portion OP1. For example, the second opening portion OP2 may be an SMD type opening portion.

[0216] For example, the second opening portion OP2 vertically overlaps the second circuit pattern 120-2. At this time, the second opening portion OP2 vertically overlaps partially with the upper surface of the second circuit pattern 120-2. For example, a portion of the upper surface of the second circuit pattern 120-2 may be covered by the first protective layer 150, and the rest of the upper surface of the second circuit pattern 120-2 may be exposed through the second opening portion OP2.

[0217] At this time, the first protective layer 150 may include a third region R3, which includes a second opening portion OP2 and is adjacent to the second opening portion OP2. The third region R3 may represent a region including the second opening portion OP2 and vertically overlapping the second circuit pattern 120-2. In addition, the first protective layer 150 may include a fourth region R4 adjacent to the third region R3. At this time, the upper surface of the third region R3 of the first protective layer 150 may have the same height as the upper surface of the fourth region R4. For example, the upper surface of the third region R3 of the first protective layer 150 and the upper surface of the fourth region R4 may not have a step. For example, the upper surface of the third region R3 of the first protective layer 150 may be located on the same plane as the upper surface of the fourth region R4. That is, compared with the first circuit pattern 120-1, the second circuit pattern 120-2 is a large area pattern. Therefore, even if the second opening portion OP2 vertically overlapping the second circuit pattern 120-2 does not have the same structure as the first opening portion OP1, the reliability of the intermetallic compound can be maintained.

[0218] Therefore, the second circuit pattern 120-2 may include a recess 120-2R, which is formed by etching a portion of the upper surface of the second circuit pattern 120-2 in a pretreatment process for forming a surface treatment layer (not shown). In addition, the width of the recess 120-2R in the horizontal direction may be greater than the width of the second opening portion OP2. For example, a portion of the recess 120-2R vertically overlaps with the second opening portion OP2, and the rest of the recess 120-2R vertically overlaps with the third region R3 of the first protective layer 150. Therefore, the surface treatment layer or a connection portion such as a solder may penetrate into the recess 120-2R. Thus, the embodiment can enable the surface treatment layer or the connection portion that penetrates into the recess 120-2R to serve as an anchor, thereby further enhancing the bonding strength between the second circuit pattern 120-2 and the surface treatment layer or the solder.

[0219] The embodiment includes an insulating layer, a first circuit pattern disposed on the insulating layer, and a first protective layer disposed on the insulating layer, the first protective layer including a first opening portion vertically overlapping the first circuit pattern.

[0220] That is, the first protective layer includes a first region adjacent to and including the first opening portion. In addition, the first protective layer includes a second region adjacent to the first region. At this time, the height of the upper surface of the first region is lower than the height of the upper surface of the second region. Preferably, the height of the upper surface of the first region is lower than the height of the upper surface of the first circuit pattern. Therefore, in an embodiment, a first protective layer including a first region having a first opening portion and a second region may be arranged in an area where a protective layer is not provided due to the exposure resolution of the protective layer. In addition, the first region is provided around the first circuit pattern and includes a first opening portion having a width substantially the same as that of the first circuit pattern.

[0221] Therefore, the embodiment can stably protect the first circuit pattern from damage caused by various stresses. Therefore, the embodiment can improve the physical reliability and / or electrical reliability of the first circuit pattern.

[0222] At this time, a gap may be formed between the inner side surface of the first region of the first protection layer and the outer side surface of the first circuit pattern.

[0223] Specifically, the inner side surface of the first region includes a first inner side surface contacting the outer side surface of the first circuit pattern, and a second inner side surface spaced apart from the outer side surface of the first circuit pattern by a gap and not contacting the outer side surface of the first circuit pattern.

[0224] In addition, the embodiment allows the surface treatment layer and / or solder to be disposed in the gap. Therefore, the embodiment can increase the distance between the intermetallic compound formed by disposing the solder and the uppermost surface of the first protective layer. Therefore, the embodiment can greatly reduce the occurrence of cracks in the intermetallic compound, thereby improving the physical reliability and / or electrical reliability of the circuit board and the semiconductor package.

[0225] In addition, the embodiment can increase the distance by using the gap without increasing the thickness of the first protection layer. Therefore, the embodiment can achieve the thinning of the circuit board and the semiconductor package.

[0226] In addition, the outer side surface of the first circuit pattern includes a first outer side surface that contacts the outer side surface of the first region of the first protective layer and a second outer side surface that does not contact the first protective layer. In addition, the surface roughness of the second outer side surface may be greater than the surface roughness of the first outer side surface. Therefore, the embodiment can ensure the adhesion between the surface treatment layer disposed on the second outer side surface and the first circuit pattern, thereby improving the physical reliability and / or electrical reliability of the circuit board and the semiconductor package including the circuit board.

[0227] In addition, the embodiment allows a recessed portion to be formed inwardly at the boundary between the first region and the second region by controlling the thickness of the first region. In addition, during the solder bonding process, the recessed portion can be filled with a connecting portion such as solder. In addition, the connecting portion disposed in the recessed portion can be used as an anchor, thereby improving the bonding strength between the connecting portion and the first circuit pattern.

[0228] Hereinafter, a circuit board according to another embodiment will be described.

[0229] The circuit board described below is similar to Figure 5 The circuit board of the first embodiment shown is different in the shape of the first circuit pattern. Therefore, the following description of the circuit board of another embodiment will focus on the shape of the first circuit pattern.

[0230] Figure 8 is a diagram showing a circuit board according to a second embodiment.

[0231] refer to Figure 8 The circuit board of the second embodiment includes an insulating layer 210 , a first circuit pattern 220 - 1 and a first protective layer 250 .

[0232] The first protective layer 250 includes a first opening portion OP1. For example, the first protective layer 250 includes a first region R1, the first region R1 includes the first opening portion OP1 and is adjacent to the first opening portion OP1. In addition, the first protective layer 250 may include a second region R2, the second region R2 is adjacent to the first region R1 and has a step with the first region R1.

[0233] In addition, the first circuit pattern 220 - 1 includes a first portion 220 - 1 a and a second portion 220 - 1 b .

[0234] Here, the insulating layer 210 and the first protective layer 250 have the same structure as the insulating layer 110 and the first protective layer 150 of the first embodiment. Therefore, the description thereof will be omitted.

[0235] The first portion 220-1a of the first circuit pattern 220-1 has the same structure as the first portion 120-1a of the first circuit pattern 110-1 of the first embodiment. Therefore, a description thereof will also be omitted.

[0236] Meanwhile, the second portion 220-1b of the first circuit pattern 220-1 is disposed on the first portion 220-1a. At this time, the second portion 220-1b may have a step with the first portion 220-1a.

[0237] Specifically, the first portion 120-1a and the second portion 120-1b in the first embodiment have no step. That is, in the first embodiment, the width of the first portion 120-1a at the portion closest to the second portion 120-1b is the same as the width of the second portion 120-1b at the portion closest to the first portion 120-1a.

[0238] Different from this, the second portion 220-1b in the second embodiment may have a step with the first portion 220-1a. Specifically, the width of the second portion 220-1b at the portion closest to the first portion 220-1a may be different from the width of the first portion 220-1a at the portion closest to the second portion 220-1b. More specifically, the width of the second portion 220-1b at the portion closest to the first portion 220-1a is smaller than the width of the first portion 220-1a at the portion closest to the second portion 220-1b.

[0239] Therefore, a step portion 220-1ST may be provided between the first portion 220-1a and the second portion 220-1b of the first circuit pattern 220-1. The step portion 220-1ST may refer to a portion where a portion of the upper surface of the first portion 220-1a is exposed due to a width difference between the first portion 220-1a and the second portion 220-1b of the first circuit pattern 220-1. That is, the upper surface of the first portion 220-1a does not contact the second portion 220-1b and the first protective layer 250.

[0240] In addition, the outer side surface 220 - 1bs of the second portion 220 - 1b may have a slope such that the width gradually decreases as it moves away from the first portion 220 - 1a.

[0241] For example, the outer side surface 220 - 1bs of the second portion 220 - 1b may be a straight line having a certain slope gradually decreasing the width, but is not limited thereto.

[0242] For example, the outer side surface 220-1bs of the second portion 220-1b may have a certain curvature that decreases the width toward the upper surface. In addition, the outer side surface 220-1bs of the second portion 220-1b having the curvature may have a convex shape toward the outside, or alternatively, may have a concave shape toward the inside.

[0243] Fig. 9 is a diagram showing a circuit board according to a third embodiment.

[0244] refer to Fig. 9 The circuit board of the third embodiment includes an insulating layer 310 , a first circuit pattern 320 - 1 and a first protective layer 350 .

[0245] The first protective layer 350 includes a first opening portion OP1. For example, the first protective layer 350 includes a first region R1 including the first opening portion OP1 and adjacent to the first opening portion OP1. In addition, the first protective layer 350 may include a second region R2 adjacent to the first region R1 and having a step with the first region R1.

[0246] In addition, the first circuit pattern 320 - 1 includes a first portion 320 - 1 a and a second portion 320 - 1 b .

[0247] Here, the insulating layer 310 and the first protective layer 350 have the same structure as the insulating layer 110 and the first protective layer 150 of the first embodiment. Therefore, the description thereof will be omitted.

[0248] The first portion 320-1a of the first circuit pattern 320-1 has the same structure as the first portion 120-1a of the first circuit pattern 120-1 of the first embodiment. Therefore, a description thereof will also be omitted.

[0249] Meanwhile, the second portion 320-1b of the first circuit pattern 320-1 is disposed on the first portion 320-1a. At this time, the second portion 320-1b may have a step with the first portion 320-1a.

[0250] That is, the width of the second portion 320-1b at the portion closest to the first portion 320-1a may be different from the width of the first portion 320-1a at the portion closest to the second portion 320-1b. Specifically, the width of the second portion 320-1b at the portion closest to the first portion 320-1a is smaller than the width of the first portion 320-1a at the portion closest to the second portion 320-1b.

[0251] Therefore, a step portion 320-1ST may be provided between the first portion 320-1a and the second portion 320-1b of the first circuit pattern 320-1. The step portion 320-1ST may refer to a portion where a portion of the upper surface of the first portion 320-1a is exposed due to a width difference between the first portion 320-1a and the second portion 320-1a of the first circuit pattern 320-1. That is, the upper surface of the first portion 320-1a does not contact the second portion 320-1b and the first protective layer 350.

[0252] In addition, the width of the second portion 320-1b may not change as the distance from the first portion 320-1a increases. For example, the outer side surface 320-1bs of the second portion 320-1b may be a straight line perpendicular to the lower surface of the first circuit pattern 320-1 without changing the width.

[0253] Fig.10is a diagram showing a circuit board according to a fourth embodiment.

[0254] refer to Fig.10 The circuit board of the fourth embodiment includes an insulating layer 410 , a first circuit pattern 420 - 1 and a first protective layer 450 .

[0255] The first protective layer 450 includes a first opening portion OP1. For example, the first protective layer 450 includes a first region R1 including the first opening portion OP1 and adjacent to the first opening portion OP1. In addition, the first protective layer 450 may include a second region R2 adjacent to the first region R1 and having a step with the first region R1.

[0256] In addition, the first circuit pattern 420 - 1 includes a first portion 420 - 1 a and a second portion 420 - 1 b .

[0257] Here, the insulating layer 410 and the first protective layer 450 have the same structure as the insulating layer 110 and the first protective layer 150 of the first embodiment. Therefore, the description thereof will be omitted.

[0258] The first portion 420-1a of the first circuit pattern 420-1 has the same structure as the first portion 120-1a of the first circuit pattern 120-1 of the first embodiment. Therefore, a description thereof will also be omitted.

[0259] Meanwhile, the second portion 420 - 1 b of the first circuit pattern 420 - 1 is disposed on the first portion 420 - 1 a .

[0260] At this time, the second portion 420 - 1 b may be divided into a plurality of sub-portions.

[0261] For example, the second portion 420 - 1 b may be divided into a plurality of sub-portions based on the shape or inclination of the outer side surface.

[0262] The second portion 420-1b includes a first sub-portion 420-1b1 disposed on the first portion 420-1a. In addition, the second portion 420-1b may include a second sub-portion 420-1b2 disposed on the first sub-portion 420-1b1.

[0263] At this time, the vertical cross-sections of the first sub-portion 420-1b1 and the second sub-portion 420-1b2 may have different shapes. For example, the outer side surfaces of the first sub-portion 420-1b1 and the second sub-portion 420-1b2 may have different slopes.

[0264] The outer side surface 420-1b1s of the first sub-portion 420-1b1 may be a curved surface having a specific curvature. Therefore, based on the curvature of the curved surface, the width of the first sub-portion 420-1b1 may decrease as it moves away from the first portion 420-1a. In addition, the outer side surface 420-1b1s of the first sub-portion 420-1b1 having a curvature may have an outwardly convex shape, or differently, may have an inwardly concave shape.

[0265] In addition, the outer side surface 420 - 1 b 2 s of the second sub-portion 420 - 1 b 2 may have a slope in which the width gradually decreases as it moves away from the first sub-portion 420 - 1 b 1 .

[0266] For example, the outer side surface 420-1b2s of the second sub-portion 420-1b2 may be a straight line having a specific slope that gradually reduces the width, but is not limited thereto. For example, the outer side surface 420-1b2s of the second sub-portion 420-1b2 may have a specific curvature. In addition, the outer side surface 420-1b2s of the second sub-portion 420-1b2 having a curvature may have an outwardly convex shape, or differently, may have an inwardly concave shape.

[0267] Fig.11 is a diagram showing a circuit board according to a fifth embodiment.

[0268] refer to Fig.11 The circuit board of the fifth embodiment includes an insulating layer 510 , a first circuit pattern 520 - 1 and a first protective layer 550 .

[0269] The first protective layer 550 includes a first opening portion OP1. For example, the first protective layer 550 includes a first region R1, the first region R1 includes the first opening portion OP1 and is adjacent to the first opening portion OP1. In addition, the first protective layer 550 may include a second region R2, the second region R2 is adjacent to the first region R1 and has a step with the first region R1.

[0270] In addition, the first circuit pattern 520 - 1 includes a first portion 520 - 1 a and a second portion 520 - 1 b .

[0271] Here, the insulating layer 510 and the first protective layer 550 have the same structure as the insulating layer 110 and the first protective layer 150 of the first embodiment. Therefore, the description thereof will be omitted.

[0272] The first portion 520-1a of the first circuit pattern 520-1 has the same structure as the first portion 120-1a of the first circuit pattern 120-1 of the first embodiment. Therefore, a description thereof will also be omitted.

[0273] Meanwhile, the second portion 520 - 1 b of the first circuit pattern 520 - 1 is disposed on the first portion 520 - 1 a .

[0274] At this time, the second portion 520 - 1 b may be divided into a plurality of sub-portions.

[0275] For example, the second portion 520 - 1 b may be divided into a plurality of sub-portions based on the shape or slope of the outer side surface.

[0276] The second portion 520-1b includes a first sub-portion 520-1b1 disposed on the first portion 520-1a. In addition, the second portion 520-1b may include a second sub-portion 520-1b2 disposed on the first sub-portion 520-1b1.

[0277] At this time, the vertical cross-sections of the first sub-portion 520-1b1 and the second sub-portion 520-1b2 may have different shapes. For example, the outer side surfaces of the first sub-portion 520-1b1 and the second sub-portion 520-1b2 may have different slopes.

[0278] The outer side surface 520-1b1s of the first sub-portion 520-1b1 may be a curved surface having a specific curvature. Therefore, based on the curvature of the curved surface, the width of the first sub-portion 520-1b1 may decrease as it moves away from the first portion 520-1a. In addition, the outer side surface 520-1b1s of the first sub-portion 520-1b1 having a curvature may have an outwardly convex shape, and differently, may have an inwardly concave shape.

[0279] The width of the second sub-portion 520 - 1 b 2 may not change as it moves away from the first sub-portion 520 - 1 b 1 .

[0280] For example, the outer side surface 520 - 1 b 2 s of the second sub-portion 520 - 1 b 2 may be perpendicular to the lower surface of the first circuit pattern 520 - 1 .

[0281] [Semiconductor packaging]

[0282] Fig.12 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0283] refer to Fig.12 , the semiconductor package of the embodiment may include Figure 5 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 Any one of the circuit boards shown in . In addition, the circuit board can have a multilayer structure.

[0284] The semiconductor package of the embodiment includes the first connection portion 610. That is, the circuit pattern layer of the circuit pattern includes a pad disposed in a mounting region of the semiconductor device 6420. The pad may refer to the pad 120-11 of the first circuit pattern 120-1 of the first circuit pattern layer.

[0285] The first connection portion 610 may have a hexahedral shape. The cross section of the first connection portion 610 may include a square shape. The cross section of the first connection portion 610 may include a rectangular or square shape. For example, the first connection portion 610 may include a spherical shape. For example, the cross section of the first connection portion 610 may include a circular shape or a semicircular shape. For example, the cross section of the first connection portion 610 may include a partial circular shape or a complete circular shape. The cross-sectional shape of the first connection portion 610 may be flat on one side and curved on the other side. The first connection portion 610 may be a solder ball, but is not limited thereto. At the same time, at least a portion of the first connection portion 610 may be disposed in the gap.

[0286] The semiconductor package of the embodiment includes a configuration disposed on the first connection portion 610. The configuration disposed on the first connection portion 610 may be a semiconductor device, or alternatively, an interposer. Hereinafter, the configuration disposed on the first connection portion 610 is described as a semiconductor device 620.

[0287] The semiconductor device 620 may be a logic chip, but is not limited thereto. For example, the semiconductor device 620 may be a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and an application processor (AP) chip in a microcontroller. The semiconductor device 620 includes a terminal 625 disposed on the lower surface. In addition, the terminal 625 of the semiconductor device 620 is connected to the circuit pattern layer of the circuit board through the first connection portion 610.

[0288] In addition, the semiconductor package may include an underfill 630. The underfill 630 may be provided to cover the periphery of the semiconductor device 620 on the circuit board. However, the underfill 630 may be optionally omitted. For example, when the underfill 630 is omitted, the semiconductor package may perform the function of the underfill 630 in the molding layer 650.

[0289] The semiconductor package may include a second connection portion 640. The second connection portion 640 is disposed on the first circuit pattern layer of the circuit board. For example, the second connection portion 640 may be disposed on the second circuit pattern 120-2 of the first circuit pattern layer 120.

[0290] The second connection portion 640 may be a bump. For example, the second connection portion 640 may be a solder bump, but is not limited thereto. For example, the second connection portion 640 may be a column bump. For example, the second connection portion 640 may include a copper column and a solder bump disposed on the copper column. The upper surface of the second connection portion 640 may be positioned higher than the upper surface of the semiconductor device 620. Therefore, during the bonding process of the external substrate 600 to be disposed on the second connection portion 640, the semiconductor device 620 may be prevented from being damaged.

[0291] The semiconductor package may include a molding layer 650. The molding layer 650 may mold a configuration disposed on a circuit board.

[0292] The mold layer 650 may be EMC (epoxy mold compound), but is not limited thereto. The mold layer 650 may have a low dielectric constant. For example, the dielectric constant (Dk) of the mold layer 650 may be 0.2 to 10. For example, the dielectric constant (Dk) of the mold layer 650 may be 0.5 to 8. For example, the dielectric constant (Dk) of the mold layer 650 may be 0.8 to 5. Therefore, in an embodiment, the mold layer 650 may have a low dielectric constant, thereby improving the heat dissipation characteristics of the heat generated from the semiconductor device 620. The mold layer 650 may include an opening. For example, the mold layer 650 may include an opening vertically overlapping the upper surface of the second connection portion 640.

[0293] The semiconductor package includes a third connection portion 660 .

[0294] The third connection portion 660 may be disposed below the circuit pattern layer at the lowermost side of the circuit board. The third connection portion 660 may be solder for connecting the semiconductor package of the embodiment to a separate external substrate (eg, a main board of an electronic device), but is not limited thereto.

[0295] The semiconductor package includes an external substrate 700. The external substrate 700 may refer to a separate substrate combined with the circuit board of the embodiment. For example, the semiconductor device 620 provided on the circuit board may be a logic chip such as a CPU or a GPU, and the external substrate 700 may refer to a memory substrate on which a memory chip connected to the logic chip is provided. The external substrate 700 may be an interposer connected between the memory substrate and the circuit board, and a semiconductor device 780 corresponding to the memory chip is provided on the memory substrate.

[0296] The external substrate 700 may include an insulating layer 710, a circuit layer 720, a through electrode 730, an upper protective layer 740, and a lower protective layer 750. In addition, the external substrate 700 may include a fourth connection portion 760. The fourth connection portion 760 may be disposed between the external substrate 700 and the third connection portion 740.

[0297] In addition, the semiconductor package may include a fifth connection portion 770 . The fifth connection portion 770 may be provided on the external substrate 700 .

[0298] The semiconductor package may include a semiconductor device 780. The semiconductor device 780 may be mounted on the external substrate 700 through the fifth connection portion 770. The semiconductor device 780 may be a memory chip, but is not limited thereto. The terminal 785 of the semiconductor device 780 may be electrically connected to the external substrate 700 through the fifth connection portion 770. At this time, the semiconductor device 780 is shown as being mounted in a flip chip manner, but is not limited thereto. The semiconductor device 780 may be a stacked memory chip and may therefore be electrically connected to the external substrate 700 through a separate connection member such as a wire.

[0299] [Manufacturing method]

[0300] Hereinafter, a method for manufacturing a circuit board according to an embodiment will be described.

[0301] Figures 13 to 18 are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment in process order.

[0302] refer to Fig.13 , the insulating layer 110 is prepared in an embodiment.

[0303] Thereafter, the embodiment forms a via hole VH penetrating the upper and lower surfaces of the insulating layer 110 .

[0304] Next, refer to Fig.14 , the embodiment may form a through electrode 140 filling the through hole VH on the insulating layer 110. In addition, the embodiment may form a first circuit pattern layer 120 including a first circuit pattern 120-1 and a second circuit pattern 120-2 on the upper surface of the insulating layer 110. In addition, the embodiment may form a second circuit pattern layer 130 on the lower surface of the insulating layer 120.

[0305] Afterwards, refer to Fig.15 , the embodiment forms a first barrier layer R1 on the insulating layer 120. At this time, the first barrier layer R1 may refer to a protective layer before the opening portion is formed in the first protective layer 150. The first barrier layer R1 may be a solder resist layer, but is not limited thereto.

[0306] In addition, the embodiment forms a second barrier layer R2 under the insulating layer 120. At this time, the second barrier layer R2 may mean a protective layer before the opening portion is formed in the second protective layer 160. The second barrier layer R2 may be a solder resist layer, but is not limited thereto.

[0307] Next, refer to Fig.16, embodiments may perform a process of exposing the first barrier layer R1 to form first and second exposure patterns ER1 and ER2. The first and second exposure patterns ER1 and ER2 may be formed to correspond to regions where opening portions are to be formed in the first barrier layer R1.

[0308] In addition, embodiments may perform a process of exposing the second barrier layer R2 to form a third exposure pattern ER3.

[0309] Next, refer to Fig.17 When the first to third exposure patterns ER1, ER2, and ER3 are formed, embodiments may perform a process of curing the remaining regions of the first and second barrier layers R1 and R2 except for the first to third exposure patterns ER1, ER2, and ER3. Thereafter, embodiments may perform a thinning process of reducing the thickness of the regions corresponding to the first to third exposure patterns ER1, ER2, and ER3 to a target thickness.

[0310] The thinning process may be performed using an organic alkaline compound including tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline).

[0311] Thus, the embodiment may form the first opening portion OP1 and the second opening portion OP2 in the first protective layer 150 , respectively.

[0312] Thereafter, the embodiment may perform an OSP pre-treatment. Then, when the OSP pre-treatment is performed, a portion of the outer surface of the first circuit pattern 120 - 1 that is not covered by the first protective layer 150 may be removed by etching.

[0313] As a result, a gap may be formed between the first protection layer 150 and the first circuit pattern 120-1. In addition, OSP pretreatment may also be performed on the upper surface of the second circuit pattern 120-2 vertically overlapping the second opening portion OP2. As a result, a recessed portion 120-2R may be formed on the upper surface of the second circuit pattern 120-2 by OSP pretreatment.

[0314] On the other hand, when the circuit board having the above-mentioned features of the present invention is used for IT equipment or household appliances (such as smart phones, server computers, TVs, etc.), functions such as signal transmission or power supply can be stably performed. For example, when the circuit board having the features of the present invention performs a semiconductor packaging function, it can be used to safely protect the semiconductor chip from external moisture or pollutants, or alternatively, it can solve the problems of leakage current, electrical short circuit and electrical open circuit of the terminals provided to the semiconductor chip. In addition, when the signal transmission function is dominant, the noise problem can be solved. Thus, the circuit board having the above-mentioned features of the present invention can maintain the stable function of IT equipment or household appliances, so that the entire product and circuit board to which the present invention is applied can achieve functional unification or technical interlocking with each other.

[0315] When the circuit board having the above features of the present invention is used for a transportation device such as a vehicle, the problem of signal distortion transmitted to the transportation device can be solved, or alternatively, the safety of the transportation device can be further improved by safely protecting the semiconductor chip controlling the transportation device from external influences and solving the problem of leakage current or electrical short circuit between terminals provided to the semiconductor chip or electrical open circuit of the terminals. Therefore, the transportation device and the circuit board to which the present invention is applied can achieve functional unification or technical interlocking with each other.

[0316] The characteristics, structures and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, a person skilled in the art to which the embodiments belong may even combine or modify the characteristics, structures and effects shown in each embodiment relative to other embodiments. Therefore, it should be understood that the contents related to such combination and such modification are included within the scope of the embodiments.

[0317] The above description has focused on the embodiments, but it is merely illustrative and does not limit the embodiments. It will be appreciated by those skilled in the art that various modifications and applications not shown above are possible without departing from the basic features of the embodiments. For example, each component specifically indicated in the embodiments may be modified and implemented. In addition, it should be understood that the differences associated with these changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: Insulation layer; a first circuit pattern, the first circuit pattern being disposed on the insulating layer; as well as a first protective layer disposed on the insulating layer and including a first opening portion vertically overlapping the first circuit pattern, The first protective layer includes a first region and a second region, the first region includes the first opening portion and has a first thickness, and the second region has a second thickness greater than the first thickness and does not include the first opening portion. wherein the first thickness of the first region is less than the third thickness of the first circuit pattern, The inner surface of the first region constituting the first opening portion includes a first inner surface and a second inner surface, the first inner surface directly contacts the outer surface of the first circuit pattern, and the second inner surface is spaced apart from the outer surface of the first circuit pattern.

2. The circuit board according to claim 1, wherein: The second inner side surface of the first region is connected to the first inner side surface of the first region, and has a slope corresponding to a slope of the first inner side surface.

3. The circuit board according to claim 1, wherein: The second thickness of the second region is greater than the third thickness of the first circuit pattern.

4. The circuit board according to claim 1, wherein: the first circuit pattern includes a region whose width decreases toward an upper surface of the first circuit pattern, The second inner surface of the first region is spaced apart from an outer surface of a region where the width of the first circuit pattern is reduced.

5. The circuit board according to any one of claims 1 to 4, wherein: The first thickness of the first region is in a range of 20% to 90% of the third thickness of the first circuit pattern.

6. The circuit board according to claim 5, wherein: The first circuit pattern comprises: a first portion disposed on an upper surface of the insulating layer and having an outer surface in contact with the first inner surface of the first region; and a second portion, the second portion being disposed on the first portion and having an outer side surface that does not contact the first protective layer, The second portion includes a region whose width is smaller than that of the first portion.

7. The circuit board according to claim 6, wherein: The width of the first opening portion corresponds to the width of the first portion.

8. The circuit board according to claim 6, wherein: The first portion has a fourth thickness in a range of 20% to 90% of the first thickness of the first region.

9. The circuit board according to claim 6, wherein: The outer side surface of the second portion has a linear slope that gradually decreases the width toward the upper surface of the second portion.

10. The circuit board according to claim 6, wherein: The outer side surface of the second portion includes a curved slope having a certain curvature that decreases the width toward the upper surface of the second portion.

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