Integrated circuit low-power-consumption design method based on dynamic voltage and frequency regulation

Abstract

The invention discloses an integrated circuit low-power-consumption design method based on dynamic voltage and frequency regulation, which relates to the technical field of integrated circuits, and comprises the following steps: reducing power supply voltage: increasing transistor delay time, reducing circuit response speed and reducing threshold voltage. According to the invention, by realizing dynamic voltage and frequency adjustment on the integrated circuit, a voltage range can be set according to design parameters and performance requirements of the circuit under the condition that the working stability of the integrated circuit is ensured, the integrated circuit can be ensured to operate stably when the voltage is adjusted in the range, and meanwhile, the integrated circuit is enabled to operate stably. Meanwhile, the influence of the voltage change on the circuit performance can be monitored, a proper frequency range is set, when the frequency is adjusted, it is ensured that the integrated circuit can stably operate within the preset frequency, meanwhile, the performance requirement is met, and the purpose of reducing power consumption under the condition that the stability of the integrated circuit is ensured is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-power design method for integrated circuits based on dynamic voltage and frequency regulation. Background Art

[0002] An integrated circuit is a miniature electronic device or component that uses a certain process to interconnect components such as transistors, resistors, capacitors, inductors, and wiring. It is made on a small piece or several small pieces of semiconductor chips or dielectric substrates, and then packaged in a tube shell to form a miniature structure with the required circuit function.

[0003] In the prior art, in the design optimization of integrated circuits, power consumption control is usually achieved by reducing the overall frequency and voltage. However, this control method will limit the operating speed of the integrated circuit and affect the operating stability of the integrated circuit.

[0004] Therefore, we propose a low-power design method for integrated circuits based on dynamic voltage and frequency adjustment to solve the above problems. Summary of the invention

[0005] The purpose of the present invention is to provide a low-power design method for integrated circuits based on dynamic voltage and frequency adjustment, so as to solve the problem raised in the above background technology that in the design optimization of integrated circuits, power consumption control is usually achieved by reducing the overall frequency and voltage, but this control method will lead to the operating speed of the integrated circuit being limited, thereby affecting the operating stability of the integrated circuit.

[0006] To achieve the above object, the present invention provides the following technical solution: a low-power design method for integrated circuits based on dynamic voltage and frequency adjustment, characterized in that it includes the following steps:

[0007] S1: Reduce the power supply voltage: increase the transistor delay time, reduce the circuit response speed, and reduce the threshold voltage;

[0008] S2: Logic synthesis optimization, using state recoding of state allocation, recoding the state allocation according to the activity of the integrated circuit, and reducing the gate flip frequency when switching between states after recoding, so as to achieve the purpose of low-power state allocation. State recoding extracts state transitions from the synchronous network, and then completes the probability conversion according to the transition probability between states and the circuit capacitance weighted state, and further improves the threshold reduction ratio in step S1;

[0009] S3: Static power consumption optimization, by reducing the threshold voltage in step S2, the purpose of reducing static power consumption is achieved. The static power consumption is reduced by using a variable threshold method. The variable threshold method is to add a reverse bias voltage to the substrate position of the integrated circuit element. By using the reverse bias voltage, the difference between the gate-source voltage and the threshold voltage can be reduced, thereby achieving the purpose of reducing the subthreshold leakage current, and further optimizing and reducing the static power consumption.

[0010] S4: Algorithm optimization: Based on the static power optimization result of step S3, the energy consumption of the number of operations, input and output, and basic memory access in the reference circuit is further optimized by the algorithm;

[0011] S5: Introduce dynamic voltage and frequency adjustment improvement technology. The improvement technology is divided into two aspects: dynamic and static. The static technology uses clock gating and power gating technology to shut down redundant resources in the circuit when the circuit is not in operation. The dynamic technology dynamically adjusts the operating frequency and voltage of the circuit according to different requirements in the circuit operation state.

[0012] Preferably, the power supply voltage reduction method in step S1 is: it is known that the power supply voltage, system clock frequency and load capacitance in the existing integrated circuit are related, and the dynamic power consumption is proportional to the power supply voltage, so reducing the power supply voltage can achieve the purpose of reducing the dynamic power consumption of the integrated circuit. In order to avoid the transistor source-drain difference caused by reducing the power supply voltage, increase the delay time of the transistor, and improve the running speed of the integrated circuit, the power supply voltage adjustment method is optimized by the following calculation formula:

[0013]

[0014] Where, u is the mobility of the load current, C ox is the gate capacitance, is the transistor aspect ratio, V GS is the gate-source voltage, V T is the threshold voltage, I DS is the source-drain current.

[0015] Preferably, according to the calculation formula of step S1, when the power supply voltage of the integrated circuit is reduced to reduce power consumption, the gate-source voltage will also be reduced synchronously. At the same time, in order not to change the source-drain current, the threshold voltage will also be reduced synchronously while the gate-source voltage is reduced.

[0016] Preferably, the algorithm optimization method in step S4 is: by adopting the algorithm optimization method, the power consumption of the integrated circuit caused by the number of operations, input and output quantities, and basic memory access in the circuit is reduced; the algorithm optimization adopts an accelerated transformation method, and the number of integrated circuit control steps is optimized through accelerated transformation; while keeping the throughput unchanged, a slower control clock is used, assuming that each operation occupies one control step.

[0017] Preferably, the output mode in step S4 is expressed as:

[0018] Y N-1 =X N-1 +A*Y N-2 ;

[0019] Y N =X N +A*X N-1 +A 2 *Y N-2 .

[0020] Preferably, the dynamic adjustment method in step S5 is: during the adjustment process, the frequency and voltage of the circuit operation are dynamically adjusted according to the real-time load state. On the premise of satisfying the circuit operation stability, the frequency and voltage are appropriately reduced, and the circuit operation state is flipped and calculated. In one calculation, the circuit operation power is set to P, and the energy consumed by the circuit operation is expressed as E.

[0021] Preferably, the calculation formula in step S5 is expressed as:

[0022] P=aCV 2 f;

[0023] E=P·T d =aCV 2 f·T d ;

[0024] Where C is the total load capacitance of the integrated circuit, a is the flip factor, V is the circuit voltage, f is the circuit operating frequency, T d The time taken to complete a scheduled task.

[0025] Preferably, in the flip calculation based on step S5, the current circuit load is calculated according to the signal value, and the value of the current circuit load is obtained after the calculation is completed. According to the current load value, the computing performance required by the integrated circuit in the next time period is predicted, and the predicted result is converted into the required frequency, so as to make real-time adjustments to the frequency setting of the circuit, and the corresponding voltage value of the circuit is calculated according to the real-time adjusted frequency, and the integrated circuit control system is notified to adjust the voltage of the circuit.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] 1. In the present invention, the dynamic consumption of the circuit can be reduced by reducing the frequency. In the typical working tasks of the integrated circuit, reducing the operating frequency of the circuit can achieve the purpose of reducing the overall power consumption. At the same time, the reduction of the operating frequency can also reduce the voltage, thereby further reducing the power consumption of the integrated circuit. By implementing dynamic voltage and frequency adjustment for the integrated circuit, a voltage range can be set according to the design parameters and performance requirements of the circuit while ensuring the working stability of the integrated circuit, ensuring that the integrated circuit can operate stably when the voltage is adjusted within this range. At the same time, the influence of voltage changes on circuit performance is monitored, and a suitable frequency range is set. When adjusting the frequency, it is ensured that the integrated circuit can operate stably within a predetermined frequency and meet the performance requirements at the same time, thereby achieving the purpose of reducing power consumption while ensuring the stability of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The present invention is a system flow chart of the integrated circuit low power design method based on dynamic voltage and frequency regulation. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the implementation regulations described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] Example

[0031] Reference Figure 1 As shown: A low power consumption design method for integrated circuits based on dynamic voltage and frequency adjustment includes the following steps:

[0032] S1: Reduce the power supply voltage: increase the transistor delay time, reduce the circuit response speed, and reduce the threshold voltage;

[0033] The power supply voltage reduction method in step S1 is: it is known that the power supply voltage, system clock frequency and load capacitance in the existing integrated circuit are related, and the dynamic power consumption is proportional to the power supply voltage. Therefore, reducing the power supply voltage can achieve the purpose of reducing the dynamic power consumption of the integrated circuit. In order to avoid the source and drain of the transistor when reducing the power supply voltage, increase the delay time of the transistor, and improve the operation speed of the integrated circuit, the power supply voltage adjustment method is optimized by the following calculation formula:

[0034]

[0035] Where, u is the mobility of the load current, C ox is the gate capacitance, is the transistor aspect ratio, V GS is the gate-source voltage, V T is the threshold voltage, I DS is the source-drain current;

[0036] According to the calculation formula of step S1, when the power supply voltage of the integrated circuit is reduced to reduce power consumption, the gate-source voltage will also be reduced synchronously. At the same time, in order not to change the source-drain current, when the gate-source voltage is reduced, the threshold voltage will also be reduced synchronously.

[0037] S2: Logic synthesis optimization, using state recoding of state allocation, recoding the state allocation according to the activity of the integrated circuit, and reducing the gate flip frequency when switching between states after recoding, so as to achieve the purpose of low-power state allocation. State recoding extracts state transitions from the synchronous network, and then completes the probability conversion according to the transition probability between states and the circuit capacitance weighted state, and further improves the threshold reduction ratio in step S1;

[0038] S3: Static power consumption optimization, by reducing the threshold voltage in step S2, the purpose of reducing static power consumption is achieved, and the reduction of static power consumption adopts a variable threshold method. The variable threshold method is to add a reverse bias voltage at the position of the integrated circuit element substrate. By using the reverse bias voltage, the difference between the gate-source voltage and the threshold voltage can be reduced, thereby achieving the purpose of reducing the subthreshold leakage current, and further optimizing and reducing the static power consumption;

[0039] In the subthreshold region, even if the gate-source voltage is lower than the threshold voltage, a certain amount of leakage current will still flow through the transistor. This current is called subthreshold leakage current, which is an important component of static power consumption in integrated circuits. By reducing the difference between the gate-source voltage and the threshold voltage, the variable threshold method effectively suppresses the generation of subthreshold leakage current. As the difference decreases, the leakage current is significantly reduced, thereby achieving further optimization of static power consumption.

[0040] S4: Algorithm optimization: Based on the static power optimization result of step S3, the energy consumption of the number of operations, input and output, and basic memory access in the reference circuit is further optimized by the algorithm;

[0041] The algorithm optimization method in step S4 is: by adopting the algorithm optimization method, the power consumption of the integrated circuit caused by the number of operations, input and output, and basic memory access in the circuit is reduced. The algorithm optimization adopts the accelerated transformation method, and the number of integrated circuit control steps is optimized by the accelerated transformation. While keeping the throughput unchanged, a slower control clock is used. Assuming that each operation occupies one control step, its output method is expressed as:

[0042] Y N-1 =X N-1 +A*Y N-2 ;

[0043] Y N =X N +A*X N-1 +A 2 *Y N-2 ;

[0044] By accelerating the transformation, the control process of the integrated circuit is finely adjusted to reduce the number of control steps. Under the premise of keeping the overall system throughput unchanged, a slower control clock frequency is used. This strategy is based on reducing the active time of the control unit, because the power consumption of the control unit often increases significantly with the increase of frequency. Although each operation takes one control step, the overall power consumption of the integrated circuit can be reduced by optimizing the execution efficiency of the control step and reducing unnecessary operations.

[0045] S5: Introducing dynamic voltage and frequency adjustment improvement technology. The improvement technology is divided into two aspects: dynamic and static. The static technology uses clock gating and power gating technology to shut down the redundant resources in the circuit when the circuit is not in operation. The dynamic technology dynamically adjusts the operating frequency and voltage of the circuit according to different requirements in the circuit operation state.

[0046] The dynamic adjustment method in step S5 is: during the adjustment process, the frequency and voltage of the circuit operation are dynamically adjusted according to the real-time load state. Under the premise of meeting the circuit operation stability, the frequency and voltage are appropriately reduced, and the circuit operation state is reversed. In one calculation, the circuit operation power is set to P, and the energy consumed by the circuit operation is expressed as E. The calculation formula is expressed as:

[0047] P=aCV 2 f;

[0048] E=P·T d =aCV 2 f·T d ;

[0049] Where C is the total load capacitance of the integrated circuit, a is the flip factor, V is the circuit voltage, f is the circuit operating frequency, T d The time taken to complete the scheduled tasks;

[0050] In the rollover calculation based on the above formula, relevant steps are required to complete the process. First, the signal related to the system load is collected, and the current circuit load is calculated according to the signal value. After the calculation is completed, the value of the current circuit load is obtained. According to the current load value, the computing performance required by the integrated circuit in the next time period is predicted, and the predicted result is converted into the required frequency, so as to adjust the frequency setting of the circuit in real time, calculate the corresponding voltage value of the circuit according to the real-time adjusted frequency, and then notify the integrated circuit control system to adjust the voltage of the circuit;

[0051] According to the flip calculation in step S5, it can be concluded that the dynamic consumption of the circuit can be reduced by reducing the frequency. In the typical working tasks of the integrated circuit, reducing the operating frequency of the circuit can achieve the purpose of reducing the overall power consumption. At the same time, the reduction of the operating frequency can also reduce the voltage, thereby further reducing the power consumption of the integrated circuit;

[0052] According to the above calculation method, by implementing dynamic voltage and frequency adjustment for the integrated circuit, a voltage range can be set according to the design parameters and performance requirements of the circuit while ensuring the working stability of the integrated circuit, ensuring that the integrated circuit can operate stably when the voltage is adjusted within this range. At the same time, the impact of voltage changes on circuit performance is monitored, and a suitable frequency range is set. When adjusting the frequency, it is ensured that the integrated circuit can operate stably within a predetermined frequency while meeting performance requirements, thereby achieving the purpose of reducing power consumption while ensuring the stability of the integrated circuit.

[0053] Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A low-power design method for integrated circuits based on dynamic voltage and frequency regulation, characterized in that: The following steps are involved: S1: Reduce the power supply voltage: increase the transistor delay time, reduce the circuit response speed, and reduce the threshold voltage; S2: Logic synthesis optimization, using state recoding of state allocation, recoding the state allocation according to the activity of the integrated circuit, and reducing the gate flip frequency when switching between states after recoding, so as to achieve the purpose of low-power state allocation. State recoding extracts state transitions from the synchronous network, and then completes the probability conversion according to the transition probability between states and the circuit capacitance weighted state, and further improves the threshold reduction ratio in step S1; S3: Static power consumption optimization, by reducing the threshold voltage in step S2, the purpose of reducing static power consumption is achieved. The static power consumption is reduced by using a variable threshold method. The variable threshold method is to add a reverse bias voltage to the substrate position of the integrated circuit element. By using the reverse bias voltage, the difference between the gate-source voltage and the threshold voltage can be reduced, thereby achieving the purpose of reducing the subthreshold leakage current, and further optimizing and reducing the static power consumption. S4: Algorithm optimization: Based on the static power optimization result of step S3, the energy consumption of the number of operations, input and output, and basic memory access in the reference circuit is further optimized by the algorithm; S5: Introduce dynamic voltage and frequency adjustment improvement technology. The improvement technology is divided into two aspects: dynamic and static. The static technology uses clock gating and power gating technology to shut down redundant resources in the circuit when the circuit is not in operation. The dynamic technology dynamically adjusts the operating frequency and voltage of the circuit according to different requirements in the circuit operation state.

2. The low power consumption design method for integrated circuits based on dynamic voltage and frequency adjustment according to claim 1, characterized in that: The power supply voltage reduction method in step S1 is: it is known that the power supply voltage, system clock frequency and load capacitance in the existing integrated circuit are related, and the dynamic power consumption is proportional to the power supply voltage. Therefore, reducing the power supply voltage can achieve the purpose of reducing the dynamic power consumption of the integrated circuit. In order to avoid the source-drain difference of the transistor when reducing the power supply voltage, increase the delay time of the transistor, and improve the running speed of the integrated circuit, the power supply voltage adjustment method is optimized by the following calculation formula: Where, u is the mobility of the load current, C ox is the gate capacitance, is the transistor aspect ratio, V GS is the gate-source voltage, V T is the threshold voltage, I DS is the source-drain current.

3. The low power consumption design method for integrated circuits based on dynamic voltage and frequency adjustment according to claim 2, characterized in that: According to the calculation formula of step S1, when the power supply voltage of the integrated circuit is reduced to reduce power consumption, the gate-source voltage will also be reduced synchronously. At the same time, in order not to change the source-drain current, when the gate-source voltage is reduced, the threshold voltage will also be reduced synchronously.

4. The low power consumption design method for integrated circuits based on dynamic voltage and frequency adjustment according to claim 1, characterized in that: The algorithm optimization method in step S4 is: by adopting the algorithm optimization method, the power consumption of the integrated circuit caused by the number of operations, input and output quantities, and basic memory access in the circuit is reduced. The algorithm optimization adopts the accelerated transformation method, and the number of integrated circuit control steps is optimized through the accelerated transformation. While keeping the throughput unchanged, a slower control clock is used, assuming that each operation occupies one control step.

5. The low power consumption design method for integrated circuits based on dynamic voltage and frequency adjustment according to claim 4, characterized in that: The output mode in step S4 is expressed as: AND N-1 =X N-1 +A*Y N-2 ; AND N =X N +A*X N-1 +A 2 *AND N-2 。 6. The low power consumption design method for integrated circuits based on dynamic voltage and frequency adjustment according to claim 1, characterized in that: The dynamic adjustment method in step S5 is: during the adjustment process, the frequency and voltage of the circuit operation are dynamically adjusted according to the real-time load state. Under the premise of meeting the circuit operation stability, the frequency and voltage are appropriately reduced, and the circuit operation state is flipped and calculated. In one calculation, the circuit operation power is set to P, and the energy consumed by the circuit operation is expressed as E.

7. The low power consumption design method for integrated circuits based on dynamic voltage and frequency adjustment according to claim 6, characterized in that: The calculation formula in step S5 is expressed as: P=aCV 2 f; E=P·T d =aCV 2 f·T d ; Where C is the total load capacitance of the integrated circuit, a is the flip factor, V is the circuit voltage, f is the circuit operating frequency, T d The time taken to complete a scheduled task.

8. The low power consumption design method for integrated circuits based on dynamic voltage and frequency adjustment according to claim 6, characterized in that: In the flip calculation based on step S5, the current circuit load is calculated according to the signal value, and the value of the current circuit load is obtained after the calculation is completed. According to the current load value, the computing performance required by the integrated circuit in the next time period is predicted, and the predicted result is converted into the required frequency, so as to adjust the frequency setting of the circuit in real time, and the corresponding voltage value of the circuit is calculated according to the real-time adjusted frequency, and the integrated circuit control system is notified to adjust the voltage of the circuit.

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