Semiconductor device with row decoder circuit
By designing multiple levels of level displacement circuits and main word line drive circuits in the semiconductor memory device, it solves the problem of low efficiency and large area occupation of the existing technology decoder circuit, and achieves more efficient line address decoding. And the main word line driver.
Patent Information
- Application Number
- CN202410991216.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-25
- Filing Date
- 2024-07-23
- Publication Date
- 2025-01-28
AI Technical Summary
In the existing semiconductor memory devices, the design of the row decoder circuit has problems of inefficiency and large area occupancy, especially in terms of level shifting between multiple memory cell arrays and main word line driving.
The line -definter circuit that includes multiple levels of level shifting circuits and the main word wire drive is designed. The pre -decoding signal is converted into a suitable level through the level shift circuit to use Effective decoding and high -efficiency driving of the main word line.
The design improves the efficiency and density of the line decoder circuit, reduces the area occupation of the chip, and improves the overall performance of the memory device.
Smart Images
Figure CN119380781A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a semiconductor device having a row decoder circuit. Background Art
[0002] There are cases where a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) has a configuration in which a word line is selected based on a row address and a bit line is selected based on a column address. There are cases where the word line is hierarchical in a main word line selected by a higher-order bit of a row address and a sub-word line selected by a lower-order bit of the row address. There are cases where a main word driver that drives the main word line includes a level shift circuit that converts the amplitude of a pre-decoding signal obtained by pre-decoding the higher-order bit of the row address and a main word driver circuit that drives the main word line based on the level-shifted pre-decoding signal. Summary of the invention
[0003] In one aspect, the present application provides a device comprising: a first memory cell array; a second memory cell array, the second memory cell array and the first memory cell array are arranged in a first direction; a plurality of first sub-word line drivers and a plurality of second sub-word line drivers, a plurality of main word line drivers and a plurality of level shifting circuits, the plurality of level shifting circuits being each arranged in an intermediate area between the first memory cell array and the second memory cell array, wherein the plurality of first sub-word line drivers are arranged in a second direction perpendicular to the first direction and along the first memory cell array, wherein the plurality of second sub-word line drivers are arranged in the second direction and along the second memory cell array, wherein the plurality of main word line drivers are arranged in the second direction and adjacently along the plurality of second sub-word line drivers, and wherein the plurality of level shifting circuits are arranged in the second direction and adjacently along the plurality of first sub-word line drivers, and wherein the plurality of level shifting circuits are configured to provide voltage level shifting signals to the plurality of main word line drivers, respectively.
[0004] In one aspect, the present application provides an apparatus comprising: a first circuit area, which is at least partially divided into a first well area of a first conductivity type, a second well area of the first conductivity type, and a third well area of a second conductivity type arranged between the first well area and the second well area; and a second circuit area, which is at least partially divided into a fourth well area of the first conductivity type, a fifth well area of the first conductivity type, and a sixth well area of the second conductivity type arranged between the fourth well area and the fifth well area, the second circuit area being arranged to be a specific distance away from the first circuit area in a first direction; wherein a portion of the first well area and the third well area contains a plurality of first sub-word line drivers arranged in a second direction perpendicular to the first direction; wherein a portion of the fourth well area and the sixth well area contains a plurality of second sub-word line drivers arranged in the second direction; wherein another portion of the second well area and the third well area contains a plurality of level shift circuits arranged in the second direction, the plurality of level shift circuits being configured to respectively generate a plurality of level shift decoding signals; and wherein another portion of the fifth well area and the sixth well area contains a plurality of main word line drivers arranged in the second direction, the plurality of main word line drivers being configured to respectively receive the plurality of level shift decoding signals.
[0005] In one aspect, the present application provides a device comprising: first and second memory cell array areas; a row decoder area arranged between the first and second memory cell array areas in a first direction, wherein the row decoder area includes a first area adjacent to the first memory cell array area, a second area adjacent to the second memory cell array area, and a third area adjacent to the second area, so that the second area is arranged between the second memory cell array area and the third area in the first direction; a plurality of first level shifting circuits arranged on the first area; a plurality of second level shifting circuits arranged on the third area; and a plurality of main word driver circuits arranged on the second area, wherein a predetermined one of the plurality of first level shifting circuits is configured to control a first one of the plurality of main word driver circuits, and wherein a predetermined one of the plurality of second level shifting circuits is configured to control a second one of the plurality of main word driver circuits. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 is a schematic diagram showing the configuration of a main part of a semiconductor memory device according to an embodiment of the present disclosure;
[0007] Figure 2 is a schematic diagram for explaining the configuration of a unit row decoder area in more detail;
[0008] Figure 3is a schematic circuit diagram for explaining the functions of circuits included in a row decoder region;
[0009] Figure 4 and 5 is a circuit diagram of a level shift circuit;
[0010] Figure 6 is a circuit diagram of a main word driver circuit;
[0011] Figure 7 is a schematic diagram for explaining the configuration of a unit row decoder area and a sub-word driver area; and
[0012] Figure 8 FIG. 1 is a diagram for explaining another configuration of the unit row decoder area and the sub-word driver area. DETAILED DESCRIPTION
[0013] Various embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show specific aspects and various embodiments of the present disclosure by way of illustration. The detailed description provides sufficient details to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized, and structural changes, logical changes, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, because some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.
[0014] Figure 1 is a schematic diagram showing the configuration of a main part of a semiconductor memory device according to an embodiment of the present disclosure. Figure 1 The semiconductor memory device shown in FIG. 1 is a DRAM and includes array areas 1 and 2 each including a plurality of memory cell arrays 10 and a row decoder area 4 sandwiched between the array areas 1 and 2 in the X direction. In the array areas 1 and 2, a sub-word driver area 11 is disposed on each side of the memory cell array 10 in the X direction, and a sense amplifier area 12 is disposed on each side of the memory cell array 10 in the Y direction. The row decoder area 4 includes a plurality of unit row decoder areas 20 arranged in the Y direction. The X direction and the Y direction may be perpendicular to each other.
[0015] Figure 2 2 is a schematic diagram for explaining the configuration of the unit row decoder area 20 in more detail. Figure 2, the unit row decoder area 20 includes an area 21 in which a plurality of level shift circuits 31 are arranged, an area 22 in which a plurality of main word driver circuits 32 are arranged, an area 23 in which a plurality of word selection circuits 33 are arranged, and an area 24 in which a plurality of sense amplifier control circuits 34 are arranged. A pre-decoding signal RF345, a pre-decoding signal RF678, and a pre-decoding signal RF910 are supplied to the level shift circuit 31, wherein the pre-decoding signal RF345 is obtained by pre-decoding address bits X3 to X5 constituting a row address, the pre-decoding signal RF678 is obtained by pre-decoding address bits X6 to X8 constituting a row address, and the pre-decoding signal RF910 is obtained by pre-decoding address bits X9 to X10 constituting a row address. The level shift circuit 31 controls the main word driver circuit 32 based on these pre-decoding signals RF345, RF678, and RF910. The main word driver circuit 32 supplies the main word signal MW to the main word line MWL extending in the X direction. The word select circuit 33 supplies a sub-word select signal FX to a word select line WSL extending in the X direction based on other bits of the row address (eg, address bits X0 to X2). The sense amplifier control circuit 34 supplies a control signal ARAC to the sense amplifier regions 121 and 123 associated therewith.
[0016] exist Figure 2In the example shown in , the memory cell array 101 is arranged on the -X direction side of the unit row decoder area 20, and the memory cell array 101 is arranged on the +X direction side of the unit row decoder area 20. The memory cell array 103 is arranged on the -Y direction side of the memory cell array 101. The sub-word driver areas 111 and 113 are respectively arranged on both sides of the memory cell array 101 in the X direction. The sub-word driver areas 112 and 114 are respectively arranged on both sides of the memory cell array 102 in the X direction. The sub-word driver area 111 is adjacent to the area 21 and is sandwiched between the memory cell array 101 and the unit row decoder area 20 in the X direction. The sub-word driver area 112 is adjacent to the area 22 and is sandwiched between the memory cell array 102 and the unit row decoder area 20 in the X direction. A plurality of sub-word drivers 35 are arranged in the sub-word driver areas 111 to 114. The sub-word drivers 35 each activate an associated sub-word line SWL based on a sub-word selection signal FX supplied via a word selection line WSL and a main word line signal MW supplied via a main word line MWL. Sense amplifier regions 121 and 122 are respectively disposed on both sides of the memory cell array 101 in the Y direction. Sense amplifier regions 123 and 124 are respectively disposed on both sides of the memory cell array 102 in the Y direction. A plurality of sense amplifiers 36 are disposed in the sense amplifier regions 121 to 124. Each of the sense amplifiers 36 amplifies a potential difference appearing on a pair of bit lines BL. The memory cell MC is disposed at the intersection of the sub-word line SWL and the bit line BL. By this configuration, when the data held in the memory cell MC in response to the activation of the sub-word line SWL is read through the bit line BL, the data read through the bit line BL is amplified by an associated one of the sense amplifiers 36.
[0017] Figure 3 is a schematic circuit diagram for explaining the functions of the circuits included in the row decoder area. Figure 3In the example shown in FIG. 4 , address bits X3 to X5 constituting the row address are supplied to the predecoder 41. The predecoder 41 generates a predecode signal RF345 based on the address bits X3 to X5. The predecode signal RF345 has, for example, a predecode bit RF345. <0> To RF345 <7> The 8-bit configuration is formed, where the pre-decoding bit RF345 <0> To RF345 <7> Any one of them is activated. The address bits X6 to X8 constituting the row address are supplied to the predecoder 42. The predecoder 42 generates a predecode signal RF678 based on the address bits X6 to X8. The predecode signal RF678 has, for example, <0> To RF678 <7> The 8-bit configuration is formed, where the pre-decoding bit RF678 <0> To RF678 <7> Any one of them is activated. The address bits X9 and X10 constituting the row address are supplied to the predecoder 43. The predecoder 43 generates a predecode signal RF910 based on the address bits X9 and X10. The predecode signal RF910 has, for example, a predecode bit RF910. <0> To RF910 <3> 4-bit configuration, where the pre-decoding bit RF910 <0> To RF910 <3> Any one of them is activated.
[0018] exist Figure 3 43, two level shift circuits 45 and 46 are included in the level shift circuit 31. The pre-decoding signal RF345 is converted into a pre-decoding signal RF345P by the level shift circuit 45. The pre-decoding signals RF678 and RF910 are converted into a pre-decoding signal RF610P by the level shift circuit 46. The pre-decoding signals RF345P and RF610P are supplied to the main word driver circuit 32 via the signal line S. The main word driver circuit 32 activates the associated main word line MWL based on the pre-decoding signal RF345P and the pre-decoding signal RF610P. The power supply potential VCCP of the level shift circuit 31 and the power supply potential VccpRdec of the main word driver circuit 32 are higher than the power supply potential VDD2 of the pre-decoders 41 to 43. In some embodiments, the power supply potential VccpRdec has the same level as the power supply potential VCCP. The power supply potential VccpRdec may be independent of the VCCP voltage node. That is, the level shift circuit 31 converts the pre-decoding signals RF345, RF678 and RF910 having the amplitude VDD2 into pre-decoding signals RF345P and RF610P having the amplitude VCCP.
[0019] Figure 4 4 is a circuit diagram of the level shift circuit 45. Figure 4, the level shift circuit 45 includes cascade-coupled inverter circuits 51 and 52, an N-channel MOS transistor 53, and a P-channel MOS transistor 54. A control signal C1 is supplied to an input node of the inverter circuit 51. An output node of the inverter circuit 51 and an input node of the inverter circuit 52 are coupled to each other via a signal line 55. A power supply potential VCCP is supplied to high-potential-side power supply nodes of the inverter circuits 51 and 52. The transistor 53 is coupled between a low-potential-side power supply node of the inverter circuit 51 and a power supply line 56 to which a ground potential VSS is supplied. Any bit (RF345) constituting the pre-decoding signal RF345 <0> To RF345 <7> Any of the above) is supplied to the gate electrode of the transistor 53. With this configuration, the inverter circuit 51 included in each level shift circuit 45 is activated when the associated bit of the pre-decoding signal RF345 is at a high level. The transistor 54 is coupled between the power supply line 57 to which the power supply potential VCCP is supplied and the signal line 55. The gate electrode of the transistor 54 is coupled to the output node of the inverter circuit 52. The associated bit (RF345P) of the level-converted pre-decoding signal RF345P is activated. <0> To RF345P <7> ) is output from the output node of the inverter circuit 52. With this circuit configuration, the pre-decoding signal RF345 having the amplitude VDD2 is converted into the pre-decoding signal RF345P having the amplitude VCCP in response to the control signal C1.
[0020] Figure 5 4 is a circuit diagram of the level shift circuit 46. Figure 5, the level shift circuit 46 includes cascade-coupled inverter circuits 61 and 62, N-channel MOS transistors 63 and 64, and a P-channel MOS transistor 65. The control signal C2 is supplied to the input node of the inverter circuit 61. The output node of the inverter circuit 61 and the input node of the inverter circuit 62 are coupled to each other via a signal line 66. The power supply potential VCCP is supplied to the high potential side power supply node of the inverter circuits 61 and 62. The transistors 63 and 64 are coupled in series between the low potential side power supply node of the inverter circuit 61 and the power supply line 67 to which the ground potential VSS is supplied. Any bit (RF678) constituting the pre-decoding signal RF678 <0> To RF678 <7> Any bit (RF910) constituting the pre-decoding signal RF910 is supplied to the gate electrode of the transistor 63. <0> To RF910 <3> Any of the above) is supplied to the gate electrode of the transistor 64. Therefore, the inverter circuit 61 included in each level shift circuit 46 is activated when both the associated bit of the pre-decoding signal RF678 and the associated bit of the pre-decoding signal RF910 are at a high level. The transistor 65 is coupled between the power supply line 68 to which the power supply potential VCCP is supplied and the signal line 66. The gate electrode of the transistor 65 is coupled to the output node of the inverter circuit 62. The associated bit (e.g., RF610P) of the level-converted pre-decoding signal RF610P is <0> To RF610P <24> Any of ) is output from the output node of the inverter circuit 62. With this circuit configuration, the pre-decoding signals RF678 and RF910 having the amplitude VDD2 are converted into the pre-decoding signal RF610P having the amplitude VCCP in response to the control signal C2.
[0021] Figure 6 3 is a circuit diagram of the main word driver circuit 32. Figure 6 , the main word driver circuit 32 is configured by a NAND gate circuit that receives any bit constituting the pre-decoding signal RF345P and any bit constituting the pre-decoding signal RF610P. The main word signal MW serving as the output of the main word driver circuit 32 is supplied to the associated main word line MWL.
[0022] Figure 7 1 is a schematic diagram for explaining the configuration of the unit row decoder section 20 and the sub-word driver sections 111 and 112. Figure 7, N-well regions NW1 and NW2 whose source potential is the power supply potential VCCP are provided to overlap with the boundaries between the array regions 1 and 2 and the row decoder region 4, respectively. The N-well region NW1 includes regions N1 and N2 arranged in the X direction. In region N1, P-channel MOS transistors constituting the level shift circuit 31 are arranged. In region N2, P-channel MOS transistors constituting the sub-word driver 35 in the sub-word driver region 111 are arranged. Although the boundary between region N1 and region N2 extends in the Y direction, the N-well region NW1 is a single well and there is no physical boundary, such as another well between region N1 and region N2. The N-channel MOS transistors constituting the level shift circuit 31 are arranged in region P1 adjacent to region N1. The N-channel MOS transistors constituting the sub-word driver 35 in the sub-word driver region 111 are arranged in region P2 adjacent to region N2. The N-well region NW1 is sandwiched between regions P1 and P2 in the X direction.
[0023] Similarly, the N-well region NW2 includes a region N3 and a region N4 arranged in the X direction. The P-channel MOS transistors constituting the main word driver circuit 32 are arranged in the region N3. The P-channel MOS transistors constituting the sub-word driver 35 in the sub-word driver region 112 are arranged in the region N4. Although the boundary between the region N3 and the region N4 extends in the Y direction, the N-well region NW2 is a single well and there is no physical boundary, such as another well between the region N3 and the region N4. The N-channel MOS transistors constituting the main word driver circuit 32 are arranged in the region P3 adjacent to the region N2. The N-channel MOS transistors constituting the sub-word driver 35 in the sub-word driver region 112 are arranged in the region P4 adjacent to the region N4. The N-well region NW2 is sandwiched between the regions P3 and P4 in the X direction.
[0024] The regions P1 to P4 are semiconductor substrates or P-well regions in which the source potential thereof is the ground potential VSS. The width Wn1 of the region N1 in the X direction is allowed to be different from the width Wn3 of the region N3 in the X direction. The width Wp1 of the region P1 in the X direction is allowed to be different from the width Wp3 of the region P3 in the X direction. In the region 23 in which the word selection circuit 33 is arranged and the region 24 in which the bit selection circuit 34 is arranged, a plurality of N-well regions in which the source potential thereof is the power supply potential VDD2 or the like and a semiconductor substrate or P-well region in which the source potential thereof is the ground potential VSS are arranged.
[0025] As described above, in Figure 7In the example shown in , the area 21 in which the level shift circuit 31 is arranged is positioned at the -X direction side end of the unit row decoder area 20, and the area 22 in which the main word driver circuit 32 is arranged is positioned at the +X direction side end of the unit row decoder area 20. Therefore, the signal line S that couples the level shift circuit 31 and the main word driver circuit 32 to each other extends in the X direction to pass through the area 23 or the area 24. In addition, since the N-type area N1 included in the area 21 and the N-type area N2 included in the sub-word driver area 111 are adjacent to each other in the X direction and integrated with each other, it is not necessary to provide an isolation area or the like between the unit row decoder area 20 and the sub-word driver area 111. Similarly, since the N-type area N3 included in the area 22 and the N-type area N4 included in the sub-word driver area 112 are adjacent to each other in the X direction and integrated with each other, it is not necessary to provide an isolation area or the like between the unit row decoder area 20 and the sub-word driver area 112. With this configuration, the chip size can be further reduced.
[0026] Figure 8 1 is a diagram for explaining another configuration of the unit row decoder section 20 and the sub-word driver sections 111 and 112. Figure 8 In the example shown in FIG. 1 , the level shift circuits 31 are arranged to be distributed in two regions 21A and 21B. One region 21A is located at the -X direction side end of the unit row decoder region 20 and includes a region N1 and a region P1. In the region 21A, half of the plurality of level shift circuits 31 included in the unit row decoder region 20 are arranged. The other region 21B is located between the region 22 and the regions 23 and 24, and the remaining half of the level shift circuits 31 included in the unit row decoder region 20 are arranged in the other region 21B. With this configuration, the width Wn1 of the region N1 in the X direction and the width Wp1 of the region P1 in the X direction are Figure 7 About half of the examples shown in Figure 8 , the width Wn1 is smaller than the width Wn3, and the width Wp1 is smaller than the width Wp3. By this configuration, among the signal lines S coupling the level shift circuit 31 and the main word driver circuit 32 to each other, the length of the signal line S associated with the level shift circuit 31 arranged in the region 21B in the X direction is shortened. Therefore, the wiring design flexibility on the regions 23 and 24 is enhanced. In addition, in this example, the N-type region N1 included in the region 21A and the N-type region N2 included in the sub-word driver region 111 are integrated with each other, so that similar to Figure 7 As shown in the example, the chip size can be further reduced.
[0027] Although various embodiments have been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the scope of the present disclosure extends beyond the explicitly disclosed embodiments to other alternative embodiments and / or uses of the embodiments and obvious modifications and equivalents thereof. In addition, other modifications within the scope of the present disclosure will be readily apparent to those skilled in the art based on the present disclosure. It is also contemplated that various combinations or sub-combinations may be made to the specific features and aspects of the embodiments and that they still fall within the scope of the present disclosure. It should be understood that the various features and aspects of the disclosed embodiments may be combined or substituted with one another to form different modes of the disclosed embodiments. Therefore, it is desired that the scope of at least some of the present disclosure should not be limited by the above-mentioned specific disclosed embodiments.
Claims
1. A device comprising: a first memory cell array; a second memory cell array, wherein the second memory cell array and the first memory cell array are arranged in a first direction; a plurality of first sub-word line drivers and a plurality of second sub-word line drivers, a plurality of main word line drivers, and a plurality of level shift circuits, wherein each of the plurality of level shift circuits is arranged in an intermediate area between the first memory cell array and the second memory cell array, wherein the plurality of first sub-word line drivers are arranged in a second direction perpendicular to the first direction and along the first memory cell array, wherein the plurality of second sub-word line drivers are arranged in the second direction and along the second memory cell array, wherein the plurality of main word line drivers are arranged in the second direction and adjacently arranged along the plurality of second sub word line drivers, and Wherein the plurality of level shift circuits are arranged in the second direction and adjacently arranged along the plurality of first sub word line drivers, the plurality of level shift circuits are configured to provide voltage level shift signals to the plurality of main word line drivers, respectively.
2. The device according to claim 1, wherein the middle region includes a first circuit region on which the plurality of level shift circuits are arranged, The first circuit region includes a first transistor region of a first conductivity type and a second transistor region of a second conductivity type opposite to the first conductivity type, and The first transistor region and the second transistor region are arranged in the first direction.
3. The device according to claim 2, wherein the middle area further includes a first sub-word line driver area on which the plurality of first sub-word line drivers are arranged, wherein the first sub-word line driver region includes a third transistor region having the first conductivity type and a fourth transistor region having the second conductivity type, and The third transistor region and the fourth transistor region are arranged in the first direction.
4. The apparatus of claim 3, wherein the first transistor region and the third transistor region are integrated.
5. The device according to claim 4, wherein the middle area includes a second circuit area on which the plurality of main word line drivers are arranged, wherein the second circuit region includes a fifth transistor region of the first conductivity type and a sixth transistor region of the second conductivity type, and The fifth transistor region and the sixth transistor region are arranged in the first direction.
6. The device according to claim 5, wherein the middle area further includes a second sub word line driver area on which the plurality of second sub word line drivers are arranged, wherein the second sub-word line driver region includes a seventh transistor region having the first conductivity type and an eighth transistor region having the second conductivity type, and The seventh transistor region and the eighth transistor region are arranged in the first direction.
7. The apparatus of claim 6, wherein the fifth transistor region and the seventh transistor region are integrated.
8. The apparatus of claim 7, further comprising: a plurality of word select circuits each configured to generate an associated one of a plurality of word select signals; and a plurality of word selection lines supplied with associated ones of the plurality of word selection signals and extending in the first direction so as to overlap the first memory cell array and the second memory cell array, wherein the middle region further includes a third circuit region arranged between the first circuit region and the second circuit region in the first direction, and The plurality of word selection circuits are arranged on the third circuit area.
9. The apparatus of claim 8, further comprising supplying one of the voltage level shift signals from one of the plurality of level shift circuits to a first signal line of one of the plurality of main word line drivers, The first signal line extends in the first direction so as to cross the third circuit area.
10. The apparatus of claim 8, further comprising a sense amplifier region on which a plurality of sense amplifiers are arranged, Wherein the first memory cell array further includes a bit line coupled to an associated one of the plurality of sense amplifiers and a memory cell coupled to a first sub-word line and the bit line.
11. The apparatus of claim 10, further comprising a plurality of bit selection circuits configured to control the plurality of sense amplifiers, wherein the middle region further includes a fourth circuit region arranged between the first circuit region and the second circuit region in the first direction, and The plurality of bit selection circuits are arranged on the fourth region. 12 . The apparatus of claim 11 , wherein the third region and the fourth region are arranged in a second direction perpendicular to the first direction.
13. The apparatus of claim 11 , further comprising a second signal line that supplies another one of the voltage level shift signals from another one of the plurality of level shift circuits to one of the plurality of main word line drivers, The second signal line extends in the first direction so as to cross the fourth circuit area.
14. The apparatus of claim 7, further comprising a plurality of additional level shifting circuits arranged between the second circuit area and the third and fourth circuit areas.
15. An apparatus comprising: a first circuit region at least partially divided into a first well region of a first conductivity type, a second well region of the first conductivity type, and a third well region of a second conductivity type disposed between the first well region and the second well region; and a second circuit region at least partially divided into a fourth well region of the first conductivity type, a fifth well region of the first conductivity type, and a sixth well region of the second conductivity type arranged between the fourth well region and the fifth well region, the second circuit region being arranged at a specific distance from the first circuit region in a first direction; wherein the first well region and a portion of the third well region contain a plurality of first sub-word line drivers arranged in a second direction perpendicular to the first direction; wherein the fourth well region and a portion of the sixth well region contain a plurality of second sub-word line drivers arranged in the second direction; wherein the second well region and another part of the third well region contain a plurality of level shift circuits arranged in the second direction, the plurality of level shift circuits being configured to respectively generate a plurality of level shift decoding signals; and The fifth well region and another portion of the sixth well region contain a plurality of main word line drivers arranged in the second direction, and the plurality of main word line drivers are configured to receive the plurality of level-shift decoding signals, respectively.
16. The apparatus of claim 15, further comprising: a third circuit area, arranged between the first circuit area and the second circuit area in the first direction; and a signal line that supplies one of the plurality of level-shifted decoded signals from one of the plurality of level-shifting circuits to one of the plurality of main word line drivers, The signal line extends in the first direction so as to cross the third circuit region. 17 . The apparatus of claim 15 , wherein a width of the portion of the third well region in the first direction is different from a width of the portion of the sixth well region in the first direction. 18 . The apparatus of claim 17 , wherein a width of the second well region in the first direction is different from a width of the fifth region in the first direction.
19. An apparatus comprising: first and second memory cell array regions; a row decoder region arranged between the first and second memory cell array regions in a first direction, wherein the row decoder region includes a first region adjacent to the first memory cell array region, a second region adjacent to the second memory cell array region, and a third region adjacent to the second region, such that the second region is arranged between the second memory cell array region and the third region in the first direction; a plurality of first level shift circuits arranged on the first region; a plurality of second level shift circuits arranged on the third region; and a plurality of main word driver circuits arranged on the second area, wherein a predetermined one of the plurality of first level shift circuits is configured to control a first one of the plurality of main word driver circuits, and Wherein a predetermined one of the plurality of second level shift circuits is configured to control a second one of the plurality of main word driver circuits.
20. The apparatus of claim 19, further comprising a plurality of word select circuits configured to be controlled by a first portion of a row address, wherein the row decoder area further includes a fourth area arranged between the first area and the third area in the first direction, wherein the plurality of main word driver circuits are configured to be controlled by a second portion of the row address, and Wherein each of the first and second memory cell array regions includes a plurality of sub-word driver circuits each configured to be controlled by an associated one of the plurality of main word driver circuits and an associated one of the plurality of word selection circuits.