IGBT device and manufacturing method thereof
By forming isolation side walls and sacrificial layers in IGBT device manufacturing, back-etching and filling the dielectric layer, self-alignment etching is achieved to form contact holes, which solves the problems of increasing difficulty in manufacturing process and high alignment accuracy requirements of IGBT device manufacturing, and improves Saturation pressure drop consistency and manufacturing efficiency.
Patent Information
- Application Number
- CN202411516592.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-02-07
AI Technical Summary
The difficulty of manufacturing process of IGBT devices is increasing, and the alignment accuracy of the body area contact hole mask plate and the trench gate mask plate is required, resulting in a decrease in the consistency of saturation voltage drop.
By forming isolation side walls and sacrificial layers on the substrate, back-etching the gate conductive layer forms grooves, and filling the dielectric layer in the grooves, removing the sacrificial layer to form openings, realizing self-alignment etching to form contact holes, reducing the need for a lowering Accuracy requirements.
It improves the consistency of saturation pressure drop in and between IGBT wafers, simplifies the manufacturing process, and improves batch generation yield and efficiency.
Smart Images
Figure CN119403147A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an IGBT device and a manufacturing method thereof. Background Art
[0002] IGBT (Insulated Gate Bipolar Transistor) is a hybrid power device with the characteristics of MOS structure input and bipolar structure output. Therefore, IGBT devices have the advantages of high MOSFET input impedance, low drive circuit power, simple drive operation, fast switching speed and low switching power consumption, and have the advantages of high current density, strong current handling capability and low on-saturation voltage drop of bipolar power transistors. This makes IGBT devices widely used in new energy vehicles, industrial frequency conversion, photovoltaics, smart grids, locomotives and other fields.
[0003] After nearly four decades of development, IGBT devices have evolved from planar to trench type, and the pitch between repeated structural units is getting smaller and smaller, which makes the distance between the body contact hole and the trench gate smaller and smaller, and the problem of wafer warpage is becoming more and more serious. This leads to higher and higher requirements for the alignment accuracy of the body contact hole mask and the alignment accuracy of the trench gate mask, which ultimately leads to the increasing difficulty of the process of IGBT device manufacturing. If the alignment of the body contact hole mask and the trench gate mask is poor, the distance between the body contact hole and the trench gate will be too narrow, which will lead to the discrete saturation voltage drop (Vcesat) in the IGBT device. Moreover, the consistency of the distance between the body contact hole and the trench gate between multiple IGBT devices and between different storage units of the same IGBT device depends entirely on the consistency of the alignment of the body contact hole mask and the trench gate mask.
[0004] Therefore, how to reduce the difficulty of the IGBT device manufacturing process and lower the requirements for the alignment accuracy of the body contact hole mask and the trench gate mask, thereby improving the consistency of the saturation voltage drop within the IGBT wafer and between IGBT wafers, is a technical problem that needs to be solved urgently. Summary of the invention
[0005] The present invention provides an IGBT device and a manufacturing method thereof, which are used to reduce the difficulty of the IGBT device manufacturing process and reduce the requirements for the alignment accuracy of the body region contact hole mask and the trench gate mask, thereby improving the consistency of the saturation voltage drop within the IGBT wafer and between the IGBT wafers, and improving the yield and efficiency of batch production of IGBT devices.
[0006] According to some embodiments, the present invention provides a method for manufacturing an IGBT device, comprising the following steps:
[0007] Forming a substrate, the substrate comprising a top surface and a bottom surface relatively distributed along a first direction and a plurality of trench gate structures spaced apart along a second direction, the trench gate structure comprising a gate trench extending from the top surface of the substrate to the inside of the substrate along the first direction, a gate dielectric layer covering the inner wall of the gate trench, and a gate conductive layer filled in the gate trench and covering the gate dielectric layer, the gate conductive layer protruding from the top surface of the substrate along the first direction, and the second direction being parallel to the top surface of the substrate;
[0008] forming an isolation sidewall covering the sidewall of the gate conductive layer and a sacrificial layer located between adjacent isolation sidewalls on the top surface of the substrate;
[0009] Etching back the gate conductive layer to form a groove above the remaining gate conductive layer, and the top surface of the remaining gate conductive layer is lower than the top surface of the substrate;
[0010] forming a filling medium layer filled in the groove;
[0011] removing the sacrificial layer to form an opening exposing the substrate;
[0012] The substrate is etched downward along the opening to form a contact hole.
[0013] In some embodiments, the specific steps of forming the substrate include:
[0014] providing an initial substrate;
[0015] Implanting doping ions into the initial substrate in sequence, forming a carrier storage region, a body region located above the carrier storage region along the first direction, and an emitter region located above the body region along the first direction in the initial substrate, the remaining initial substrate below the carrier storage region serves as a substrate, forming the base including the substrate, the carrier storage region, the body region, and the emitter region, and the surface of the emitter region facing away from the substrate serves as the top surface of the base;
[0016] forming a mask layer located above the emitter region, wherein the mask layer has a plurality of etching windows arranged at intervals along the second direction and penetrating the mask layer along the first direction;
[0017] Etching the substrate along the etching window to form the gate trench that penetrates the emitter region, the body region, and the carrier storage region along the first direction and extends into the substrate;
[0018] forming the gate dielectric layer covering the inner wall of the gate trench and the gate conductive layer filling the gate trench and the etching window;
[0019] The mask layer is removed.
[0020] In some embodiments, the specific steps of forming the substrate include:
[0021] providing an initial substrate;
[0022] forming a mask layer located above the initial substrate, wherein the mask layer has a plurality of etching windows arranged at intervals along the second direction and penetrating the mask layer along the first direction;
[0023] Etching the initial substrate along the etching window to form the gate trench;
[0024] forming the gate dielectric layer covering the inner wall of the gate trench and the gate conductive layer filling the gate trench and the etching window;
[0025] removing the mask layer;
[0026] Doping ions are sequentially implanted into the initial substrate to form a carrier storage region, a body region located above the carrier storage region along the first direction, and an emitter region located above the body region along the first direction in the initial substrate, the remaining initial substrate below the carrier storage region serves as a substrate to form a base including the substrate, the carrier storage region, the body region, and the emitter region, the surface of the emitter region facing away from the substrate serves as the top surface of the base, and the bottom surface of the gate trench is lower than the bottom surface of the carrier storage region.
[0027] In some embodiments, the specific steps of forming an isolation sidewall covering the sidewall of the gate conductive layer and a sacrificial layer located between adjacent isolation sidewalls on the top surface of the substrate include:
[0028] Depositing an oxide material on the top surface of the substrate to form the isolation sidewall covering the sidewall of the gate conductive layer;
[0029] A nitride material is deposited on the top surface of the substrate to form the sacrificial layer filled between adjacent isolation sidewalls.
[0030] In some embodiments, the thickness of the isolation sidewall along the second direction is
[0031] In some embodiments, the specific steps of forming the filling dielectric layer filled in the groove include:
[0032] Borophosphosilicate glass is deposited on the substrate to form the filling dielectric layer filled in the groove, and the top surface of the filling dielectric layer, the top surface of the isolation sidewall and the top surface of the sacrificial layer are flush.
[0033] In some embodiments, the material of the body region is a silicon material including a first doping ion, and the material of the emitter region is a silicon material including a second doping ion, and the conductivity type of the second doping ion is opposite to the conductivity type of the first doping ion; the specific steps of etching the substrate downward along the opening to form the contact hole include:
[0034] The substrate is etched downward along the opening using a self-aligned etching process to form the contact hole that penetrates the emitter region along the first direction and extends into the body region.
[0035] In some embodiments, the sidewall of the contact hole intersects the top surface of the substrate vertically; or,
[0036] The sidewall of the contact hole obliquely intersects with the top surface of the substrate.
[0037] In some embodiments, after forming the contact hole, the following steps are further included:
[0038] forming a conductive contact layer at the bottom of the contact hole;
[0039] A front metal layer is formed which at least covers the conductive contact layer and the emitter region and fully fills the contact hole and the opening.
[0040] According to some other embodiments, the present invention further provides an IGBT device, including:
[0041] A substrate, the substrate comprising a top surface and a bottom surface relatively distributed along a first direction and a plurality of trench gate structures spaced apart along a second direction, the trench gate structure comprising a gate trench extending from the top surface of the substrate to the inside of the substrate along the first direction, a gate dielectric layer covering the inner wall of the gate trench, and a gate conductive layer filled in the gate trench and covering the gate dielectric layer, the gate conductive layer being lower than the top surface of the substrate along the first direction, and being parallel to the top surface of the substrate in the second direction;
[0042] A filling dielectric layer, wherein a plurality of the filling dielectric layers are respectively covered on the top surfaces of the plurality of gate conductive layers, and a portion of the filling dielectric layers protrudes from the top surface of the substrate;
[0043] An isolation sidewall is located on the top surface of the substrate, and a plurality of the isolation sidewalls are respectively covered on the sidewalls of a plurality of the filling dielectric layers;
[0044] The lead-out structure is filled between the adjacent isolation sidewalls and extends from the top surface of the substrate to the inside of the substrate along the first direction, and the lead-out structure is electrically connected to the substrate.
[0045] In some embodiments, the base includes a substrate, a carrier storage region located above the substrate along the first direction, a body region located above the carrier storage region along the first direction, and an emitter region located above the body region along the first direction;
[0046] The lead-out structure includes an opening located between adjacent isolation side walls, a contact hole connected to the opening and penetrating the emitter region along the first direction and extending into the body region, a conductive contact layer located at the bottom of the contact hole, and a front metal layer covering the conductive contact layer and the emitter region and filling the contact hole and the opening.
[0047] In some embodiments, the sidewall of the contact hole intersects the top surface of the substrate vertically; or,
[0048] The sidewall of the contact hole obliquely intersects with the top surface of the substrate.
[0049] In some embodiments, a distance between the contact hole and the gate trench is less than 0.2 μm.
[0050] In some embodiments, the front metal layer includes a first metal layer covering the conductive contact layer and the emitter region and filling the contact hole and the opening, and a second metal layer covering the first metal layer, the isolation spacer and the filling dielectric layer;
[0051] The top surface of the first metal layer, the top surface of the isolation sidewall and the top surface of the filling dielectric layer are flush.
[0052] In some embodiments, the material of the isolation sidewall is silicon dioxide, the material of the filling dielectric layer is borophosphosilicate glass, the material of the body region is a silicon material including a first doping ion, and the material of the emitter region is a silicon material including a second doping ion, and the conductivity type of the second doping ion is opposite to the conductivity type of the first doping ion.
[0053] The IGBT device and the manufacturing method thereof provided by the present invention make the gate conductive layer protrude from the top surface of the substrate after depositing the gate conductive layer, and form an isolation sidewall covering the sidewall of the gate conductive layer and a sacrificial layer located between adjacent isolation sidewalls on the top surface of the substrate, after etching back the gate conductive layer to form a groove located above the gate conductive layer, a filling dielectric layer is formed in the groove, and after removing the sacrificial layer, an opening is formed between adjacent isolation sidewalls, so that the substrate can be etched along the opening to form a contact hole, and self-aligned etching of the substrate through the opening is realized, thereby reducing the requirements for the alignment accuracy of the contact hole mask and the gate trench mask, thereby improving the consistency of the saturation voltage drop within the IGBT wafer and between IGBT wafers, and improving the yield and efficiency of batch production of IGBT devices. Moreover, after etching back the gate conductive layer to form the groove, the present invention does not need to use a thermal oxidation process to form a thermal oxidation layer above the gate conductive layer and the substrate, which not only simplifies the manufacturing process of the IGBT device, but also facilitates the control of the consistency of the thickness of the gate conductive layer, thereby further improving the consistency of electrical performance within the IGBT wafer and between IGBT wafers. BRIEF DESCRIPTION OF THE DRAWINGS
[0054] Figure 1 is a flow chart of a method for manufacturing an IGBT device in a specific embodiment of the present invention;
[0055] Figure 2 is a schematic diagram of a structure after a gate trench is formed in a specific embodiment of the present invention;
[0056] Figure 3 is a schematic diagram of a structure after a trench gate structure is formed in a specific embodiment of the present invention;
[0057] Figure 4 is a schematic diagram of a structure after forming an isolation sidewall in a specific embodiment of the present invention;
[0058] Figure 5 is a schematic diagram of a structure after a sacrificial layer is formed in a specific embodiment of the present invention;
[0059] Figure 6 is a schematic diagram of a structure after the gate conductive layer is etched back in a specific embodiment of the present invention;
[0060] Figure 7 is a schematic diagram of a structure after a filling dielectric layer is formed in a specific embodiment of the present invention;
[0061] Figure 8 is a schematic diagram of a structure after the sacrificial layer is removed in a specific embodiment of the present invention;
[0062] Fig. 9 is a schematic diagram of a structure after a contact hole is formed in a specific embodiment of the present invention;
[0063] Fig.10 is a schematic diagram of a structure after forming a front metal layer and a back metal layer in a specific embodiment of the present invention;
[0064] Fig.11 is another structural schematic diagram after forming a contact hole in a specific embodiment of the present invention;
[0065] Fig.12 It is another structural schematic diagram after the front metal layer and the back metal layer are formed in a specific embodiment of the present invention. DETAILED DESCRIPTION
[0066] The specific implementation manner of the IGBT device and the manufacturing method thereof provided by the present invention is described in detail below with reference to the accompanying drawings.
[0067] This specific embodiment provides a method for manufacturing an IGBT device. Figure 1 FIG. 1 is a flow chart of a method for manufacturing an IGBT device in a specific embodiment of the present invention. Figure 1 As shown, the manufacturing method of the IGBT device comprises the following steps:
[0068] Step S11, forming a substrate, the substrate comprising a top surface and a bottom surface relatively distributed along a first direction and a plurality of trench gate structures spaced apart along a second direction, the trench gate structure comprising a gate trench extending from the top surface of the substrate to the inside of the substrate along the first direction, a gate dielectric layer covering the inner wall of the gate trench, and a gate conductive layer filled in the gate trench and covering the gate dielectric layer, the gate conductive layer protruding from the top surface of the substrate along the first direction, and the second direction being parallel to the top surface of the substrate;
[0069] Step S12, forming an isolation sidewall covering the sidewall of the gate conductive layer and a sacrificial layer located between adjacent isolation sidewalls on the top surface of the substrate;
[0070] Step S13, etching back the gate conductive layer to form a groove above the remaining gate conductive layer, and the top surface of the remaining gate conductive layer is lower than the top surface of the substrate;
[0071] Step S14, forming a filling dielectric layer filled in the groove;
[0072] Step S15, removing the sacrificial layer to form an opening exposing the substrate;
[0073] Step S16, etching the substrate downward along the opening to form a contact hole.
[0074] Figure 2 is a schematic diagram of a structure after a gate trench is formed in a specific embodiment of the present invention, Figure 3 1 is a schematic diagram of a structure after forming a trench gate structure in a specific embodiment of the present invention. In some embodiments, the specific steps of forming a substrate include:
[0075] providing an initial substrate;
[0076] Implanting doping ions into the initial substrate in sequence, forming a carrier storage region 21, a body region 22 located above the carrier storage region 21 along the first direction D1, and an emitter region 23 located above the body region 22 along the first direction D1 in the initial substrate, the remaining initial substrate below the carrier storage region 21 serves as the substrate 20, forming the base including the substrate 20, the carrier storage region 21, the body region 22, and the emitter region 23, and the surface of the emitter region 23 facing away from the substrate 20 serves as the top surface of the base;
[0077] forming a mask layer 24 located above the emitter region 23, wherein the mask layer 24 has a plurality of etching windows 26 arranged at intervals along the second direction D2 and penetrating the mask layer 24 along the first direction D1;
[0078] The substrate is etched along the etching window 26 to form the gate trench 25 that penetrates the emitter region 23, the body region 22 and the carrier storage region 21 along the first direction D1 and extends into the substrate 20. Figure 2 As shown;
[0079] The gate dielectric layer 30 covering the inner wall of the gate trench 25 and the gate conductive layer 31 filling the gate trench 25 and the etching window 26 are formed. Figure 3 As shown;
[0080] The mask layer 24 is removed.
[0081] For example, the initial substrate may be a silicon substrate doped with N-type ions. N-type ions (e.g., phosphorus ions) are implanted into the initial substrate to form the carrier storage region 21. In one example, during the process of implanting phosphorus ions into the initial substrate to form the carrier storage region 21, the implantation energy may be 1 MeV to 2 MeV, and the implantation dose may be 1×10 12 Pieces / cm 2 ~5×10 13 Pieces / cm 2, the advancement temperature is 1050°C to 1250°C, and the injection time is 30min to 300min. After forming the carrier storage region 21, P-type ions (such as boron ions) are injected into the initial substrate to form the body region 22 located above the carrier storage region 21 along the first direction D1. In one example, during the process of injecting boron ions into the initial substrate to form the body region 22, the injection energy may be 60keV to 200keV, and the injection dose may be 2×10 13 Pieces / cm 2 ~5×10 14 Pieces / cm 2 , the advancement temperature is 1050℃~1250℃, and the injection time is 1min~120min. After forming the body region 22, N-type ions (such as arsenic ions) are injected into the initial substrate to form the emitter region 23 located above the body region 22 along the first direction D1. In one example, during the process of injecting arsenic ions into the initial substrate to form the emitter region 23, the injection energy can be 60keV~600keV, and the injection dose is 3×10 15 Pieces / cm 2 ~2×10 16 Pieces / cm 2 , the advancement temperature is 900℃~1000℃, and the injection time is 0.5min~120min. Among them, the ion doping concentration in the substrate 20, the ion doping concentration in the carrier storage area 21, the ion doping concentration in the body area 22, and the ion doping concentration in the emitter area 23 can be set according to the parameters such as the on-resistance and reverse withstand voltage performance of the IGBT device to be prepared. The remaining initial substrate below the carrier storage area 21 is used as the substrate 20, and the substrate 20 includes a first main surface 201 facing the carrier storage area 21 and a second main surface 202 opposite to the first main surface 201 along the first direction D1. The surface of the emitter area 23 away from the substrate 20 is used as the top surface of the base, and the surface of the substrate 20 away from the carrier storage area 21 is used as the bottom surface of the base.
[0082] After forming the emitter region 23, a mask material is deposited on the substrate to form the mask layer 24 covering the top surface of the emitter region 23 (i.e., the surface of the emitter region 23 facing away from the substrate 20). The mask layer 24 is patterned to form a plurality of etching windows 26 arranged at intervals along the second direction D2 and penetrating the mask layer 24 along the first direction D1. In the example, the thickness of the mask layer 24 (e.g., the thickness of the mask layer 24 along the first direction D1) is The substrate is etched downward along the plurality of etching windows 26 by dry etching to form a plurality of gate trenches 25 that penetrate the emitter region 23, the body region 22, and the carrier storage region 21 along the first direction D1 and extend into the substrate 20. Figure 2 In one example, the depth of the gate trench 25 (for example, the depth of the gate trench 25 along the first direction D1) is 2 μm to 6 μm. Then, the gate dielectric layer 30 made of silicon dioxide is formed on the inner wall of the gate trench 25 by a thermal oxidation process. In one example, the thickness of the gate dielectric layer 30 (for example, the thickness of the gate dielectric layer 30 along the second direction D2) is Polysilicon material is deposited on the substrate to form the gate conductive layer 31 covering the gate dielectric layer 30 and filling the gate trench 25 and the etching window 26. Figure 3 The gate conductive layer 31 is partially etched back so that the top surface of the gate conductive layer 31 is flush with the top surface of the mask layer 24, so that the height of the gate conductive layer 31 protruding from the top surface of the substrate is also
[0083] In some other embodiments, the specific steps of forming the substrate include:
[0084] providing an initial substrate;
[0085] forming a mask layer 24 located above the initial substrate, wherein the mask layer 24 has a plurality of etching windows 26 arranged at intervals along the second direction D2 and penetrating the mask layer 24 along the first direction D1;
[0086] Etching the initial substrate along the etching window 26 to form the gate trench 25;
[0087] Forming the gate dielectric layer 30 covering the inner wall of the gate trench 25 and the gate conductive layer 31 filling the gate trench 25 and the etching window 26;
[0088] removing the mask layer 24;
[0089] Doping ions are sequentially implanted into the initial substrate to form a carrier storage region 21, a body region 22 located above the carrier storage region 21 along the first direction D1, and an emitter region 23 located above the body region 22 along the first direction D1 in the initial substrate, the remaining initial substrate below the carrier storage region 21 serves as the substrate 20, and the base including the substrate 20, the carrier storage region 21, the body region 22 and the emitter region 23 is formed, the surface of the emitter region 23 facing away from the substrate 20 serves as the top surface of the base, and the bottom surface of the gate trench 25 is lower than the bottom surface of the carrier storage region 21.
[0090] For example, after providing the initial substrate, a layer with a thickness of The mask layer 24 is formed. Then, the mask layer 24 is patterned to form a plurality of etching windows 26 that are arranged at intervals along the second direction D2 and penetrate the mask layer 24 along the first direction D1. The initial substrate is etched downward along the plurality of etching windows 26 using a dry etching process to form a plurality of gate trenches 25 that are arranged at intervals along the second direction D2 and extend to the interior of the initial substrate. Afterwards, a gate dielectric layer 30 made of silicon dioxide is formed on the inner wall of the gate trench 25 using a thermal oxidation process. Polysilicon material is deposited on the initial substrate to form the gate conductive layer 31 that covers the gate dielectric layer 30 and fills the gate trench 25 and the etching windows 26. Then, the mask layer 24 is removed, and N-type ions (such as phosphorus ions) are implanted into the initial substrate to form the carrier storage area 21. After forming the carrier storage region 21, P-type ions (e.g., boron ions) are implanted into the initial substrate to form the body region 22 located above the carrier storage region 21 along the first direction D1. After forming the body region 22, N-type ions (e.g., arsenic ions) are implanted into the initial substrate to form the emitter region 23 located above the body region 22 along the first direction D1.
[0091] Figure 4 is a schematic diagram of a structure after forming an isolation sidewall in a specific embodiment of the present invention, Figure 5 is a schematic diagram of a structure after a sacrificial layer is formed in a specific embodiment of the present invention, Figure 6 3 is a schematic diagram of a structure after etching back the gate conductive layer in a specific embodiment of the present invention. In some embodiments, the specific steps of forming an isolation sidewall 40 covering the sidewall of the gate conductive layer 31 and a sacrificial layer 50 located between adjacent isolation sidewalls 40 on the top surface of the substrate include:
[0092] Depositing an oxide material on the top surface of the substrate to form the isolation sidewall 40 covering the sidewall of the gate conductive layer 31, Figure 4 As shown;
[0093] A nitride material is deposited on the top surface of the substrate to form the sacrificial layer 50 filling between adjacent isolation sidewalls 40. Figure 5 shown.
[0094] For example, a silicon dioxide material is deposited on the substrate to form the isolation spacer 40 covering the sidewall of the gate conductive layer 31, such as Figure 4 In one example, the plurality of isolation sidewalls 40 are distributed around the periphery of the plurality of gate conductive layers 31 protruding from the substrate. The plurality mentioned in this specific embodiment refers to more than two. Next, a silicon nitride material is deposited on the substrate to form the sacrificial layer 50 filling between adjacent isolation sidewalls 40, as shown in FIG. Figure 5 As shown. By etching back the sacrificial layer 50, the top surface of the sacrificial layer 50 (i.e., the surface of the sacrificial layer 50 facing away from the substrate 20) is flush with the top surface of the isolation sidewall 40 (i.e., the surface of the isolation sidewall 40 facing away from the substrate 20), so as to expose the top surface of the gate conductive layer 31, so as to facilitate the subsequent back etching process of the gate conductive layer 31. Next, a portion of the gate conductive layer 31 is etched back, so that the top surface of the remaining gate conductive layer 31 is lower than the top surface of the emitter region 23, and the top surface of the remaining gate conductive layer 31 is higher than the bottom surface of the emitter region, so as to form the groove 60 located above the remaining gate conductive layer 31, as shown. Figure 6 In one example, along the first direction D1, the distance between the bottom surface of the groove 60 and the top surface of the emitter region 23 is 0.4 μm to 0.8 μm.
[0095] In this specific embodiment, the gate conductive layer 31 is etched back after the isolation sidewall 40 and the sacrificial layer 50 are formed. Since the materials of the isolation sidewall 40 and the sacrificial layer 50 are insulating dielectric materials, and the material of the gate conductive layer 31 is conductive material, that is, the materials of the isolation sidewall 40 and the sacrificial layer 50 are different from the material of the gate conductive layer 31, the gate conductive layer 31 can be etched back using a self-aligned etching process, which reduces the difficulty of the etching back process, avoids damage to the emitter region 23, and facilitates the control of the depth of the groove 60 formed after the etching back. At the same time, since the isolation sidewall 40 and the sacrificial layer 50 covering the top surface of the substrate have been formed before the etching back of the gate conductive layer 31, there is no need to perform a thermal oxidation process to form a thermal oxidation layer after the etching back, thereby further simplifying the manufacturing method of the IGBT device.
[0096] In some embodiments, the thickness of the isolation sidewall 40 along the second direction is Thereby, sufficient space can be reserved for the subsequent etching of the substrate to form the contact hole, and the trench gate structure and the lead-out structure subsequently formed in the contact hole can be fully isolated.
[0097] Figure 7 60 is a schematic diagram of a structure after forming a filling dielectric layer in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the filling dielectric layer 70 filled in the groove 60 include:
[0098] Borophosphosilicate glass is deposited on the substrate to form the filling dielectric layer 70 filling the groove 60 , and the top surface of the filling dielectric layer 70 , the top surface of the isolation sidewall 40 and the top surface of the sacrificial layer 50 are flush.
[0099] For example, a 1 μm to 1.5 μm thick borophosphosilicate glass (BPSG) is deposited on the substrate to form the filling dielectric layer 70 filling the groove 60, and the top surface of the remaining filling dielectric layer 70 is flush with the top surface of the isolation sidewall 40 and the top surface of the sacrificial layer 50 by etching back. Figure 7 As shown, the sacrificial layer 50 is exposed to facilitate the subsequent process of etching the contact hole.
[0100] Figure 8 is a schematic diagram of a structure after the sacrificial layer is removed in a specific embodiment of the present invention, Fig. 9 is a schematic diagram of a structure after a contact hole is formed in a specific embodiment of the present invention, Fig.112 is another structural schematic diagram after the contact hole is formed in a specific embodiment of the present invention. In some embodiments, the material of the body region 22 is a silicon material including a first doping ion, and the material of the emitter region 23 is a silicon material including a second doping ion, and the conductivity type of the second doping ion is opposite to the conductivity type of the first doping ion; the specific steps of etching the substrate downward along the opening 80 to form the contact hole 90 include:
[0101] The substrate is etched downward along the opening 80 using a self-aligned etching process to form the contact hole 90 that penetrates the emitter region 23 along the first direction D1 and extends into the body region 22 .
[0102] For example, after forming the filling dielectric layer 70, the sacrificial layer 50 is removed to form the opening 80 located between the adjacent isolation spacers 40 and exposing the emitter region 23, as shown in FIG. Figure 8 As shown. Since the emitter region 23 is exposed by removing the sacrificial layer 50, and the material of the filling dielectric layer 70 and the material of the isolation sidewall 40 are different from the material of the emitter region 23, the substrate can be etched downward along the opening 80 by a self-aligned etching process to form the contact hole 90 that penetrates the emitter region 23 along the first direction D1 and extends into the body region 22, thereby reducing the requirements for the alignment accuracy of the contact hole mask, especially when the distance between the contact hole 90 and the gate trench 25 is less than 0.2μm, the consistency of the saturation voltage drop within the IGBT wafer and between IGBT wafers can be effectively improved, thereby improving the yield and efficiency of batch production of IGBT devices.
[0103] In some embodiments, the sidewall of the contact hole 90 intersects the top surface of the substrate vertically. Fig. 9 as shown; or,
[0104] The sidewall of the contact hole 90 intersects the top surface of the substrate at an angle. Fig.11 shown.
[0105] In one example, the side wall of the contact hole 90 intersects perpendicularly with the top surface of the substrate to further simplify the etching process of the contact hole 90, wherein the side wall of the contact hole 90 intersects perpendicularly with the top surface of the substrate means that the angle between the side wall of the contact hole 90 and the top surface of the substrate is 85°-90°.
[0106] In another example, the sidewall of the contact hole 90 intersects obliquely with the top surface of the substrate, thereby increasing the area of the emitter region 23 exposed on the sidewall of the contact hole 90, so as to increase the RBSOA (Reverse Bias SOA) of the IGBT device. The oblique intersection of the sidewall of the contact hole 90 and the top surface of the substrate means that the angle between the sidewall of the contact hole 90 and the top surface of the substrate is 70°-85°, that is, the cross section of the contact hole 90 is an inverted trapezoidal shape.
[0107] Fig.10 is a schematic diagram of a structure after forming a front metal layer and a back metal layer in a specific embodiment of the present invention, Fig.12 1 is another structural schematic diagram after forming the front metal layer and the back metal layer in a specific embodiment of the present invention. In some embodiments, after forming the contact hole, the manufacturing method of the IGBT device further includes the following steps:
[0108] A conductive contact layer 91 is formed at the bottom of the contact hole 90. Fig. 9 and Fig.11 As shown;
[0109] A front metal layer is formed which at least covers the conductive contact layer 91 and the emitter region 23 and fully fills the contact hole 90 and the opening 80 .
[0110] For example, the material of the body region 22 is a silicon material including a first doping ion (e.g., a P-type ion), and the material of the emitter region 23 is a silicon material including a second doping ion (e.g., an N-type ion), and the conductivity type of the second doping ion is opposite to that of the first doping ion. The first doping ion is injected into the body region 22 at the bottom of the contact hole 80 to form the conductive contact layer 90, and the concentration of the first doping ion in the conductive contact layer 90 is higher than the concentration of the first doping ion in the body region 22. By forming the conductive contact layer 91 with a high doping concentration, it can be ensured that the front metal layer formed in the contact hole 90 subsequently has a good ohmic contact with the body region 22. After forming the conductive contact layer 91, an atomic layer deposition process can be used to deposit materials such as Ti / TiN / W in the contact hole 90 to form a first metal layer 100 that fills the contact hole 90 and the opening 80. Then, AlCu or the like is deposited on the substrate by an atomic layer deposition process to form a second metal layer 101 that continuously covers the first metal layers 100, the isolation sidewalls 40 and the filling dielectric layer 70. Fig.10 and Fig.12 As shown, the first metal layer 100 and the second metal layer 101 together serve as the front metal layer.
[0111] After forming the front metal layer, the substrate is turned over, and the substrate 20 is thinned starting from the second main surface 202 of the substrate 20. The thickness of the substrate 20 thinned depends on the voltage resistance requirements of the IGBT device. Afterwards, the first doping ions (such as boron ions) are implanted into the substrate 20 from the bottom surface of the thinned substrate, and the implanted first doping ions are activated by an annealing process to form a collector region 103. In one example, the ion implantation energy when forming the collector region 103 is 20keV to 60keV, and the implantation dose is 1×10 12 Pieces / cm 2 ~1×10 14 Pieces / cm 2 Next, hydrogen ions are implanted from the bottom surface of the substrate, and annealing is performed to form a buffer layer 102 on the side of the collector region 103 facing the top surface of the substrate. Then, an Al / Ti / Ni / Ag metal stack is deposited on the surface of the collector region 103 to form a back metal layer 104. Fig.10 and Fig.12 shown.
[0112] This specific embodiment also provides an IGBT device. The IGBT device can be used as follows Figure 1-Figure 12 The manufacturing method of the IGBT device shown in FIG. 1 is formed, and the structure of the IGBT device can be seen in FIG. Fig.10 and Fig.12 .like Figure 1-Figure 12 As shown, the IGBT device comprises:
[0113] A substrate, the substrate comprising a top surface and a bottom surface relatively distributed along a first direction D1 and a plurality of trench gate structures spaced apart along a second direction D2, the trench gate structure comprising a gate trench 25 extending from the top surface of the substrate to the inside of the substrate along the first direction D1, a gate dielectric layer 30 covering the inner wall of the gate trench 25, and a gate conductive layer 31 filled in the gate trench 25 and covering the gate dielectric layer 25, the gate conductive layer 31 being lower than the top surface of the substrate along the first direction D1, and being parallel to the top surface of the substrate in the second direction D2;
[0114] A filling dielectric layer 70, wherein a plurality of the filling dielectric layers 70 are respectively covered on the top surfaces of the plurality of the gate conductive layers 31, and a portion of the filling dielectric layers 70 protrudes from the top surface of the substrate;
[0115] An isolation sidewall 40 is located on the top surface of the substrate, and a plurality of the isolation sidewalls 40 are respectively covered on the sidewalls of a plurality of the filling dielectric layers 70;
[0116] The lead-out structure is filled between adjacent isolation sidewalls 40 and extends from the top surface of the substrate to the inside of the substrate along the first direction D1 , and the lead-out structure is electrically connected to the substrate.
[0117] In some embodiments, the base includes a substrate 20, a carrier storage region 21 located above the substrate 20 along the first direction D1, a body region 22 located above the carrier storage region 21 along the first direction D1, and an emitter region 23 located above the body region 22 along the first direction D1;
[0118] The lead-out structure includes an opening 80 located between adjacent isolation sidewalls 40, a contact hole 90 connected to the opening 80 and penetrating the emitter region 23 along the first direction D1 and extending into the body region 22, a conductive contact layer 91 located at the bottom of the contact hole 90, and a front metal layer covering the conductive contact layer 91 and the emitter region 23 and filling the contact hole 90 and the opening 80.
[0119] In some embodiments, the sidewall of the contact hole 90 intersects the top surface of the substrate vertically; or,
[0120] The sidewall of the contact hole 90 intersects the top surface of the substrate at an angle.
[0121] In some embodiments, the distance between the contact hole 90 and the gate trench 25 is less than 0.2 μm.
[0122] In some embodiments, the front metal layer includes a first metal layer 100 covering the conductive contact layer 91 and the emitter region 23 and filling the contact hole 90 and the opening 80, and a second metal layer 101 covering the first metal layer 100, the isolation spacer 40 and the filling dielectric layer 70;
[0123] The top surface of the first metal layer 100 , the top surface of the isolation spacer 40 , and the top surface of the filling dielectric layer 70 are flush.
[0124] In some embodiments, the material of the isolation sidewall 40 is silicon dioxide, the material of the filling dielectric layer 70 is borophosphosilicate glass, the material of the body region 22 is a silicon material including a first doping ion, and the material of the emitter region 23 is a silicon material including a second doping ion, and the conductivity type of the second doping ion is opposite to the conductivity type of the first doping ion.
[0125] The IGBT device and the manufacturing method thereof provided in this specific embodiment are as follows: after depositing the gate conductive layer, the gate conductive layer is made to protrude from the top surface of the substrate, and an isolation sidewall covering the sidewall of the gate conductive layer and a sacrificial layer located between adjacent isolation sidewalls are formed on the top surface of the substrate; after etching back the gate conductive layer to form a groove located above the gate conductive layer, a filling dielectric layer is formed in the groove; and after removing the sacrificial layer, an opening is formed between adjacent isolation sidewalls, so that the substrate can be etched along the opening to form a contact hole, thereby realizing self-aligned etching of the substrate through the opening, thereby reducing the requirements for the alignment accuracy of the contact hole mask and the gate trench mask, thereby improving the consistency of the saturation voltage drop within the IGBT wafer and between IGBT wafers, and improving the yield and efficiency of batch production of IGBT devices. Moreover, after etching back the gate conductive layer to form the groove, this specific embodiment does not need to use a thermal oxidation process to form a thermal oxidation layer above the gate conductive layer and the substrate, which not only simplifies the manufacturing process of the IGBT device, but also facilitates the control of the consistency of the thickness of the gate conductive layer, thereby further improving the consistency of electrical performance within the IGBT wafer and between IGBT wafers.
[0126] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for manufacturing an IGBT device, characterized in that: The steps include: Forming a substrate, the substrate comprising a top surface and a bottom surface relatively distributed along a first direction and a plurality of trench gate structures spaced apart along a second direction, the trench gate structure comprising a gate trench extending from the top surface of the substrate to the inside of the substrate along the first direction, a gate dielectric layer covering the inner wall of the gate trench, and a gate conductive layer filled in the gate trench and covering the gate dielectric layer, the gate conductive layer protruding from the top surface of the substrate along the first direction, and the second direction being parallel to the top surface of the substrate; forming an isolation sidewall covering the sidewall of the gate conductive layer and a sacrificial layer located between adjacent isolation sidewalls on the top surface of the substrate; Etching back the gate conductive layer to form a groove above the remaining gate conductive layer, and the top surface of the remaining gate conductive layer is lower than the top surface of the substrate; forming a filling medium layer filled in the groove; removing the sacrificial layer to form an opening exposing the substrate; The substrate is etched downward along the opening to form a contact hole.
2. The method for manufacturing an IGBT device according to claim 1, characterized in that: The specific steps of forming the substrate include: providing an initial substrate; Implanting doping ions into the initial substrate in sequence, forming a carrier storage region, a body region located above the carrier storage region along the first direction, and an emitter region located above the body region along the first direction in the initial substrate, the remaining initial substrate below the carrier storage region serves as a substrate, forming the base including the substrate, the carrier storage region, the body region, and the emitter region, and the surface of the emitter region facing away from the substrate serves as the top surface of the base; forming a mask layer located above the emitter region, wherein the mask layer has a plurality of etching windows arranged at intervals along the second direction and penetrating the mask layer along the first direction; Etching the substrate along the etching window to form the gate trench that penetrates the emitter region, the body region, and the carrier storage region along the first direction and extends into the substrate; forming the gate dielectric layer covering the inner wall of the gate trench and the gate conductive layer filling the gate trench and the etching window; The mask layer is removed.
3. The method for manufacturing an IGBT device according to claim 1, characterized in that: The specific steps of forming the substrate include: providing an initial substrate; forming a mask layer located above the initial substrate, wherein the mask layer has a plurality of etching windows arranged at intervals along the second direction and penetrating the mask layer along the first direction; Etching the initial substrate along the etching window to form the gate trench; forming the gate dielectric layer covering the inner wall of the gate trench and the gate conductive layer filling the gate trench and the etching window; removing the mask layer; Doping ions are sequentially implanted into the initial substrate to form a carrier storage region, a body region located above the carrier storage region along the first direction, and an emitter region located above the body region along the first direction in the initial substrate, the remaining initial substrate below the carrier storage region serves as a substrate to form a base including the substrate, the carrier storage region, the body region, and the emitter region, the surface of the emitter region facing away from the substrate serves as the top surface of the base, and the bottom surface of the gate trench is lower than the bottom surface of the carrier storage region.
4. The method for manufacturing an IGBT device according to claim 2 or 3, characterized in that: The specific steps of forming an isolation sidewall covering the sidewall of the gate conductive layer and a sacrificial layer located between adjacent isolation sidewalls on the top surface of the substrate include: Depositing an oxide material on the top surface of the substrate to form the isolation sidewall covering the sidewall of the gate conductive layer; A nitride material is deposited on the top surface of the substrate to form the sacrificial layer filled between adjacent isolation sidewalls.
5. The method for manufacturing an IGBT device according to claim 1, characterized in that: The thickness of the isolation sidewall along the second direction is 6. The method for manufacturing an IGBT device according to claim 4, characterized in that: The specific steps of forming a filling medium layer filled in the groove include: Borophosphosilicate glass is deposited on the substrate to form the filling dielectric layer filled in the groove, and the top surface of the filling dielectric layer, the top surface of the isolation sidewall and the top surface of the sacrificial layer are flush.
7. The method for manufacturing an IGBT device according to claim 6, characterized in that: The material of the body region is a silicon material including a first doping ion, and the material of the emitter region is a silicon material including a second doping ion, and the conductivity type of the second doping ion is opposite to the conductivity type of the first doping ion; the specific steps of etching the substrate downward along the opening to form a contact hole include: etching the substrate downward along the opening using a self-aligned etching process to form the contact hole that passes through the emitter region along the first direction and extends into the body region.
8. The method for manufacturing an IGBT device according to claim 1, characterized in that: The sidewall of the contact hole intersects the top surface of the substrate vertically; or, The sidewall of the contact hole obliquely intersects with the top surface of the substrate.
9. The method for manufacturing an IGBT device according to claim 1, characterized in that: After forming the contact hole, the following steps are also included: forming a conductive contact layer at the bottom of the contact hole; A front metal layer is formed which at least covers the conductive contact layer and the emitter region and fully fills the contact hole and the opening.
10. An IGBT device, characterized in that: include: A substrate, the substrate comprising a top surface and a bottom surface relatively distributed along a first direction and a plurality of trench gate structures spaced apart along a second direction, the trench gate structure comprising a gate trench extending from the top surface of the substrate to the inside of the substrate along the first direction, a gate dielectric layer covering the inner wall of the gate trench, and a gate conductive layer filled in the gate trench and covering the gate dielectric layer, the gate conductive layer being lower than the top surface of the substrate along the first direction, and being parallel to the top surface of the substrate in the second direction; A filling dielectric layer, wherein a plurality of the filling dielectric layers are respectively covered on the top surfaces of the plurality of gate conductive layers, and a portion of the filling dielectric layers protrudes from the top surface of the substrate; An isolation sidewall is located on the top surface of the substrate, and a plurality of the isolation sidewalls are respectively covered on the sidewalls of a plurality of the filling dielectric layers; The lead-out structure is filled between the adjacent isolation sidewalls and extends from the top surface of the substrate to the inside of the substrate along the first direction, and the lead-out structure is electrically connected to the substrate.
11. The IGBT device according to claim 10, characterized in that: The base includes a substrate, a carrier storage region located above the substrate along the first direction, a body region located above the carrier storage region along the first direction, and an emitter region located above the body region along the first direction; The lead-out structure includes an opening located between adjacent isolation side walls, a contact hole connected to the opening and penetrating the emitter region along the first direction and extending into the body region, a conductive contact layer located at the bottom of the contact hole, and a front metal layer covering the conductive contact layer and the emitter region and filling the contact hole and the opening.
12. The IGBT device according to claim 11, characterized in that: The sidewall of the contact hole intersects the top surface of the substrate vertically; or, The sidewall of the contact hole obliquely intersects with the top surface of the substrate.
13. The IGBT device according to claim 11, characterized in that: The distance between the contact hole and the gate trench is less than 0.2 μm.
14. The IGBT device according to claim 11, characterized in that: The front metal layer includes a first metal layer covering the conductive contact layer and the emitter region and filling the contact hole and the opening, and a second metal layer covering the first metal layer, the isolation sidewall and the filling dielectric layer; The top surface of the first metal layer, the top surface of the isolation sidewall and the top surface of the filling dielectric layer are flush.
15. The IGBT device according to claim 11, characterized in that: The material of the isolation sidewall is silicon dioxide, the material of the filling dielectric layer is borophosphosilicate glass, the material of the body region is a silicon material including a first doping ion, and the material of the emitter region is a silicon material including a second doping ion, and the conductivity type of the second doping ion is opposite to the conductivity type of the first doping ion.