Pseudo-random sequence storage method, pressure test method, device and system
By designing an external module connected to an integrated circuit, generating and storing pseudo-random binary sequences and expected data, the problems of poor flexibility and high cost in the prior art are solved, and pseudo-flexibility and lower complexity are achieved. Random sequence generation and testing.
Patent Information
- Application Number
- CN202411451898.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-16
- Publication Date
- 2025-02-11
AI Technical Summary
The prior art has poor flexibility and high cost in the simulation and testing of pseudo-random binary sequences, which cannot meet the application needs of different scenarios.
By designing an external module, connected to the integrated circuit, a pseudo-random binary sequence and expected data are generated and stored in memory for pressure testing. This external module can more conveniently generate pseudo-random binary sequences of different orders, reducing hardware design complexity.
It improves the flexibility of generating pseudo-random binary sequences, reduces the complexity of hardware design, meets the needs of different application scenarios, and achieves the purpose of DDR stress testing.
Smart Images
Figure CN119415065A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of simulation testing technology, and in particular to a storage method, a stress testing method, a device and a system for a pseudo-random sequence. Background Art
[0002] Pseudo-Random Binary Sequence (PRBS) refers to a pseudo-random sequence that contains only 0 and 1. It not only has the statistical characteristics of a random sequence and the good autocorrelation characteristics of Gaussian noise, but also has a certain coding rule, can be repeatedly generated and processed, and is widely used in the field of communications. For example, in the simulation and testing of high-speed digital communication links, it is used to simulate real data streams. Among them, PRBS can be generated by primitive polynomials, which are characterized by multiple linear feedback shift registers connected in series. The length of the shift register is called the order n. Commonly used orders are 7, 9, 11, 15, 20, 23, and 31, so the cycle period of PRBS is 2n-1.
[0003] PRBS data is often used in the simulation and testing of high-speed digital communication links to simulate real data streams. At present, the operating frequency of the shift register core of the PRBS generator is relatively high, which increases the difficulty of design. In addition, for PRBS patterns of different orders, a PRBS generator and a checker need to be set up accordingly, which makes the simulation and testing costs high, especially during chip self-test, because different pattern data streams need to be simulated, and a single PRBS generator and checker cannot meet the chip's self-test requirements, resulting in low chip self-test efficiency. Summary of the invention
[0004] In view of this, the present invention provides a storage method, stress testing method, device and system for a pseudo-random sequence to solve the problems of poor flexibility, high cost and inability to meet application requirements of different scenarios during simulation and testing of pseudo-random binary sequences of different orders.
[0005] In a first aspect, the present invention provides a method for storing a pseudo-random sequence, which is applied to an external module, wherein the external module is connected to an integrated circuit, wherein a processor and a memory are integrated on the integrated circuit, and the method comprises:
[0006] Acquire memory information of the memory and the address of the reserved storage resource in the memory, wherein the memory information includes the size of the memory resource of the memory;
[0007] Generate pseudo-random binary sequence PRBS original data according to the memory resource size and pseudo-random binary sequence algorithm;
[0008] Processing the PRBS original data according to a preset clustering algorithm to generate expected data corresponding to the PRBS original data, wherein the expected data is used to perform a stress test on the PRBS original data;
[0009] The PRBS original data and the expected data are stored in the reserved storage resources of the memory according to the address.
[0010] In combination with the first aspect, in a possible implementation manner, the address of the reserved storage resource in the memory includes: a first address and a second address, and the first address corresponds to a first storage unit, and the second address corresponds to a second storage unit;
[0011] The storing the PRBS original data and the expected data in the reserved storage resources of the memory according to the address includes:
[0012] storing the PRBS original data in a first storage unit reserved in the memory according to the first address;
[0013] The expected data is stored in a second storage unit reserved in the memory according to the second address.
[0014] In combination with the first aspect, in another possible implementation, the preset clustering algorithm is a reduce algorithm;
[0015] The processing of the PRBS original data according to a preset clustering algorithm to generate expected data corresponding to the PRBS original data includes:
[0016] The PRBS original data is processed according to the reduce algorithm to generate the expected data.
[0017] In combination with the first aspect, in another possible implementation, after storing the PRBS original data and the expected data in the reserved storage resource of the memory according to the address, it also includes:
[0018] generating an indication signal;
[0019] The indication signal is sent to the processor, where the indication signal is used to notify the processor that a write operation on the PRBS original data and the expected data has been completed.
[0020] In a second aspect, the present invention provides a stress test method, which is applied to a processor, wherein the processor is connected to an external module, and the processor is also connected to a memory, and the processor and the memory are both integrated on an integrated circuit, and the method comprises:
[0021] Start a signal detection function to detect whether there is an indication signal sent from an external module, wherein the indication signal is used to notify the processor that the writing operation of the PRBS original data and the expected data has been completed;
[0022] If yes, reading the PRBS original data and the expected data from the reserved storage resources of the memory respectively according to the address of the reserved storage resources in the memory;
[0023] Preprocessing the PRBS original data to generate PRBS evolved data, and comparing whether the PRBS evolved data is the same as the expected data;
[0024] If they are the same, it is determined that the stress test on the memory has passed; otherwise, the stress test has failed.
[0025] In combination with the second aspect, in a possible implementation, the preprocessing of the PRBS original data to generate the PRBS evolved data includes: performing a matrix multiplication operation on the PRBS original data to generate the PRBS evolved data.
[0026] In combination with the second aspect, in another possible implementation, the address of the reserved storage resource in the memory includes: a first address and a second address, and the first address corresponds to a first storage unit, and the second address corresponds to a second storage unit;
[0027] The step of reading the PRBS original data and the expected data from the reserved storage resources of the memory according to the addresses of the reserved storage resources in the memory comprises:
[0028] The PRBS original data is obtained from the first storage unit of the memory according to the first address, and the expected data is obtained from the second storage unit of the memory according to the second address.
[0029] In a third aspect, the present invention provides a storage device for a pseudo-random sequence, the device being connected to an integrated circuit on which a processor and a memory are integrated, the device comprising:
[0030] An acquisition module, used to acquire memory information of the memory and the address of the reserved storage resource in the memory, wherein the memory information includes the size of the memory resource of the memory;
[0031] A generating module, used for generating pseudo-random binary sequence PRBS original data according to the size of the memory resource and the pseudo-random binary sequence algorithm;
[0032] A processing module, used for processing the PRBS original data according to a preset clustering algorithm to generate expected data corresponding to the PRBS original data, wherein the expected data is used for performing a stress test on the PRBS original data;
[0033] A storage module is used to store the PRBS original data and the expected data in the reserved storage resources of the memory according to the address.
[0034] In a fourth aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the method for storing a pseudo-random sequence of the first aspect or any corresponding embodiment thereof by executing the computer instructions.
[0035] In addition, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the method for storing a pseudo-random sequence of the first aspect or any corresponding embodiment thereof.
[0036] In addition, the computer is also used to execute the stress testing method described in the above-mentioned second aspect or any corresponding embodiment thereof.
[0037] In addition, the present invention provides a computer program product, including computer instructions, which are used to enable a computer to execute the pseudo-random sequence storage method of the above-mentioned first aspect or any corresponding embodiment, and execute the stress testing method described in the above-mentioned second aspect or any corresponding embodiment.
[0038] In a fifth aspect, the present invention further provides a system, the system comprising an external module and an integrated circuit, the external module being connected to the integrated circuit, and the integrated circuit being integrated with a processor and a memory;
[0039] Among them, the external module is used to execute the pseudo-random sequence storage method of the above-mentioned first aspect or any corresponding embodiment; the memory is used to store the PRBS original data and expected data generated by the external module; the processor is used to execute the stress testing method described in the above-mentioned second aspect or any corresponding embodiment.
[0040] The storage method of the pseudo-random sequence provided by the present invention removes the PRBS module from the original hardware circuit and designs an external module to be connected with the hardware circuit, thereby avoiding adding the PRBS module into the hardware and reducing the complexity of the design.
[0041] In addition, since this solution removes the PRBS module in the hardware circuit, the function of the original PRBS module is implemented by an external module, which generates PRBS data and expected data and stores these data in the memory of the hardware circuit, paving the way for subsequent stress testing of the processor. The external module can more conveniently generate pseudo-random binary sequences of different orders, has higher flexibility, and can meet the needs of different application scenarios, thereby achieving the purpose of DDR stress testing. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0043] Figure 1 is a circuit diagram of a hardware circuit according to an embodiment of the present invention;
[0044] Figure 2 is a circuit diagram of another hardware circuit according to an embodiment of the present invention;
[0045] Figure 3 is a schematic flow chart of a method for storing a pseudo-random sequence according to an embodiment of the present invention;
[0046] Figure 4 is a schematic flow chart of a stress testing method according to an embodiment of the present invention;
[0047] Figure 5 is a structural block diagram of a storage device for a pseudo-random sequence according to an embodiment of the present invention;
[0048] Figure 6 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
[0050] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0051] Furthermore, the terms “first” and “second” are used for descriptive purposes only and should not be understood as indicating or implying relative importance.
[0052] The technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0053] First, the application scenarios and related technical terms involved in the embodiments of the present invention are introduced.
[0054] The technical solution provided by the embodiment of the present invention is applied to the field of chip circuit simulation test technology, specifically, a stress test based on a pseudo-random binary sequence PRBS.
[0055] PRBS calibration is a commonly used calibration method used to test the stability and reliability of memory, such as DDR (Double Data Rate) SDRAM. Figure 1 As shown in FIG. 1 , a PRBS module, a DDR, and a processor are integrated in the hardware. One method is to generate PRBS patterns through the PRBS module. These patterns are mainly some specific random binary sequences, which can be collectively referred to as PRBS data. They can be used to simulate random changes in actual data streams, thereby achieving the purpose of comprehensive testing of DDR.
[0056] exist Figure 1 In the hardware structure shown, the designed PRBS module mainly includes three parts: PRBS generation module, main control module and PRBS receiving module. Among them, the PRBS generation module is used to encode and send data by PRBS, that is, to generate a PRBS code stream and write the PRBS code stream into DDR. The PRBS receiving module is used to receive and save the data read back from DDR; the main control module is used to compare the PRBS sending module data with the PRBS receiving module data, and to count and display the comparison results.
[0057] The above method of generating PRBS code stream and comparing it through the main control module has two main problems: first, the PRBS module needs to be designed in advance, which increases the complexity of hardware design; second, the designed PRBS module is not flexible enough. Common PRBS orders are 7, 9, 11, 15, 20, 23, and 31. When the order of the designed PRBS module is 20, if the order is greater than 20, the PRBS verification is not supported, which limits the application.
[0058] Based on the above problems, the embodiment of the present invention proposes a stress test method based on pseudo-random binary sequence, which uses the existing chip hardware structure and does not require the design and addition of a PRBS module, thereby reducing the hardware complexity problem. At the same time, since this solution uses the existing hardware structure, the flexibility is greatly improved and is not limited to the PRBS hardware structure.
[0059] The technical solution of the embodiment of the present invention is described in detail below.
[0060] See also Figure 2 , is a circuit diagram of a hardware circuit provided by an embodiment of the present invention. The hardware circuit does not include the aforementioned Figure 1 Instead of using the PRBS module shown in FIG. 1 , the PRBS module is placed outside the hardware circuit. Figure 2 The term "external module" is used as an example. The external module may be a PRBS module or a function of an integrated PRBS module.
[0061] The external module is connected to the memory and processor in the hardware circuit. Further, it can be connected to the hardware circuit by wire through an interface. Among them, the memory can be a RAM random access memory, and the RAM random access memory can be a static memory SRAM or a dynamic memory DRAM; or it can also be a memory (memory) in other forms. In this embodiment, the memory can be a DRAM, such as DDR (DDR SDRAM, double rate synchronous dynamic random access memory).
[0062] The processor is a device with computing and processing functions, including but not limited to NPU (Neural Network Processing Unit), GPU (Graphics Processing Unit), CPU (Central Processing Unit), DSP (Digital Signal Processor), etc. It should be understood that the above processor can also be a processing unit or processing module, processing circuit, etc., and this application does not limit this.
[0063] Optionally, in this embodiment, the processor may be a processor core, such as an NPU.
[0064] The processor is connected to the external module via a signal port.
[0065] The external device includes preset functional software for generating a pseudo-random binary sequence and storing the sequence in a memory. In addition, the external device also calculates or reduces the generated pseudo-random binary sequence according to the expected processing method to obtain an expected data, such as golden data.
[0066] Based on the above Figure 2 The circuit structure shown in the embodiment of the present invention provides a storage method for a pseudo-random sequence. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.
[0067] Figure 3 1 is a flow chart of a method for storing a pseudo-random sequence according to an embodiment of the present invention. The method flow can be executed by an external module, and the external module is connected to an integrated circuit. Optionally, the integrated circuit is a hardware circuit that integrates a processor and a memory. Figure 3 As shown, the storage method includes:
[0068] Step S101: Obtain memory information of a memory and addresses of reserved storage resources in the memory.
[0069] The memory information of the memory usually depends on the memory capacity and available space of the hardware device. The memory information includes the memory resource size of the memory, such as the DDR resource size, and specifically includes the available resource size and the usage of each resource.
[0070] The address of the reserved storage resource in the memory means that the processor pre-allocates certain memory resources in the DDR for storing the original PRBS data and / or expected data generated by the external module. Therefore, in the preparation stage of this embodiment, the external module needs to negotiate with the processor to obtain an address that can be used to store data. For example, the first address and the second address are obtained. The first address is used to indicate the first storage unit in the memory, and the first storage unit can be used to store the original PRBS data; similarly, the second address is used to indicate the second storage unit of the memory, and the second storage unit can be used to store the expected data.
[0071] After configuring the idle storage units, the processor informs the corresponding storage address to the external module, so that the external module obtains the address in advance, and the storage resource corresponding to the address is used as the reserved storage resource inside the memory.
[0072] It should be understood that the above-mentioned reserved memory resources may also include more or fewer storage units such as a third storage unit and a fourth storage unit, and this embodiment is not limited to this.
[0073] In addition, optionally, the memory information of the memory also includes: the arrangement of banks inside the memory, in which bank refers to the number of storage arrays. Each bank contains components such as a row address decoder, a column address decoder, a sensor amplifier, and a DRAM memory array.
[0074] In step S101, a possible implementation of the external module acquiring the memory information of the memory is: first sending a request to the processor, and in response to the request acquiring the memory information of the memory sent by the processor. Alternatively, another implementation is: the processor periodically sends the memory information of the memory to the external module.
[0075] Step S102: Generate pseudo-random binary sequence PRBS original data according to the pseudo-random binary sequence algorithm based on the memory resource size.
[0076] The PRBS original data is a binary sequence consisting of 0 and 1. Optionally, the number of 0 and 1 in the binary sequence is the same and randomly distributed.
[0077] The order of PRBS determines the period and complexity of the sequence. The higher the order, the longer the period of the sequence, but the more memory resources are occupied. Therefore, when selecting the PRBS order, it is necessary to weigh the size of the memory resources. In this step, when generating the PRBS raw data, the memory information of the memory is considered to ensure that the PRBS data does not exceed the available memory resources.
[0078] Step S103: Processing the original PRBS data according to a preset clustering algorithm to generate expected data corresponding to the original PRBS data.
[0079] Among them, the preset clustering algorithm is a processing algorithm that comes with the processor. Optionally, the preset clustering algorithm is a reduce algorithm. Specifically, the Reduce method is a technology used to extract data from a fixed-size set. It transforms all elements in the input data set into a single output value through calculation. It is often used to calculate statistical data, such as average, maximum, minimum, etc. In addition, the Reduce method can also convert multi-dimensional abstract data into one-dimensional data, so that complex data relationships can be expressed through one value.
[0080] A specific implementation method of this step S103 is: process the PRBS original data according to the reduce algorithm to generate the expected data. Among them, the expected data can be golden data, and golden data (also known as golden files) generally refers to known correct data used as a reference or standard in the test or verification process. In the fields of software development, hardware verification or algorithm testing, golden data is used to compare with the test results to verify whether the implementation is correct or whether the performance meets expectations. In this embodiment, the golden data is used to perform a stress test on the PRBS original data; test whether the memory stress test passes.
[0081] Step S104: storing the PRBS original data and the expected data into the reserved storage resources of the memory according to the address.
[0082] In a specific implementation, the address of the reserved storage resource in the memory includes: a first address and a second address, and the first address corresponds to the first storage unit, and the second address corresponds to the second storage unit. The first storage unit and the second storage unit are two storage resources in the reserved storage resources in the memory, and both storage resources are available resources. In addition, the number of the first storage unit and the second storage unit can be one or more, and this embodiment does not limit this.
[0083] This step specifically includes: the external module stores the PRBS original data in a first storage unit reserved in the memory according to the first address; and stores the expected data in a second storage unit reserved in the memory according to the second address, and the second storage unit is used to store verification data.
[0084] In addition, after step S104: storing the PRBS original data and the expected data in the reserved storage resources of the memory according to the address, the method further includes:
[0085] The external module generates an indication signal and sends the indication signal to the processor, where the indication signal is used to notify the processor that the writing operation of the PRBS original data and the expected data has been completed.
[0086] At this time, the reserved storage resources of the memory store the original PRBS data and the expected data. After receiving the indication signal, the processor can perform subsequent operations, such as stress testing.
[0087] Optionally, the above indication signal is a DONE signal.
[0088] The pseudo-random sequence storage method provided in this embodiment removes the PRBS module from the original hardware circuit and designs it into an external module connected to the hardware circuit, thereby avoiding adding the PRBS module to the hardware and reducing the complexity of the design.
[0089] In addition, since this solution removes the PRBS module in the hardware circuit, the function of the original PRBS module is implemented by an external module, which generates PRBS data and expected data and stores these data in the memory of the hardware circuit, paving the way for subsequent stress testing of the processor. The external module can more conveniently generate pseudo-random binary sequences of different orders, has higher flexibility, and can meet the needs of different application scenarios.
[0090] In another embodiment of the present application, a stress test method is also provided, which can be applied to the aforementioned Figure 2 Specifically, the stress test method in this embodiment is applied to a processor, which is connected to an external module. In addition, the processor is also connected to a memory, such as Figure 4 As shown, the stress testing method includes:
[0091] Step S201: Start a signal detection function to detect whether there is an indication signal sent from an external module, wherein the indication signal is used to notify the processor that the writing operation of the PRBS original data and the expected data has been completed.
[0092] The processor starts the signal detection mode to detect the indication signal from the external module, such as the DONE signal. In the preparation stage, the processor and the external device agree in advance that when the external device stores the PRBS original data and the expected data in the memory, it will send an indication signal, such as the DONE signal, to the processor.
[0093] If the indication signal is received, step S202 is executed; if the indication signal is not received, the receiving is continued.
[0094] Step S202: If yes, then read the PRBS original data and the expected data from the reserved storage resources in the memory respectively according to the addresses of the reserved storage resources in the memory.
[0095] One implementation mode is that if the address of the reserved storage resources in the memory includes: a first address and a second address, and the first address corresponds to a first storage unit, and the second address corresponds to a second storage unit; the first storage unit and the second storage unit are both available resources in the reserved storage resources, then the processor obtains the original PRBS data from the first storage unit of the memory according to the first address, and obtains the expected data from the second storage unit of the memory according to the second address.
[0096] Step S203: pre-processing the PRBS original data to generate PRBS evolved data.
[0097] Specifically, a preprocessing method includes: a processor performs a matrix multiplication operation on the PRBS original data to generate PRBS evolution data.
[0098] Optionally, the matrix multiplication operation includes but is not limited to a Column-wise Matmul algorithm, where the Column-wise Matmul algorithm is a special matrix multiplication algorithm that emphasizes matrix multiplication operations by columns (rather than by rows).
[0099] The implementation of the Column-wise Matmul algorithm may vary depending on the specific hardware architecture and algorithm requirements. This embodiment provides a possible implementation method: the original PRBS data can be represented as two input matrices A and B, and the output PRBS evolution data can be represented by a result matrix C. Column-wise iteration: For each column of the result matrix C, traverse each row of the input matrix A and the corresponding column of the input matrix B, perform multiplication and accumulate the results. Finally, store the results: store the accumulated results in the corresponding position of the result matrix C.
[0100] In this embodiment, the Column-wise Matmul algorithm is used to generate PRBS evolution data, which can be expected data of a fixed length. The amount of the expected data is greatly reduced compared to the original PRBS data, thereby improving the test efficiency.
[0101] Step S204: Compare whether the PRBS evolved data is the same as the expected data, that is, compare whether each bit of the two binary sequences is the same.
[0102] If they are the same, execute step S205; if they are not the same, execute step S206.
[0103] Step S205: If they are the same, the processor determines that the stress test on the memory (such as DDR) passes, and executes the subsequent process.
[0104] Step S206: Otherwise, the stress test fails, and a shutdown inspection or maintenance procedure is initiated.
[0105] For example: Assume that the original PRBS data is a hexadecimal data, ffffffff 6666 66669696 96960cf3 0cf3 02a4 fd5b 546d fc63 32e3 037c a4b5 aa2a 926c 66e6 24494b4b 388e 738c c00f 7cf000f0 7f00 0000 80ff 0000 0000 0000 0000.... The original PRBS data is subjected to matrix multiplication operation to generate PRBS evolved data, for example, the PRBS evolved data is e966 0500.
[0106] The expected data read from the memory in step S202 is also a hexadecimal sequence, for example, the expected data is: e9670500. The processor compares the PRBS evolution data e966 0500 with the expected data e967 0500 to determine whether they are the same. After comparison, the two are different, so it is determined that the DDR stress test fails.
[0107] If the PRBS evolution data is e967 0500, the comparison is the same as the expected data. At this time, the processor determines that the DDR stress test has passed. This embodiment can verify the correctness of the DDR data by comparing the expected data, and by comparing the PRBS evolution data with the PRBS original data, the amount of expected data is greatly reduced, and the verification efficiency is improved.
[0108] This paper proposes a memory stress test method based on pseudo-random binary. Since the PRBS data is generated by an external module (software), there is no need to set up a PRBS module in the original hardware circuit, thereby reducing the complexity of the design. At the same time, through the external module of the software, pseudo-random binary sequences of different orders can be easily generated, which improves the flexibility of generating PRBS data, not only meeting the needs of different application scenarios, but also achieving the purpose of DDR stress testing.
[0109] In the present embodiment, a storage device for a pseudo-random sequence is also provided, and the device is used to implement the above-mentioned embodiment and the preferred implementation mode, and the description has been made no further. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.
[0110] This embodiment provides a storage device for a pseudo-random sequence, which is connected to an integrated circuit on which a processor and a memory are integrated. Figure 5 As shown, the device includes: an acquisition module 510, a generation module 520, a processing module 530 and a storage module 540. In addition, the device may also include other more or fewer modules, such as a storage module, a sending module, etc., which is not limited in this embodiment.
[0111] The acquisition module 510 is used to acquire memory information of the memory and the address of the reserved storage resource in the memory, and the memory information includes the size of the memory resource of the memory.
[0112] The generating module 520 is used to generate the pseudo-random binary sequence PRBS original data according to the pseudo-random binary sequence algorithm according to the memory resource size.
[0113] The processing module 530 is used to process the PRBS original data according to a preset clustering algorithm to generate expected data corresponding to the PRBS original data, and the expected data is used to perform stress testing on the PRBS original data.
[0114] The storage module 540 is used to store the PRBS original data and the expected data into the reserved storage resources of the memory according to the address.
[0115] Optionally, in a specific implementation, the address of the reserved storage resource in the memory includes: a first address and a second address, and the first address corresponds to a first storage unit, and the second address corresponds to a second storage unit.
[0116] The storage module 540 is specifically used to store the PRBS original data in a first storage unit reserved in the memory according to the first address; and store the expected data in a second storage unit reserved in the memory according to the second address.
[0117] Optionally, in another specific implementation, the preset clustering algorithm is a reduce algorithm; the processing module 530 is specifically used to process the original PRBS data according to the reduce algorithm to generate expected data.
[0118] Optionally, in another specific embodiment, the generation module 520 is also used to generate an indication signal after the PRBS original data and the expected data are stored in the reserved storage resources; and then the indication signal is sent to the processor through the sending module to notify the processor that the writing operation of the PRBS original data and the expected data has been completed.
[0119] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.
[0120] In addition, in this embodiment, one or more of the acquisition module 510, the generation module 520, the processing module 530 and the storage module 540 are also used to implement the aforementioned stress testing function.
[0121] Specifically, when the above device is used as a stress test device, the processing module 530 is used to start the signal detection function to detect whether there is an indication signal sent from an external module. If so, the PRBS original data and the expected data are read from the reserved storage resources of the memory according to the address of the reserved storage resources in the memory.
[0122] The generating module 520 is used to pre-process the original PRBS data to generate PRBS evolved data.
[0123] The processing module 530 is further used to compare whether the PRBS evolution data is the same as the expected data; if they are the same, it is determined that the stress test on the memory has passed; otherwise, the stress test has failed.
[0124] Furthermore, the processing module 530 is specifically configured to perform a matrix multiplication operation on the original PRBS data to generate PRBS evolved data.
[0125] The storage device of the pseudo-random sequence in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.
[0126] The device provided in this embodiment generates a pseudo-random binary sequence by means of software, and there is no need to design a PRBS module in the original hardware circuit to generate a pseudo-random binary sequence, thereby simplifying the hardware design; at the same time, pseudo-random binary sequences of different orders can be generated more conveniently and flexibly to meet the DDR stress testing requirements.
[0127] In addition, this embodiment verifies and compares the pseudo-random binary sequence based on the processor, and outputs the comparison result to determine the correctness of the verified data, thereby achieving the purpose of stress testing the memory.
[0128] The embodiment of the present invention also provides a computer device having the above Figure 5 A storage device for the pseudo-random sequence shown.
[0129] See also Figure 6 , is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses for communication, and can be installed on a common motherboard or in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface).
[0130] In some optional embodiments, if desired, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6 A processor 10 is taken as an example.
[0131] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.
[0132] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the storage method of the pseudo-random sequence shown in the above embodiment.
[0133] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
[0134] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.
[0135] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 6 The example of connecting through bus is taken in the following.
[0136] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.
[0137] In addition, the computer device also includes at least one communication interface for the computer device to communicate with other devices or communication networks. In this embodiment, the communication interface is used to connect the processor and the memory in the hardware circuit.
[0138] The embodiment of the present invention also provides a hardware system, see the above Figure 2 The results shown in the figure show that the system includes an external module and an integrated circuit, wherein the external module is connected to the integrated circuit, and a processor and a memory are integrated on the integrated circuit.
[0139] Figure 2 In the embodiment, the integrated circuit is a hardware circuit. The external module is used to execute the aforementioned Figure 3 The storage method of the pseudo-random sequence shown in the figure; the memory is used to store the PRBS original data and expected data generated by the external module; the processor is used to execute the aforementioned Figure 4 The stress test method shown in the figure. This hardware system design simplifies the design of the PRBS module and reduces the complexity of the hardware design; at the same time, it can also generate pseudo-random binary sequences of different orders, which is more flexible and can meet the application requirements of different scenarios, achieving the purpose of stress testing DDR.
[0140] An embodiment of the present invention also provides a computer-readable storage medium, and the above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented by downloading through a network and originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware.
[0141] The storage medium may be a disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium may also include a combination of the above-mentioned types of memories. It is understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the storage method and stress test method of the pseudo-random sequence shown in the above embodiment are implemented.
[0142] Embodiments of the present application may also provide a computer program product, including computer program instructions, which, when executed by a processor, cause the processor to perform the steps in the above method. Wherein, the computer program product may be written in any combination of one or more programming languages to perform program codes for performing the operations of the disclosed embodiments, wherein the programming languages include object-oriented programming languages, such as Java, C++, etc., and also include conventional procedural programming languages, such as "C" language or similar programming languages. The program code may be executed entirely on a user computing device, partially on a user device, as an independent software package, partially on a user computing device, partially on a remote computing device, or entirely on a remote computing device or server.
[0143] The above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the embodiments of the present invention are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some of the technical features therein by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for storing a pseudo-random sequence, characterized in that: Applied to an external module, the external module is connected to an integrated circuit, the integrated circuit is integrated with a processor and a memory, the method comprises: Acquire memory information of the memory and the address of the reserved storage resource in the memory, wherein the memory information includes the size of the memory resource of the memory; Generate pseudo-random binary sequence PRBS original data according to the memory resource size and pseudo-random binary sequence algorithm; Processing the PRBS original data according to a preset clustering algorithm to generate expected data corresponding to the PRBS original data, wherein the expected data is used to perform a stress test on the PRBS original data; The PRBS original data and the expected data are stored in the reserved storage resources of the memory according to the address.
2. The method according to claim 1, characterized in that The address of the reserved storage resource in the memory includes: a first address and a second address, and the first address corresponds to a first storage unit, and the second address corresponds to a second storage unit; The storing the PRBS original data and the expected data in the reserved storage resources of the memory according to the address includes: storing the PRBS original data in a first storage unit reserved in the memory according to the first address; The expected data is stored in a second storage unit reserved in the memory according to the second address.
3. The method according to claim 1, characterized in that The preset clustering algorithm is a reduce algorithm; The processing of the PRBS original data according to a preset clustering algorithm to generate expected data corresponding to the PRBS original data includes: The PRBS original data is processed according to the reduce algorithm to generate the expected data.
4. The method according to any one of claims 1 to 3, characterized in that: After storing the PRBS original data and the expected data in the reserved storage resources of the memory according to the address, the method further includes: generating an indication signal; The indication signal is sent to the processor, where the indication signal is used to notify the processor that a write operation on the PRBS original data and the expected data has been completed.
5. A stress test method, characterized in that: Applied to a processor, the processor is connected to an external module, the processor is also connected to a memory, the processor and the memory are both integrated on an integrated circuit, the method comprises: Start a signal detection function to detect whether there is an indication signal sent from an external module, wherein the indication signal is used to notify the processor that the writing operation of the PRBS original data and the expected data has been completed; If yes, reading the PRBS original data and the expected data from the reserved storage resources of the memory respectively according to the address of the reserved storage resources in the memory; Preprocessing the PRBS original data to generate PRBS evolved data, and comparing whether the PRBS evolved data is the same as the expected data; If they are the same, it is determined that the stress test on the memory has passed; otherwise, the stress test has failed.
6. The method according to claim 5, characterized in that The preprocessing of the PRBS original data to generate PRBS evolution data includes: A matrix multiplication operation is performed on the PRBS original data to generate the PRBS evolved data.
7. The method according to claim 5 or 6, characterized in that: The address of the reserved storage resource in the memory includes: a first address and a second address, and the first address corresponds to a first storage unit, and the second address corresponds to a second storage unit; The step of reading the PRBS original data and the expected data from the reserved storage resources of the memory according to the addresses of the reserved storage resources in the memory comprises: The PRBS original data is obtained from the first storage unit of the memory according to the first address, and the expected data is obtained from the second storage unit of the memory according to the second address.
8. A storage device for a pseudo-random sequence, characterized in that: The device is connected to an integrated circuit, on which a processor and a memory are integrated, and the device comprises: An acquisition module, used to acquire memory information of the memory and the address of the reserved storage resource in the memory, wherein the memory information includes the size of the memory resource of the memory; A generating module, used for generating pseudo-random binary sequence PRBS original data according to the size of the memory resource and the pseudo-random binary sequence algorithm; A processing module, used for processing the PRBS original data according to a preset clustering algorithm to generate expected data corresponding to the PRBS original data, wherein the expected data is used for performing a stress test on the PRBS original data; A storage module is used to store the PRBS original data and the expected data in the reserved storage resources of the memory according to the address.
9. A computer-readable storage medium, characterized in that: The computer readable storage medium has computer instructions stored thereon. The computer instructions are used to enable a computer to execute the pseudo-random sequence storage method as described in any one of claims 1 to 4, or to execute the stress testing method as described in any one of claims 5 to 7.
10. A system, characterized in that: The system includes an external module and an integrated circuit, wherein the external module is connected to the integrated circuit, and a processor and a memory are integrated on the integrated circuit; Wherein, the external module is used to execute the storage method of the pseudo-random sequence according to any one of claims 1 to 4; The memory is used to store the PRBS original data and expected data generated by the external module; The processor is used to execute the stress testing method as described in any one of claims 5 to 7.