Interconnection high-speed interface, core particle and communication method

Abstract

The invention provides an interconnection high-speed interface, a core particle and a communication method, and the interconnection high-speed interface comprises a first packaging module which is used for receiving home terminal write address request information, home terminal write data information and home terminal read address request information of a core particle main body, carrying out the packaging processing of the information, and sending the information to a far-end core particle; the first decapsulation module is used for receiving far-end write completion information and far-end read data information of a far-end core particle, performing decapsulation processing and sending the information to the core particle main body; the second de-encapsulation module is used for receiving far-end write address request information, far-end write data information and far-end read address request information from a far-end core particle, performing de-encapsulation processing and sending the information to the core particle main body; and the second packaging module is used for receiving the local-end write completion information and the local-end read data information of the core particle main body, performing packaging processing and sending the information to the far-end core particle. Through the interconnection high-speed interface, the core particle and the communication method provided by the invention, the AXI interface can be adapted to the UCIe link.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to an interconnection high-speed interface, a core particle and a communication method. Background Art

[0002] The current system-on-chip (SoC) and some high-performance computing solutions widely use the AXI (Advanced Xtensible Interface) bus protocol as the internal communication bus. The AXI bus has become an important part of the system-on-chip due to its efficient data transmission capabilities and flexible memory mapping characteristics. However, with the continuous growth of modern computing needs, the chip area growth of a single SoC has encountered a bottleneck. Chiplet is the mainstream technology to solve this problem. The interconnection between chiplets is the key technology to realize the chiplet solution. The AXI bus is not suitable for communication between chiplets due to the large number of interface signals. Traditional interconnection solutions such as PCIe are limited in transmission bandwidth, latency and power consumption, and it is difficult to meet the needs of high-performance applications.

[0003] On the other hand, the UCIe (Universal Chiplet Interconnect Express) protocol, as an emerging high-speed interconnect bus protocol between chiplets, provides high-bandwidth and low-latency data transmission capabilities. The UCIe link is designed for high-speed data communication between chiplets, and is suitable for interconnection between chiplets and between chips on boards. However, there is currently no ready-made implementation method for adapting the AXI interface to the UCIe link on the market, which greatly limits the application of the UCIe link in existing AXI systems. Therefore, there is room for improvement. Summary of the invention

[0004] The object of the present invention is to provide an interconnect high-speed interface, a core particle and a communication method, which can adapt an AXI interface to a UCIe link.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides an interconnect high-speed interface, comprising:

[0007] A first encapsulation module is used to receive local write address request information, local write data information, and local read address request information of the core particle body through the AXI bus, and encapsulate and process them to send them to the remote core particle through the UCIe link;

[0008] A first decapsulation module is used to receive, through the UCIe link, remote write completion information fed back by the remote core particle according to the local write address request information and the local write data information, and is also used to receive, through the UCIe link, remote read data information fed back by the remote core particle according to the local read address request information, and decapsulate the remote write completion information and the remote read data information to send them to the core particle body through the AXI bus;

[0009] a second decapsulation module, configured to receive remote write address request information, remote write data information, and remote read address request information from the remote core particle through the UCIe link, and perform decapsulation processing to send the information to the core particle body through the AXI bus; and

[0010] The second encapsulation module is used to receive the local write completion information fed back by the core particle body according to the remote write address request information and the remote write data information through the AXI bus, and is also used to receive the local read data information fed back by the core particle body according to the remote read address request information through the AXI bus, and encapsulate the local write completion information and the local read data information to send them to the remote core particle through the UCIe link.

[0011] In one embodiment of the present invention, the first packaging module includes:

[0012] A first write address cache unit, used for caching the local end write address request information;

[0013] A first write data cache unit, used for caching the local end write data information;

[0014] A first read address cache unit, used for caching the local end read address request information;

[0015] A first arbitrator, configured to send the local-end write address request information, the local-end write data information, and the local-end read address request information in sequence according to a priority order;

[0016] a first encapsulation unit, configured to encapsulate the local-end write address request information, the local-end write data information, and the local-end read address request information to generate a data frame; and

[0017] The first sending unit is configured to send the data frame to the remote chiplet through a UCIe link.

[0018] In one embodiment of the present invention, the first decapsulation module includes:

[0019] A first receiving unit, configured to receive a data frame sent by the remote chiplet;

[0020] A first decapsulation unit, configured to decapsulate the data frame to generate the remote write completion information and the remote read data information;

[0021] A second write completion cache unit, used for caching the remote write completion information;

[0022] A second read data cache unit, configured to cache the remote read data information; and

[0023] The first interface unit is used to send the remote write completion information and the remote read data information to the core body.

[0024] In one embodiment of the present invention, the second decapsulation module includes:

[0025] A second receiving unit, configured to receive a data frame sent by the remote core;

[0026] A second decapsulation unit, configured to decapsulate the data frame to generate the remote write address request information, the remote write data information, and the remote read address request information;

[0027] A second write address cache unit, used for caching the remote write address request information;

[0028] A second write data cache unit, used for caching the remote write data information;

[0029] A second read address cache unit, configured to cache the remote read address request information; and

[0030] The second interface unit is used to send the remote write address request information, the remote write data information, and the remote read address request information to the core body.

[0031] In one embodiment of the present invention, the second packaging module includes:

[0032] A first write completion cache unit, used for caching the local end write completion information;

[0033] A first read data cache unit, used for caching the local end read data information;

[0034] A second arbitrator is used to send the local end write completion information and the local end read data information in sequence according to the priority order;

[0035] A second encapsulation unit is used to encapsulate the local end write completion information and the local end read data information to generate a data frame; and

[0036] The second sending unit is used to send the data frame to the remote core particle.

[0037] In one embodiment of the present invention, the first encapsulation module further includes a first processing unit, the first processing unit being used to divide the local write address request information, the local write data information and the local read address request information in the AXI format into data packets of a fixed size, so as to cache different data packets in corresponding cache units;

[0038] The first encapsulation unit is used to obtain at least one data packet and write the data packet into a payload area of ​​a data frame in a UCIe format to generate a corresponding data frame.

[0039] In one embodiment of the present invention, the second encapsulation module further includes a second processing unit, which is used to divide the local write completion information and the local read data information in the AXI format into data packets of fixed size, so as to cache different data packets in corresponding cache units;

[0040] The second encapsulation unit is used to obtain at least one data packet and write the data packet into a payload area of ​​a data frame in a UCIe format to generate a corresponding data frame.

[0041] In one embodiment of the present invention, the data frame is 64 bytes of data, the frame header includes 2 bytes of data, the frame tail includes 2 bytes of data, the transmission block includes 60 bytes of data, and the data frame includes:

[0042] Frame header, used to store identifier;

[0043] a payload area, used to write at least one of the data packets, the data packets being used to store one of the local-end write address request information, the local-end write data information, the local-end read address request information, the local-end write completion information, and the local-end read data information; and

[0044] Frame tail, used to store the checksum.

[0045] In one embodiment of the present invention, when writing the data packet into the payload area, the data of the data packet is aligned with the byte boundary of the data frame, and when there is a non-aligned portion in the data packet, invalid data is filled into the non-aligned portion.

[0046] The present invention also provides a core particle, wherein the core particle comprises the interconnection high-speed interface.

[0047] The present invention also provides a communication method of a core particle, which is applied to a core particle, wherein the core particle is divided into a local core particle and a remote core particle, and the interconnection high-speed interface of the local core particle includes a first encapsulation module, a second encapsulation module, a first decapsulation module, and a second decapsulation module. The communication method includes:

[0048] The first encapsulation module receives the local write address request information, the local write data information, and the local read address request information of the core particle body through the AXI bus, and encapsulates and processes them to send them to the remote core particle through the UCIe link;

[0049] The first decapsulation module receives, through the UCIe link, remote write completion information fed back by the remote chip according to the local write address request information and the local write data information;

[0050] The first decapsulation module receives, through the UCIe link, remote read data information fed back by the remote chip according to the local read address request information;

[0051] The first decapsulation module decapsulates the remote write completion information and the remote read data information to send them to the core particle body through the AXI bus;

[0052] The second decapsulation module receives remote write address request information, remote write data information, and remote read address request information from the remote core particle through the UCIe link, and performs decapsulation processing to send the information to the core particle body through the AXI bus;

[0053] The second encapsulation module receives, through the AXI bus, local write completion information fed back by the core particle body according to the remote write address request information and the remote write data information;

[0054] The second encapsulation module receives the local end read data information fed back by the core particle body according to the remote end read address request information through the AXI bus;

[0055] The second encapsulation module encapsulates the local write completion information and the local read data information to send them to the remote chip through the UCIe link.

[0056] The present invention provides an interconnection high-speed interface, a core particle and a communication method, which are compatible with the AXI bus protocol and the UCIe high-speed interconnection transmission protocol. This compatibility enables the solution to be applied to the interconnection between core particles in complex SoC packages and between chips on boards in the field of high-performance computing and data centers, greatly improving the flexibility and adaptability of the system. By encapsulating the AXI bus message into a data frame in Flit format and designing a corresponding Flit transmission processing mechanism, the UCIe bus can be better connected to interconnect core particles and chips. The data frame in Flit format is more suitable for efficient transmission in a high-performance computing environment and can support high-bandwidth and low-latency communication requirements. By designing a multi-channel multiplexing mechanism, the bandwidth and efficiency of data transmission are further improved, while ensuring low latency and high reliability. This is very important for systems that require fast and large-scale data exchange, and can meet the needs of modern data centers and high-performance computing for efficient data processing. By optimizing the data encapsulation and transmission mechanism, while achieving high-performance transmission, the power consumption of the system can also be significantly reduced. This is an important advantage for large-scale data processing and continuously running high-performance computing systems, which can reduce energy consumption and heat generation and extend system life. The above scheme is simple and efficient in design, so that the data of AXI bus protocol can be transmitted through the high-speed interface of UCIe link. Compared with the traditional scheme, the implementation of this conversion scheme is more direct, reducing the complex design workload while maintaining high-performance transmission effect.

[0057] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0059] Figure 1 is a schematic diagram of a first packaging module in an embodiment of the present invention;

[0060] Figure 2 is a schematic diagram of a first decapsulation module in an embodiment of the present invention;

[0061] Figure 3 is a schematic diagram of a second decapsulation module in one embodiment of the present invention;

[0062] Figure 4 is a schematic diagram of a second packaging module in one embodiment of the present invention;

[0063] Figure 5It is a schematic diagram of the cooperation between the arbitrator and the data frame in one embodiment of the present invention.

[0064] In the figure:

[0065] 100, AXI bus;

[0066] 200, first encapsulation module; 210, first processing unit; 220, first write address cache unit; 230, first write data cache unit; 240, first read address cache unit; 250, first arbitrator; 260, first encapsulation unit; 270, first sending unit; 280, first bus interface unit;

[0067] 300, first decapsulation module; 310, second bus interface unit; 320, first receiving unit; 330, first decapsulation unit; 340, second write completion cache unit; 350, second read data cache unit; 360, first interface unit;

[0068] 400, second decapsulation module; 410, third bus interface unit; 420, second receiving unit; 430, second decapsulation unit; 440, second write address cache unit; 450, second write data cache unit; 460, second read address cache unit; 470, second interface unit;

[0069] 500, second encapsulation module; 510, second processing unit; 520, first write completion cache unit; 530, first read data cache unit; 540, second arbitrator; 550, second encapsulation unit; 560, second sending unit; 570, fourth bus interface unit;

[0070] 600. UCIe link. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0072] See also Figure 1 The present invention provides a high-speed interface for interconnecting chiplets, where the chiplets can be processor chiplets, memory chiplets, I / O chiplets, etc. Multiple chiplets with different functions can be packaged into one chip to improve the performance of the chip. The chiplets can be interconnected through UCIe links to form a fully functional system. UCIe links support high-speed data transmission, ensuring high bandwidth and low latency for data exchange between chiplets.

[0073] In one embodiment, the chiplet may include a chiplet body and an interconnection high-speed interface. The interconnection high-speed interface may include an AXI bus 100, a first encapsulation module 200, a first decapsulation module 300, a second decapsulation module 400, a second encapsulation module 500, and a UCIe link 600. Among them, the chiplet body can send AXI bus instructions and information to the remote chiplet through the UCIe link, and receive AXI bus instructions and information of the remote chiplet through the UCIe link. The AXI bus and the UCIe link may be connected with a first encapsulation module 200, a second encapsulation module 300, a first decapsulation module 400, and a second decapsulation module 500. The above-mentioned encapsulation module can encapsulate the AXI format of instructions and information into the UCIe format so as to be transmitted through the UCIe link. The above-mentioned decapsulation module can decapsulate the UCIe format of instructions and information into the AXI format so as to be transmitted to the chiplet body through the AXI format.

[0074] Specifically, the core particle body refers to the core functional modules inside the core particle, such as computing units, storage units or dedicated processing units (such as AI accelerators, GPU cores, etc.). These core functional modules are responsible for executing the main computing tasks of the core particle.

[0075] See also Figure 1 In one embodiment, when the local chip needs to access the remote chip, the first encapsulation module 200 may be connected between the AXI bus 100 and the UCIe link 600. The first encapsulation module 200 may be used to receive the local write address request information, the local write data information, and the local read address request information of the chip body of the local chip through the AXI bus 100, and encapsulate and process them to send them to the remote chip through the UCIe link 600.

[0076] See also Figure 1 In one embodiment, the first encapsulation module 200 may include a first processing unit 210 (AXI-4slave, SAXI4), a first write address cache unit 220 (Address Write FIFO, AW FIFO), a first write data cache unit 230 (Data Write FIFO, DW FIFO), a first read address cache unit 240 (Address Read FIFO, ARFIFO), a first arbitrator 250 (TX arbitrator), a first encapsulation unit 260 (Flit Framer), a first sending unit 270 (FLIT_TX), and a first bus interface unit 280 (Stream).

[0077] In one embodiment, in an AXI bus, bus transmission generally involves a master device (Master) and a slave device (Slave). The master device initiates a transmission request, and the slave device responds to these requests. The first processing unit 210 can be an AXI-4 standard slave device interface. The interface is responsible for receiving AXI bus signals sent from the chip body (master device). AXI bus signals may include but are not limited to address signals (including local write address request information and local read address request information, used to indicate the memory address to be read and written by data), control signals (such as read-write control), data signals (including local write data information, referring to the actual data content), etc.

[0078] In one embodiment, after the first processing unit 210 receives the local write address request information, local write data information, and local read address request information of the core body, the local write address request information, local write data information, and local read address request information in AXI format can be divided into fixed-size data packets to cache different data packets in corresponding cache units. For example, the data packet corresponding to the local write address request information can be cached in the first write address cache unit 220, the data packet corresponding to the local write data information can be cached in the first write data cache unit 230, and the data packet corresponding to the local read address request information can be cached in the first read address cache unit 240.

[0079] In one embodiment, the first write address cache unit 220 can be used to cache information on the write address channel. The stored content may include write address, user ID, burst transfer length, effective transfer byte length, etc. The write address refers to the memory address where the data needs to be written. The user ID refers to the unique user or transaction ID used to identify the current transmission, which is important for distinguishing different write operations in parallel operation and multi-user environments. The burst transfer length refers to the amount of data contained in a burst transfer, usually in bytes or words. The effective transfer byte length refers to the actual effective number of transfer bytes, which determines which data is meaningful during the transmission process. The first write address cache unit 220 can be used to manage and temporarily store information on the write address channel to ensure that information such as write address, user ID and transfer length can be transmitted to the slave device in an orderly and correct manner.

[0080] In one embodiment, the first write data cache unit 230 can be used to cache information on the write data channel. The storage content may include data, byte write enable (wstrobe), the last write data indication (wlast), etc. Data refers to the written data itself. Byte write enable refers to a control signal used to indicate which bytes are valid write operations. Because in some operations, only part of the bytes may need to be written, rather than the entire data word. The last write data refers to a flag signal used to indicate whether the currently transmitted write data is the last one. The AXI bus supports a burst transfer mode, in which a transmission may contain multiple data cycles, and the last write data indication signal is used to mark the end of the burst transfer. The first write data cache unit 230 can be used to temporarily store and manage all data packets to be sent or processed on the write data channel and related control signals. It can ensure the orderly transmission of write data and ensure that the data is correctly written to the target location.

[0081] In one embodiment, the first read address cache unit 240 can be used to cache information on the read address channel. The stored content may include a read address, a user ID, a burst transfer length, an effective transfer byte length, etc. The read address refers to the memory address from which data is read. The user ID is used to identify the unique ID of each read transaction. The burst transfer length refers to the amount of read data contained in a burst transfer. The effective transfer byte length refers to the actual effective number of transfer bytes. The first read address cache unit 240 can be responsible for managing the address information in the read operation, ensuring that the read operation can start from the correct address, and can identify different read transactions in a multi-user environment.

[0082] In one embodiment, the first write address cache unit 220, the first write data cache unit 230, and the first read address cache unit 240 may correspond to different channels in the AXI bus protocol, and are used for information storage and management of write data, write address, and read address, respectively. Their main function is to ensure that such information can be correctly processed and managed during the transmission process, thereby ensuring smooth data transmission. The information stored in each channel includes not only the data or address itself, but also related control signals, ensuring that data transmission can still be completed correctly in a complex transmission environment.

[0083] In one embodiment, the first arbitrator 250 can be used to manage how to select and schedule these requests when multiple AXI channels send send requests at the same time, ensuring that they are processed and transmitted in a predetermined priority order. The first arbitrator 250 can be a logic unit responsible for decision-making and scheduling. When multiple channels send send requests at the same time, the task of the arbitrator is to decide which channel's request will be processed first according to the preset priority rules, ensuring that system resources can be reasonably allocated to avoid conflicts or congestion in data transmission. The first arbitrator 250 can be used to send local write address request information, local write data information, and local read address request information in sequence according to the priority order.

[0084] In one embodiment, the first encapsulation unit 260 is a component that encapsulates the information of the AXI bus protocol into a fixed-size data frame for transmission through the UCIe link, so that the data packets of the AXI bus can be efficiently transmitted in different transmission protocols (such as UCIe). In the UCIe link, the size of Flit is usually fixed to 64 bytes (64B). Flit is the abbreviation of data frame, which refers to the basic data unit transmitted in the UCIe link. The function of the first encapsulation unit 260 is to package various information in the AXI bus into one or more 64B data frames to meet the transmission requirements of the UCIe link.

[0085] Specifically, the first encapsulation unit 260 reorganizes the data and control information in the AXI bus according to the requirements of the UCIe link. This includes integrating the local write address request information, the local write data information, the local read address request information and other control signals into one or more data frames. If the AXI information is not enough to fill 64B, additional invalid data needs to be filled to reach the specified data frame size.

[0086] In one embodiment, the first sending unit 270 and the first bus interface unit 280 can cooperate with each other to be responsible for data transmission within the system. The first sending unit 270 is responsible for sending the data packaged into Flit to the first bus interface unit 280, and the first bus interface unit 280 is responsible for receiving the data and passing it to the UCIe link, and finally sending it to the remote chiplet through the UCIe link.

[0087] In one embodiment, the first sending unit 270 and the first bus interface unit 280 can interact through Tvld, Tdat and TREADY signals to form a handshake mechanism to ensure reliable data transmission. The first sending unit 270 is responsible for sending data and the first bus interface unit 280 is responsible for receiving data, while Tvld and TREADY signals ensure coordination between the sender and the receiver. Through this mechanism, efficient data transmission can be achieved between different units while ensuring the integrity and correctness of the data.

[0088] Specifically, Tvld (Transmit Valid) is a validity signal used to indicate whether the data currently being transmitted is valid. When Tvld is high (1), it indicates that the data on the current data line is valid and can be read by the receiving end. Tdat (Transmit Data) is the actual data line or data bus used to transmit the data block to be sent. Tdat carries the specific content of the Flit data. TREADY (Transmit Ready) is a readiness signal used to indicate whether the receiving end is ready to receive data. When TREADY is high (1), it indicates that the receiving end can receive new data. When both Tvld and TREADY are high, data transmission is successful. If Tvld is high and TREADY is low, it means that the receiving end is not ready to receive data and the sending end needs to wait.

[0089] In one embodiment, after the first encapsulation module 200 sends the above data frame (including local write address request information, local write data information, local read address request information) to the remote core particle through the UCIe link, the remote core particle can feedback remote write completion information to the local core particle based on the local write address request information and the local write data information. The remote core particle can feedback remote read data information to the local core particle based on the local read address request information. Among them, the remote write completion information and remote read data information fed back by the remote core particle can be sent to the first decapsulation module 300 through the UCIe link. At this time, the remote write completion information and remote read data information are sent to the local core particle in the form of data frames.

[0090] See also Figure 2 In one embodiment, the first decapsulation module 300 may be connected between the AXI bus 100 and the UCIe link 600. The first decapsulation module 300 may be used to receive the data frame sent by the remote core particle and decapsulate the data frame to send the decapsulated remote write completion information and remote read data information to the core particle body of the local core particle through the AXI bus.

[0091] See also Figure 2In one embodiment, the first decapsulation module 300 may include a second bus interface unit 310 (Stream), a first receiving unit 320 (FLIT_RX), a first decapsulation unit 330 (Flit deFramer), a second write completion cache unit 340 (Write Response FIFO, WRSP FIFO), a second read data cache unit 350 (Read Data FIFO, RD), and a first interface unit 360 (AXI-4Slave, SAXI4).

[0092] In one embodiment, the second bus interface unit 310 and the first receiving unit 320 can cooperate with each other to be responsible for data transmission within the system. The second bus interface unit 310 is responsible for sending the data encapsulated into Flit to the first receiving unit 320, and the first receiving unit 320 is responsible for receiving the data and passing it to the first decapsulation unit 330. The second bus interface unit 310 and the first receiving unit 320 can interact through Tvld, Tdat and TREADY signals to form a handshake mechanism to ensure reliable data transmission.

[0093] In one embodiment, the first decapsulation unit 330 is a unit for receiving and processing the transmitted Flit data block, and its main function is to decapsulate the AXI bus information previously encapsulated in the Flit, thereby extracting the original remote write completion information and remote read data information. The first decapsulation unit 330 can reverse the previous encapsulation process and restore the Flit to the original information format of the AXI bus. This process involves parsing the data structure of the Flit, extracting the various information contained therein, and converting the information into a format that the AXI bus can recognize and process.

[0094] Specifically, the first decapsulation unit 330 first needs to parse the received Flit data block and identify the information carried by different parts thereof. When transmitting a write operation, Flit will contain relevant information about the completion of the write, which is used to indicate whether the write operation is successfully completed, such as remote write completion information. The first decapsulation unit 330 will extract this information so that the system can perform corresponding subsequent processing or confirmation. For a read operation, Flit will carry the requested remote read data information. After the first decapsulation unit 330 decapsulates Flit, it will extract the remote read data information and pass it to the unit that needs to use the data.

[0095] In one embodiment, the second write completion cache unit 340 can be used to cache and manage data streams, and can temporarily store and queue the decapsulated remote write completion information for subsequent processing by the system. This cache mechanism plays a role of buffering and regulation in the data transmission chain, ensuring that data can be processed according to the rhythm of the system without causing system performance degradation due to excessive or uneven instantaneous data transmission.

[0096] Specifically, the second write completion cache unit 340 is used to cache remote write completion information, that is, to store the write operation completion status decapsulated from the first decapsulation unit 330. This information includes whether the write operation is successful, error status, etc. When the first decapsulation unit 330 decapsulates the remote write completion information, this information is written into the second write completion cache unit 340.

[0097] In one embodiment, the second read data cache unit 350 is used to cache and manage data streams, which can temporarily store and queue the decapsulated remote read data information for subsequent processing by the system. The second read data cache unit 350 is used to cache the remote read data information, which is the data content read by the local chip from the remote chip.

[0098] In one embodiment, the first interface unit 360 can extract the remote write completion information and the remote read data information from the second write completion cache unit 340 and the second read data cache unit 350, and send the information to the core particle main bus through the AXI bus. In this way, the first interface unit 360 ensures that the local core particle can correctly initiate write operations and read operations to the remote core particle, and can timely process the completion of the write operation and the data return of the read operation.

[0099] See also Figure 3 In one embodiment, when the remote chip needs to access the local chip, the second decapsulation module 400 may be connected between the AXI bus 100 and the UCIe link 600. The second decapsulation module 400 may be used to receive remote write address request information, remote write data information, and remote read address request information from the remote chip through the UCIe link 600, and perform decapsulation processing to send them to the chip body through the AXI bus.

[0100] See also Figure 3In one embodiment, the second decapsulation module 400 may include a third bus interface unit 410 (Stream), a second receiving unit 420 (FLIT_RX), a second decapsulation unit 430 (Flit deFramer), a second write address cache unit 440 (Address Write FIFO, AW FIFO), a second write data cache unit 450 (Data Write FIFO, DW FIFO), a second read address cache unit 460 (Address Read FIFO, AR FIFO), and a second interface unit 470 (AXI-4Master, MAXI4).

[0101] In one embodiment, the third bus interface unit 410 and the second receiving unit 420 can cooperate with each other to be responsible for data transmission within the system. The third bus interface unit 410 is responsible for sending the data encapsulated into Flit to the second receiving unit 420, and the second receiving unit 420 is responsible for receiving the data and passing it to the second decapsulation unit 430. The third bus interface unit 410 and the second receiving unit 420 can interact through Tvld, Tdat and TREADY signals to form a handshake mechanism to ensure reliable data transmission.

[0102] In one embodiment, the second decapsulation unit 430 is a unit for receiving and processing the transmitted Flit data block, and its main function is to decapsulate the AXI bus information previously encapsulated in the Flit, thereby extracting the original remote core grain access to the local core grain remote write address request information, remote write data information, remote read address request information and other information. The second decapsulation unit 430 can be used to restore the Flit to the original information format of the AXI bus. Among them, the specific structure of the second decapsulation unit 430 and the first decapsulation unit 330 can be the same, so as to decapsulate different Flits.

[0103] In one embodiment, the second write address cache unit 440 can be used to cache information on the write address channel. The stored content may include a write address, a user ID, a burst transmission length, a valid transmission byte length, etc. Specifically, the second write address cache unit 440 can be used to cache remote write address request information for a remote chip to access a local chip.

[0104] In one embodiment, the second write data cache unit 450 can be used to cache information on the write data channel. The stored content may include data, byte write enable (wstrobe), the last write data indication (wlast), etc. Specifically, the second write data cache unit 450 can be used to cache the remote write data information of the remote chip to access the local chip.

[0105] In one embodiment, the second read address cache unit 460 can be used to cache information on the read address channel. The stored content may include a read address, a user ID, a burst transmission length, a valid transmission byte length, etc. Specifically, the second read address cache unit 460 can be used to cache remote read address request information for a remote chip to access a local chip.

[0106] In one embodiment, the second interface unit 470 can extract remote write address request information, remote write data information, remote read address request information and other information of the remote chip to access the local chip from the second write address cache unit 440, the second write data cache unit 450, and the second read address cache unit 460, and send this information to the chip main bus through the AXI bus.

[0107] In one embodiment, after the second decapsulation module 400 receives the above-mentioned data frame (including remote write address request information, remote write data information, and remote read address request information) through the UCIe link 600, it can be decapsulated. The core grain body of the local core grain can feedback the local write data information to the remote core grain according to the remote write address request information and the remote write data information. The core grain body of the local core grain can feedback the local read data information to the remote core grain according to the remote read address request information. Among them, the local write data information and the local read data information fed back by the core grain body of the local core grain can be sent to the second encapsulation module 500 through the AXI bus 100.

[0108] See also Figure 4 In one embodiment, the second encapsulation module 500 may be connected between the AXI bus 100 and the UCIe link 600. The second encapsulation module 500 may be used to receive local write data information and local read data information of the chiplet body of the local chiplet through the AXI bus 100, and encapsulate and process the information so as to send the information to the remote chiplet through the UCIe link 600.

[0109] See also Figure 4 In one embodiment, the second encapsulation module 500 may include a second processing unit 510 (AXI-4Master, MAXI4), a first write completion cache unit 520 (Write Response FIFO, WRSP FIFO), a first read data cache unit 530 (Read Data FIFO, RD), a second arbitrator 540 (TX arbitrator), a second encapsulation unit 550 (Flit Framer), a second sending unit 560 (FLIT_TX), and a fourth bus interface unit 570 (Stream).

[0110] In one embodiment, the second processing unit 510 may be an AXI-4 standard master device interface, which is responsible for receiving local write completion information and local read data information sent from the chip body (slave device).

[0111] In one embodiment, after the second processing unit 510 receives the local write completion information and the local read data information of the core body, the local write completion information and the local read data information in the AXI format can be divided into fixed-size data packets to cache different data packets in corresponding cache units. For example, the data packet corresponding to the local write completion information can be cached in the first write completion cache unit 520, and the data packet corresponding to the local read data information can be cached in the first read data cache unit 530.

[0112] In one embodiment, the first write completion cache unit 520 can be used to cache and manage data streams, which can temporarily store and queue the local write completion information for subsequent processing by the system. This cache mechanism plays a role of buffering and regulation in the data transmission chain, ensuring that data can be processed according to the rhythm of the system without causing system performance degradation due to excessive or uneven instantaneous data transmission. Specifically, the first write completion cache unit 520 is used to cache the local write completion information, that is, to store the completion status of the write operation from the core particle body. This information includes whether the write operation is successful, error status, etc.

[0113] In one embodiment, the first read data cache unit 530 is used to cache and manage data streams, which can temporarily store and queue local read data information for subsequent processing by the system. The first read data cache unit 530 is used to cache remote read data information, which is the data content read by the remote chip from the local chip.

[0114] In one embodiment, the second arbiter 540 can be used to manage how to select and schedule these requests when multiple AXI channels send transmission requests at the same time, ensuring that they are processed and transmitted in a predetermined priority order. The second arbiter 540 can be used to send the local write data information and the local read data information in sequence according to the priority order.

[0115] In one embodiment, the second encapsulation unit 550 is a component that encapsulates the information of the AXI bus protocol into a fixed-size data block for transmission over the UCIe link, so that the data of the AXI bus can be efficiently transmitted in different transmission protocols (such as UCIe). The second encapsulation unit 550 reorganizes the data and control information in the AXI bus according to the requirements of the UCIe link. This includes integrating the local write data information with the local read data information and other control signals into one or more data frames. If the AXI information is not enough to fill 64B, additional invalid data needs to be filled to reach the specified data frame size.

[0116] In one embodiment, the second sending unit 560 and the fourth bus interface unit 570 can cooperate with each other to be responsible for data transmission within the system. The second sending unit 560 is responsible for sending the data encapsulated into Flit to the fourth bus interface unit 570, and the fourth bus interface unit 570 is responsible for receiving the data and passing it to the UCIe link 600, and finally feeding back to the remote core particle through the UCIe link 600. The second sending unit 560 and the fourth bus interface unit 570 can interact through Tvld, Tdat and TREADY signals to form a handshake mechanism to ensure reliable data transmission.

[0117] In one embodiment, a priority order can be preset in the first arbitrator 250 and the second arbitrator 540 to send the local write data information, the local write address request information, the local read address request information, the local read data information, and the local write completion information respectively. For example, the priorities of the local write data information, the local write address request information, the local read address request information, the local read data information, and the local write completion information are successively reduced. For another example, the priorities of the local write data information, the local write address request information, the local read address request information, the local read data information, and the local write completion information are successively increased. In this embodiment, the specific priority order of the local write data information, the local write address request information, the local read address request information, the local read data information, and the local write completion information is not limited, as long as it can satisfy the requirement of sending different information in sequence.

[0118] In one embodiment, the first encapsulation module 200 can encapsulate the local write data information, local write address request information, and local read address request information in AXI format into a data frame in UCIe format. Specifically, the first processing unit 210 can divide the local write data information into data packets of a fixed size, in which case the number of the data packets can be at least one. The first processing unit 210 can also divide the local write address request information into data packets of a fixed size, in which case the number of the data packets can be at least one. The first processing unit 210 can also divide the local read address request information into data packets of a fixed size, in which case the number of the data packets can be at least one.

[0119] In one embodiment, the length of the data frame specified by the UCIe link 600 is fixed at 64 bytes, and the data frame may include a frame header, a payload area, and a frame tail. The frame header may be used to carry control information, metadata, identifiers, and other information. This information helps the receiving end understand how to process the received data. This information typically includes the destination address, priority, data type, or sequence number, etc. The length of the frame header may be 2 bytes of data. The payload area is the part of the Flit frame that carries the actual data, called the payload. This part of the data is directly related to the application layer and is the actual information transmitted from the high-level application or protocol. The length of the payload area may be 60 bytes of data. The frame tail may be used to store a checksum (CRC). CRC (Cyclic Redundancy Check) is a checksum mechanism for detecting data transmission errors. By calculating the data using a specific algorithm, the receiving end may verify whether an error has occurred in the transmission process of the transmitted data through the CRC checksum. The length of the frame tail may be 2 bytes of data. When the first processing unit 210 writes a data packet into the payload area, the data of the data packet needs to be aligned with the byte boundary of the data frame. When there is a non-aligned portion in the data packet, invalid data may be filled into the non-aligned portion.

[0120] In one embodiment, when decapsulating a data frame sent by a remote core particle through the first decapsulation module 300, the first decapsulation unit 330 can read out the data packet in the payload area according to the information stored in the frame header of the data frame, and divide the data packet into remote write completion information and remote read data information according to the type of the data packet.

[0121] In one embodiment, when decapsulating a data frame sent by a remote core particle through the second decapsulation module 400, the second decapsulation unit 430 can read out the data packet in the payload area according to the information stored in the frame header of the data frame, and divide the data packet into remote write address request information, remote write data information, and remote read address request information according to the type of the data packet.

[0122] In one embodiment, the second encapsulation module 500 can encapsulate the local write completion information and the local read data information in AXI format into a data frame in UCIe format. Specifically, the second processing unit 510 can divide the local write data information into data packets of a fixed size, and at this time, the number of the data packets can be at least one. The second processing unit 510 can also divide the local write completion information into data packets of a fixed size, and at this time, the number of the data packets can be at least one. The second processing unit 510 can also divide the local read data information into data packets of a fixed size, and at this time, the number of the data packets can be at least one. When the second processing unit 510 writes the data packet to the payload area, the data of the data packet needs to be aligned with the byte boundary of the data frame. When there is an unaligned part in the data packet, invalid data can be filled into the unaligned part.

[0123] In one embodiment, the number of data packets in a data frame may be at least one. In the same data packet, only one type of data among local write data information, local write address request information, local read address request information, local read data information, and local write completion information can be stored. When the number of data packets is multiple, different data packets can be used to store different types of data. The lengths of different data packets may be the same or different. For example, when the number of data packets is 3, the length of the first data packet may be 18 bytes of data, the length of the second data packet may be 20 bytes of data, and the length of the third data packet may be 22 bytes of data. For another example, the lengths of the three data packets may all be 20 bytes of data.

[0124] In one embodiment, as shown in Table 1, the data frame may consist of a frame header, three data packets of 20 bytes of data, and a frame trailer.

[0125] Table 1: Contents of the data frame.

[0126]

[0127] In one embodiment, the information stored in the frame header may include a data frame sequence number (SQ-ID[7:0]), a protocol type indication (type_f[1:0]), a first data packet type indication (type_f0[1:0]), a second data packet type indication (type_f1[1:0]), and a third data packet type indication (type_f2[1:0]).

[0128] In one embodiment, the default value of the data frame sequence number is 0. When the data frames need to be numbered, the data frame sequence number may start from 1. Each time a data frame is sent, the data frame sequence number of the next data frame is incremented by 1. Since the data frame sequence number is represented by eight bits of binary, when the data frame sequence number of a data frame is 255, the data frame sequence number of the next data frame may start from 1 again. The number 0 is not available.

[0129] In one embodiment, the protocol type indication may be a protocol type indication of a 64-byte Flit. The protocol type may be encoded by 2 bits to indicate the specific purpose or protocol of the Flit. During data transmission, each Flit contains this 2-bit protocol type field to indicate which type of frame it belongs to. The 2-bit encoding may represent 4 different values, ranging from 00 to 11, each value representing a different protocol type. Among them, 00 may represent an IDLE frame, which indicates an idle frame, with no actual data transmission, and is only used to keep the link active or for synchronization. 01 may represent an AXI bus, and this value indicates that the payload portion in the current Flit carries AXI (Advanced eXtensible Interface) protocol information, which is used for data transmission in high-performance computing systems. 10 may represent a test frame, which is used for testing purposes to verify the correctness of the link or for debugging. 11 may represent a flow control frame, which is used for flow control, management and coordination of the speed of data transmission, and prevention of data congestion or packet loss.

[0130] In one embodiment, the contents contained in the first data packet type indication, the second data packet type indication, and the third data packet type indication may be the same, and the first data packet type indication is used as an example for explanation. Here, the 20-byte data packet is named transfer, and the first data packet is named transfer0. The transfer type is indicated by a 2-bit encoding, which is used to indicate the specific type of the currently transmitted data during the transmission process. This 2-bit field can represent four different types of transfers (Transfer), each type being associated with specific data content. Among them, 00 can be represented as IDLE transfer, which represents idle transmission, has no valid data load, and is only used to keep the link active or achieve synchronization, similar to an idle frame, and is used when there is no actual data to be transmitted. 01 can be represented as AXI write address / read address / write response channel information loaded in transfer, indicating that the transmission content is control information related to the write address, read address or write response channel in the AXI bus. 10 can be represented as AXI write data channel information loaded in transfer, indicating that the transmission data load is the content of the AXI write data channel, that is, the data written by the master device to the slave device, and this channel is used for actual data write operations. 11 can be represented as AXI read data channel information loaded in transfer. This code indicates that the transmitted data is the content of the AXI read data channel, that is, the read data returned from the device to the master device.

[0131] In one embodiment, the frame tail (CRC16[15:0]) can be used to store the CRC check field of Flit. CRC (Cyclic Redundancy Check) is a technology used to detect data transmission errors. During the transmission process, the data may be interfered by noise or other factors, resulting in errors. CRC generates a check code by performing specific mathematical operations on the data, and recalculates and compares it at the receiving end to detect errors in transmission. In the above protocol, the range of CRC check protection starts from the lower byte of the Flit frame header (that is, bit[7:0] of the overhead field) and ends at the last byte of transfer2, covering a total of 62 bytes of data. The CRC check will perform check calculations on these 62 bytes of data in Flit. The CRC generator polynomial defines the calculation method of the CRC code, which can be expressed as (x+1)*(x15+x+1)=x16+x15+……+x2+1. For the given data (62 bytes), the sender will use the above generating polynomial to segment the data and calculate a 16-bit CRC check code bit by bit. This check code will be attached to the end of the Flit. When the receiver receives the data, it will recalculate the CRC using the same generating polynomial and compare it with the transmitted CRC check code. If the two are consistent, it means that there is no error in the data; if they are inconsistent, it means that an error occurred during the data transmission process.

[0132] See also Figure 5 In one embodiment, the first arbitrator 250 in the first encapsulation module 200 can arbitrate according to the sending request status of the three FIFOs of write address request information, write data information, and read address request information. At this time, the three signals aw_avail, dw_avail, and ar_avail can respectively represent the sending request status of the three FIFOs of write address request information, write data information, and read address request information. Among them, aw_avail = 0 means that the AXI write address channel has no data to be sent to the UCIe link, and aw_avail = 1 means that the AXI write address channel has data to be sent to the UCIe link. dw_avail = 0 means that the AXI write data channel has no data to be sent to the UCIe link, and dw_avail = 1 means that the AXI write data channel has data to be sent to the UCIe link. ar_avail = 0 means that the AXI read address channel has no data to be sent to the UCIe link, and ar_avail = 1 means that the AXI read address channel has no data to be sent to the UCIe link.

[0133] In one embodiment, when aw_avail=0, dw_avail=0, and ar_avail=0, it indicates that no AXI information needs to be sent and no Flit is generated.

[0134] In one embodiment, when aw_avail=0, dw_avail=0, and ar_avail=1, it indicates that only the AXI read address channel has data to be transmitted, while the other two channels have no data. At this time, a Flit containing the AXI read address information needs to be generated so as to be sent through the UCIe link. In the frame header, the type_t encoding value is 1: indicating that the current Flit is related to the AXI bus, and the receiving end can know that the transmission data inside this Flit conforms to the AXI bus format. The type_f0 encoding value is 1: indicating that the first data packet (transfer0) in the current Flit carries the information of the AXI read address channel. This is because ar_avail=1, so the data of this channel needs to be filled in transfer0. The type_f1 encoding value is 0: indicating that the second data packet (transfer1) in the current Flit is an IDLE transfer, that is, there is no actual data, indicating that this transmission unit is an invalid payload. This is because aw_avail=0, and there is no AXI write address data to be transmitted. transfer2 is an IDLE transfer: indicates that the third data packet (transfer2) is also an IDLE transfer. This is because dw_avail=0 and there is no AXI write data to be transferred.

[0135] In one embodiment, when aw_avail=0, dw_avail=1, and ar_avail=0, it indicates that only the AXI write data channel has data to be sent, and the AXI write address channel and the AXI read address channel have no data. At this time, a Flit containing write data needs to be generated so that it can be sent through the UCIe link. In the frame header, the type_t encoding value is 1: indicating that the current Flit is related to the AXI bus. The type_f0 encoding value is 0: indicating that the AXI read address channel has no data, so the first data packet (transfer0) is an IDLE transfer and has no actual data. The type_f1 encoding value is 1: indicating that the AXI write data channel has data, so the second data packet (transfer1) will carry AXI write data. transfer2 is an IDLE transfer: indicating that the AXI write address channel has no data, so the third data packet (transfer2) is an invalid payload (IDLE transfer).

[0136] In one embodiment, when aw_avail=0, dw_avail=1, and ar_avail=1, it indicates that both the AXI write data channel and the AXI read address channel have data to be sent, but the AXI write address channel has no data. At this time, the generated Flit will contain read address information and write data information. In the frame header, the type_t encoding value is 1: indicating that the current Flit carries AXI bus data. The type_f0 encoding value is 1: indicating that the AXI read address channel has data, so the first data packet (transfer0) carries the AXI read address information. The type_f1 encoding value is 1: indicating that the AXI write data channel has data, so the second data packet (transfer1) carries the AXI write data information. transfer2 is an IDLE transfer: indicating that the AXI write address channel has no data, and the third data packet (transfer2) is in an idle state (IDLE transfer).

[0137] In one embodiment, when aw_avail=1, dw_avail=0, and ar_avail=0, it indicates that only the AXI write address channel has data to be sent, and the other two channels have no data. At this time, the generated Flit will contain write address request information. In the frame header, the type_t encoding value is 1: indicating that the current Flit carries AXI bus data. The type_f0 encoding value is 1: indicating that the first data packet (transfer0) in the current Flit carries the information of the AXI write address channel. The type_f1 encoding value is 0: indicating that the write data channel has no data, so the second data packet (transfer1) is in an idle state (IDLEtransfer). transfer2 is an IDLE transfer: indicating that the read address channel has no data, so the third data packet (transfer2) is an invalid payload.

[0138] In one embodiment, when aw_avail=1, dw_avail=0, and ar_avail=1, it indicates that both the AXI write address channel and the AXI read address channel have data to be sent, but the AXI write data channel has no data. In the frame header, the type_t encoding value is 1: indicating that the current Flit contains AXI bus data. The type_f0 encoding value is 1: indicating that the AXI write address channel has data, and the first data packet (transfer0) carries the write address request information. The type_f1 encoding value is 0: indicating that the write data channel has no data, and the second data packet (transfer1) is in an idle state. transfer2 is the AXI read address information: indicating that the AXI read address channel has data, and the third data packet (transfer2) carries the read address information.

[0139] In one embodiment, when aw_avail=1, dw_avail=1, and ar_avail=0, it indicates that both the AXI write address channel and the write data channel have data to be sent, but the read address channel has no data. In the frame header, the type_t encoding value is 1: indicating that the current Flit contains AXI bus data. The type_f0 encoding value is 1: indicating that the AXI write address channel has data, and the first data packet (transfer0) carries the write address request information. The type_f1 encoding value is 1: indicating that the write data channel has data, and the second data packet (transfer1) carries the write data information. transfer2 is an IDLE transfer: indicating that the AXI read address channel has no data, and the third data packet (transfer2) is in an idle state.

[0140] In one embodiment, when aw_avail=1, dw_avail=1, and ar_avail=1, it indicates that all channels (AXI write address, write data, read address) have data to be sent, so the generated Flit will contain all the data of these channels. In the frame header, the type_t encoding value is 1: indicating that the current Flit contains AXI bus data. The type_f0 encoding value is 1: indicating that the AXI write address channel has data, and the first data packet (transfer0) carries the write address request information. The type_f1 encoding value is 1: indicating that the write data channel has data, and the second data packet (transfer1) carries the write data information. transfer2 is the AXI read address information: indicating that the AXI read address channel has data, and the third data packet (transfer2) carries the read address information.

[0141] In one embodiment, different priority orders may be preset in the first arbiter 250, and write address request information, write data information and read address request information may be transmitted according to different priorities by judging the three signals aw_avail, dw_avail and ar_avail.

[0142] See also Figure 5In one embodiment, the second arbitrator 540 in the second encapsulation module 500 can arbitrate according to the sending request status of the three FIFOs of write completion information and read data information. At this time, the sending request status of the three FIFOs of write completion information and read data information can be represented by the two signals wrsp_avail and dr_avail respectively. Among them, wrsp_avail = 0 means that the AXI write completion channel has no data to be sent to the UCIe link, and wrsp_avail = 1 means that the AXI write completion channel has data to be sent to the UCIe link. dr_avail = 0 means that the AXI read data channel has no data to be sent to the UCIe link, and dr_avail = 1 means that the AXI read data channel has data to be sent to the UCIe link.

[0143] In one embodiment, when wrsp_avail=0 and dr_avail=0, it indicates that no AXI information needs to be sent and no Flit is generated.

[0144] In one embodiment, when wrsp_avail=0 and dr_avail=1, it indicates that the AXI read data channel has data to be sent, but the AXI write completion channel has no data to be sent. In the frame header, the type_t encoding value is 1: indicating that the current Flit contains AXI bus data. The type_f0 encoding value is 0: indicating that the AXI write completion channel has no data, so the first data packet (transfer0) is an invalid payload (IDLE transfer), that is, it is in an idle state. The type_f1 encoding value is 1: indicating that the AXI read data channel has data, so the second data packet (transfer1) will carry AXI read data.

[0145] In one embodiment, when wrsp_avail=1 and dr_avail=0, it indicates that the AXI write completion channel has data to be sent, while the AXI read data channel has no data to be sent. In the frame header, the type_t encoding value is 1: indicating that the current Flit contains AXI bus data. The type_f0 encoding value is 1: indicating that the AXI write completion channel has data, so the first data packet (transfer0) will carry the information of the AXI write completion channel. The type_f1 encoding value is 0: indicating that the AXI read data channel has no data, so the second data packet (transfer1) is in an idle state (IDLE transfer).

[0146] In one embodiment, when wrsp_avail=1 and dr_avail=1, it indicates that both the AXI write completion channel and the AXI read data channel have data to be sent. In the frame header, the type_t encoding value is 1: indicating that the current Flit contains AXI bus data. The type_f0 encoding value is 1: indicating that the AXI write completion channel has data, so the first data packet (transfer0) will carry the information of the AXI write completion channel. The type_f1 encoding value is 1: indicating that the AXI read data channel has data, so the second data packet (transfer1) will carry the AXI read data.

[0147] In one embodiment, different priority orders may be preset in the second arbiter 540 , and the write completion information and the read data information may be transmitted according to different priorities by judging the two signals wrsp_avail and dr_avail.

[0148] It can be seen that in the above scheme, the AXI bus protocol and the UCIe high-speed interconnection transmission protocol are compatible. This compatibility enables the scheme to be applied to the interconnection between core particles in complex SoC packages and between chips on boards in the field of high-performance computing and data centers, greatly improving the flexibility and adaptability of the system. By encapsulating the AXI bus message into a data frame in Flit format and designing a corresponding Flit transmission processing mechanism, the UCIe bus can be better connected for interconnection between core particles and chips. The data frame in Flit format is more suitable for efficient transmission in a high-performance computing environment and can support high-bandwidth and low-latency communication requirements. By designing a multi-channel multiplexing mechanism, the bandwidth and efficiency of data transmission are further improved, while ensuring low latency and high reliability. This is very important for systems that require fast and large-scale data exchange, and can meet the needs of modern data centers and high-performance computing for efficient data processing. By optimizing the data encapsulation and transmission mechanism, while achieving high-performance transmission, the power consumption of the system can be significantly reduced. This is an important advantage for large-scale data processing and continuously running high-performance computing systems, which can reduce energy consumption and heat generation and extend system life. The above scheme is simple and efficient in design, so that the data of AXI bus protocol can be transmitted through the high-speed interface of UCIe link. Compared with the traditional scheme, the implementation of this conversion scheme is more direct, reducing the complex design workload while maintaining high-performance transmission effect.

[0149] The present invention also discloses a communication method of a core particle, which can be applied to the core particles mentioned above. The core particles are divided into local core particles and remote core particles. The local core particles include a first encapsulation module, a second encapsulation module, a first decapsulation module, and a second decapsulation module. The communication method includes:

[0150] The first encapsulation module receives the local write address request information, local write data information, and local read address request information of the core particle body through the AXI bus, and encapsulates and processes them to send them to the remote core particle through the UCIe link;

[0151] The first decapsulation module receives remote write completion information fed back by the remote chip according to the local write address request information and the local write data information through the UCIe link;

[0152] The first decapsulation module receives remote read data information fed back by the remote chip according to the local read address request information through the UCIe link;

[0153] The first decapsulation module decapsulates the remote write completion information and the remote read data information to send them to the core particle body through the AXI bus;

[0154] The second decapsulation module receives remote write address request information, remote write data information, and remote read address request information from the remote chiplet through the UCIe link, and performs decapsulation processing to send the information to the chiplet body through the AXI bus;

[0155] The second encapsulation module receives local write completion information fed back by the core particle body according to the remote write address request information and the remote write data information through the AXI bus;

[0156] The second encapsulation module receives the local end read data information fed back by the core particle body according to the remote end read address request information through the AXI bus;

[0157] The second encapsulation module encapsulates the local write completion information and the local read data information to send them to the remote chip through the UCIe link.

[0158] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An interconnect high-speed interface, characterized in that: include: A first encapsulation module is used to receive local write address request information, local write data information, and local read address request information of the core particle body through the AXI bus, and encapsulate and process them to send them to the remote core particle through the UCIe link; A first decapsulation module is used to receive, through the UCIe link, remote write completion information fed back by the remote core particle according to the local write address request information and the local write data information, and is also used to receive, through the UCIe link, remote read data information fed back by the remote core particle according to the local read address request information, and decapsulate the remote write completion information and the remote read data information to send them to the core particle body through the AXI bus; A second decapsulation module is used to receive remote write address request information, remote write data information, and remote read address request information from the remote core particle through the UCIe link, and perform decapsulation processing to send them to the core particle body through the AXI bus; as well as The second encapsulation module is used to receive the local write completion information fed back by the core particle body according to the remote write address request information and the remote write data information through the AXI bus, and is also used to receive the local read data information fed back by the core particle body according to the remote read address request information through the AXI bus, and encapsulate the local write completion information and the local read data information to send them to the remote core particle through the UCIe link.

2. The interconnect high-speed interface according to claim 1, characterized in that: The first packaging module comprises: A first write address cache unit, used for caching the local end write address request information; A first write data cache unit, used for caching the local end write data information; A first read address cache unit, used for caching the local end read address request information; A first arbitrator, configured to send the local-end write address request information, the local-end write data information, and the local-end read address request information in sequence according to a priority order; a first encapsulation unit, configured to encapsulate the local-end write address request information, the local-end write data information, and the local-end read address request information to generate a data frame; and The first sending unit is configured to send the data frame to the remote core.

3. The interconnect high-speed interface according to claim 1, characterized in that: The first decapsulation module comprises: A first receiving unit, configured to receive a data frame sent by the remote chiplet; A first decapsulation unit, configured to decapsulate the data frame to generate the remote write completion information and the remote read data information; A second write completion cache unit, used for caching the remote write completion information; A second read data cache unit, configured to cache the remote read data information; and The first interface unit is used to send the remote write completion information and the remote read data information to the core body.

4. The interconnect high-speed interface according to claim 1, characterized in that: The second decapsulation module comprises: A second receiving unit, configured to receive a data frame sent by the remote core; A second decapsulation unit, configured to decapsulate the data frame to generate the remote write address request information, the remote write data information, and the remote read address request information; A second write address cache unit, used for caching the remote write address request information; A second write data cache unit, used for caching the remote write data information; A second read address cache unit, configured to cache the remote read address request information; and The second interface unit is used to send the remote write address request information, the remote write data information, and the remote read address request information to the core body.

5. The interconnect high-speed interface according to claim 1, characterized in that: The second packaging module comprises: A first write completion cache unit, used for caching the local end write completion information; A first read data cache unit, used for caching the local end read data information; A second arbitrator is used to send the local end write completion information and the local end read data information in sequence according to the priority order; A second encapsulation unit is used to encapsulate the local end write completion information and the local end read data information to generate a data frame; and The second sending unit is used to send the data frame to the remote core particle.

6. The interconnect high-speed interface according to claim 2, characterized in that: The first encapsulation module further includes a first processing unit, which is used to divide the local write address request information, the local write data information and the local read address request information in the AXI format into data packets of a fixed size, so as to cache different data packets in corresponding cache units; The first encapsulation unit is used to obtain at least one data packet and write the data packet into a payload area of ​​a data frame in a UCIe format to generate a corresponding data frame.

7. The interconnect high-speed interface according to claim 5, characterized in that: The second encapsulation module further includes a second processing unit, which is used to divide the local write completion information and the local read data information in the AXI format into data packets of fixed size, so as to cache different data packets in corresponding cache units; The second encapsulation unit is used to obtain at least one data packet and write the data packet into a payload area of ​​a data frame in a UCIe format to generate a corresponding data frame.

8. The interconnect high-speed interface according to claim 6 or 7, characterized in that: The data frame is 64 bytes of data, the frame header includes 2 bytes of data, the frame tail includes 2 bytes of data, the transmission block includes 60 bytes of data, and the data frame includes: Frame header, used to store identifier; a payload area, used to write at least one of the data packets, the data packets being used to store one of the local-end write address request information, the local-end write data information, the local-end read address request information, the local-end write completion information, and the local-end read data information; and Frame tail, used to store the checksum.

9. The interconnect high-speed interface according to claim 8, characterized in that: When writing the data packet into the payload area, the data of the data packet is aligned with the byte boundary of the data frame, and when there is a non-aligned part in the data packet, invalid data is filled into the non-aligned part.

10. A core particle, characterized in that: The core particle comprises the interconnect high-speed interface as claimed in any one of claims 1 to 9.

11. A chiplet communication method, characterized in that: Applied to a core particle, the core particle is the core particle described in claim 10, the core particle is divided into a local core particle and a remote core particle, the interconnection high-speed interface of the local core particle includes a first encapsulation module, a second encapsulation module, a first decapsulation module, and a second decapsulation module, and the communication method includes: The first encapsulation module receives local write address request information, local write data information, and local read address request information of the core particle body through the AXI bus, and encapsulates and processes them to send them to the remote core particle through the UCIe link; The first decapsulation module receives, through the UCIe link, remote write completion information fed back by the remote chip according to the local write address request information and the local write data information; The first decapsulation module receives, through the UCIe link, remote read data information fed back by the remote chip according to the local read address request information; The first decapsulation module decapsulates the remote write completion information and the remote read data information to send them to the core particle body through the AXI bus; The second decapsulation module receives remote write address request information, remote write data information, and remote read address request information from the remote core particle through the UCIe link, and performs decapsulation processing to send the information to the core particle body through the AXI bus; The second encapsulation module receives, through the AXI bus, local write completion information fed back by the core particle body according to the remote write address request information and the remote write data information; The second encapsulation module receives the local end read data information fed back by the core particle body according to the remote end read address request information through the AXI bus; The second encapsulation module encapsulates the local write completion information and the local read data information to send them to the remote chip through the UCIe link.

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