DRAM (Dynamic Random Access Memory) data security policy management method and device

Abstract

The invention provides a DRAM (Dynamic Random Access Memory) data security policy management method and device. The method comprises the following steps: acquiring the maximum refresh cycle of a target DRAM and the hardware power-on reset time of a processor; determining a refreshing mode and read-write task time of the target DRAM according to the received task requirement; determining self-refreshing time according to the refreshing mode and task requirements; and according to the maximum refresh cycle, the self-refresh time, the hardware power-on reset time and the read-write task time, determining the latest self-refresh completion time when the processor is reset. According to the scheme, the reliable self-refreshing method of the DRAM is provided, self-refreshing of the DRAM can still be completed when hardware reset occurs, and data safety is guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular to a DRAM data security policy management method and device. Background Art

[0002] Static random access memory (SRAM) has the advantages of high performance, fast speed, and non-volatility of data during power failure. Therefore, onboard computers in traditional high-reliability application scenarios usually use SRAM as the processor's running cache.

[0003] With the development of spacecraft, the computing tasks undertaken by onboard computers have the characteristics of high integration, high computing power and high bandwidth. The program and temporary data storage requirements of onboard computer processors have increased from the original MB level to the GB level. Therefore, the SRAM in traditional onboard computers can no longer meet the application requirements of high data volume due to problems such as low integration and high cost, and GB-level dynamic random access memory (DRAM) has been widely used as program cache.

[0004] Although DRAM has the advantage of large capacity, it needs to be refreshed regularly to save data, otherwise the stored data will be lost. Therefore, once a hardware reset failure occurs before the DRAM data refresh is completed, the stored data will be lost, making DRAM unable to be reliably used in onboard computers. Summary of the invention

[0005] The present invention provides a DRAM data security policy management method and device, which can still complete DRAM self-refresh when hardware reset occurs, thereby ensuring data security.

[0006] In a first aspect, the present invention provides a DRAM data security policy management method, comprising:

[0007] Get the maximum refresh cycle of the target DRAM and the hardware power-on reset time of the processor;

[0008] Determine the refresh mode and read / write task time of the target DRAM according to the received task requirements;

[0009] Determining the time taken for self-refresh according to the refresh mode and the task requirements;

[0010] The latest completion time of the self-refresh when the processor is reset is determined according to the maximum refresh cycle, the time used for the self-refresh, the hardware power-on reset time and the read-write task time.

[0011] Optionally, determining a refresh mode of the target DRAM according to the received task requirement includes:

[0012] According to the task requirements and the hardware resources of the processor, a refresh mode matching the target DRAM is determined; wherein the refresh mode includes centralized refresh, distributed refresh and asynchronous refresh.

[0013] Optionally, determining the time taken for self-refresh according to the refresh mode and the task requirement includes:

[0014] According to the task requirement, determining the memory space to be refreshed included in the target DRAM;

[0015] The maximum refresh cycle is used as a task cycle, and the time used for the self-refresh is determined within the task cycle according to the refresh mode and the memory space to be refreshed.

[0016] Optionally, determining the latest completion time of the self-refresh when the processor is reset according to the maximum refresh cycle, the time taken for the self-refresh, the hardware power-on reset time, and the read / write task time includes:

[0017] The time taken for the self-refresh, the hardware power-on reset time and the read-write task time are summed to obtain the latest completion time of the first self-refresh;

[0018] The latest completion time of the second self-refresh is obtained by summing the time taken for the self-refresh and the hardware power-on reset time;

[0019] A time interval consisting of the first self-refresh latest completion time and the second self-refresh latest completion time is determined as the self-refresh latest completion time; wherein the self-refresh latest completion time is less than 1 / 2 of the maximum refresh cycle.

[0020] Optionally, it also includes:

[0021] According to the task requirement, determining the memory space to be refreshed included in the target DRAM;

[0022] The stored data in the memory space to be refreshed is divided into different levels according to a preset level order to obtain storage data sets corresponding to different priorities;

[0023] A read-back check is performed on the stored data set corresponding to a priority level higher than a preset priority threshold, and an error correction time is determined.

[0024] Optionally, determining the latest completion time of the self-refresh when the processor is reset includes:

[0025] The time taken for the self-refresh, the hardware power-on reset time, the read-write task time, and the error correction time are summed to obtain the latest completion time of the third self-refresh;

[0026] The latest completion time of the second self-refresh is obtained by summing the time taken for the self-refresh and the hardware power-on reset time;

[0027] The time interval formed by the third self-refresh latest completion time and the second self-refresh latest completion time is determined as the self-refresh latest completion time; wherein the self-refresh latest completion time is less than 1 / 2 of the maximum refresh cycle.

[0028] In a second aspect, the present invention provides a DRAM data security policy management device, comprising:

[0029] An acquisition module is used to acquire the maximum refresh cycle of the target DRAM and the hardware power-on reset time of the processor;

[0030] A task time determination module, used to determine the refresh mode and read / write task time of the target DRAM according to the received task requirements; and determine the time used for self-refresh according to the refresh mode and the task requirements;

[0031] The policy management module is used to determine the latest completion time of the self-refresh when the processor is reset according to the maximum refresh cycle, the time used for the self-refresh, the hardware power-on reset time and the read-write task time.

[0032] Optionally, the policy management module is further configured to perform the following operations:

[0033] The time taken for the self-refresh, the hardware power-on reset time and the read-write task time are summed to obtain the latest completion time of the first self-refresh;

[0034] The latest completion time of the second self-refresh is obtained by summing the time taken for the self-refresh and the hardware power-on reset time;

[0035] A time interval consisting of the first self-refresh latest completion time and the second self-refresh latest completion time is determined as the self-refresh latest completion time; wherein the self-refresh latest completion time is less than 1 / 2 of the maximum refresh cycle.

[0036] Optionally, the task time determination module is further configured to perform the following operations:

[0037] According to the task requirement, determining the memory space to be refreshed included in the target DRAM;

[0038] The stored data in the memory space to be refreshed is divided into different levels according to a preset level order to obtain storage data sets corresponding to different priorities;

[0039] A read-back check is performed on the stored data set corresponding to a priority level higher than a preset priority threshold, and an error correction time is determined.

[0040] In a third aspect, an embodiment of the present invention further provides a computing device, comprising a memory and a target processor, wherein the memory stores a computer program, and when the target processor executes the computer program, the method described in any first aspect of this specification is implemented.

[0041] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, enables the computer to execute the method described in any first aspect of this specification.

[0042] The present invention provides a DRAM data security policy management method and device. The method obtains the latest self-refresh completion time of the self-refresh process within a refresh cycle according to the maximum refresh cycle allowed by the target DRAM, the hardware power-on reset time, the self-refresh time of the target DRAM, and the read-write task time, thereby ensuring that even if a hardware reset occurs during the operation of the target DRAM, the data can still complete the self-refresh retention, ensuring that the data will not be lost, and ensuring data security. At the same time, the data security policy management provided by the present invention can occupy the refresh cycle as little as possible, ensuring that there is enough time for the processor to read and write, and at the same time can reduce the coupling with the hardware, and has higher versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 is a flow chart of a DRAM data security policy management method provided by one embodiment of the present invention;

[0045] Figure 2 is a hardware architecture diagram of a computing device provided by an embodiment of the present invention;

[0046] Figure 3 It is a structural diagram of a DRAM data security policy management device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0048] like Figure 1 As shown, an embodiment of the present invention provides a DRAM data security policy management method, the method comprising:

[0049] Step 100, obtaining the maximum refresh cycle of the target DRAM and the hardware power-on reset time of the processor;

[0050] Step 102, determining the refresh mode and read / write task time of the target DRAM according to the received task requirements;

[0051] Step 104, determining the time used for self-refresh according to the refresh mode and task requirements;

[0052] Step 106, determining the latest completion time of the self-refresh when the processor is reset according to the maximum refresh cycle, the time used for self-refresh, the hardware power-on reset time and the read-write task time.

[0053] In the present invention, when a processor is reset, the hardware power-on reset time of the processor is obtained, and the latest self-refresh completion time of the self-refresh process within a refresh cycle is obtained according to the maximum refresh cycle allowed by the target DRAM, the hardware power-on reset time, the self-refresh time of the target DRAM, and the read-write task time, so as to ensure that even if a hardware reset occurs during the operation of the target DRAM, the data can still complete the self-refresh retention, ensure that the data will not be lost, and ensure data security. At the same time, the data security policy management provided by the present invention can occupy the refresh cycle as little as possible, ensure that there is enough time for the processor to read and write, and reduce the coupling with the hardware, and has higher versatility.

[0054] It should be noted that the latest self-refresh completion time specifically refers to the latest self-refresh completion time that can tolerate a processor reset. Once it is later than this time, the data cannot reliably complete self-refresh after the processor is reset.

[0055] For step 100, the maximum refresh cycle of the target DRAM is the task cycle. By dividing the task cycle into time slices, different strategies can be implemented in different time slices. Specifically, the strategies include refresh, task execution, hardware power-on reset, read and write tasks, checksum error correction, etc. The hardware power-on reset time of the processor can be obtained from the hardware design of the processor. The hardware power-on reset time is a time collection of a series of operations including hardware error detection, hardware reset, hardware power-on, software initialization, etc.

[0056] In step 102, according to the received task requirements, a refresh mode of the target DRAM is determined, including:

[0057] According to the task requirements and the hardware resources of the processor, a refresh mode matching the target DRAM is determined; wherein the refresh modes include centralized refresh, decentralized refresh and asynchronous refresh.

[0058] It should be noted that the task requirements are the task requirements required by users in specific application scenarios and are flexibly determined by users.

[0059] In the present invention, according to the application scenario of the target DRAM, the different tasks included in the task requirements and the hardware resources of the current processor, the refresh method that is more suitable for the target DRAM can be further determined, and centralized refresh, distributed refresh and asynchronous refresh methods can be flexibly adopted.

[0060] With respect to step 104, the time taken for self-refresh is determined according to the refresh mode and task requirements, including:

[0061] According to the task requirements, determine the memory space to be refreshed included in the target DRAM;

[0062] The maximum refresh cycle is used as the task cycle, and the time used for self-refresh is determined according to the refresh mode and the memory space to be refreshed within the task cycle.

[0063] Specifically, concentrated refresh refers to refreshing all storage cells row by row for a period of time within a specified refresh cycle. Distributed refresh refers to refreshing each row of storage cells in each access cycle. Asynchronous refresh refers to not specifying a fixed refresh cycle, and each row is divided into two groups, and it only needs to be refreshed once within 2ms. Different refresh methods have different corresponding refresh times.

[0064] In the present invention, the target DRAM includes multiple memory spaces, and the user's task requirements include refreshing all or part of the memory space. In order to improve the refresh efficiency, it is necessary to first determine the memory space to be refreshed corresponding to the task requirement, and then calculate the time to refresh all the memory spaces to be refreshed according to the refresh method within the task cycle to obtain the time used for self-refresh.

[0065] For step 106, determining the latest completion time of self-refresh when the processor is reset according to the maximum refresh cycle, the time used for self-refresh, the hardware power-on reset time, and the read-write task time includes:

[0066] The time used for self-refresh, the hardware power-on reset time and the read-write task time are summed to obtain the latest completion time of the first self-refresh;

[0067] The latest completion time of the second self-refresh is obtained by summing the time used for self-refresh and the hardware power-on reset time;

[0068] The time interval composed of the first self-refresh latest completion time and the second self-refresh latest completion time is determined as the self-refresh latest completion time; wherein the self-refresh latest completion time is less than 1 / 2 of the maximum refresh cycle.

[0069] Specifically, the latest completion time of the first self-refresh is determined by the following formula:

[0070] t1=t a +t b +t c

[0071]

[0072] The latest completion time of the second self-refresh is determined by the following formula:

[0073] t2=t a +t b

[0074]

[0075] Among them, t a The time taken for self-refresh; t b is the hardware power-on reset time; t c is the reading and writing task time; t T is the maximum refresh cycle; t1 is the latest completion time of the first self-refresh; t2 is the latest completion time of the second self-refresh; the latest completion time of the self-refresh is [t1, t2] or [t2, t1].

[0076] In the present invention, the first self-refresh latest completion time satisfies: the sum of the time used for self-refresh, the hardware power-on reset time, and the read-write task time is less than half of the maximum refresh cycle. Since a certain normal read-write task time is sacrificed, data security can be guaranteed to the maximum extent, which belongs to a reliable priority strategy. The second self-refresh latest completion time satisfies: the sum of the time used for self-refresh and the hardware power-on reset time is less than half of the maximum refresh cycle, and the remaining time can be used for the execution of tasks including read-write tasks and software verification and error correction, which belongs to the maximum task time strategy. In this way, the first self-refresh latest completion time and the second self-refresh latest completion time are respectively used as the upper and lower limits of the self-refresh latest completion time, and self-refresh is completed within this range, thereby ensuring that even if a hardware reset occurs during the operation of the DRAM, the data can still complete self-refresh retention.

[0077] In a preferred embodiment, the method further comprises:

[0078] According to the task requirements, determine the memory space to be refreshed included in the target DRAM;

[0079] The storage data in the memory space to be refreshed is divided into different levels according to a preset level order to obtain storage data sets corresponding to different priorities;

[0080] A read-back check is performed on the stored data set corresponding to the priority level higher than the preset priority threshold, and an error correction time is determined.

[0081] In the present invention, after determining the memory space to be refreshed in the target DRAM according to the task requirements, it also includes hierarchical division of the memory space to be refreshed according to the user's preset hierarchical order when the task cycle time is sufficient, that is, in the idle time outside the read-write task or refresh, so as to perform a read-back check on the stored data in the memory space to be refreshed with a higher priority, so as to rewrite the erroneous data in the DRAM after a single-bit error is found, so as to prevent the spread of erroneous data under abnormal circumstances. This process is software verification and error correction, and the process time is recorded as the error correction time.

[0082] In the present invention, in order to further improve data security, a software error checking and correction security strategy is added to supplement the hardware security strategy. When used, the DRAM storage area is graded according to the data criticality to give priority to ensuring the security of high-priority data.

[0083] In a preferred embodiment, for step 106, after obtaining the error correction time, determining the latest completion time of the self-refresh when the processor is reset includes:

[0084] The time used for self-refresh, the hardware power-on reset time, the read-write task time and the error correction time are summed to obtain the latest completion time of the third self-refresh;

[0085] The latest completion time of the second self-refresh is obtained by summing the time used for self-refresh and the hardware power-on reset time;

[0086] The time interval formed by the third self-refresh latest completion time and the second self-refresh latest completion time is determined as the self-refresh latest completion time; wherein the self-refresh latest completion time is less than 1 / 2 of the maximum refresh cycle.

[0087] Specifically, the latest completion time of the third self-refresh is determined by the following formula:

[0088] t1=t a +t b +t c +t d

[0089]

[0090] The latest completion time of the second self-refresh is determined by the following formula:

[0091] t2=t a +t b

[0092]

[0093] Among them, t a The time taken for self-refresh; t b is the hardware power-on reset time; t c is the reading and writing task time; t d is the error correction time; t T is the maximum refresh cycle; t3 is the latest completion time of the third self-refresh; t2 is the latest completion time of the second self-refresh; the latest completion time of self-refresh is [t3, t2] or [t2, t3].

[0094] In the present invention, in order to further improve data security, a software error checking and correction security strategy is added to supplement the hardware security strategy. At the same time, the reliability priority strategy is adjusted based on the error correction time, so that the latest completion time of the third self-refresh satisfies: the sum of the time used for self-refresh, hardware power-on reset time, read and write task time, and error correction time is less than half of the maximum refresh cycle, further improving data security.

[0095] The DRAM data security policy management method provided by the present invention can not only ensure that data is not lost when a hardware reset occurs when DRAM data refresh is not completed, but also occupy as few refresh cycles as possible to ensure that there is enough time for processor reading and writing; at the same time, it can also reduce resource overhead such as hardware and software, reduce hardware coupling, and has higher versatility, and is suitable for various software and hardware environments of DRAM applications.

[0096] The DRAM data security policy management method provided by the present invention is adapted to the self-refresh mode of most existing DRAMs. It can flexibly adopt centralized refresh, distributed refresh and asynchronous refresh modes according to different tasks, and has good compatibility. The present invention provides a data protection strategy that combines software refresh and hardware refresh. Under the premise of maintaining hardware refresh, data is read back and verified during idle time to prevent the spread of erroneous data under abnormal circumstances; the hardware self-refresh strategy and software verification and error correction protection strategy provided by the present invention can be flexibly selected according to the requirements for reliability and performance, providing a strong guarantee for the promotion and application of DRAM in onboard computers, and can be extended to related application scenarios.

[0097] like Figure 2 , Figure 3 As shown, an embodiment of the present invention provides a DRAM data security policy management device. The device embodiment can be implemented by software, or by hardware or a combination of software and hardware. From the hardware level, Figure 2 As shown in FIG. 1 , a hardware architecture diagram of a computing device where a DRAM data security policy management device provided by an embodiment of the present invention is located is shown in FIG. Figure 2 In addition to the processor, memory, network interface, and non-volatile memory shown in the figure, the computing device in which the device is located in the embodiment may also generally include other hardware, such as a forwarding chip responsible for processing messages, etc. Taking software implementation as an example, Figure 3 As shown, as a device in a logical sense, the CPU of the computing device in which it is located reads the corresponding computer program in the non-volatile memory into the memory for execution. This embodiment provides a DRAM data security policy management device, which includes:

[0098] An acquisition module 300 is used to acquire a maximum refresh cycle of a target DRAM and a hardware power-on reset time of a processor;

[0099] The task time determination module 302 is used to determine the refresh mode and read / write task time of the target DRAM according to the received task requirements; and determine the time used for self-refresh according to the refresh mode and task requirements;

[0100] The policy management module 304 is used to determine the latest completion time of the self-refresh when the processor is reset according to the maximum refresh cycle, the time used for self-refresh, the hardware power-on reset time and the read-write task time.

[0101] In some specific implementations, the acquisition module 300 may be used to execute the above step 100 , the task time determination module 302 may be used to execute the above steps 102 and 104 , and the policy management module 304 may be used to execute the above step 106 .

[0102] In one embodiment of the present invention, the task time determination module 302 is further configured to perform the following operations:

[0103] Determine a refresh mode that matches the target DRAM according to task requirements and processor hardware resources; wherein the refresh modes include centralized refresh, decentralized refresh, and asynchronous refresh;

[0104] According to the task requirements, determine the memory space to be refreshed included in the target DRAM;

[0105] The maximum refresh cycle is used as the task cycle, and the time used for self-refresh is determined according to the refresh mode and the memory space to be refreshed within the task cycle.

[0106] In one embodiment of the present invention, the task time determination module 302 is further configured to perform the following operations:

[0107] According to the task requirements, determine the memory space to be refreshed included in the target DRAM;

[0108] The storage data in the memory space to be refreshed is divided into different levels according to a preset level order to obtain storage data sets corresponding to different priorities;

[0109] A read-back check is performed on the stored data set corresponding to the priority level higher than the preset priority threshold, and an error correction time is determined.

[0110] In one embodiment of the present invention, the policy management module 304 is further configured to perform the following operations:

[0111] The time used for self-refresh, the hardware power-on reset time and the read-write task time are summed to obtain the latest completion time of the first self-refresh;

[0112] The latest completion time of the second self-refresh is obtained by summing the time used for self-refresh and the hardware power-on reset time;

[0113] The time interval composed of the first self-refresh latest completion time and the second self-refresh latest completion time is determined as the self-refresh latest completion time; wherein the self-refresh latest completion time is less than 1 / 2 of the maximum refresh cycle.

[0114] In one embodiment of the present invention, the policy management module 304 is further configured to perform the following operations:

[0115] The time used for self-refresh, the hardware power-on reset time, the read-write task time and the error correction time are summed to obtain the latest completion time of the third self-refresh;

[0116] The latest completion time of the second self-refresh is obtained by summing the time used for self-refresh and the hardware power-on reset time;

[0117] The time interval formed by the third self-refresh latest completion time and the second self-refresh latest completion time is determined as the self-refresh latest completion time; wherein the self-refresh latest completion time is less than 1 / 2 of the maximum refresh cycle.

[0118] It is to be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on a DRAM data security policy management device. In other embodiments of the present invention, a DRAM data security policy management device may include more or fewer components than those illustrated, or combine certain components, or split certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0119] The information interaction, execution process and other contents between the modules in the above-mentioned device are based on the same concept as the embodiment of the method of the present invention. For the specific contents, please refer to the description in the embodiment of the method of the present invention, and no further description is given here.

[0120] An embodiment of the present invention further provides a computing device, including a memory and a target processor, wherein a computer program is stored in the memory, and when the target processor executes the computer program, a DRAM data security policy management method in any embodiment of the present invention is implemented.

[0121] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the processor executes a DRAM data security policy management method in any embodiment of the present invention.

[0122] Specifically, a system or device equipped with a storage medium can be provided, on which software program code that implements the functions of any of the above-mentioned embodiments is stored, and a computer (or CPU or MPU) of the system or device can be enabled to read and execute the program code stored in the storage medium.

[0123] In this case, the program code itself read from the storage medium can realize the function of any one of the above-mentioned embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present invention.

[0124] The storage medium embodiments for providing the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), a magnetic tape, a non-volatile memory card, and a ROM. Alternatively, the program code can be downloaded from a server computer by a communication network.

[0125] In addition, it should be clear that the functions of any of the above embodiments can be implemented not only by executing the program code read by the computer, but also by enabling the operating system on the computer to complete part or all of the actual operations based on the instructions of the program code.

[0126] In addition, it can be understood that the program code read from the storage medium is written to a memory provided in an expansion board inserted into the computer or to a memory provided in an expansion module connected to the computer, and then based on the instructions of the program code, a CPU installed on the expansion board or expansion module is enabled to perform part or all of the actual operations, thereby realizing the functions of any of the above-mentioned embodiments.

[0127] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical factors in the process, method, article or device including the elements.

[0128] A person of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, etc., various media that can store program codes.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A DRAM data security policy management method, characterized in that: include: Get the maximum refresh cycle of the target DRAM and the hardware power-on reset time of the processor; Determine the refresh mode and read / write task time of the target DRAM according to the received task requirements; Determining the time taken for self-refresh according to the refresh mode and the task requirements; The latest completion time of the self-refresh when the processor is reset is determined according to the maximum refresh cycle, the time used for the self-refresh, the hardware power-on reset time and the read-write task time.

2. The method according to claim 1, characterized in that Determining the refresh mode of the target DRAM according to the received task requirement includes: According to the task requirements and the hardware resources of the processor, a refresh mode matching the target DRAM is determined; wherein the refresh mode includes centralized refresh, distributed refresh and asynchronous refresh.

3. The method according to claim 1, characterized in that The step of determining the time taken for self-refresh according to the refresh mode and the task requirement includes: According to the task requirement, determining the memory space to be refreshed included in the target DRAM; The maximum refresh cycle is used as a task cycle, and the time used for the self-refresh is determined within the task cycle according to the refresh mode and the memory space to be refreshed.

4. The method according to claim 1, characterized in that Determining the latest completion time of the self-refresh when the processor is reset according to the maximum refresh cycle, the time used for the self-refresh, the hardware power-on reset time, and the read-write task time includes: The time taken for the self-refresh, the hardware power-on reset time and the read-write task time are summed to obtain the latest completion time of the first self-refresh; The second self-refresh latest completion time is obtained by summing the self-refresh time and the hardware power-on reset time; A time interval consisting of the first self-refresh latest completion time and the second self-refresh latest completion time is determined as the self-refresh latest completion time; wherein the self-refresh latest completion time is less than 1 / 2 of the maximum refresh cycle.

5. The method according to any one of claims 1 to 4, characterized in that: Also includes: According to the task requirement, determining the memory space to be refreshed included in the target DRAM; The stored data in the memory space to be refreshed is divided into different levels according to a preset level order to obtain storage data sets corresponding to different priorities; A read-back check is performed on the stored data set corresponding to a priority level higher than a preset priority threshold, and an error correction time is determined.

6. The method according to claim 5, characterized in that The determining the latest completion time of the self-refresh when the processor is reset includes: The time taken for the self-refresh, the hardware power-on reset time, the read-write task time, and the error correction time are summed to obtain the latest completion time of the third self-refresh; The latest completion time of the second self-refresh is obtained by summing the time taken for the self-refresh and the hardware power-on reset time; The time interval formed by the third self-refresh latest completion time and the second self-refresh latest completion time is determined as the self-refresh latest completion time; wherein the self-refresh latest completion time is less than 1 / 2 of the maximum refresh cycle.

7. A DRAM data security policy management device, characterized in that: include: An acquisition module is used to acquire the maximum refresh cycle of the target DRAM and the hardware power-on reset time of the processor; A task time determination module, used to determine the refresh mode and read / write task time of the target DRAM according to the received task requirements; and determine the time used for self-refresh according to the refresh mode and the task requirements; The policy management module is used to determine the latest completion time of the self-refresh when the processor is reset according to the maximum refresh cycle, the time used for the self-refresh, the hardware power-on reset time and the read-write task time.

8. The device according to claim 7, characterized in that The policy management module is also used to perform the following operations: The time taken for the self-refresh, the hardware power-on reset time and the read-write task time are summed to obtain the latest completion time of the first self-refresh; The latest completion time of the second self-refresh is obtained by summing the time taken for the self-refresh and the hardware power-on reset time; A time interval consisting of the first self-refresh latest completion time and the second self-refresh latest completion time is determined as the self-refresh latest completion time; wherein the self-refresh latest completion time is less than 1 / 2 of the maximum refresh cycle.

9. The device according to claim 7 or 8, characterized in that The task time determination module is also used to perform the following operations: According to the task requirement, determining the memory space to be refreshed included in the target DRAM; The stored data in the memory space to be refreshed is divided into different levels according to a preset level order to obtain storage data sets corresponding to different priorities; A read-back check is performed on the stored data set corresponding to a priority level higher than a preset priority threshold, and an error correction time is determined.

10. A computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to execute the method according to any one of claims 1 to 6.

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