Three-dimensional integrated circuit stack structure manufacturing method and wafer reconstruction method

Abstract

The embodiment of the invention discloses a three-dimensional integrated circuit stack structure manufacturing method and a wafer reconstruction method, and relates to the technical field of semiconductor chips. The manufacturing method of the three-dimensional integrated circuit stack structure comprises the following steps: fixing at least two first chips at preset positions of a first carrier to form a reconstructed first carrier; the first chip is a chip meeting the specification; correspondingly bonding the at least two first chips on the reconstructed first bearing body with the at least two second chips on the second bearing body to form a stacked structure body; the second chip is a chip meeting the specification; cutting the stacked structure body to form a single three-dimensional integrated circuit stacked structure; wherein each single three-dimensional integrated circuit stack structure comprises a first chip and a second chip which are bonded together. The embodiment of the invention can be used for manufacturing the three-dimensional integrated circuit stack structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chips, and in particular to a method for manufacturing a three-dimensional integrated circuit stacking structure and a wafer reconstruction method. Background Art

[0002] With the development of science and technology, the three-dimensional development of chip structure is sweeping the entire semiconductor industry to further meet the needs of high integration, small size and excellent performance. At present, there are many ways to stack three-dimensional integrated circuits, mainly including: wafer-to-wafer stacking (W2W), chip-to-chip stacking (D2D) and chip-to-wafer stacking (D2W). Wafer-to-wafer stacking has the advantage of fast stacking speed. However, since there is a certain proportion of defective chips on the wafer, it is inevitable that defective chips will be bonded with good chips, thereby reducing the yield of the three-dimensional integrated circuit stacking structure. Summary of the invention

[0003] In view of this, the present invention provides a method for manufacturing a three-dimensional integrated circuit stacking structure and a wafer reconstruction method, so as to improve the yield of the three-dimensional integrated circuit stacking structure.

[0004] In a first aspect, an embodiment of the present invention provides a method for manufacturing a three-dimensional integrated circuit stacking structure, comprising: fixing at least two first chips at preset positions on a first carrier to form a reconstructed first carrier; the first chip is a chip that meets the specifications; at least two first chips on the reconstructed first carrier are correspondingly bonded to at least two second chips on a second carrier to form a stacking structure; the second chip is a chip that meets the specifications; the stacking structure is cut to form a monomer three-dimensional integrated circuit stacking structure; wherein each monomer three-dimensional integrated circuit stacking structure includes a first chip and a second chip bonded together.

[0005] In one embodiment, fixing at least two first chips at preset positions of the first carrier to form a reconstructed first carrier includes: providing a first carrier; forming at least two placement marks on the carrying surface of the first carrier; wherein each placement mark identifies a placement area; placing at least two first chips respectively in the placement areas identified by different placement marks; and filling positioning materials between adjacent first chips to form a reconstructed first carrier.

[0006] In one embodiment, at least two placement marks are formed on the carrying surface of the first carrier, including: based on the outer dimensions of the largest chip between the first chip and the second chip, at least two placement marks are formed on the carrying surface of the first carrier; wherein the outline dimensions of the placement areas marked by each placement mark are consistent, and the outline dimensions of the placement areas marked by each placement mark are equal to the outer dimensions of the largest chip between the first chip and the second chip or equal to the sum of the outer dimensions of the largest chip between the first chip and the second chip and a preset value.

[0007] In one embodiment, after at least two placement marks are formed on the carrying surface of the first carrier, the method further includes: etching a groove at a specified position in the placement area marked by each placement mark; the contour size of the groove matches the outer size of the first chip to be placed therein; wherein, placing the at least two first chips respectively in the placement areas marked by different placement marks includes: placing the at least two first chips respectively in the grooves in the placement areas marked by different placement marks.

[0008] In one embodiment, fixing at least two first chips at a preset position of the first carrier includes: fixing at least two first chips of the same performance type or the same quality grade at a preset position of the first carrier; or fixing at least two first chips of the first type or the first quality grade at a first preset position of the first carrier; fixing at least two first chips of the second type or the second quality grade at a second preset position of the first carrier.

[0009] In one embodiment, after fixing the at least two first chips at preset positions of the first carrier, the method further comprises: forming a bonding layer on surfaces of the at least two first chips facing away from the first carrier.

[0010] In one embodiment, an alignment mark is formed on the carrying surface of the first carrying body and / or in a placement area marked by at least one placement mark.

[0011] In one embodiment, bonding at least two first chips on the reconstructed first carrier to at least two second chips on the second carrier includes: bonding two first chips on the reconstructed first carrier to the same second chip on the second carrier.

[0012] In one embodiment, before bonding at least two first chips on the reconstructed first carrier to correspondingly bond at least two second chips on the second carrier, the method further includes: fixing at least two second chips at preset positions on the second carrier to form a second carrier having the second chips.

[0013] In one embodiment, fixing at least two second chips at preset positions of a second carrier to form a second carrier having the second chips includes: providing a second carrier; forming at least two placement marks on a carrying surface of the second carrier; wherein each placement mark identifies a placement area; placing at least two second chips respectively in placement areas identified by different placement marks; and filling positioning materials between adjacent second chips to form a reconstructed second carrier.

[0014] In one embodiment, at least two placement marks are formed on the carrying surface of the second carrier, including: based on the outer dimensions of the largest chip between the first chip and the second chip, at least two placement marks are formed on the carrying surface of the second carrier; wherein the outline dimensions of the placement areas marked by each placement mark are consistent, and the outline dimensions of the placement areas marked by each placement mark are equal to the outer dimensions of the largest chip between the first chip and the second chip or equal to the sum of the outer dimensions of the largest chip between the first chip and the second chip and a preset value.

[0015] In one embodiment, after at least two placement marks are formed on the carrying surface of the second carrier, the method further includes: etching at least one groove at a specified position in the placement area marked by each placement mark; the contour size of the groove matches the outer size of the second chip to be placed therein; wherein, placing the at least two second chips respectively in the placement areas marked by different placement marks includes: placing the at least two second chips respectively in the grooves in the placement areas marked by different placement marks.

[0016] In one embodiment, fixing at least two second chips at a preset position of the second carrier includes: fixing at least two second chips of the same performance type or the same quality grade at a preset position of the second carrier; or fixing at least two second chips of the first type or the first quality grade at a first preset position of the second carrier; fixing at least two second chips of the second type or the second quality grade at a second preset position of the second carrier.

[0017] In one embodiment, after fixing the at least two second chips at preset positions of the second carrier, the method further comprises: forming a bonding layer on surfaces of the at least two second chips facing away from the second carrier.

[0018] In one embodiment, an alignment mark is formed on the carrying surface of the second carrying body and / or in a placement area marked by at least one placement mark.

[0019] In a second aspect, an embodiment of the present invention further provides a wafer reconstruction method, comprising: obtaining at least two chips; the chips are chips that meet specifications; and fixing the at least two chips at preset positions of a carrier to form a reconstructed wafer.

[0020] In one embodiment, fixing the at least two chips at preset positions of a carrier to form a reconstructed wafer includes: providing a carrier; forming at least two placement marks on a carrying surface of the carrier; wherein each placement mark identifies a placement area; placing at least two chips respectively in placement areas identified by different placement marks; and filling positioning materials between adjacent chips to form a reconstructed carrier.

[0021] In one embodiment, at least two placement marks are formed on the carrying surface of the carrier, including: based on the outer dimensions of the chip, at least two placement marks are formed on the carrying surface of the carrier; wherein the outline dimensions of the placement areas marked by each placement mark are consistent, and the outline dimensions of the placement areas marked by each placement mark are equal to the outer dimensions of the largest chip among the chips or equal to the sum of the outer dimensions of the largest chip among the chips and a preset value.

[0022] In one embodiment, after at least two placement marks are formed on the carrying surface of the carrier, the method further includes: etching at least one groove at a specified position in the placement area marked by each placement mark; the contour size of the groove matches the outer size of the chip to be placed therein; wherein, placing at least two chips respectively in the placement areas marked by different placement marks includes: placing at least two chips respectively in the grooves in the placement areas marked by different placement marks.

[0023] In one embodiment, fixing at least two chips at preset positions of a carrier includes: fixing at least two chips of the same performance type or the same quality grade at preset positions of the carrier; or fixing at least two chips of a first type or a first quality grade at a first preset position of the carrier; fixing at least two chips of a second type or a second quality grade at a second preset position of the carrier.

[0024] In one embodiment, after fixing the at least two chips at preset positions of the carrier, the method further comprises: forming a bonding layer on surfaces of the at least two chips facing away from the carrier.

[0025] In one embodiment, an alignment mark is formed on the carrying surface of the carrying body and / or in a placement area marked by at least one placement mark.

[0026] The method for manufacturing a three-dimensional integrated circuit stacking structure provided by an embodiment of the present invention fixes at least two first chips at preset positions on a first carrier to form a reconstructed first carrier; bonds at least two first chips on the reconstructed first carrier to at least two second chips on a second carrier to form a stacking structure; and cuts the stacking structure to form a single three-dimensional integrated circuit stacking structure. The present invention avoids the problem of bonding defective products to good products that inevitably occurs during the wafer-to-wafer stacking process by selecting chips that meet the specifications and fixing them on a carrier. Therefore, the method facilitates improving the yield of the three-dimensional integrated circuit stacking structure.

[0027] The wafer reconstruction method provided in the embodiment of the present invention selects chips that meet the specifications for wafer reconstruction, fixes at least two chips at preset positions of a carrier, and forms a reconstructed wafer. The reconstructed wafer can be provided for a three-dimensional integrated circuit stacking structure, thereby facilitating improving the yield of the three-dimensional integrated circuit stacking structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A flow chart of a method for manufacturing a three-dimensional integrated circuit stacking structure provided by an embodiment of the present invention; Figure 2 A schematic diagram of placing marks on a carrying surface provided by an embodiment of the present invention; FIG3 is a schematic diagram of etching grooves on a bearing surface provided by an embodiment of the present invention; Figure 4 A schematic diagram of a partial manufacturing process of a three-dimensional integrated circuit stacking structure provided by an embodiment of the present invention; Figure 5 A flow chart of a first carrier reconstruction method for manufacturing a three-dimensional integrated circuit stacking structure provided by an embodiment of the present invention; Figure 6 A flow chart of a second carrier reconstruction method for manufacturing a three-dimensional integrated circuit stacking structure provided by an embodiment of the present invention; Figure 7 A flow chart of a wafer reconstruction method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In a first aspect, an embodiment of the present invention provides a method for manufacturing a three-dimensional integrated circuit stacking structure, which can improve the yield of the three-dimensional integrated circuit stacking structure.

[0033] like Figure 1 As shown, an embodiment of the present invention provides a method for manufacturing a three-dimensional integrated circuit stacking structure, comprising: S11, fixing at least two first chips at preset positions of a first carrier to form a reconstructed first carrier; the first chips are chips that meet specifications; In this step, at least two first chips are fixed at preset positions of the first carrier to form a reconstructed first carrier. The first chip is a chip to be stacked that meets the specifications after screening. The first carrier can be a carrier wafer, or it can include other carriers such as a carrier blue film and a carrier glass sheet. The preset position is the area where the chips to be stacked are fixed to facilitate bonding and alignment in subsequent processes. In this step, the chips to be stacked are fixed on the carrier to form a reconstructed wafer.

[0034] For example, in an embodiment of the present invention, a wafer test is first performed on the wafer before the first chip is cut, and a chip that meets the specifications is selected as the first chip according to the wafer test result. In this way, by eliminating some unqualified chips, defective products are avoided from participating in the stacking, and the yield of the chips participating in the stacking is guaranteed, thereby ensuring that the yield of the three-dimensional integrated circuit stacking structure is improved as a whole.

[0035] For example, after defective chips are eliminated, the chips involved in stacking can be directly stacked, or they can be classified or sorted according to certain classification standards before being stacked.

[0036] S12, bonding at least two first chips on the reconstructed first carrier to at least two second chips on the second carrier to form a stacked structure; the second chips are chips that meet the specifications; In the step, the chip on the reconstructed first carrier is bonded to the chip on the second carrier to form a stacked structure. The second carrier can be a wafer or a reconstructed wafer. The former is equivalent to stacking chips on wafers, and the latter is equivalent to stacking chips on chips. This step is not limited to this.

[0037] Exemplarily, a wafer test is first performed on the wafer before the second chip is cut, and according to the wafer test result, a chip that meets the specification is selected as the second chip to participate in the stacking. In this way, based on the screening of the first chip in S11, this step screens the second chip, eliminates unqualified chips, and avoids defective chips from participating in the stacking, thereby ensuring that the yield of forming the three-dimensional integrated circuit stacking structure is improved as a whole.

[0038] For example, after defective chips are eliminated, the chips involved in stacking can be directly stacked, or they can be classified or sorted according to certain classification standards before being stacked.

[0039] S13, cutting the stacked structure to form a single three-dimensional integrated circuit stacked structure; wherein each single three-dimensional integrated circuit stacked structure includes a first chip and a second chip bonded together.

[0040] In this step, the stacked structure formed in step S12 is cut to form a single three-dimensional integrated circuit stacked structure. After the bonding in step S12 is completed, a carrier can be removed according to actual needs, and then cut according to design requirements to obtain a single three-dimensional integrated circuit stacked structure. The single three-dimensional integrated circuit stacked structure obtained in this step realizes the bonding of the first chip and the second chip by reconstructing the wafer.

[0041] The method for manufacturing a three-dimensional integrated circuit stacking structure provided by an embodiment of the present invention fixes at least two first chips at preset positions on a first carrier to form a reconstructed first carrier; bonds at least two first chips on the reconstructed first carrier to at least two second chips on a second carrier to form a stacking structure; and cuts the stacking structure to form a single three-dimensional integrated circuit stacking structure. The present invention avoids the problem of bonding defective products to good products that inevitably occurs during the wafer-to-wafer stacking process by selecting chips that meet the specifications and fixing them on a carrier. Therefore, the method can improve the yield of the three-dimensional integrated circuit stacking structure.

[0042] In addition, in the chip-to-chip stacking or chip-to-wafer stacking process, the chips need to be aligned and bonded one by one, and the alignment and bonding waiting time is long, resulting in low efficiency. In the embodiment of the present invention, the wafers are stacked in a wafer-to-wafer manner and then bonded as a whole, which improves the process efficiency.

[0043] Specifically, in one embodiment of the present invention, step S11 includes the following steps: S111 provides a first carrier; S112. On the carrying surface of the first carrier, at least two placement marks are formed; wherein each placement mark identifies a placement area; In this step, if Figure 2 As shown, at least two placement marks 2 are formed on the carrying surface of the first carrier 1. The placement marks 2 can ensure that the chip is placed as required, fix the position of the chip, prevent chip mismatch, and create conditions for subsequent alignment and bonding processes.

[0044] S113. The at least two first chips are placed in different placement areas indicated by placement marks; In this step, the chips can be thinned before being placed to ensure that all chips have the same thickness. The consistent thickness of the chips is conducive to the flatness of the reconstructed wafer and also lays the foundation for subsequent bonding.

[0045] S114. Filling positioning material between adjacent first chips to form a reconstructed first carrier.

[0046] After completing step S113, a certain thickness of positioning material can be filled in the gap between the chips. For example, the positioning material can be made of insulating materials including oxides, silicon nitride, and silicon oxynitride. Filling in the gap between the chips can stabilize the chips and prevent chip displacement and mismatch. In a specific implementation, a certain thickness of positioning material can also be filled in the gap between the chip and the groove as needed. Filling in the gap between the chip and the groove further stabilizes the chip.

[0047] By selecting chips that meet the specifications for wafer reconstruction, a reconstructed wafer can be provided for a three-dimensional integrated circuit stacking structure, thereby facilitating improving the yield of the three-dimensional integrated circuit stacking structure.

[0048] In one embodiment of the present invention, in step S112, at least two placement marks are formed on the carrying surface of the first carrier, including: based on the outer dimensions of the largest chip of the first chip and the second chip, at least two placement marks are formed on the carrying surface of the first carrier; wherein the outline dimensions of the placement areas marked by each placement mark are consistent, and the outline dimensions of the placement areas marked by each placement mark are equal to the outer dimensions of the largest chip of the first chip and the second chip or equal to the sum of the outer dimensions of the largest chip of the first chip and the second chip and a preset value. The preset value is the reserve between the outer dimensions of the largest chip and the placement mark. The placement mark can ensure that the chip is placed as required, fix the position of the chip, prevent chip mismatch, and create conditions for subsequent alignment and bonding processes.

[0049] In another embodiment of the present invention, after at least two placement marks are formed on the carrying surface of the first carrier, the method further includes: etching a groove at a specified position in the placement area marked by each placement mark; the outline size of the groove matches the outer size of the first chip to be placed therein; wherein, placing at least two first chips in the placement areas marked by different placement marks, respectively, includes: placing at least two first chips in the grooves in the placement areas marked by different placement marks, respectively. A groove is made by photolithography and etching according to the size of the first core and the position in the placement mark, so that the first chip is placed therein to fix the chip.

[0050] In a specific implementation, as shown in FIG3 , grooves 31 can be made on the first carrier wafer according to a specific placement scheme. First, the position of the chip 11 in the placement mark 21 is determined according to the design scheme and size. Second, a corresponding model (pattern) is made in the placement mark by photolithography. Finally, a groove 31 of a certain depth is made on the carrier wafer according to the model by wet etching, for example, a groove 31 with a depth of 20 μm.

[0051] The outline size of the groove is consistent with the model, thus ensuring that the outer dimensions of the chip to be placed therein match, that is, the chip can be fixed in the chip groove. The specific depth of the groove can be adjusted according to the actual situation, but it needs to be unified to ensure that the thickness of all wafers to be bonded is consistent. In the specific implementation process, the groove may be uneven after etching, and the groove can be backfilled to make the bottom of the groove flatter.

[0052] In another embodiment of the present invention, in step S112, at least two first chips of the same performance type or the same quality level can be placed at the placement mark of the first carrier, or at least two first chips of the first type or the first quality level can be placed at the first preset position of the first carrier, and at least two first chips of the second type or the second quality level can be placed at the second preset position of the first carrier. After the chips are classified, the chips are placed in order, so that the classification standards of the chips participating in the stacking can be matched, thereby improving the quality of the three-dimensional integrated circuit stacking structure.

[0053] In a specific implementation, the chips to be stacked can be classified according to chip level, device characteristics, etc., and the corresponding types can be placed on the same carrier according to customized requirements. For example, they can be classified according to whether there is memory repair, etc. For another example, they can be classified according to frequency or current characteristics.

[0054] In another embodiment of the present invention, after fixing at least two first chips at preset positions of the first carrier, the method further comprises: forming a bonding layer on the surface of the at least two first chips facing away from the first carrier. In a specific implementation, a corresponding bonding layer can be made on the chip. The specific level of the bonding layer can be selected according to the design scheme. For example, the top chip and the bottom chip can be made with bonding pads and through holes as required.

[0055] In another embodiment of the present invention, an alignment mark is formed on the bearing surface of the first carrier and / or in the placement area marked by at least one placement mark. In order to ensure the functional connectivity of the devices in the chip, an alignment mark can be added to the boundary of the placement area or the edge of the chip. The alignment mark can ensure alignment when wafer-to-wafer stacking and bonding, prevent chip mismatch, improve bonding alignment accuracy, and improve yield.

[0056] In specific implementation, the shape and position of the alignment mark model can be adjusted according to actual conditions. Specific graphic units can be made on the first carrier respectively. The placement direction of the graphic units needs to be paid attention to in order to adapt to one-to-one correspondence after possible flipping.

[0057] In another embodiment of the present invention, the step of bonding at least two first chips on the reconstructed first carrier to at least two second chips on the second carrier includes: bonding the two first chips on the reconstructed first carrier to the same second chip on the second carrier.

[0058] In an embodiment, before bonding at least two first chips on the reconstructed first carrier to correspondingly bond at least two second chips on the second carrier, the method further includes: fixing at least two second chips at preset positions on the second carrier to form a second carrier having the second chips.

[0059] It should be noted that the second carrier can be made by the same method as the first carrier. However, compared with the first carrier, the second carrier can implement a more complex process. For example, the number of second chip grooves can be more than one, and the outline size of the groove matches the outer size of the second chip to be placed therein. In this way, one groove on the first carrier matches multiple grooves on the second carrier, thereby achieving stacking of one first chip and multiple second chips.

[0060] In a specific implementation, for the case where multiple top chips are aligned with one bottom chip, the distance between each chip and the placement mark boundary can be determined according to the design plan to determine the specific position, and then the grooves can be photolithographically etched in the same manner as in the above case.

[0061] In traditional wafer-to-wafer stacking, the sizes of the two chips must be consistent. The grooves can not only fix the chips, but also align the chips when stacking, solving the problem that the sizes of the two chips must be consistent when stacking wafers. By etching different numbers of grooves in the placement mark, it can support chip stacking in different forms such as 1 to 1, 1 to many, and many to many. The grooves can fix the chips, improve the accuracy of bonding alignment, and prevent bonding mismatch and chip mismatch.

[0062] Figure 4The figure shows a schematic diagram of the manufacturing process of the three-dimensional integrated circuit stacking structure provided by an embodiment of the present invention. In a specific implementation, the carrier 31 carrying the top chip 11 can be flipped over and then pre-bonded, bonded, and post-bonded with the carrier 32 carrying the bottom chip 12. In this process, the wafers need to be aligned before bonding to avoid problems such as mismatching. When bonding in a face-to-back manner, the chip can be selected, TSV (Through Silicon Via) can be made according to the design plan, and then the corresponding chip can be flipped and transferred to the carrier wafer. After the bonding is completed, a carrier wafer is removed according to actual needs, and finally cut according to the design requirements to obtain the required three-dimensional integrated circuit stacking chip. The method for manufacturing a three-dimensional integrated circuit stacking structure provided by the embodiment of the present invention can support chip stacking of different forms such as 1 to 1, 1 to many, and many to many by using photolithography and etching to etch different numbers of grooves in the positions of the placement marks of the first carrier and the second carrier, thereby solving the problem that traditional wafers can only be stacked 1 to 1, and the size of the two chips must be consistent when wafers are stacked, and solving the size limitation when chips are stacked. In addition, technical means such as filling in the gap between the chip and the groove, adding alignment marks at the boundary of the placement area or the edge of the chip, etc. can ensure alignment when wafers are stacked and bonded, prevent chip mismatch, improve the accuracy of bonding alignment, and improve yield.

[0063] The following describes in detail the method for manufacturing a three-dimensional integrated circuit stacking structure provided by an embodiment of the present invention through a specific embodiment.

[0064] The method for manufacturing a three-dimensional integrated circuit stacking structure provided by an embodiment of the present invention may include the following steps: S301. Obtain at least two first chips; the first chip is a chip that meets the specifications; S302. Providing a first carrier; S303. Based on the outer dimensions of the largest chip among the first chip and the second chip, at least two placement marks are formed on the carrying surface of the first carrier; wherein each placement mark identifies a placement area; The outline size of the placement area marked by each placement mark is consistent, and the outline size of the placement area marked by each placement mark is equal to the outer size of the largest chip between the first chip and the second chip or equal to the sum of the outer size of the largest chip between the first chip and the second chip and a preset value; S304. Etching a groove at a designated position in each placement area identified by the placement mark; the outline size of the groove matches the outer dimensions of the first chip to be placed therein; S305. The same performance type or the same quality level of at least two first chips, respectively placed in the groove of the first carrier; Or at least two first chips of the first type or the first quality grade are placed in the first grooves of the first carrier respectively; at least two first chips of the second type or the second quality grade are placed in the second grooves of the first carrier respectively; S306. An alignment mark is formed on the carrying surface of the first carrier and / or in the placement area indicated by at least one placement mark; S307. Forming a bonding layer on the surface of the at least two first chips away from the first carrier; S308. Fill positioning material between adjacent first chips to form a reconstructed first carrier.

[0065] Figure 5 , Figure 6 A flow chart of the reconstruction method of the first carrier and the second carrier is shown respectively.

[0066] S401. Obtain at least two second chips; the second chip is a chip that meets the specifications; S402. Providing a second carrier; S403. Based on the outer dimensions of the largest chip among the first chip and the second chip, at least two placement marks are formed on the carrying surface of the second carrier; wherein each placement mark identifies a placement area; Among them, the outline dimensions of the placement area marked by each placement mark are consistent, and the outline dimensions of the placement area marked by each placement mark are equal to the outer dimensions of the largest chip between the first chip and the second chip, or equal to the sum of the outer dimensions of the largest chip between the first chip and the second chip and a preset value.

[0067] S404. Etching at least one groove at a designated position in each placement area identified by the placement mark; the contour size of the groove matches the outer dimensions of the second chip to be placed therein; S405. The same performance type or the same quality level of at least two second chips, respectively placed in the groove of the second carrier; Or at least two second chips of the first type or the first quality grade are placed in the first grooves of the second carrier respectively; at least two second chips of the second type or the second quality grade are placed in the second grooves of the second carrier respectively; S406. An alignment mark is formed on the carrying surface of the second carrier and / or in the placement area indicated by at least one placement mark; S407. Forming a bonding layer on the surface of the at least two second chips away from the second carrier; S408. Filling the positioning material between adjacent second chips to form a reconstructed second carrier; S501. The at least two first chips on the reconstructed first carrier are bonded to the at least two second chips on the second carrier to form a stacked structure; S502. Cutting the stacked structure to form a single three-dimensional integrated circuit stacked structure; wherein each single three-dimensional integrated circuit stacked structure includes a first chip and a second chip bonded together.

[0068] In a second aspect, an embodiment of the present invention provides a wafer reconstruction method, which can provide a reconstructed wafer for a three-dimensional integrated circuit stacking structure by selecting chips that meet the specifications for wafer reconstruction, thereby facilitating improving the yield of the three-dimensional integrated circuit stacking structure.

[0069] An embodiment of the present invention also provides a wafer reconstruction method, comprising: obtaining at least two chips; the chips are chips that meet specifications; and fixing the at least two chips at preset positions of a carrier to form a reconstructed wafer.

[0070] In one embodiment, fixing the at least two chips at preset positions of a carrier to form a reconstructed wafer includes: providing a carrier; forming at least two placement marks on a carrying surface of the carrier; wherein each placement mark identifies a placement area; placing at least two chips respectively in placement areas identified by different placement marks; and filling positioning materials between adjacent chips to form a reconstructed carrier.

[0071] In one embodiment, at least two placement marks are formed on the carrying surface of the carrier, including: based on the outer dimensions of the chip, at least two placement marks are formed on the carrying surface of the carrier; wherein the outline dimensions of the placement areas marked by each placement mark are consistent, and the outline dimensions of the placement areas marked by each placement mark are equal to the outer dimensions of the largest chip among the chips or equal to the sum of the outer dimensions of the largest chip among the chips and a preset value.

[0072] In one embodiment, after at least two placement marks are formed on the carrying surface of the carrier, the method further includes: etching a groove at a specified position in the placement area marked by each placement mark; the contour size of the groove matches the outer size of the chip to be placed therein; wherein, placing at least two chips respectively in the placement areas marked by different placement marks includes: placing at least two chips respectively in the grooves in the placement areas marked by different placement marks.

[0073] In one embodiment, fixing at least two chips at preset positions of a carrier includes: fixing at least two chips of the same performance type or the same quality grade at preset positions of the carrier; or fixing at least two chips of a first type or a first quality grade at a first preset position of the carrier; fixing at least two chips of a second type or a second quality grade at a second preset position of the carrier.

[0074] In one embodiment, after fixing the at least two chips at preset positions of the carrier, the method further comprises: forming a bonding layer on surfaces of the at least two chips facing away from the carrier.

[0075] In one embodiment, an alignment mark is formed on the carrying surface of the carrying body and / or in a placement area marked by at least one placement mark.

[0076] The wafer reconstruction method provided by the embodiment of the present invention fixes at least two chips at preset positions of a carrier to form a reconstructed wafer. The present invention can provide a reconstructed wafer for a three-dimensional integrated circuit stacking structure by selecting chips that meet the specifications for wafer reconstruction, thereby facilitating improving the yield of the three-dimensional integrated circuit stacking structure.

[0077] The wafer reconstruction provided by the embodiment of the present invention is described in detail below through a specific embodiment.

[0078] like Figure 7 As shown, the wafer reconstruction method provided by the embodiment of the present invention may include the steps of: S601. Obtain at least two chips; the chip is a chip that meets the specifications; S602. Providing a carrier; S603. Based on the outer dimensions of the chip, at least two placement marks are formed on the carrying surface of the carrier; wherein each placement mark identifies a placement area; The outline size of the placement area marked by each placement mark is consistent, and the outline size of the placement area marked by each placement mark is equal to the outer size of the largest chip among the chips or equal to the sum of the outer size of the largest chip among the chips and a preset value. The preset value is a reserve between the outer size of the chip and the placement mark.

[0079] S604. Etching at least one groove at a designated position in each placement area identified by the placement mark; the contour size of the groove matches the outer dimensions of the chip to be placed therein; S605. Place at least two chips in grooves in placement areas marked by different placement marks.

[0080] S606. An alignment mark is formed on the carrying surface of the carrying body and / or in a placement area marked by at least one placement mark.

[0081] S607. Form a bonding layer on the surfaces of the at least two chips facing away from the carrier.

[0082] S608. Fill positioning material between adjacent chips to form a reconstructed wafer.

[0083] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0084] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0085] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

[0086] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for manufacturing a three-dimensional integrated circuit stacking structure, characterized in that: include: Fixing at least two first chips at preset positions of the first carrier to form a reconstructed first carrier; The first chip is a chip that meets the specifications; Bonding at least two first chips on the reconstructed first carrier to at least two second chips on the second carrier to form a stacked structure; the second chips are chips that meet the specifications; The stacked structure is cut to form a single three-dimensional integrated circuit stacked structure; wherein each single three-dimensional integrated circuit stacked structure includes a first chip and a second chip bonded together.

2. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 1, characterized in that: The step of fixing at least two first chips at preset positions of the first carrier to form a reconstructed first carrier comprises: providing a first carrier; At least two placement marks are formed on the carrying surface of the first carrying body, wherein each placement mark identifies a placement area; Placing at least two first chips respectively in placement areas marked by different placement marks; Positioning material is filled between adjacent first chips to form a reconstructed first carrier.

3. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 2, characterized in that: At least two placement marks are formed on the carrying surface of the first carrying body, including: Based on the outer dimensions of the largest chip between the first chip and the second chip, at least two placement marks are formed on the carrying surface of the first carrier; wherein the outline dimensions of the placement areas marked by each placement mark are consistent, and the outline dimensions of the placement areas marked by each placement mark are equal to the outer dimensions of the largest chip between the first chip and the second chip or equal to the sum of the outer dimensions of the largest chip between the first chip and the second chip and a preset value.

4. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 2, characterized in that: After forming at least two placement marks on the carrying surface of the first carrying body, the method further includes: Etching a groove at a designated position in the placement area marked by each placement mark; the outline size of the groove matches the outer size of the first chip to be placed therein; The step of placing at least two first chips respectively in placement areas marked by different placement marks includes: At least two first chips are placed in grooves in placement areas marked by different placement marks respectively.

5. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 1, wherein: The step of fixing at least two first chips at preset positions of the first carrier includes: Fixing at least two first chips of the same performance type or the same quality grade at preset positions of the first carrier; or Fixing at least two first chips of a first type or a first quality level at first preset positions on a first carrier; At least two first chips of a second type or a second quality grade are fixed at second preset positions on the first carrier.

6. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 1, characterized in that: After fixing the at least two first chips at the preset positions of the first carrier, the method further includes: A bonding layer is formed on surfaces of the at least two first chips facing away from the first carrier.

7. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 2, characterized in that: Also includes: An alignment mark is formed on the carrying surface of the first carrying body and / or in a placement area marked by at least one placement mark.

8. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 1, characterized in that: The step of correspondingly bonding the at least two first chips on the reconstructed first carrier to the at least two second chips on the second carrier includes: The two first chips on the reconstructed first carrier are bonded correspondingly to the same second chip on the second carrier.

9. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 1, characterized in that: Before bonding the at least two first chips on the reconstructed first carrier to the at least two second chips on the second carrier, the method further includes: At least two second chips are fixed at preset positions of the second carrier to form a second carrier having the second chips.

10. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 9, characterized in that: The method of fixing at least two second chips at preset positions of a second carrier to form a second carrier having the second chips comprises: providing a second carrier; At least two placement marks are formed on the carrying surface of the second carrying body, wherein each placement mark identifies a placement area; Placing at least two second chips respectively in placement areas marked by different placement marks; Positioning material is filled between adjacent second chips to form a reconstructed second carrier.

11. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 10, characterized in that: At least two placement marks are formed on the carrying surface of the second carrying body, including: Based on the outer dimensions of the largest chip between the first chip and the second chip, at least two placement marks are formed on the carrying surface of the second carrier; wherein the outline dimensions of the placement areas marked by each placement mark are consistent, and the outline dimensions of the placement areas marked by each placement mark are equal to the outer dimensions of the largest chip between the first chip and the second chip or equal to the sum of the outer dimensions of the largest chip between the first chip and the second chip and a preset value.

12. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 10, characterized in that: After forming at least two placement marks on the carrying surface of the second carrying body, the method further includes: Etching at least one groove at a designated position in the placement area marked by each placement mark; the outline size of the groove matches the outer size of the second chip to be placed therein; The step of placing at least two second chips respectively in placement areas marked by different placement marks includes: At least two second chips are placed in grooves in placement areas marked by different placement marks respectively.

13. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 9, wherein: The step of fixing at least two second chips at preset positions of the second carrier includes: Fixing at least two second chips of the same performance type or the same quality level at preset positions of the second carrier; or Fixing at least two second chips of a first type or a first quality level at first preset positions on a second carrier; At least two second chips of a second type or a second quality grade are fixed at second preset positions on the second carrier.

14. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 9, characterized in that: After fixing the at least two second chips at the preset positions of the second carrier, the method further includes: A bonding layer is formed on surfaces of the at least two second chips facing away from the second carrier.

15. The method for manufacturing a three-dimensional integrated circuit stacking structure according to claim 9, characterized in that: Also includes: An alignment mark is formed on the carrying surface of the second carrying body and / or in a placement area marked by at least one placement mark.

16. A wafer reconstruction method, characterized in that: include: Obtain at least two chips; the chips are chips that meet the specifications; The at least two chips are fixed at preset positions of the carrier to form a reconstructed wafer.

17. The wafer reconstruction method according to claim 16, characterized in that: The step of fixing the at least two chips at preset positions of a carrier to form a reconstructed wafer includes: providing a carrier; At least two placement marks are formed on the carrying surface of the carrying body; wherein each placement mark identifies a placement area; Place at least two chips in placement areas marked by different placement marks respectively; Positioning materials are filled between adjacent chips to form a reconstructed carrier.

18. The wafer reconstruction method according to claim 17, characterized in that: At least two placement marks are formed on the carrying surface of the carrying body, including: Based on the outer dimensions of the chip, at least two placement marks are formed on the carrying surface of the carrier; wherein the outline dimensions of the placement areas marked by each placement mark are consistent, and the outline dimensions of the placement areas marked by each placement mark are equal to the outer dimensions of the largest chip among the chips or equal to the sum of the outer dimensions of the largest chip among the chips and a preset value.

19. The wafer reconstruction method according to claim 17, characterized in that: After forming at least two placement marks on the carrying surface of the carrying body, the method further includes: Etching at least one groove at a designated position in the placement area marked by each placement mark; the outline size of the groove matches the outer size of the chip to be placed therein; The step of placing at least two chips in placement areas marked by different placement marks includes: At least two chips are placed in grooves in placement areas marked by different placement marks.

20. The wafer reconstruction method according to claim 16, characterized in that: The step of fixing at least two chips at preset positions of a carrier includes: Fixing at least two chips of the same performance type or the same quality level at preset positions of the carrier; or Fixing at least two chips of a first type or a first quality level at first preset positions on a carrier; At least two chips of the second type or of the second quality level are fixed at second preset positions of the carrier.

21. The wafer reconstruction method according to claim 16, characterized in that: After fixing at least two chips at preset positions of the carrier, the method further includes: A bonding layer is formed on the surfaces of the at least two chips facing away from the carrier.

22. The wafer reconstruction method according to claim 17, characterized in that: Also includes: An alignment mark is formed on the carrying surface of the carrying body and / or in a placement area marked by at least one placement mark.

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