SiC device with trench gate oxide protection junction and preparation method thereof

Abstract

The invention discloses a SiC device with a trench gate oxide protection junction and a preparation method. Relates to the technical field of semiconductors. Comprising the following steps: S100, sequentially forming a SiC Drift layer, a P-body region and an NP region on the top surface of a SiC Sub layer; s200, etching the top surface of the NP region downwards to form a first groove; s300, forming a second groove in the bottom surface of the first groove through downward etching; s400, forming a P-shield region on the bottom surface of the second groove through Al ion implantation; s500, gate oxide layers are formed on the side walls of the first groove and the second groove through high-temperature dry-oxygen oxidation; s600, forming a Poly layer on the surface of the gate oxide layer in a polycrystalline silicon deposition mode; s700, forming isolation dielectric layers on the top surfaces of the NP region, the gate oxide layer, the Poly layer and the P-shield region in an oxide deposition mode; the ohmic contact is prepared on the top surface of the P-shield region to connect the source electrode, so that grounding processing of the P-shield region is realized, and the protection capability of the P-shield region is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SiC device with a trench gate oxide protection junction and a preparation method thereof. Background Art

[0002] Voltage-controlled switching devices have always been dominated by Si-based devices. In the low and medium voltage fields, Si MOSFET devices are popular due to their excellent switching performance. In the medium and high voltage fields, Si IGBT devices are more advantageous because it is difficult for Si MOSFET to achieve a performance compromise between high voltage and low conduction loss. However, the obvious disadvantage is poor switching performance, and the switching frequency is basically below 60kHz. However, with the continuous development of society, new energy vehicles, clean energy, and industrial power supplies are all moving towards high voltage and high power, and the efficiency requirements for the system are also constantly increasing. However, due to the physical performance limits of their own materials, SiMOSFET and Si IGBT devices have been difficult to achieve higher efficiency. Therefore, the third-generation wide bandgap semiconductor power devices represented by SiC MOSFET have been favored. Their physical properties are very advantageous, and they also have the conduction and switching characteristics of SiMOSFET and SiIGBT devices.

[0003] Trench gate SiC MOSFET has a smaller source cell structure, which allows the chip size to be smaller at the same power level, achieving advantages such as switching performance and product cost. Many chip manufacturers also use trench gate structure as the future development direction of SiC MOSFET products. However, due to the electric field concentration problem at the bottom corner of the trench and the quality problem of the gate oxide layer grown by direct thermal oxidation, trench gate SiC MOSFET is prone to breakdown failure at the gate oxide layer at the bottom corner of the trench during long-term use, which is unacceptable for increasingly harsh operating conditions. Therefore, how to better protect the trench gate oxide layer during the long-term use of trench gate SiC MOSFET is a necessary issue to determine its safe and stable use. Summary of the invention

[0004] In view of the above problems, the present invention provides a trench gate oxide layer for protecting the device, which improves the stability of the device and prolongs the service life of the device, and provides a SiC device with a trench gate oxide protection junction and a preparation method.

[0005] The technical solution of the present invention is: A method for preparing a SiC device with a trench gate oxide protection junction comprises the following steps: S100, forming a SiC Drift layer, a P-body region and a NP region in sequence on the top surface of the SiC Sub layer; S200, etching downwards on the top surface of the NP region to form a first trench; S300, forming a second trench on the bottom surface of the first trench by etching downwards; S400, forming a P-shield region on the bottom surface of the second trench by Al ion implantation; S500, forming a gate oxide layer on the sidewalls of the first trench and the second trench by high temperature dry oxygen oxidation; S600, forming a Poly layer on the surface of the gate oxide layer by depositing polysilicon; S700, forming an isolation dielectric layer on the top surfaces of the NP region, the gate oxide layer, the Poly layer, and the P-shield region by means of oxide deposition; S800, forming an ohmic contact alloy layer on the top surface of the NP region and the P-shield region by Ni metal sputtering or deposition followed by thermal annealing; S900, forming a front electrode metal layer on the top of the device by sputtering Ti and AlCu metals.

[0006] Specifically, the doping concentration of the SiC Sub layer in step S100 is 1E19-3E19cm -2 , the doping concentration of SiC Drift layer is 1E15-5E16cm -2 .

[0007] Specifically, in step S100, the depth from the bottom surface of the P-body region to the top surface of the SiC Drift layer is 0.6um-2um, and the doping concentration is 1E17-3E18cm -2 .

[0008] Specifically, in step S100, the depth between the bottom surface of the NP region and the top surface of the SiC Drift layer is 0.3um-1.5um, and the doping concentration is 1E18-1E19cm -2 .

[0009] Specifically, in step S200 , the depth between the bottom surface of the first trench and the top surface of the SiC Drift layer is 1 um-3 um.

[0010] Specifically, in step S300, the depth of the bottom surface of the second groove from the bottom surface of the first groove is 0.4um-0.8um, and the distances between the left and right ends and the two sides of the first groove are 0.2um-0.5um.

[0011] Specifically, the depth of the bottom surface of the P-shield region from the bottom surface of the second trench in step S400 is 0.3um-0.8um, and the doping concentration is 5E18-1E19cm -2 .

[0012] Specifically, the thickness of the gate oxide layer in step S500 is 30 nm-100 nm.

[0013] A SiC device with a trench gate oxide protection junction, comprising a SiC Sub layer, a SiCDrift layer, a P-body region, an NP region, an ohmic contact alloy layer and a front electrode metal layer arranged in sequence from bottom to top; A pair of first grooves extending downward from the top surface of the NP region is provided in the SiC Drift layer; a second groove extending downward is provided on the bottom surface of the first groove, and the second groove is located in the SiC Drift layer; A P-shield region extending downward is provided at the bottom of the second trench; the lateral width of the P-shield region is smaller than the lateral width of the first trench; A gate oxide layer is provided in the first trench, extending downward along the sidewall of the first trench through the sidewall of the second trench and connected to the P-shield region; A Poly layer is provided on the sidewall of the gate oxide layer in the first trench; A horizontally extending isolation dielectric layer is provided on the top surface of the NP region, and the isolation dielectric layer extends downward in the first trench after passing through the gate oxide layer and the Poly layer, and is connected to the P-shield region; The ohmic contact alloy layer is located on the side of the isolation dielectric layer and is formed on the top surface of the NP region and the top surface of the P-shield region respectively.

[0014] Specifically, the bottom surface of the front electrode metal layer is connected to the ohmic contact alloy layer and the isolation dielectric layer respectively.

[0015] The present invention aims at the problem of safe and stable use of the trench gate oxide layer of the trench gate SiC MOSFET. The first and second trench designs are adopted in the device. A P-shield region with a deeper junction depth and a narrower width than the first trench is formed by implanting at the bottom of the second trench. The purpose of this design is to prevent the depletion layer generated by the narrower P-shield region and the SiC Drift layer from expanding too much and thus affecting the conduction performance of the device. The deeper junction depth of the P-shield region can ensure that the generated depletion layer can wrap around the bottom corner of the trench, thereby protecting the trench gate oxide layer. At the same time, the present invention also prepares an ohmic contact connection source electrode on the top surface of the P-shield region, realizes the grounding treatment of the P-shield region, and further improves its protection capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of a trench gate SiC MOSFET of the present invention; Figure 2 is a structural schematic diagram of step S100 of the present invention; Figure 3 is a schematic structural diagram of step S200 of the present invention; Figure 4is a schematic structural diagram of step S300 of the present invention; Figure 5 is a schematic structural diagram of step S400 of the present invention; Figure 6 is a schematic structural diagram of step S500 of the present invention; Figure 7 is a schematic diagram of the structure of step S600 of the present invention; Figure 8 is a schematic diagram of the structure of step S700 of the present invention; Fig. 9 is a structural schematic diagram of step S800 of the present invention; Fig.10 is a structural schematic diagram of step S900 of the present invention; Fig.11 is a structural schematic diagram of step S1000 of the present invention; Fig.12 is a structural schematic diagram of step S1100 of the present invention; In the figure, 1 is SiC Sub layer, 2 is SiCDrift layer, 3 is P-body region, 4 is NP region, 5 is the first trench, 6 is the second trench, 7 is P-shield region, 8 is gate oxide layer, 9 is Poly layer, 10 is isolation dielectric layer, 11 is ohmic contact alloy layer, and 12 is front electrode metal layer. DETAILED DESCRIPTION

[0017] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0018] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0019] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0020] A SiC device with a trench gate oxide protection junction comprises the following steps: S100, forming a SiC Drift layer 2 on the top surface of the SiC Sub layer 1 by epitaxial deposition; The doping concentration of SiC Sub layer 1 in step S100 is 1E19-3E19cm -2 , SiC Drift layer 2 doping concentration is 1E15-5E16cm -2 .

[0021] S200, forming a P-body region 3 on the top surface of the SiC Drift layer 2 by Al ion implantation; The depth of the bottom surface of the P-body region 3 from the top surface of the SiC Drift layer (2) in step S200 is 0.6um-2um, and the doping concentration is 1E17-3E18cm -2 .

[0022] S300, forming an NP region 4 on the top surface of the P-body region 3 by N ion implantation; The depth of the bottom surface of the NP region 4 in step S300 from the top surface of the SiC Drift layer (2) is 0.3um-1.5um, and the doping concentration is 1E18-1E19cm -2 .

[0023] S400, etching downwards to form a first trench 5 on the top surface of the NP region 4; In step S400 , the depth between the bottom surface of the first trench 5 and the top surface of the SiC Drift layer ( 2 ) is 1 um-3 um.

[0024] S500, forming a second trench 6 on the bottom surface of the first trench 5 by etching downwards; In step S500, the depth of the bottom surface of the second groove 6 from the bottom surface of the first groove (5) is 0.4um-0.8um, and the left and right ends are 0.2um-0.5um away from the two sides of the first groove 5.

[0025] S600, forming a P-shield region 7 at the bottom surface of the second trench 6 by Al ion implantation, and then activating the implanted regions of the P-body region 3, the NP region 4 and the P-shield region 7 by high temperature ion annealing; In step S600, the depth of the bottom surface of the P-shield region 7 from the bottom surface of the second trench 6 is 0.3um-0.8um, and the doping concentration is 5E18-1E19cm -2 .

[0026] S700, forming a gate oxide layer 8 on the sidewalls of the first trench 5 and the second trench 6 by high temperature dry oxygen oxidation; The thickness of the gate oxide layer 8 in step S700 is 30 nm-100 nm.

[0027] S800, forming a Poly layer 9 on the surface of the gate oxide layer 8 by polysilicon deposition; S900, forming an isolation dielectric layer 10 on the top surfaces of the NP region 4, the gate oxide layer 8, the Poly layer 9 and the P-shield region 7 by oxide deposition; S1000, forming an ohmic contact alloy layer 11 on the top surface of the NP region 4 and the P-shield region 7 by Ni metal sputtering or deposition followed by thermal annealing; The Ni metal thickness in step S1000 is 0.3um-1um.

[0028] S1100, forming a front electrode metal layer 12 on the top of the device by sputtering Ti and AlCu metals.

[0029] In step S1100 , the thickness of the Ti metal is 0.1um-0.6um, and the thickness of the AlCu metal is 2um-5um.

[0030] A SiC device with a trench gate oxide protection junction comprises a SiC Sub layer 1, a SiCDrift layer 2, a P-body region 3, an NP region 4, an ohmic contact alloy layer 11 and a front electrode metal layer 12 arranged in sequence from bottom to top; A pair of first trenches 5 extending downward from the top surface of the NP region 4 is provided in the SiC Drift layer 2; a second trench 6 extending downward is provided on the bottom surface of the first trench 5, and the second trench 6 is located in the SiC Drift layer 2; A P-shield region 7 extending downward is provided at the bottom of the second groove 6; the lateral width (value range 0.3um-1um) of the P-shield region 7 is larger than the lateral width of the second groove 6 and smaller than the lateral width of the first groove 5; A gate oxide layer 8 is provided in the first trench 5 and extends downward along the sidewall of the first trench 5 through the sidewall of the second trench 6 and connected to the P-shield region 7; A Poly layer 9 is provided on the sidewall of the gate oxide layer 8 in the first trench 5; A horizontally extending isolation dielectric layer 10 is provided on the top surface of the NP region 4. After passing through the gate oxide layer 8 and the Poly layer 9, the isolation dielectric layer 10 extends downward in the first trench 5 and is connected to the P-shield region 7. The ohmic contact alloy layer 11 is located at the side of the isolation dielectric layer 10 and is formed on the top surface of the NP region 4 and the top surface of the P-shield region 7 respectively; The bottom surface of the front electrode metal layer 12 is connected to the ohmic contact alloy layer 11 and the isolation dielectric layer 10 respectively.

[0031] The present invention adopts the first trench 5 and the second trench 6 structural design in the trench gate SiC MOSFET. The first trench is for preparing the gate oxide layer and the Poly layer 9 to form the gate electrode, and the second trench is for forming the P-shield region 7. By implanting a P-shield region 7 with a deeper junction depth and a narrower width than the first trench 5 at the bottom surface of the second trench 6, the depletion layer represented by the dotted line generated by the narrower P-shield region 7 and the SiC Drift layer 2 will not expand too much, thereby affecting the conduction performance of the device, and the deeper junction depth of the P-shield region 7 can ensure that the generated depletion layer can wrap the bottom corner of the trench, thereby protecting the trench gate oxide layer. At the same time, the present invention also prepares an ohmic contact connection source electrode on the top surface of the P-shield region 7, realizes the grounding treatment of the P-shield region 7, and further improves its protection capability.

Claims

1. A method for preparing a SiC device with a trench gate oxide protection junction, characterized in that: The steps include: S100, forming a SiC Drift layer (2), a P-body region (3) and a NP region (4) in sequence on the top surface of the SiC Sub layer (1); S200, etching downwards on the top surface of the NP region (4) to form a first trench (5); S300, forming a second groove (6) on the bottom surface of the first groove (5) by etching downwards; S400, forming a P-shield region (7) on the bottom surface of the second trench (6) by Al ion implantation; S500, forming a gate oxide layer (8) on the side walls of the first trench (5) and the second trench (6) by high-temperature dry oxygen oxidation; S600, forming a Poly layer (9) on the surface of the gate oxide layer (8) by depositing polysilicon; S700, forming an isolation dielectric layer (10) on the top surfaces of the NP region (4), the gate oxide layer (8), the Poly layer (9) and the P-shield region (7) by means of oxide deposition; S800, forming an ohmic contact alloy layer (11) on the top surface of the NP region (4) and the P-shield region (7) by Ni metal sputtering or deposition followed by thermal annealing; S900, forming a front electrode metal layer (12) on the top of the device by sputtering Ti and AlCu metals.

2. A method for preparing a SiC device with a trench gate oxide protection junction according to claim 1, characterized in that: The doping concentration of the SiC Sub layer (1) in step S100 is 1E19-3E19cm -2 , the doping concentration of SiC Drift layer (2) is 1E15-5E16cm -2 .

3. The method for preparing a SiC device with a trench gate oxide protection junction according to claim 1, characterized in that: In step S100, the depth of the bottom surface of the P-body region (3) from the top surface of the SiC Drift layer (2) is 0.6um-2um, and the doping concentration is 1E17-3E18cm -2 .

4. The method for preparing a SiC device with a trench gate oxide protection junction according to claim 1, characterized in that: In step S100, the depth of the bottom surface of the NP region (4) from the top surface of the SiC Drift layer (2) is 0.3um-1.5um, and the doping concentration is 1E18-1E19cm -2 .

5. The method for preparing a SiC device with a trench gate oxide protection junction according to claim 1, characterized in that: In step S200, the depth between the bottom surface of the first trench (5) and the top surface of the SiC Drift layer (2) is 1 um-3 um.

6. The method for preparing a SiC device with a trench gate oxide protection junction according to claim 1, characterized in that: In step S300, the depth of the bottom surface of the second groove (6) from the bottom surface of the first groove (5) is 0.4um-0.8um, and the distances between the left and right ends and the two sides of the first groove (5) are 0.2um-0.5um.

7. The method for preparing a SiC device with a trench gate oxide protection junction according to claim 1, characterized in that: The depth of the bottom surface of the P-shield region (7) from the bottom surface of the second trench (6) in step S400 is 0.3um-0.8um, and the doping concentration is 5E18-1E19cm -2 .

8. The method for preparing a SiC device with a trench gate oxide protection junction according to claim 1, characterized in that: The thickness of the gate oxide layer (8) in step S500 is 30 nm-100 nm.

9. A SiC device with a trench gate oxide protection junction, prepared by the method for preparing a SiC device with a trench gate oxide protection junction according to any one of claims 1 to 8, characterized in that: It comprises a SiC Sub layer (1), a SiC Drift layer (2), a P-body region (3), an NP region (4), an ohmic contact alloy layer (11) and a front electrode metal layer (12) which are arranged in sequence from bottom to top; The SiC Drift layer (2) is provided with a pair of first grooves (5) extending downward from the top surface of the NP region (4); the bottom surface of the first groove (5) is provided with a second groove (6) extending downward, and the second groove (6) is located in the SiC Drift layer (2); A P-shield region (7) extending downward is provided at the bottom of the second groove (6); the lateral width of the P-shield region (7) is smaller than the lateral width of the first groove (5); A gate oxide layer (8) is provided in the first trench (5), extending downward along the side wall of the first trench (5) through the side wall of the second trench (6) and connected to the P-shield region (7); A Poly layer (9) is provided on the side wall of the gate oxide layer (8) in the first trench (5); A horizontally extending isolation dielectric layer (10) is provided on the top surface of the NP region (4); the isolation dielectric layer (10) extends downward in the first trench (5) after passing through a gate oxide layer (8) and a Poly layer (9) to connect with the P-shield region (7); The ohmic contact alloy layer (11) is located on the side of the isolation dielectric layer (10), and is formed on the top surface of the NP region (4) and the top surface of the P-shield region (7), respectively.

10. The SiC device with trench gate oxide protection junction according to claim 1, characterized in that: The bottom surface of the front electrode metal layer (12) is respectively connected to the ohmic contact alloy layer (11) and the isolation dielectric layer (10).

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