Double-sided high-K dielectric silicon-on-insulator groove LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor

Abstract

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor with a double-sided high-K dielectric silicon-on-insulator groove. The transistor comprises a substrate layer, a buried oxide layer, a silicon film layer and a device top layer which are stacked in sequence, high-K dielectric regions are arranged on two sides of the silicon material main body in the silicon film layer; the widths of the two high-K dielectric regions are equal, and K values are equal; the width of the high-K dielectric region is 0.3 to 0.7 [mu] m; high-K dielectric regions which cover a silicon material main body and have the same thickness and K value are respectively arranged on two sides of a silicon film layer; the high-K dielectric regions on the two sides of the silicon film layer contribute to guiding the electric flux and modulating the distribution of a circle of electric field around the trench, so that the distribution of the electric field around the trench is more uniform, the RESURF effect is improved, and the breakdown voltage of the device is favorably improved. In addition, the high-K dielectric region contributes to consuming electrons in the drift region and assisting to deplete the drift region, so that the doping concentration of the drift region is improved, and the on-resistance of the device is greatly reduced.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor high-voltage power integrated circuit special devices, and in particular relates to a double-sided high-K dielectric silicon trench LDMOS transistor on an insulating layer. Background Art

[0002] With the continuous development of electronic power technology, the concept of integrated circuit technology has been proposed and has attracted widespread attention. Nowadays, the development of all walks of life is closely related to integrated circuit technology. As an important branch of integrated circuit technology, power integration technology has also developed rapidly in recent years. The continuous improvement of technology level and the rapid development of various fields have put forward higher requirements for power integration technology. Lateral double diffused metal oxide semiconductor devices (LDMOS), which occupy an important position in power integration technology, often need to have high withstand voltage and low on-resistance to meet the needs of various application scenarios. Therefore, relevant researchers need to optimize the design of devices in three aspects: structure, materials and manufacturing process. LDMOS devices based on silicon on insulator (SOI) occupy an important position in the field of power devices due to their fast conversion rate and low power consumption. With the continuous development of trench technology and high-K dielectrics, trench technology and high-K materials have also been applied to the design of power devices. The trench termination technology removes the curved junction part of the main junction by groove engraving, fills the trench with dielectric material, and transfers the high electric field to the dielectric area with lower dielectric constant but higher interface breakdown electric field, thereby improving the withstand voltage. High-K dielectrics guide the electric flux and improve the electric field distribution of the device, effectively increasing the breakdown voltage of the device and reducing its on-resistance. This paper uses trench technology and high-K dielectrics to design a double-sided high-K dielectric silicon trench LDMOS transistor (DHK TSOI LDMOS), which effectively increases the breakdown voltage of the device and reduces the on-resistance of the device, which plays a positive role in promoting the innovation of power devices and the development of power integrated circuits. Summary of the invention

[0003] The object of the present invention is to provide a lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor based on a silicon-on-insulator (SOI) substrate and having a trench and a high-K dielectric structure on both sides of a silicon film layer.

[0004] The present invention provides a double-sided high-K dielectric on-insulating-layer silicon trench LDMOS transistor, comprising a substrate layer, a buried oxide layer, a silicon film layer and a device top layer stacked in sequence; high-K dielectric regions are provided on both sides of a silicon material body in the silicon film layer; the two high-K dielectric regions have equal widths and equal K values; the width of the high-K dielectric region is 0.3 μm to 0.7 μm; and the K value of the high-K dielectric region is greater than or equal to 50.

[0005] Preferably, the width of the high-K dielectric region is 0.5 μm to 0.6 μm.

[0006] Preferably, the K value of the high-K dielectric region is 50-200.

[0007] Preferably, the silicon film layer includes a source region, a silicon body, a drift region, a trench and a drain region; the drift region is arranged on the top of the buried oxide layer; the source region, the trench and the drain region arranged in sequence are arranged on the top of the drift region; the source region includes a source region N+ part and a source region P+ part arranged in parallel; the silicon body is located between the source region and the drift region; the source region, the silicon body, the drift region and the drain region together constitute the main body of the silicon material of the silicon film layer.

[0008] Preferably, the drift region is doped with N-type doping and the doping concentration is 1×10 15 cm -3 ~1.6×10 16 cm -3 .

[0009] Preferably, the groove is made of silicon dioxide with a length of 4 μm to 6 μm and a thickness of 8 μm to 11.5 μm.

[0010] Preferably, the top layer of the device includes a gate electrode, a source electrode and a drain electrode; the gate electrode is located on the side of the source region and the silicon body away from the groove; the source electrode is located above the source region, and the drain electrode is located above the drain region.

[0011] Preferably, the silicon film layer has a length of 7 μm to 9 μm, a width of 1 μm to 2 μm, and a thickness of 9 μm to 12 μm.

[0012] Preferably, the buried oxide layer is made of silicon dioxide with a thickness of 2 μm to 4 μm.

[0013] Preferably, the doping type of the substrate layer is P type, and the doping concentration is 1×10 14 cm -3 ~1×10 15 cm -3 of silicon material.

[0014] The present invention has the following beneficial effects: 1. The present invention provides U-shaped high-K dielectric regions with the same thickness and K value as the main body of the silicon material on both sides of the silicon film layer; the high-K dielectric regions on both sides of the silicon film layer help to guide the electric flux and modulate the distribution of the electric field around the groove, so that the electric field distribution around the groove is more uniform, the RESURF effect is improved, and the breakdown voltage of the device is improved.

[0015] 2. The high-K dielectric region provided in the silicon film layer of the present invention helps to consume electrons in the drift region and assists in depleting the drift region, thereby increasing the doping concentration of the drift region and greatly reducing the on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a device structure diagram of Example 1 of the present invention.

[0017] Figure 2 This is a cross-sectional view of the device at z=1 according to Example 1 of the present invention.

[0018] Figure 3 This is a device structure diagram of comparative example 1.

[0019] Figure 4 This is a comparison diagram of the change of the surface electric field of the silicon film layer with the lateral position in Example 1 of the present invention and Comparative Example 1.

[0020] Figure 5 This is a comparison diagram of the electric field around the silicon film layer groove changing with position in Example 1 of the present invention and Comparative Example 1.

[0021] Figure 6 This is a comparison diagram of the effect of the width of the high-K dielectric regions on the breakdown voltage of the device according to the present invention.

[0022] Figure 7 This is a comparison diagram of the effect of the width of the high-K dielectric regions on the on-resistance of the device according to the present invention.

[0023] Figure 8 This is a comparison diagram of the effect of the width of the high-K dielectric regions on the two sides of the silicon film layer of the present invention on the FOM value of the device.

[0024] Fig. 9 This is a comparison diagram of the effect of the K value of the high-K dielectric regions on the breakdown voltage of the device of the present invention.

[0025] Fig.10 This is a comparison diagram of the effect of the K value of the high-K dielectric regions on the on-resistance of the device according to the present invention.

[0026] Fig.11 This is a comparison diagram of the effect of the K value of the high-K dielectric regions on the device FOM value of the present invention.

[0027] Fig.12This is a comparison diagram of the effect of the depth of the groove in the silicon film layer of the present invention on the breakdown voltage, on-resistance and FOM value of the device.

[0028] Fig.13 The figure is a relationship diagram between breakdown voltage and on-resistance comparing Example 1 with other devices in the related field. DETAILED DESCRIPTION

[0029] The present invention is further described below with reference to the accompanying drawings and examples.

[0030] Example 1 like Figure 1 and 2 As shown, a double-sided high-K dielectric silicon trench LDMOS transistor on an insulating layer includes a substrate layer 8, a buried oxide layer 7, a silicon film layer and a device top layer stacked in sequence from bottom to top. The LDMOS transistor has an overall device length of 9 μm, an overall thickness of 25 μm, and a width of 2 μm; a silicon film layer thickness of 12 μm; a buried oxide layer thickness of 3 μm; and a substrate layer thickness of 10 μm.

[0031] The substrate layer 8 is arranged at the bottom, and the doping type is P type, and the doping concentration is 7×10 14 cm -3 The substrate layer 8 is made of silicon material, and the thickness of the substrate layer 8 is 10 μm; the substrate layer 8 is provided with a buried oxide layer 7, and the buried oxide layer 7 is made of silicon dioxide material with a thickness of 3 μm.

[0032] The buried oxide layer 7 is provided with a silicon film layer, which includes a source region, a silicon body 3, a drift region 4, a trench 5, a drain region 6 and a high-K dielectric region 9. The drift region 4 is arranged on the top of the buried oxide layer 7. The source region, the trench 5 and the drain region 6 are arranged on the top of the drift region 4 and are arranged in sequence along the length direction; the source region includes a source region N+ part 1 and a source region P+ part 2 arranged in parallel. The silicon body 3 is located between the source region and the drift region 4, and the cross-sectional shape is the same as the cross-sectional shape of the source region.

[0033] The source region, silicon body 3, drift region 4, and drain region 6 together constitute the silicon material body of the silicon film layer. Both sides of the silicon material body are provided with high-K dielectric regions 9 in a U-shaped structure. The two high-K dielectric regions 9 are respectively close to the two sides of the silicon material body, and the width and K value are equal.

[0034] The source region N+ part 1 is made of silicon material, the doping type is N-type, and the doping concentration is 1×10 20 cm -3 , the width and thickness are both 0.75μm; the source region P+ part 2 is made of silicon material, the doping type is P type, and the doping concentration is 1×10 20 cm -3 , length and thickness are both 0.75 μm.

[0035] The silicon body 3 is made of silicon material with a length of 1.5 μm and a thickness of 0.75 μm, and the doping type is P type with a doping concentration of 1×10 17 cm -3 .

[0036] The drain region 6 is made of silicon material with a length of 2 μm and a thickness of 0.75 μm, and the doping type is N-type with a doping concentration of 1×10 20 cm -3 ; The doping type of drift region 4 is N-type, and the doping concentration is 1.2×10 16 cm -3 .

[0037] In this embodiment, the width W of the high-K dielectric region 9 (ie, the dimension along the width direction of the silicon film layer) is 0.6 μm, and the K value is 200; the thickness t of the trench 5 (ie, the dimension along the thickness direction of the silicon film layer) is 11 μm.

[0038] The top layer of the device includes a gate electrode 10, a source electrode 11 and a drain electrode 12; the gate electrode 10 is located on the side of the source region and the silicon body 3 away from the trench 5; the source electrode 11 is located above the source region N+ part 1 and the source region P+ part 2, and the drain electrode 12 is located above the drain region 6. The gate electrode 10 is separated from the source region N+ part 1, the silicon body 3 and the drift region 4 by a gate oxide layer.

[0039] Comparative Example 1 like Figure 3 As shown, a silicon trench LDMOS transistor on insulating layer (CTSOI LDMOS) is shown. The difference between this comparative example and Example 1 is that: no high-K dielectric region 9 is provided on both sides of the silicon material body in the silicon film layer; the thickness of the trench 5 is 9 μm; and the other parameters are consistent with Example 1. According to the test, under the structure of this embodiment, the optimal doping concentration of the drift region 4 is 8×10 14 cm -3 .

[0040] The device length direction is set as the X-axis direction, the device thickness direction is set as the Y-axis direction, and the device width direction is set as the Z-axis direction. Based on the three-dimensional TCAD software simulation, the following experiments are performed to obtain the performance of the LDMOS transistor provided in Example 1 and Comparative Example 1. In the simulation study, the substrate layer 8 is grounded.

[0041] The following is a description of the significant superiority of Example 1 over Comparative Example 1: According to the above parameters, simulation is performed to obtain curves of the electric field on the silicon film layer of the LDMOS transistor provided in Example 1 (DHK TSOI LDMOS) and Comparative Example 1 (CTSOILDMOS) as a function of the lateral position. Figure 4 As shown. Figure 4It can be seen that Example 1 can introduce a higher electric field on the surface of the silicon film layer, effectively improving the lateral withstand voltage of the device, so that it is no longer limited by the lateral breakdown voltage, and instead the breakdown voltage of the device depends on the electric field around the groove.

[0042] The curve comparison of the electric field around the trench of the LDMOS transistor provided by Example 1 (DHK TSOI LDMOS) and Comparative Example 1 (CTSOI LDMOS) as a function of position is shown in FIG. Figure 5 As shown. Figure 5 It can be seen that the presence of high-K dielectric regions 9 on both sides of the silicon material in the silicon film layer of Example 1 can guide the electric flux (i.e., more electric flux flows to the high-K dielectric), making the electric field outside the groove in the silicon film layer more uniform, improving the RESURF effect of the device, and effectively avoiding the device from being broken down prematurely, thereby increasing the breakdown voltage of the device.

[0043] Determination process of the optimal values ​​of each key parameter in Example 1: The drift region doping concentration, trench 5 thickness, and high-K dielectric region 9 width W and K value of the LDMOS transistor provided in Example 1 are changed to study the influence of key parameters on the device's performance such as breakdown voltage, on-resistance and FOM value.

[0044] Figure 6 , Figure 7 and Figure 8 Describe the influence of the width of the high-K dielectric region 9 on both sides of the silicon material of the silicon film layer on the device breakdown voltage, on-resistance and FOM value. At this time, the K value of the high-K dielectric is 200, the thickness of the trench 5 is 11μm, and the other related parameters remain unchanged. In the figure, t HK is the width of the high-K dielectric region 9; when the width of the high-K dielectric region 9 is 0.6 μm, the concentration of the drift region 4 is 8×10 15 cm -3 When the device achieves the highest breakdown voltage of 451.2V and a lower on-resistance. The concentration of drift region 4 is further increased. When the doping concentration of drift region 4 is 1.2×10 16 cm -3 When the breakdown voltage drops slightly, the on-resistance decreases significantly, and the highest FOM value of 11.04MW / cm is obtained. 2 , showing the best overall performance.

[0045] Fig. 9 , Fig.10 and Fig.11Describe the influence of the K value of the high-K dielectric region 9 on both sides of the silicon material of the silicon film layer on the breakdown voltage, on-resistance and FOM value of the device. At this time, the width of the high-K dielectric region 9 is 0.6μm, the thickness of the trench 5 is 11μm, and the other relevant parameters remain unchanged. As can be seen from the figure, as the K value increases, the maximum breakdown voltage of the device first increases and then tends to saturation. At the same time, the optimal doping concentration of the device is also increasing, and it can have a lower on-resistance at this time. Therefore, as the K value of the high-K dielectric increases, the overall performance of the device will continue to improve.

[0046] Fig.12 The effect of the thickness of the device trench 5 on the device breakdown voltage, on-resistance and FOM value is described. At this time, the width of the high-K dielectric region 9 is 0.6μm, the K value is 200, and the doping concentration of the drift region 4 is the optimal doping concentration corresponding to the trench depth. As can be seen from the figure, as the trench thickness increases, the device breakdown voltage first increases and then decreases, and the on-resistance generally shows an upward trend. When the trench thickness is 11μm, the device has the highest FOM value (i.e. the best overall performance)

[0047] Therefore, from Fig.12 It can be seen that when the width of the high-K dielectric region 9 is 0.6 μm, the K value is 200, and the trench thickness is 11 μm, the device has the highest breakdown voltage and the lowest on-resistance. The structure with this parameter setting can show the best performance.

[0048] Fig.13 The figure is a relationship diagram of breakdown voltage and on-resistance comparing Example 1 (DHK TSOI LDMOS) with other devices in the related field, such as MR-LDMOS, SCDT-LDMOS, HKGF-LDMOS, HKMF-LDMOS, and HKT-LDMOS. Fig.13 It can be seen that the design concept of the present invention is superior, and its performance exceeds the traditional Triple RESURF curve. Compared with other devices in the relevant field, it has a higher breakdown voltage and a lower on-resistance, and has more superior performance.

Claims

1. A double-sided high-K dielectric silicon trench LDMOS transistor on an insulating layer, comprising a substrate layer (8), a buried oxide layer (7), a silicon film layer and a device top layer stacked in sequence; characterized in that: High-K dielectric regions (9) are provided on both sides of the silicon material body in the silicon film layer; the two high-K dielectric regions (9) have equal widths and equal K values; the width of the high-K dielectric region (9) is 0.3-0.7 μm; and the K value of the high-K dielectric region (9) is greater than or equal to 50.

2. The double-sided high-K dielectric silicon-on-insulator trench LDMOS transistor according to claim 1, characterized in that: The width of the high-K dielectric region (9) is 0.5-0.6 μm.

3. The double-sided high-K dielectric silicon-on-insulator trench LDMOS transistor according to claim 1, characterized in that: The K value of the high-K dielectric region (9) is 50-200.

4. The double-sided high-K dielectric silicon-on-insulator trench LDMOS transistor according to claim 1, characterized in that: The silicon film layer comprises a source region, a silicon body (3), a drift region (4), a groove (5) and a drain region (6); the drift region (4) is arranged on the top of a buried oxide layer (7); the source region, the groove (5) and the drain region (6) are arranged in sequence on the top of the drift region (4); the source region comprises a source region N+ part (1) and a source region P+ part (2) arranged in parallel; the silicon body (3) is located between the source region and the drift region (4); the source region, the silicon body (3), the drift region (4) and the drain region (6) together constitute the silicon material main body of the silicon film layer.

5. The double-sided high-K dielectric silicon-on-insulator trench LDMOS transistor according to claim 4, characterized in that: The doping type of the drift region (4) is N-type, and the doping concentration is 1×10 15 cm -3 ~1.6×10 16 cm -3 .

6. The double-sided high-K dielectric silicon-on-insulator trench LDMOS transistor according to claim 4, characterized in that: The groove (5) is made of silicon dioxide with a length of 4 μm to 6 μm and a thickness of 8 μm to 11.5 μm.

7. The double-sided high-K dielectric silicon-on-insulator trench LDMOS transistor according to claim 1, characterized in that: The top layer of the device comprises a gate electrode (10), a source electrode (11) and a drain electrode (12); the gate electrode (10) is located on the side of the source region and the silicon body (3) facing away from the groove (5); the source electrode (11) is located above the source region, and the drain electrode (12) is located above the drain region (6).

8. The double-sided high-K dielectric silicon-on-insulator trench LDMOS transistor according to claim 1, characterized in that: The silicon film layer has a length of 7 μm to 9 μm, a width of 1 μm to 2 μm, and a thickness of 9 μm to 12 μm.

9. The double-sided high-K dielectric silicon-on-insulator trench LDMOS transistor according to claim 1, characterized in that: The buried oxide layer (7) is made of silicon dioxide with a thickness of 2 μm to 4 μm.

10. The double-sided high-K dielectric silicon-on-insulator trench LDMOS transistor according to claim 1, characterized in that: The doping type of the substrate layer (8) is P type, and the doping concentration is 1×10 14 cm -3 ~1×10 15 cm -3 of silicon material.

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