High-speed TDI image sensor pixel unit and image sensor

Abstract

The invention relates to the technical field of semiconductor image sensors, in particular to a high-speed TDI image sensor pixel unit and an image sensor, the pixel unit is composed of a polysilicon gate, a buried channel and a photodiode, the active region of the photodiode is trapezoidal, the long bottom edge of the trapezoidal active region is connected with the buried channel, the active region comprises multiple stages of n-type injection regions, and the n-type injection regions are connected with the buried channel. And built-in potentials are sequentially decreased from the buried channel injection region to the short bottom edge of the trapezoidal active region. According to the TDI image sensor pixel unit, the clamping photodiode is additionally arranged on a traditional TDI image sensor pixel unit, and the photodiode adopts a combined design of a trapezoid and a multi-stage n-type injection region, so that the potential is gradually increased towards a polysilicon gate in a stepped manner, the flowing speed of charges to the polysilicon gate is increased, the flowing time is shortened, and on the premise that power consumption is not increased, the photoelectric conversion efficiency is improved. The method can be applied to high-speed scenes. The image sensor is designed based on the pixel units, so that the power consumption can be effectively reduced, the information acquisition speed is improved, and the image aliasing problem is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor image sensors, and specifically provides a high-speed TDI image sensor pixel unit and an image sensor based on a CMOS process and with expandable size. Background Art

[0002] Linear array image sensors are usually used in areas that require high-speed imaging, such as industrial inspection, high-speed moving object inspection, assembly line product inspection, etc. They have a simple structure and low cost. Usually, a linear array image sensor has only one row of photosensitive pixels, and each exposure can only capture one line in the scene, requiring continuous scanning to obtain a complete two-dimensional image. However, in high-speed inspection applications, objects move too fast, the exposure time is short, and the effective signal is small, resulting in a low signal-to-noise ratio. Even increasing the light intensity cannot make up for the loss of signal-to-noise ratio.

[0003] In order to increase the signal-to-noise ratio of the linear array image sensor, it is necessary to increase the exposure time of high-speed moving objects and enhance the signal response capability. CMOS TDI (time delay integration) image sensor pixels can be used. There are multiple rows of pixels in the TDI pixel array, and a time delay is introduced between each row of pixels, so that the exposure of the pixels row by row is synchronized with the movement of the object. Each line of the object is integrated row by row, which can effectively improve the signal-to-noise ratio of the image sensor. Unlike the inter-row transfer CCD pixels in traditional CCD image sensors, traditional CCD image sensors use a photodiode and multiple polysilicon gates to achieve global exposure. The photodiode of the inter-row transfer CCD pixel is only used to collect exposure signals and cannot perform continuous signal transfer (otherwise, it will alias the signals normally stored and read out in the previous frame), while the polysilicon gate is only used to store and transfer the previous frame signal. After the exposure is completed, the signal collected by the photodiode needs to be completely horizontally transferred to the polysilicon gate at one time. This transfer is only performed once in one imaging. This process cannot achieve the requirement of synchronous vertical charge transfer and object movement in TDI, so the TDI function cannot be realized. In addition, after the inter-row transfer CCD completes the transfer, its photodiode exposes the next frame. After receiving the valid signal, the polysilicon gate stores and reads. In this process, the signal collected by the polysilicon gate itself is a parasitic signal. Therefore, it is necessary to strictly avoid the polysilicon gate from collecting signals, otherwise the stored and read signals will be aliased. Therefore, the polysilicon gate is required to be strictly shielded from light. The usual practice is to perform metal shielding on the polysilicon gate, which also makes the quantum efficiency of the general inter-row transfer CCD pixel low.

[0004] The current advanced TDI image sensors all use standard CMOS technology, which can achieve high line rates and integrate high-speed drive circuits and readout circuits on-chip. CMOS TDI pixels are usually composed of some polysilicon gate units such as Figure 1As shown. Reasonable polysilicon gate spacing and injection conditions are designed to achieve efficient charge transfer in the vertical direction. In TDI operation, the drive circuit generates a high-speed clock drive signal, which acts on each phase of the polysilicon gate. In high-speed applications, the clock signal needs to be established quickly. However, the gate capacitance introduced by the polysilicon gate is large, and the drive current is usually increased to ensure that the clock signal of each phase is established normally. Therefore, high-speed TDI image sensors usually have large power consumption, which affects the cost of the imaging system. Summary of the invention

[0005] In order to solve the above problems, the present invention provides a high-speed TDI image sensor pixel unit, which adopts a multi-stage trapezoidal injection region structure to increase the built-in potential of the photodiode toward the polysilicon gate, which can effectively increase the electric field strength of the charge flowing to the polysilicon gate, thereby increasing the speed of the charge flowing to the polysilicon gate in the photodiode, and can achieve a higher-speed TDI operation without increasing the driving current, which is beneficial to the ultra-high-speed and low-power application of the image sensor. And by expanding the size and arranging and combining the pixel unit, TDI pixels of different sizes can be realized. Compared with the traditional TDI image sensor pixels, the pixels using this pixel unit are more suitable for high-speed and low-power applications.

[0006] On the one hand, the high-speed TDI image sensor pixel unit provided by the present invention comprises: a polysilicon gate and a buried channel, and a photodiode arranged in a horizontal direction with the buried channel, wherein the buried channel is arranged below the polysilicon gate; the active region of the photodiode is a trapezoid, and the long bottom side of the trapezoidal active region is connected to the buried channel, and a P-well region for isolating adjacent pixel units is arranged around the active region; The active area includes an n-type implantation area distributed along the height direction of the trapezoid, the built-in potential of the buried channel is higher than the built-in potential of the n-type implantation area of ​​the active area, and the potential at the long bottom side of the trapezoidal active area is higher than the potential at the short bottom side.

[0007] Preferably, the buried channel includes a zeroth n-type implantation region and a zeroth p-type implantation region, and the zeroth p-type implantation region is disposed on an upper surface of the zeroth n-type implantation region.

[0008] Preferably, the active region includes at least two n-type implantation regions distributed along the height direction of the trapezoid and whose built-in potential decreases successively from the long bottom side to the short bottom side of the trapezoidal active region.

[0009] Preferably, the active region includes an n-type implantation region distributed along the height direction of the trapezoid.

[0010] Preferably, the n-type implantation region of the active region and the zeroth n-type implantation region of the buried channel are designed as one piece.

[0011] Preferably, in the active region, different n-type implantation regions have the same length along the height direction of the trapezoid; or in the active region, at least two n-type implantation regions have unequal lengths along the height direction of the trapezoid.

[0012] Preferably, the active region of the photodiode is an isosceles trapezoid.

[0013] Preferably, a p-type injection region is provided above the n-type injection region of the active region, and the built-in potential can be changed by adjusting the injection conditions of the p-type injection region and / or the n-type injection region.

[0014] Preferably, the number of n-type injection regions and p-type injection regions in the active region is the same, and their relative positions are in one-to-one correspondence; or the number of n-type injection regions and p-type injection regions in the active region is different, and their relative positions are not in one-to-one correspondence.

[0015] Preferably, along the height direction of the trapezoid, the length of the polysilicon gate is less than half of the length of the pixel unit.

[0016] Preferably, the built-in potential gradient of the n-type implanted region of the buried channel and the active region needs to satisfy the following requirement: the time for the charges to flow horizontally from the short bottom side of the trapezoidal active region to the buried channel is less than one tenth of the time for the charges to flow vertically from the buried channel to the polysilicon gate.

[0017] Preferably, an anti-overflow structure is further included, the anti-overflow structure includes an anti-overflow gate and an anti-overflow drain, and the anti-overflow structure is provided on one side or both sides of the n-type injection region with the highest potential of the photodiode.

[0018] Preferably, two symmetrical photodiodes are provided on both sides of the buried channel.

[0019] In another aspect, an image sensor is provided with a high-speed TDI image sensor pixel unit.

[0020] Compared with the prior art, the present invention can achieve the following beneficial effects: The present invention adds a photodiode to the pixel unit of the CMOS TDI image sensor, reduces the area of ​​the polysilicon gate, reduces the gate capacitance, and improves the clock driving capability of the TDI gate driving circuit, so that faster TDI charge transfer can be achieved under the same power consumption, that is, the line frequency of the linear array is improved; or in other words, the power consumption is greatly reduced under the same line frequency application; in addition, the photodiode adopts a combination design of a trapezoidal and multi-level n-type injection area, which produces a step-like increasing potential change toward the polysilicon gate, improves the potential inclination toward the polysilicon gate, and can quickly transfer the charge collected by the photodiode to the polysilicon gate, ensuring that the introduction of the photodiode will not cause image aliasing problems, and can achieve low power consumption and high-speed applications without increasing the driving current.

[0021] The present invention designs a multi-level p-type injection area corresponding to the multi-level n-type injection area, improves the adjustment accuracy of the built-in potential, avoids the problems of signal retention and pixel full well, facilitates the rapid and continuous flow of TDI charges, facilitates speed matching with moving objects, and realizes good TDI function in high-altitude applications. In addition, since the edge effect will be generated at the junction of the photodiode and the P-well area, reducing the built-in potential of the photodiode, it is also possible to adjust the length of the short bottom side of the trapezoidal active area, that is, adjust the short bottom side angle of the trapezoidal active area. The narrower the short bottom side of the trapezoidal active area, the greater the proportion of edge effect, the more the potential is reduced, and the potential can be further tilted toward the polysilicon gate.

[0022] The pixel unit in the present invention can be expanded in size and different pixel units can be arranged and combined to realize TDI pixels of different sizes. Compared with traditional TDI image sensor pixels, the structural design is simpler, the performance is better, and the flexibility is higher.

[0023] The present invention adds an anti-overflow structure according to application requirements, thereby effectively improving the anti-overflow capability of pixels.

[0024] Under the condition of keeping the pixel unit length unchanged, the present invention can respectively set photodiodes on both sides of the polysilicon gate, reduce the length of the single-sided photodiode, shorten the single-sided charge horizontal flow distance, and reduce the flow time, which is conducive to realizing higher-speed TDI operation and greatly improves the anti-signal aliasing capability of large-size pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of the structure of a traditional TDI pixel in the background art; Figure 2 is a horizontal cross-sectional top view of a pixel unit of a high-speed TDI image sensor provided in Embodiment 1 of the present invention; Figure 3 According to the embodiment 1 of the present invention, Figure 2 middle Cross-sectional view of a high-speed TDI image sensor pixel unit; Figure 4 According to the embodiment 1 of the present invention, Figure 2 middle Cross-sectional view of a high-speed TDI image sensor pixel unit; Figure 5 According to the embodiment 1 of the present invention, Figure 2 middle Cross-sectional view of a high-speed TDI image sensor pixel unit; Figure 6 is a potential comparison diagram of a design using only a trapezoidal active region or a multi-level injection region and a design using both a trapezoidal active region and a multi-level injection region according to Embodiment 1 of the present invention; Figure 7 is a schematic diagram of a charge collection and transfer path provided according to Example 1 of the present invention; Figure 8 is a schematic diagram of pixel unit size expansion provided according to Embodiment 2 of the present invention; Fig. 9 is a schematic structural diagram of a high-speed TDI image sensor pixel unit with an anti-overflow structure provided according to Embodiment 3 of the present invention; Fig.10 is a schematic structural diagram of a high-speed TDI image sensor pixel unit with dual photodiodes provided according to Embodiment 4 of the present invention; Fig.11 A high-speed TDI image sensor pixel unit and a step-shaped potential gradient change diagram provided according to Embodiment 5 of the present invention; Fig.12 is a design diagram of a pixel structure of 5 micrometers×5 micrometers provided according to Example 6 of the present invention; Fig.13 is a design diagram of a 6 micron×6 micron pixel structure provided according to Example 7 of the present invention; Fig.14 This is a design diagram of a 10 micron×10 micron pixel structure provided according to Example 8 of the present invention.

[0026] Reference numerals include: Polysilicon gate 1, buried channel 2, photodiode 3, photodiode , P-well region 4, gate oxide insulating layer 5, substrate 6, anti-overflow drain 7, and anti-overflow gate 8. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same modules are represented by the same reference numerals. In the case of the same reference numerals, their names and functions are also the same. Therefore, the detailed description thereof will not be repeated.

[0028] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation of the present invention.

[0029] Embodiment 1: like Figure 1As shown, conventional TDI pixels are usually composed of only polysilicon gate units, which are relatively long and have high gate capacitance, and thus cannot be used in low-power and high-speed applications. Embodiment 1 of the present invention adds a photodiode to the conventional TDI pixel unit, wherein one polysilicon gate 1 corresponds to one photodiode 3, and the polysilicon gate 1 and the photodiode 3 are used to continuously collect and transfer charges, thereby reducing the size of the polysilicon gate and facilitating applications in low-power and high-speed scenarios. Figure 2 , Figure 3 , Figure 4 and Figure 5 As shown, the high-speed TDI image sensor pixel unit provided by Embodiment 1 of the present invention includes: a polysilicon gate 1, a buried channel 2, a photodiode 3, a P-well region 4 and a gate oxide insulating layer 5 prepared on a substrate 6 by a semiconductor processing technology, wherein the buried channel 2 is arranged below the polysilicon gate 1, and the photodiode 3 is arranged in the same layer as the buried channel 2 in the horizontal direction.

[0030] The buried channel 2 below the polysilicon gate 1 has an appropriately implanted n-type implant region and a p-type implant region, namely, the zeroth n-type implant region and the zeroth p-type implant region, which are respectively denoted as n and p. <0> and p <0> , p <0> Set in n <0> The upper surface of <0> and p <0> The injection conditions need to be met: the built-in potential of the buried channel 2 is higher than the built-in potential of other injection areas in the pixel unit, and the built-in potential of the buried channel 2 is greater than the built-in potential of any injection area of ​​the photodiode 3, that is, the potential at the long bottom side of the trapezoidal active area is higher than the potential at the short bottom side. This design can firstly ensure that the signal charge collected by the photodiode 3 can continue to flow to the buried channel 2; secondly, it can collect the signal charge near the potential well under the polysilicon gate 1; and thirdly, all the charges received in the buried channel 2 are transferred in the vertical direction by TDI signals.

[0031] The active area of ​​the photodiode 3 is an isosceles trapezoid, the short bottom side of the trapezoidal active area is far away from the polysilicon gate 1, and the long bottom side is close to the polysilicon gate 1, that is, the long bottom side of the trapezoidal active area is connected to the buried channel 2. The direction of the trapezoidal active area along the height of the trapezoid is defined as the length of the active area, and the direction perpendicular to the height of the trapezoid is defined as the width of the active area. The photodiode 3 is a clamped photodiode, and the area outside the trapezoidal active area is a heavily doped P-well area 4. The P-well area 4 can isolate adjacent pixel units, and the junction between the active area and the P-well area 4 will produce an edge effect, which can reduce the built-in potential of the photodiode 3. The narrower the width of the active area, the greater the proportion of the edge effect, so the more the built-in potential is reduced. Designing the active area as a trapezoid can make the built-in potential of the photodiode 3 tilt toward the polysilicon gate 1 side.

[0032] The active region of the photodiode 3 adopts a multi-level n-type injection region design. Along the length direction of the active region, starting from the long bottom side of the trapezoid close to the buried channel 2 to the short bottom side of the trapezoid active region, different n-type injection regions are sequentially denoted as n <1> , n <2> ,…,n <n-1> ，n <n>, N≥2. The length of the n-type injection region in the active area along the height of the trapezoid is defined as the length of the n-type injection region. The length of each n-type injection region can be equal or unequal, the lengths of all n-type injection regions can be unequal, or the lengths of at least two n-type injection regions can be unequal. By controlling the injection conditions such as the injection energy, dose and angle of different injection regions, the built-in potential of different injection regions can be adjusted. The n-type injection region from the buried channel 2 to the short bottom side of the trapezoidal active region is <n>, the built-in potential decreases successively, that is: n <0> The potential of <1> The potential of <2> The potential of>,…,>n <n-1>The potential of <n>The potential design requirement can ensure that the charges collected by the photodiode 3 flow quickly and continuously to the buried channel 2, and vertical TDI charge transfer is performed from the buried channel 2 to the polysilicon gate 1.

[0033] As a preferred embodiment, the active region may also be designed as a single-stage n-type implant region, that is, the trapezoidal region of the active region is designed as an n-type implant region. <0> The n-type injection region is designed as a whole with the active region to form an n-type injection region with the same overall injection conditions. At this time, the potential tilt is achieved only through the trapezoidal design of the active region.

[0034] In addition, there is p-type implantation on the silicon-based surface of the n-type implantation region of the photodiode 3, that is, a p-type implantation region is provided above the n-type implantation region, and the number of p-type implantation regions can be the same as the number of n-type implantation regions, and the size and position correspond one to one; in addition, the number of p-type implantation regions can also be designed to be different from the number of n-type implantation regions. In this case, the p-type implantation region and the n-type implantation region are not one-to-one corresponding structures, that is, the position and size of an n-type implantation region correspond to the overall size and position of multiple p-type implantation regions; or the position and size of multiple n-type implantation regions correspond to the overall size and position of different numbers of p-type implantation regions. With the design of the n-type implantation region, along the length direction of the active region, starting from the long bottom side of the trapezoid close to the buried channel 2 to the short bottom side of the trapezoidal active region, the different p-type implantation regions are sequentially recorded as p <1> , p <2> ,…,p <n-1> ，p <n>. The p-type injection region can prevent the silicon-based surface defects of the photodiode 3 from affecting charge collection and optimize the dark current. In addition, by adjusting the injection conditions of the p-type injection region, the size and distribution of the step-shaped built-in potential of the photodiode 3 and the potential difference between adjacent injection regions can also be controlled. The n-type injection region and the p-type injection region of the photodiode 3 can be adjusted together to change the built-in potential, or the injection conditions of the n-type injection region or the p-type injection region can be adjusted separately. The flexibility and accuracy of the step-shaped potential adjustment can be improved by the n-type injection region and the p-type injection region. In addition, a gate oxide insulating layer 5 is also provided on the upper surface of the p-type injection region to protect the photodiode 3.

[0035] like Figure 6 As shown, in order to meet the requirements of high-speed applications, the photodiode 3 adopts a combination design of a trapezoidal active region and a multi-level injection region, which can effectively increase the potential difference between adjacent injection regions and thus increase the n of the buried channel 2. <0> To photodiode 3 n <n>The potential difference between the two regions increases the built-in potential toward the polysilicon gate 1. Compared with only using a trapezoidal active area or a multi-level injection area or a traditional design, the combined design of the present invention can increase the potential change, and the effect of increasing the built-in potential toward the polysilicon gate 1 is more obvious. The increase in the built-in potential can effectively increase the electric field strength of the charge flowing to the polysilicon gate 1, thereby increasing the speed at which the charge in the photodiode 3 flows to the polysilicon gate 1, so that the TDI can work normally without signal retention, avoiding the problem of image aliasing in high-speed application scenarios. During the operation of the TDI pixel unit, the charge collected by the photodiode of the current pixel unit is transferred to the next pixel unit through the polysilicon gate 1 under the drive of the clock signal, thereby realizing the sequential accumulation of signals. However, if the combination design of trapezoidal active area and multi-level injection area is not adopted, the charge collection and flow speed in the TDI pixel unit cannot match the high-speed movement of the object, and the charge transfer speed cannot keep up with the clock drive speed, that is, the charge has not had time to be completely transferred to the polysilicon gate 1 of the current pixel unit, and the new signal charge has begun to form and transfer in the photodiode 3, which will cause signal retention. The new signal charge will be mixed with the residual signal charge of the previous stage, resulting in image signal distortion. This distortion will reduce the clarity and quality of the image and affect the dynamic modulation transfer function of the TDI image sensor.

[0036] like Figure 7 As shown, the embodiment of the present invention adds a photodiode 3 on the basis of the traditional TDI pixel unit, and can collect charges simultaneously through the buried channel 2 under the polysilicon gate 1 and the photodiode 3, thereby reducing the size of the polysilicon gate 1, and further reducing the gate capacitance of the polysilicon gate 1. In the horizontal flow process of the charge from the photodiode 3 to the buried channel 2, with the help of the stepped inclined built-in potential, the charge collected by the photodiode 3 can be quickly flowed to the buried channel 2. In the vertical direction, the charge flows vertically in the buried channels 2 under different polysilicon gates 1, and the entire charge collection and transfer process is continuous and fast, which can effectively match the speed of the moving object and achieve a good TDI function.

[0037] The above-mentioned high-speed TDI image sensor pixel unit can be applied to prepare a CMOS TDI image sensor. The sensor is prepared by superimposing pixel units. The pixel units in the sensor can be prepared by a back-illuminated process. Since the polysilicon gate 1 and the photodiode 3 both need to collect charges during the working process, no metal shielding is used on the back-illuminated surfaces of the polysilicon gate 1 and the photodiode 3, so that the light signal can be received to the maximum extent. The back-illuminated design and the strategy of no metal shielding can significantly improve the quantum efficiency. High quantum efficiency means that more incident photons are converted into charges, thereby improving the sensitivity and dynamic range of the image sensor.

[0038] Embodiment 2: On the basis of Example 1, the dimensions of the TDI pixel unit of the present invention in the length direction and the width direction can be expanded later. First, for the length dimension of the TDI pixel unit, the number of injection regions can be increased or decreased without changing the length of each injection region in the active area of ​​the photodiode 3, that is, the length expansion of the TDI pixel unit is achieved. The length of the TDI pixel unit will affect the charge flow time. Therefore, the length of the TDI pixel unit should not be too long. If the length of the TDI pixel unit is too long, signal retention problems may occur. In addition, the length of the TDI pixel unit will also affect the potential gradient of the adjacent injection region. When the potential difference between the adjacent injection regions in the photodiode 3 is too large, the potential difference of the buried channel 2 under the polysilicon gate 1 will be reduced, thereby reducing the full well capacity of the pixel. Reducing the full well capacity means that the pixel unit may not be able to store enough charge, resulting in a limited dynamic range of the image. Therefore, it is necessary to balance the built-in potential gradient of the n-type implanted region of the buried channel 2 and the active region, as well as the length of the short bottom side of the trapezoidal active region, to ensure that the built-in potential gradient achieves the optimal effect, that is, it does not affect the effective signal storage potential difference under the polysilicon gate 1, and at the same time, the time for the charge at the far end of the photodiode 3 to flow to the polysilicon gate 1 is short enough. Therefore, in the design process of the multi-level n-type implanted region and the trapezoidal active region, it is necessary to make the time for the charge to flow horizontally from the short bottom side of the trapezoidal active region to the buried channel 2 less than one tenth of the time for the charge to flow vertically from the buried channel 2 to the polysilicon gate 1. Figure 8 As shown, in order to facilitate the subsequent description, different n-type implant regions n <1> , n <2> ,…,n <n-1> ，n <n>The length is represented as A1, A2, ..., An-1, An, the total length of all n-type implanted regions is represented as Xn, the length of polysilicon gate 1 is represented as X, and the width of polysilicon gate 1 is represented as Y. Several continuous or discontinuous n-type implanted regions can be arbitrarily selected to form a new active area. When all the above conditions are met, a new scheme with variable pixel size in the length direction can be realized. For example, if A1, A2 and A3 are selected, the horizontal pixel size is (X+A1+A2+A3); if A2, A4 and A6 are selected, the horizontal pixel size is (X+A2+A4+A6).

[0039] For the width dimension of the TDI pixel unit, the width design of the polysilicon gate 1 needs to consider the compromise between the charge transfer efficiency and the full well. Generally, the narrower the polysilicon gate 1, the higher the charge transfer efficiency. However, a too narrow polysilicon gate 1 will result in reduced signal storage capacity and reduced full well capacity. In general, the width of the polysilicon gate 1 in the CMOS-TDI process is between 1 and 3 microns, which can achieve good charge transfer efficiency while taking into account the full well capacity requirements. The width Y of the polysilicon gate 1 needs to be simulated and experimentally verified according to the requirements, and appropriate polysilicon gate 1 and buried channel 2 width parameters are designed to ensure good charge transfer efficiency. Preferably, the charge transfer efficiency is greater than 0.9999. Based on the obtained width Y, the size of the photodiode 3 can be designed.

[0040] In addition, pixel units of the same width can be combined and superimposed. The polysilicon gate 1 in each pixel unit corresponds to a clock phase of the TDI pixel. Each TDI pixel can include multiple superimposed pixel units. For example, the superimposed width of 2 pixel units is 2Y, the superimposed width of 3 pixel units is 3Y, ..., and the superimposed width of m pixel units is mY.

[0041] Embodiment 3: On the basis of Example 1, Fig. 9 As shown, an anti-overflow structure can be added according to the application requirements to improve the pixel anti-overflow capability. When designing a TDI image sensor, the location selection of the anti-overflow structure is crucial to ensure the performance of the sensor. Since the pixel unit of the present invention adopts a trapezoidal active area and a multi-level injection area design, resulting in a tilted potential of the photodiode 3 toward the buried channel 2, the anti-overflow structure should not be placed in the low potential area at the far end of the photodiode 3, which will hinder its effective anti-overflow function; on the contrary, the anti-overflow structure should be placed on the side of the photodiode 3 with the highest potential, that is, close to the polysilicon gate 1 and the buried channel 2. This can optimize the collection and transfer of charges, reduce signal retention, and improve the dynamic modulation transfer function level of the pixel unit. Specifically, the anti-overflow structure includes an anti-overflow drain 7 and an anti-overflow gate 8. The anti-overflow structure can be set on one or both sides of the n-type injection area with the highest potential of the photodiode 3, or the anti-overflow structure can be set on one or both sides of the zeroth n-type injection area.

[0042] Embodiment 4: On the basis of Example 1, Fig.10 As shown, not only can a photodiode 3 be provided on one side of the buried channel 2, but a symmetrical photodiode 3 can also be provided on the other side of the buried channel 2. , photodiode 3 and photodiode Symmetrical about the buried channel 2. Specifically, additional photodiodes can be provided without changing the length of the photodiode 3. ; The total length of the charge collection region can also be evenly distributed to the photodiode 3 and the photodiode , that is, reducing the photodiode 3 and photodiode on one side of the buried channel 2 The length of this design can effectively shorten the charge on the single-side photodiode 3 and the photodiode The charge flows through the buried channel 2 under the polysilicon gate 1, thereby reducing the charge flow time, meeting higher-speed TDI operation, and being beneficial to the ultra-high-speed application of high-speed TDI image sensor pixel units.

[0043] Embodiment 5: On the basis of Example 1, Fig.11 As shown, Embodiment 5 of the present invention shows a 1 micron × 10 micron pixel unit, the width of the polysilicon gate 1 and the long bottom side of the active region of the photodiode 3 are both 1 micron, the short bottom side of the active region of the photodiode 3 is 0.5 micron, the length of the polysilicon gate 1 and the buried channel 2 are both 2 microns, and a total of 8 n-type injection regions are designed in the active region of the photodiode 3, and the length of each n-type injection region is equal, all 1 micron, that is, A1=A2=…=A7=A8. By adjusting the injection concentration of each n-type injection region, the potential of each n-type injection region increases from 0.6V at the farthest end to 2.0V at the buried channel 2. The potential under the polysilicon gate 1 is 3V at a high gate voltage and 2.2V at a low gate voltage. Through simulation verification, it is shown that when TDI operation is performed, the charge flow path is unobstructed, the flow time for the charge to flow from the farthest n-type injection region to the buried channel 2 is 100 nanoseconds, the time for the vertical TDI transfer from the buried channel 2 to the polysilicon gate 1 is 1 microsecond, and the time for the charge collected by the photodiode 3 to continue flowing to the buried channel 2 is less than 1 / 10 of the vertical transfer time, and the design is optimized.

[0044] Embodiment 6: On the basis of Example 5, Fig.12 As shown, Embodiment 6 of the present invention shows a 5 micron × 5 micron pixel, using 5 pixel units to be stacked side by side along the width direction, each pixel unit corresponds to 1 phase, and the charge transfer of different polysilicon gates 1 is realized by controlling the timing of the 5 phases. Adjacent pixel units are isolated by the P well region 4, the length of the polysilicon gate 1 and the buried channel 2 are both 2 microns, and the width of the polysilicon gate 1 and the long bottom side of the active area of ​​the photodiode 3 are both 1 micron. In the length direction of the photodiode 3, select Fig.10 The n-type injection regions with medium widths numbered A1, A3 and A5, and the active region length of the photodiode 3 are 3 microns. The 5 micron × 5 micron pixel can directly meet the requirement of continuous and rapid charge flow for a short time, without the need for additional simulation optimization, simplifying the design complexity, and can be quickly integrated into the pixel array of the new pixel, with low power consumption and good performance.

[0045] Embodiment 7: On the basis of Example 5, Fig.13 As shown, Embodiment 7 of the present invention shows a 6 micron × 6 micron pixel, using 6 pixel units to be stacked side by side along the width direction, each pixel unit corresponds to 1 phase, and the charge transfer of different polysilicon gates 1 is realized by controlling the timing of the 6 phases. Adjacent pixel units are isolated by the P well region 4, the length of the polysilicon gate 1 and the buried channel 2 are both 2 microns, and the width of the polysilicon gate 1 and the long bottom side of the active area of ​​the photodiode 3 are both 1 micron. In the length direction of the photodiode 3, select Fig.10 The active area length of the photodiode 3 is 4 microns in the n-type injection region with the width numbered A1, A2, A3 and A5. At the same time, an anti-overflow structure is added to the position of the n-type injection region with the width numbered A1 near the polysilicon gate 1 and the buried channel 2, and an anti-overflow structure is set on both sides of the photodiode 3, which can effectively improve the anti-overflow ability of the pixel. The 6 micron × 6 micron pixel can directly meet the requirement of continuous and rapid flow of charge for a short time, without the need for additional simulation optimization, simplifying the design complexity, and can be quickly integrated into the pixel array of the new pixel, with low power consumption and good performance.

[0046] Embodiment 8: On the basis of Example 7, Fig.14 As shown, Embodiment 8 of the present invention shows a 10 micron × 10 micron pixel, using 10 pixel units to be stacked side by side along the width direction, and every 2 pixel units correspond to 1 phase, that is, each phase controls the charge transfer of two polysilicon gates 1. The number of phases in the pixel is less than the number of polysilicon gates 1, which can save the area of ​​the phase control circuit and simplify the design complexity. By controlling the timing of the 5 phases, the charge transfer of different polysilicon gates 1 is realized. Photodiodes 3 and photodiodes 4 are symmetrically arranged on both sides of each polysilicon gate 1. , in order to shorten the distance of charge horizontal flow and improve the anti-signal aliasing capability of large-size pixels. Adjacent pixel units are isolated by P-well region 4. The length of polysilicon gate 1 and buried channel 2 are both 2 microns, and the width of polysilicon gate 1 and the long bottom side of active area of ​​photodiode 3 are both 1 micron. In the length direction, select Fig.10 The n-type implanted regions with widths numbered A1, A2, A3, and A5, photodiode 3, and photodiode The active area length of the 10 micron × 10 micron pixel can directly meet the requirement of continuous and rapid charge flow for a short time, without the need for additional simulation optimization, simplifying the design complexity, and can be quickly integrated into the pixel array of the new pixel, with low power consumption and good performance.

[0047] Although the embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limiting the present invention. Those skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

[0048] The above specific implementations of the present invention do not constitute a limitation on the protection scope of the present invention. Any other corresponding changes and modifications made based on the technical concept of the present invention should be included in the protection scope of the claims of the present invention.< / n> < / n-1> < / n> < / n> < / n-1> < / n> < / n> < / n> < / n-1>

Claims

1. A high-speed TDI image sensor pixel unit, comprising: A polysilicon gate and a buried channel, wherein the buried channel is arranged below the polysilicon gate, and is characterized in that it also includes a photodiode arranged in a horizontal direction with the buried channel, the active area of ​​the photodiode is trapezoidal, and the long bottom side of the trapezoidal active area is connected to the buried channel, and a P well area for isolating adjacent pixel units is provided around the active area; The active area includes an n-type implantation area distributed along the height direction of the trapezoid. The built-in potential of the buried channel is higher than that of the n-type implantation area of ​​the active area. The potential at the long bottom side of the trapezoidal active area is higher than that at the short bottom side.

2. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: The buried channel includes a zeroth n-type implantation region and a zeroth p-type implantation region, and the zeroth p-type implantation region is arranged on an upper surface of the zeroth n-type implantation region.

3. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: The active area includes at least two n-type implantation areas distributed along the height direction of the trapezoid, and the built-in potential decreases from the long bottom side to the short bottom side of the trapezoidal active area.

4. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: The active region includes an n-type implantation region distributed along the height direction of the trapezoid.

5. The high-speed TDI image sensor pixel unit according to claim 2, characterized in that: The n-type implantation region of the active region and the zeroth n-type implantation region of the buried channel are designed as one body.

6. The high-speed TDI image sensor pixel unit according to claim 3, characterized in that: In the active region, different n-type implantation regions have the same length along the height direction of the trapezoid; or in the active region, at least two n-type implantation regions have unequal lengths along the height direction of the trapezoid.

7. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: The active area of ​​the photodiode is an isosceles trapezoid.

8. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: A p-type injection region is provided above the n-type injection region of the active region, and the built-in potential can be changed by adjusting the injection conditions of the p-type injection region and / or the n-type injection region.

9. The high-speed TDI image sensor pixel unit according to claim 3, characterized in that: The number of n-type implantation regions and p-type implantation regions in the active region is the same, and their relative positions correspond to each other; or the number of n-type implantation regions and p-type implantation regions in the active region is different, and their relative positions are not in a one-to-one correspondence.

10. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: In the height direction of the trapezoid, the length of the polysilicon gate is less than half of the length of the pixel unit.

11. The high-speed TDI image sensor pixel unit according to claim 3, characterized in that: The built-in potential gradient of the n-type implanted region of the buried channel and the active region must satisfy the following requirement: the time for the charge to flow horizontally from the short bottom side of the trapezoidal active region to the buried channel is less than one tenth of the time for the charge to flow vertically from the buried channel to the polysilicon gate.

12. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: It also includes an anti-overflow structure, which includes an anti-overflow gate and an anti-overflow drain. The anti-overflow structure is provided on one side or both sides of the n-type injection region with the highest potential of the photodiode.

13. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: Two symmetrical photodiodes are arranged on both sides of the buried channel.

14. An image sensor, characterized in that: A high-speed TDI image sensor pixel unit as claimed in any one of claims 1 to 13 is provided.

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