Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention relates to a solar cell, a preparation method thereof and a photovoltaic module. The preparation method of the solar cell comprises the steps that a semiconductor substrate is provided, the semiconductor substrate is provided with a first face and a second face which are opposite, and the first face is provided with a first area and a second area; grooving is carried out on the first area; forming a first conductive layer in the first region, and forming a dielectric layer in the second region; forming a first electrode on one side, deviating from the semiconductor substrate, of the first conductive layer through an electroplating process; and removing the dielectric layer. The method can be used for reducing the production cost.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] Metallization is one of the important links in the production of solar cells. Through contact and non-contact technology, metallized electrodes are prepared on the front and back of solar cells to form a close and efficient ohmic contact between the electrodes and the cells, and to guide the photogenerated carriers out of the cells. Metallization affects the production cost and conversion efficiency of cells, and ultimately affects the choice of future battery paths.

[0003] Copper electroplating technology is a non-contact metallization technology. Copper is used to replace all metal silver pastes, which fundamentally solves the problem of high material costs. At the same time, copper electroplating can achieve double-sided metallization at the same time, thereby improving production efficiency.

[0004] However, the current electroplating technology requires the introduction of more equipment and materials, resulting in the cost reduction advantage of copper electroplating technology almost disappearing. Summary of the invention

[0005] Based on this, the present application provides a solar cell and a method for preparing the same, and a photovoltaic module, for reducing production costs.

[0006] In a first aspect, the present application provides a method for preparing a solar cell, comprising:

[0007] Providing a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to each other, the first surface having a first region and a second region;

[0008] Grooving the first area;

[0009] forming a first conductive layer in the first region and forming a dielectric layer in the second region;

[0010] forming a first electrode on a side of the first conductive layer facing away from the semiconductor substrate by an electroplating process;

[0011] The dielectric layer is removed.

[0012] In one embodiment, forming a first conductive layer in a first region and forming a dielectric layer in a second region comprises:

[0013] Forming a first conductive film layer on the first surface of the semiconductor substrate, wherein along the thickness direction of the semiconductor substrate, the orthographic projection of the first conductive film layer on the first surface covers the first region and the second region;

[0014] In the first solution system, the second region is laser treated and assisted by ultrasonic vibration, so that the first conductive film layer located in the first region includes the first conductive layer, and at least part of the first conductive film layer located in the second region includes the dielectric layer.

[0015] In one embodiment, the pH value of the first solution system ranges from 3 to 5;

[0016] And / or, the laser irradiation power of the laser treatment is in the range of 0.03 J / cm 2 ~0.07J / cm 2 ;

[0017] and / or, the laser spot overlap ratio ranges from 2% to 7%;

[0018] And / or, the ultrasonic frequency range of the ultrasonic oscillation is 40KHz~70KHz.

[0019] In one embodiment, in the first solution system, the first conductive film layer located in the second region is subjected to laser processing and assisted by ultrasonic vibration, so that the first conductive film layer located in the first region includes the first conductive layer, and at least part of the first conductive film layer located in the second region includes the dielectric layer including:

[0020] At least part of the first conductive film layer located in the second region and away from the semiconductor substrate along the thickness direction of the semiconductor substrate includes a dielectric layer, and at least part of the first conductive film layer located in the second region and close to the semiconductor substrate along the thickness direction of the semiconductor substrate includes a second conductive layer.

[0021] In one embodiment, along the thickness direction of the semiconductor substrate, the thickness of the first conductive film layer ranges from 50 nm to 100 nm.

[0022] In one embodiment, forming the first electrode on a side of the first conductive layer facing away from the semiconductor substrate by an electroplating process comprises:

[0023] forming a seed layer on a side of the first conductive layer facing away from the semiconductor substrate by an electroplating process;

[0024] An electrode layer is formed on a side of the seed layer facing away from the semiconductor substrate to obtain a first electrode.

[0025] In one embodiment, removing the dielectric layer includes:

[0026] The dielectric layer is removed by a second solution system.

[0027] In one embodiment, the pH value of the second solution system is in the range of 3-4.

[0028] In a second aspect, the present application provides a solar cell, the solar cell comprising:

[0029] A semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to each other, and the first surface having a first region and a second region;

[0030] The first surface of the semiconductor substrate has a first conductive layer and a first electrode located in a first region, and along the thickness direction of the semiconductor substrate, the first electrode is located on a side of the first conductive layer away from the semiconductor substrate;

[0031] A second conductive layer is disposed in a second region on the first surface of the semiconductor substrate. Along the thickness direction of the semiconductor substrate, the thickness of the second conductive layer is less than the thickness of the first conductive layer.

[0032] In a third aspect, the present application provides a photovoltaic assembly, comprising the solar cell described in any one of the above embodiments.

[0033] The solar cell and its preparation method, photovoltaic module, by grooving the first area and forming the first electrode in the first area after the grooving, can reduce the shielding of the first electrode from the incident light, while increasing the contact area between the first electrode and the solar cell, reducing the series resistance of the solar cell, which is beneficial to improving the battery efficiency and optimizing the mechanical properties of the first electrode. By forming a first conductive layer with good conductivity in the first area and a dielectric layer with poor conductivity in the second area, the subsequent first electrode will only be formed on the surface of the first conductive layer, and will not be formed on the surface of the dielectric layer. In the metal patterning process, there is no need to introduce an additional mask, which reduces the process steps required for electrode preparation, greatly simplifies the metallization process, and thus improves the output of solar cells and the yield of solar cells; at the same time, it reduces the equipment investment for patterning using masks, which can effectively control production costs and help achieve cost reduction and efficiency improvement. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG. 1 is a schematic flow chart of a method for preparing a solar cell provided in an embodiment of the present application.

[0035] 2 to 8 are schematic diagrams of some stages of a method for preparing a solar cell provided in an embodiment of the present application.

[0036] 9 to 11 are schematic diagrams of stages of forming a dielectric layer according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0038] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0039] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0040] In this application, unless otherwise clearly specified and limited, if the terms "installed", "connected", "connected", "fixed" and the like appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0041] In the present application, unless otherwise clearly specified and limited, if there is a description that a first feature is "above" or "below" a second feature, etc., or similar descriptions appear, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "above" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0042] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.

[0043] The metallization of solar cells is one of the important links in the production of solar cells. Through contact and non-contact technologies, metallized electrodes are prepared on the front and back of solar cells to form a tight and efficient ohmic contact between the electrode and the cell, and the photogenerated carriers are guided out of the cell. Metallization is related to the production cost and conversion efficiency of the cell, and ultimately affects the choice of future battery paths. Therefore, the optimization of the metallization process has not only become a key area to achieve the cost reduction plan, but also a focus of industry attention. Copper electroplating technology, as a non-contact metallization technology, is the most effective attempt to break through screen printing technology. The biggest advantage of copper electroplating technology is that it replaces all metal silver paste with copper, which fundamentally solves the problem of high material cost. At the same time, copper electroplating can achieve double-sided metallization at the same time, improving production efficiency.

[0044] Copper electroplating technology requires four steps to achieve metallization: I. Seed layer; II. Patterning; III. Electroplating; IV. Post-processing. Among them, patterning is the key step to obtain the electrode design pattern through pattern transfer technology and realize subsequent selective electroplating. Patterning technology can be roughly divided into organic mask, inorganic mask, inkjet printing and laser stripping.

[0045] At present, the two technical solutions of organic mask and inorganic mask are favored by the industry and have become the mainstream graphic solutions. However, there are many disadvantages in the two technical solutions. The technical route process is lengthy and involves many graphic equipment and processes, which inevitably leads to a sharp increase in process costs and a decrease in the yield and output of battery products. At the same time, a large amount of organic and inorganic waste will be generated in the process of preparing and removing the mask, increasing environmental pressure. Therefore, although the copper electroplating technology using the above-mentioned graphic process can be completely silver-free, it introduces more new equipment and materials in the graphic process, resulting in the cost reduction advantage of copper electroplating technology almost disappearing.

[0046] There is currently a scheme that uses electrochemical methods to reduce metals from transparent conductive oxides on the surface and use them as seed layers for plating. However, since the metal ions in the conductive oxide under the metal electrode are reduced, its conductivity decreases, and ultimately the electrical performance of the battery is affected.

[0047] In addition, the metal electrodes currently prepared are plated on a transparent conductive oxide layer. In actual use, the inclined incident light will be blocked by it, resulting in an increase in the shading area, affecting the limiting current and actual output power of the solar cell.

[0048] As shown in FIG. 1 to FIG. 8 , an embodiment of the present application provides a method for preparing a solar cell, comprising:

[0049] S100 , as shown in FIG. 2 , a semiconductor substrate 10 is provided. The semiconductor substrate 10 has a first surface 11 and a second surface opposite to each other. The first surface 11 has a first region 111 and a second region 112 .

[0050] The first region 111 is a region where a metal-semiconductor contact is subsequently formed, and the second region 112 is a non-contact region.

[0051] In some examples, the material of the semiconductor substrate 10 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). In terms of conductivity type, the semiconductor substrate 10 can be an intrinsic semiconductor substrate, an n-type semiconductor substrate, or a p-type semiconductor substrate. Preferably, the semiconductor substrate 10 is a p-type semiconductor substrate or an n-type semiconductor substrate. Compared with an intrinsic semiconductor substrate, a p-type semiconductor substrate or an n-type semiconductor substrate has better conductivity, so that the final solar cell has a lower body resistivity, thereby improving the efficiency of the solar cell.

[0052] It should be noted that the semiconductor substrate 10 mentioned in the embodiment of the present application is selected from materials such as silicon (Si) or germanium (Ge) or gallium arsenide (GaAs) as the base material of the semiconductor substrate 10. For example, taking silicon material as the base material of the semiconductor substrate 10 as an example, the base material having the above silicon material needs to be prepared through process steps such as texturing, hydrogenated intrinsic amorphous silicon deposition, doped hydrogenated amorphous silicon deposition, and transparent conductive layer deposition to prepare the semiconductor substrate 10. Of course, the present application does not limit the preparation method of the semiconductor substrate 10, and the preparation method of the semiconductor substrate 10 will not be repeated here.

[0053] Exemplarily, the semiconductor substrate 10 may be an n-type silicon substrate, which is only used as an example and is not specifically limited.

[0054] Illustratively, the first surface 11 of the semiconductor substrate 10 may be a light-facing surface, and the second surface may be a backlight surface.

[0055] S200 , as shown in FIG. 3 , the first region 111 is grooved.

[0056] Based on this, the first electrode 30 can be prepared in the groove formed in the first region 111, thereby reducing the height of the first electrode 30 along the thickness direction of the semiconductor substrate 10, which can reduce the shielding of the first electrode 30 for the incident light and reduce the shading area; at the same time, the contact area between the first electrode 30 and the solar cell is increased, the contact resistance is reduced, and thus the series resistance of the solar cell is reduced, which is beneficial to improving the battery efficiency. In addition, the first electrode 30 prepared in the groove has better mechanical properties, which is beneficial to improving the yield of the solar cell.

[0057] The grooves may be prepared in the first region 111 by methods including but not limited to laser etching, mechanical grooving, or etching ink coating. For example, a laser may be used to perform single-sided grooving on the first surface 11 of the semiconductor substrate 10 according to the pattern of the first electrode 30 to form grooves in the first region 111.

[0058] In some examples, the groove depth of the groove of the first region 111 may be 10 μm to 20 μm along the thickness direction of the semiconductor substrate 10. For example, along the thickness direction of the semiconductor substrate 10, the groove depth of the groove of the first region 111 may be 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm or 20 μm, etc., which are only examples and are not specifically limited.

[0059] In some examples, the groove width of the groove of the first region 111 can be 10μm to 20μm. For example, the groove width of the groove of the first region 111 can be 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm or 20μm, etc., which are only examples and are not specifically limited. Among them, the groove width of the groove of the first region 111 can be the distance between the two groove walls of the groove along the direction parallel to the surface of the semiconductor substrate 10 and perpendicular to the extension direction of the first region 111.

[0060] In some examples, after the first region 111 is grooved, the semiconductor substrate 10 is cleaned and dried, which can effectively reduce the damage of patterning to the semiconductor substrate 10. For example, when the first region 111 is grooved by a laser process, wet cleaning after the grooves can remove the damaged layer on the surface of the semiconductor substrate 10, effectively reducing the damage of the laser grooves to the surface of the semiconductor substrate 10.

[0061] For example, the embodiment of the present application does not limit the shape of the groove formed in the first area 111. For example, it can be an inverted trapezoidal groove as shown in the figure, or a groove with equal width from the groove mouth to the groove bottom, or a groove of other shapes, etc., which is only an example here and is not specifically limited.

[0062] S300 , forming a first conductive layer 21 in the first region 111 , and forming a dielectric layer 22 in the second region 112 .

[0063] The forming of the first conductive layer 21 in the first region 111 and the forming of the dielectric layer 22 in the second region 112 includes:

[0064] As shown in FIG. 5 , a first conductive film layer 20 is formed on the first surface 11 of the semiconductor substrate 10 , and along the thickness direction of the semiconductor substrate 10 , the orthographic projection of the first conductive film layer 20 on the first surface 11 covers the first region 111 and the second region 112 ;

[0065] As shown in FIG. 6 , in the first solution system, the second region 112 is laser processed and assisted by ultrasonic oscillation, so that the first conductive film layer 20 located in the first region 111 includes the first conductive layer 21 , and at least a portion of the first conductive film layer 20 located in the second region 112 includes the dielectric layer 22 .

[0066] It should be noted that the first conductive film layer 20 in the above-mentioned embodiment is a film layer located on one side of the first surface 11, and the film layer includes a first conductive layer 21 and a dielectric layer 22. It should be noted that the first conductive film layer 20 located in the first area 111 includes the first conductive layer 21, and at least part of the first conductive film layer 20 located in the second area 112 includes the dielectric layer 22, that is, the film layer located on one side of the first area 111 is the first conductive layer 21, and at least part of the film layer located on one side of the second area 112 is the dielectric layer 22.

[0067] Exemplarily, the first conductive film layer 20 may be a transparent conductive oxide (TCO) film layer, such as indium tin oxide (ITO), zinc oxide (ZnO), tin oxide (SnO2), indium oxide (In2O3), etc., which are only given as examples and are not specifically limited.

[0068] Based on this, as shown in FIGS. 6 to 7 and 9 to 11, the first conductive film layer 20 can be covered with the entire first surface 11 of the semiconductor substrate 10, and then a patterned dielectric layer 22 can be formed on the first surface 11 with the assistance of laser. Further, taking the semiconductor substrate 10 as an n-type semiconductor substrate 10 as an example, as shown in FIG. 9, a laser beam A with a specific wavelength can be irradiated on the second area 112 of the first surface 11 of the semiconductor substrate 10 through a first solution system, so that the electron-hole pairs generated by the photoelectric effect of the semiconductor substrate 10 located in the second area 112 are separated under the action of the built-in electric field, the holes move to the second surface of the semiconductor substrate 10, and the electrons move to the first surface 11 of the semiconductor substrate 10, and gather in the second area 112 irradiated by the laser, and finally a reduction reaction occurs at the interface between the second area 112 and the solution. Taking the first conductive film layer 20 as ITO as an example, the reduction reaction here is that the metal indium in ITO is reduced. As shown in FIG10 , the reduced metallic indium adheres to the surface of the first conductive film layer 20 facing away from the semiconductor substrate 10 . Under the action of the first solution system and the vibration of the external ultrasonic wave, as shown in FIG11 , the tiny indium particles separate from the first conductive film layer 20 , so that at least a portion of the first conductive film layer 20 located in the second region 112 loses its conductive ability due to the loss of the indium element and becomes a dielectric layer 22 . At the same time, the first conductive film layer 20 located in the first region 111 is retained and becomes the first conductive layer 21 .

[0069] When the first electrode 30 is subsequently prepared by the electroplating process, the dielectric layer 22 with poor conductivity can play a role similar to a mask, so that the first electrode 30 can be formed only in the first area 111, and will not be formed in the second area 112. It can be seen that the embodiment of the present application can use the first conductive film layer 20 to prepare the dielectric layer 22, and use the dielectric layer 22 to realize the patterning of the first electrode 30, without introducing an additional mask in the patterning step, thereby reducing the steps of spin coating, drying, exposure, development, and washing the glue required for the mask, greatly simplifying the process flow of metal patterning, and at the same time reducing the equipment investment required for these steps, effectively reducing production costs, and is conducive to achieving cost reduction and efficiency improvement, and reducing environmental pressure. In addition, with the reduction of process steps, the output of solar cells is also increased accordingly; and because the more steps, the greater the risk of solar cell fragments, therefore, the embodiment of the present application can also improve the yield of solar cells.

[0070] Exemplarily, the laser used in the laser treatment may be an ultraviolet laser with a wavelength range of 10 nm to 400 nm. The ultraviolet laser has the advantage of high single-photon energy and can improve the reduction efficiency. For example, the laser wavelength used in the laser treatment may be 10 nm, 50 nm, 100 nm, 200 nm, 300 nm, 400 nm, etc., which are only examples and are not specifically limited.

[0071] For example, the laser used in the laser processing may be a picosecond laser or a femtosecond laser.

[0072] In some examples, the pH value of the first solution system is in the range of 3-5; and / or the laser irradiation power of the laser treatment is in the range of 0.03 J / cm 2 ~0.07J / cm 2 ; and / or, the laser spot overlap rate is in the range of 2% to 7%; and / or, the ultrasonic frequency range of the ultrasonic oscillation is 40KHz to 70KHz. The laser spot overlap rate refers to the percentage of the overlapping area of ​​adjacent laser spots to the spot area.

[0073] Based on this, the first solution system, the laser and the ultrasonic wave of the ultrasonic oscillation can be defined as above, so that at least part of the first conductive film layer 20 located in the second area 112 undergoes a reduction reaction and becomes a dielectric layer 22, and the first conductive film layer 20 located in the first area 111 is retained. Among them, the first solution system can be a weak acid system with a pH value of 3 to 5, which can make the metal particles precipitated after laser reduction have poor adhesion to the first conductive film layer 20, which is convenient for subsequent removal by ultrasonic oscillation. If the pH value of the first solution system is too high, the precipitated metal particles may adhere more firmly and be difficult to remove by ultrasonic oscillation; if the pH value of the first solution system is too low, the acidity of the first solution system is too strong, which may also damage the first conductive film layer 20 located in the first area 111.

[0074] For example, the pH value of the first solution system may be 3, 3.5, 4, 4.5 or 5, etc., and the laser irradiation power of the laser treatment may be 0.03 J / cm 2 , 0.04J / cm 2 , 0.05J / cm 2 , 0.06J / cm 2 or 0.07J / cm 2 And so on, the laser spot overlap rate can be 2%, 3%, 4%, 5%, 6% or 7% and so on, the ultrasonic frequency of the ultrasonic oscillation can be 40KHz, 45KHz, 50KHz, 55KHz, 60KHz, 65KHz or 70KHz and so on, which are only examples here and are not specifically limited.

[0075] For example, the first solution system may include at least one or more acid solutions such as sulfuric acid, hydrochloric acid or phosphoric acid, which are only used as examples and are not specifically limited.

[0076] For example, the thickness of the dielectric layer 22 can be controlled by controlling the laser irradiation time. The laser irradiation time can be adjusted according to actual production, and this application is not limited thereto.

[0077] In some examples, in the first solution system, the first conductive film layer 20 located in the second region 112 is laser processed and assisted by ultrasonic vibration, so that the first conductive film layer 20 located in the first region 111 includes the first conductive layer 21, and at least a portion of the first conductive film layer 20 located in the second region 112 includes the dielectric layer 22 including:

[0078] The at least portion of the first conductive film layer 20 located in the second region 112 and away from the semiconductor substrate 10 along the thickness direction of the semiconductor substrate 10 includes a dielectric layer 22, and the at least portion of the first conductive film layer 20 located in the second region 112 and close to the semiconductor substrate 10 along the thickness direction of the semiconductor substrate 10 includes a second conductive layer 23.

[0079] It should be noted that the first conductive film layer 20 in the above-mentioned embodiment is a film layer located on one side of the first surface 11, and the film layer includes a first conductive layer 21, a dielectric layer 22 and a second conductive layer 23, and it should be noted that at least a portion of the first conductive film layer 20 located in the second region 112 and away from the semiconductor substrate 10 along the thickness direction of the semiconductor substrate 10 is the dielectric layer 22, and at least a portion of the first conductive film layer 20 located in the second region 112 and close to the semiconductor substrate 10 along the thickness direction of the semiconductor substrate 10 is the second conductive layer 23, that is, the film layer located on one side of the first region 111 is the first conductive layer 21, at least a portion of the film layer located in the second region away from the semiconductor substrate 10 is the dielectric layer 22, and at least a portion of the film layer located in the second region close to the semiconductor substrate 10 is the second conductive layer 23.

[0080] The first conductive film layer 20 mainly plays the role of transmitting carriers. After the reduction reaction occurs to form the dielectric layer 22, the conductivity and transparency of the dielectric layer 22 are reduced relative to the first conductive film layer 20. Therefore, the first conductive film layer 20 located in the second region 112 can be divided into two layers along the thickness direction of the semiconductor substrate 10. The part of the first conductive film layer 20 far away from the semiconductor substrate 10 will undergo a reduction reaction under the action of the laser and become the dielectric layer 22, and the part of the first conductive film layer 20 close to the semiconductor substrate 10 is retained as the second conductive layer 23. After the first electrode 30 is formed, the dielectric layer 22 can be removed, so that the second region 112 can realize the transmission of carriers through the second conductive layer 23, which is conducive to further improving the efficiency of the solar cell.

[0081] In some examples, along the thickness direction of the semiconductor substrate 10 , the thickness of the first conductive film layer 20 ranges from 50 nm to 100 nm.

[0082] The portion of the first conductive film layer 20 located in the second area 112 is removed after undergoing a reduction reaction to become the dielectric layer 22, which is equivalent to thinning the first conductive film layer 20 in the second area 112. Based on this, the thickness of the formed first conductive film layer 20 in the thickness direction of the semiconductor substrate 10 can be slightly thicker, which is convenient for the subsequent thinning and final removal of the portion of the first conductive film layer 20 located in the second area 112, which is beneficial to improving the conductive properties of the retained second conductive layer 23, thereby further improving the efficiency of the solar cell.

[0083] For example, along the thickness direction of the semiconductor substrate 10 , the thickness of the first conductive film layer 20 may be 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm, etc. These are merely examples and are not specifically limited.

[0084] As a possible implementation, as shown in FIG. 4 , after the first region 111 is grooved, the first conductive layer 21 is formed in the first region 111 , and before the dielectric layer 22 is formed in the second region 112 , the method for preparing a solar cell provided in the embodiment of the present application may further include:

[0085] Performing double-sided texturing on the first surface 11 and the second surface of the semiconductor substrate 10;

[0086] Depositing a first hydrogenated amorphous silicon layer on the first surface 11 of the semiconductor substrate 10, and depositing a second hydrogenated amorphous silicon layer on the second surface of the semiconductor substrate 10;

[0087] A first doped hydrogenated amorphous silicon layer 40 is deposited on a side of the first hydrogenated amorphous silicon layer facing away from the semiconductor substrate 10 , and a second doped hydrogenated amorphous silicon layer is deposited on a side of the second hydrogenated amorphous silicon layer facing away from the semiconductor substrate 10 .

[0088] Afterwards, a first conductive film layer 20 is formed on the side of the first doped hydrogenated amorphous silicon layer 40 away from the semiconductor substrate 10, and a second conductive film layer is formed on the side of the second doped hydrogenated amorphous silicon layer away from the semiconductor substrate 10. After the first conductive film layer 20 is deposited, the morphology of the groove wall and the groove bottom of the first region 111 on the first surface 11 of the semiconductor substrate 10 is the same as that of the second region 112, and also has a suede structure.

[0089] In some examples, the thickness of the first hydrogenated amorphous silicon layer in the thickness direction of the semiconductor substrate 10 may be 5 nm to 10 nm, and the thickness of the second hydrogenated amorphous silicon layer in the thickness direction of the semiconductor substrate 10 may be 5 nm to 10 nm.

[0090] Illustratively, the thickness of the first hydrogenated amorphous silicon layer in the thickness direction of the semiconductor substrate 10 may be 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, etc., and the thickness of the second hydrogenated amorphous silicon layer in the thickness direction of the semiconductor substrate 10 may be 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, etc. This is only an example and is not specifically limited.

[0091] In some examples, the first doped hydrogenated amorphous silicon layer 40 may be a boron-doped hydrogenated amorphous silicon layer, and the second doped hydrogenated amorphous silicon layer may be a phosphorus-doped hydrogenated amorphous silicon layer; or, the first doped hydrogenated amorphous silicon layer 40 may be a phosphorus-doped hydrogenated amorphous silicon layer, and the second doped hydrogenated amorphous silicon layer may be a boron-doped hydrogenated amorphous silicon layer.

[0092] For example, the first doped hydrogenated amorphous silicon layer 40 may be a phosphorus doped hydrogenated amorphous silicon layer, and the second doped hydrogenated amorphous silicon layer may be a boron doped hydrogenated amorphous silicon layer. At this time, the current transmission direction inside the solar cell is the same as the current transmission direction of the light-induced electroplating (Light-Induced Process, LIP), so the light-induced electroplating technology can be used to manufacture the first electrode 30, thereby improving the electroplating efficiency and further improving the yield of the solar cell.

[0093] For example, the thickness of the first doped hydrogenated amorphous silicon layer 40 in the thickness direction of the semiconductor substrate 10 may be 20 nm to 50 nm, and the thickness of the second doped hydrogenated amorphous silicon layer in the thickness direction of the semiconductor substrate 10 may be 30 nm to 60 nm.

[0094] For example, the thickness of the first doped hydrogenated amorphous silicon layer 40 in the thickness direction of the semiconductor substrate 10 can be 20nm, 25nm, 30nm, 35nm, 40nm, 45nm or 50nm, etc., and the thickness of the second doped hydrogenated amorphous silicon layer in the thickness direction of the semiconductor substrate 10 can be 20nm, 25nm, 30nm, 35nm, 40nm, 45nm or 50nm, etc. These are just examples and are not specifically limited.

[0095] In some examples, the second conductive film layer may also be a transparent conductive oxide (TCO) film layer, such as indium tin oxide (ITO), zinc oxide (ZnO), tin oxide (SnO2), indium oxide (In2O3), etc., which are only examples and not specifically limited.

[0096] In some examples, the thickness of the second conductive film layer in the thickness direction of the semiconductor substrate 10 may be 60 nm to 100 nm.

[0097] Illustratively, the thickness of the second conductive film layer in the thickness direction of the semiconductor substrate 10 may be 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm or 100 nm, etc., which are merely examples and not specifically limited.

[0098] S400 , as shown in FIG. 7 , a first electrode 30 is formed on a side of the first conductive layer 21 away from the semiconductor substrate 10 by an electroplating process.

[0099] The method of forming the first electrode 30 on the side of the first conductive layer 21 away from the semiconductor substrate 10 by electroplating includes:

[0100] forming a seed layer on a side of the first conductive layer 21 away from the semiconductor substrate 10 by an electroplating process;

[0101] An electrode layer is formed on a side of the seed layer facing away from the semiconductor substrate 10 to obtain a first electrode 30 .

[0102] In the electroplating process, the plated object as the cathode needs to have a conductive surface so that the plated metal ions can be deposited on the surface of the plated object after power is applied to form plated metal. Based on this, when the seed layer is plated on the first surface 11 of the semiconductor substrate 10 using the electroplating process, due to the aforementioned treatment, the first surface 11 has only the first conductive layer 21 with good conductivity in the groove of the first area 111, and the dielectric layer 22 in the second area 112 loses its conductivity. Therefore, the seed layer will only be deposited in the first area 111, specifically formed on the side of the first conductive layer 21 in the groove of the first area 111 away from the semiconductor substrate 10. Similarly, the electrode layer will only be plated on the surface of the seed layer located in the first area 111 away from the semiconductor substrate 10. It can be seen that the embodiment of the present application can use the dielectric layer 22 instead of the additionally formed mask to realize the patterning of the first electrode 30, simplifying the process flow of metal patterning, while reducing equipment investment, effectively reducing production costs, and at the same time improving the output and yield of solar cells, which is conducive to achieving cost reduction and efficiency improvement, and reducing environmental protection pressure.

[0103] In some examples, the material of the seed layer can be selected from at least one or more of copper (Cu), nickel (Ni), copper-nickel alloy, titanium (Ti) or tungsten (W), etc., and the plating solution used when electroplating the seed layer can be selected according to the material of the seed layer. Exemplarily, the seed layer can be a metal nickel seed layer, and the plating solution used when electroplating the seed layer can be a Watts nickel plating solution, which is only used as an example and is not specifically limited.

[0104] In some examples, the thickness of the formed seed layer in the thickness direction of the semiconductor substrate 10 may be 100 nm to 400 nm. Exemplarily, the thickness of the seed layer in the thickness direction of the semiconductor substrate 10 may be 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm or 400 nm, etc., which are only examples and are not specifically limited.

[0105] In some examples, the current density when electroplating the seed layer can be 1A / dm 2 ~3A / dm 2 For example, the current density during electroplating of the seed layer may be 1A / dm 2 , 1.5A / dm 2 , 2A / dm 2 , 2.5A / dm 2 or 3A / dm 2 Etc. These are just examples and are not specific limitations.

[0106] In some examples, the plating solution circulation speed during electroplating the seed layer may be 3 L / min to 8 L / min. For example, the plating solution circulation speed during electroplating the seed layer may be 3 L / min, 4 L / min, 5 L / min, 6 L / min, 7 L / min or 8 L / min, etc., which are only examples and are not specifically limited.

[0107] In some examples, the plating time of the seed layer can be 1 min to 3 min. For example, the plating time of the seed layer can be 1 min, 1.5 min, 2 min, 2.5 min or 3 min, etc., which are only examples and are not specifically limited.

[0108] In some examples, the material of the electrode layer can be selected from at least one or more of copper, silver, tin, etc. The electrode layer can also be formed by an electroplating process, and the plating solution used when electroplating the electrode layer can be selected according to the material of the electrode layer. Exemplarily, the electrode layer can be a metal copper electrode layer. In this case, the plating solution used when electroplating the seed layer can be a mixed solution including copper sulfate, sulfuric acid, sodium chloride, poly(disulfide dipropane sulfonate), polyethylene imine alkyl salt and polyethylene glycol; wherein, based on the total amount of the plating solution, the concentration of copper sulfate can be 60 g / L~200 g / L, the concentration of sulfuric acid can be 25 g / L~150 g / L, the concentration of chloride ions in sodium chloride can be 20 mg / L~100 mg / L, the concentration of poly(disulfide dipropane sulfonate) can be 1 mg / L~20 mg / L, the concentration of polyethylene imine alkyl salt can be 10 mg / L~100 mg / L, and the concentration of polyethylene glycol can be 50 mg / L~1000 mg / L; for example, based on the total amount of the plating solution, the concentration of copper sulfate can be 60 g / L, 80 g / L, 100 g / L, 140 g / L, 160 g / L, 180 g / L, 190 g / L, 200 g / L, 210 g / L, 220 g / L, 230 g / L, 240 g / L, 250 g / L, 260 g / L, 270 g / L, 280 g / L, 290 g / L, 300 g / L, 310 g / L, 320 g / L, 330 g / L, 340 g / L, 360 g / L, 370 g / L, 380 g / L, 390 g / L, 400 g / L, 410 g / L, 420 g / L, 430 g / L, 440 g / L, 450 g / L, 460 g / The concentration of sulfuric acid can be 25 g / L, 50 g / L, 75 g / L, 100 g / L, 125 g / L or 150 g / L, the concentration of chloride ion in sodium chloride can be 20 mg / L, 40 mg / L, 60 mg / L, 80 mg / L or 100 mg / L, the concentration of polydisulfide dipropane sulfonate can be 1 mg / L, 5 mg / L, 10 mg / L, 15 mg / L or 20 mg / L, the concentration of polyethylene imine alkyl salt can be 10 mg / L, 30 mg / L, 60 mg / L, 80 mg / L or 100 mg / L, and the concentration of polyethylene glycol can be 50 mg / L, 100 mg / L, 400 mg / L, 600 mg / L, 800 mg / L or 1000 mg / L, etc. These are just examples and are not specifically limited.

[0109] In some examples, the current density during electroplating of the electrode layer may be 0.5 A / dm 2 ~2A / dm2 For example, the current density during electroplating of the electrode layer may be 0.5 A / dm 2 , 1A / dm 2 , 1.5A / dm 2 or 2A / dm 2 Etc. These are just examples and are not specific limitations.

[0110] In some examples, the plating solution circulation speed during electroplating the electrode layer may be 3 L / min to 8 L / min. For example, the plating solution circulation speed during electroplating the electrode layer may be 3 L / min, 4 L / min, 5 L / min, 6 L / min, 7 L / min or 8 L / min, etc., which are only examples and are not specifically limited.

[0111] In some examples, the plating time when the electrode layer is electroplated may be 2 minutes to 7 minutes. For example, the plating time when the electrode layer is electroplated may be 2 minutes, 3 minutes, 4 minutes, 5 minutes, 6 minutes, or 7 minutes, etc., which are only examples and are not specifically limited.

[0112] In some examples, as shown in FIG8 , after forming the electrode layer, a protective layer 31 may be formed on the side of the electrode layer away from the semiconductor substrate 10 by an electroplating process. The specific preparation method of the protective layer 31 may refer to the preparation method of the seed layer described above. Exemplarily, the material of the protective layer 31 may include at least one or more of nickel, silver, tin or tellurium, etc. For example, the protective layer 31 may be a nickel metal protective layer 31; Exemplarily, the thickness of the protective layer 31 in the thickness direction of the semiconductor substrate 10 may be 80nm~100nm, for example, the thickness of the protective layer 31 in the thickness direction of the semiconductor substrate 10 may be 80nm, 85nm, 90nm, 95nm or 100nm, etc., which is only used as an example and is not specifically limited.

[0113] In addition, in FIG. 7 and FIG. 8 , the protection layer 31 is independent of the first electrode 30 . In another example, the protection layer 31 may also be a part of the first electrode 30 .

[0114] In some examples, after forming the first conductive film layer 20 and the second conductive film layer and before forming the first electrode 30, the preparation process of the solar cell provided in the embodiment of the present application may further include:

[0115] By screen printing, a second electrode is formed on a side of the second conductive film layer away from the semiconductor substrate 10 .

[0116] Furthermore, a low-temperature silver paste may be selected to print the second electrode. Meanwhile, the silver powder in the low-temperature silver paste may be spherical silver powder, which is more suitable for the solar cell manufactured by the solar cell manufacturing method provided in the embodiment of the present application.

[0117] S500 , as shown in FIG. 8 , the dielectric layer 22 is removed.

[0118] Wherein, removing the dielectric layer 22 includes: removing the dielectric layer 22 by a second solution system.

[0119] Since the dielectric layer 22 has poor conductivity and its light transmittance decreases after laser treatment, the incident light incident on the second region 112 will be reduced, resulting in a decrease in the photoelectric conversion efficiency of the solar cell. Therefore, after forming the first electrode 30, the dielectric layer 22 can be removed by the second solution system to expose the second conductive layer 23, further improving the efficiency of the solar cell.

[0120] In some examples, the pH value of the second solution system ranges from 3 to 4.

[0121] Based on this, the second solution system can be a weak acid system with a pH value of 3 to 4. While removing the dielectric layer 22, it will not damage the structure of the first conductive layer 21 and the second conductive layer 23, resulting in a decrease in the conductivity of the first conductive layer 21 and the second conductive layer 23, thereby affecting the efficiency of the solar cell.

[0122] For example, the pH value of the first solution system may be 3, 3.2, 3.6, 3.8 or 4, etc. These are merely examples and are not specifically limited.

[0123] Exemplarily, the first solution system may include at least one or more acid solutions such as acetic acid, oxalic acid or formic acid, which are merely examples and not specifically limited.

[0124] Based on this, the embodiment of the present application can reduce the shielding of the first electrode 30 for the incident light by grooving the first area 111 located on the first surface 11 of the semiconductor substrate 10, and form the first electrode 30 in the first area 111 after the grooving, and at the same time increase the contact area between the first electrode 30 and the solar cell, thereby reducing the series resistance of the solar cell, which is beneficial to improving the cell efficiency and optimizing the mechanical properties of the first electrode 30. Before forming the first electrode 30, by forming a first conductive layer 21 with good conductivity in the first area 111, and forming a dielectric layer 22 with poor conductivity in the second area 112, when the first electrode 30 is subsequently formed by the electroplating process, the first electrode 30 will only be formed on the surface of the first conductive layer 21, and will not be formed on the surface of the dielectric layer 22. In the metal patterning process, no additional mask is required, which reduces the environmental pressure, reduces the process steps required for electrode preparation, greatly simplifies the metallization process, and thus improves the output of solar cells and the yield of solar cells; at the same time, the equipment investment for patterning using masks is reduced, which can effectively control the production cost and is beneficial to achieving cost reduction and efficiency improvement. In addition, the dielectric layer 22 in the second region 112 is removed after the first electrode 30 is formed, so as to avoid the dielectric layer 22 affecting the light absorption and cell efficiency of the solar cell.

[0125] The method for preparing solar cells provided in the embodiments of the present application mainly improves the metallization process of solar cells. In addition to heterojunction cells, it can also be applied to other types of crystalline silicon cells, such as PERC cells, TOPCON cells, BC cells, etc., to form a new type of cell structure formed by combining any one or more cell structures. In addition, it can also be applied to a new type of cell structure formed by combining a heterojunction cell structure with at least one other crystalline silicon cell structure.

[0126] The following describes the method for preparing a solar cell provided by the present application in conjunction with specific embodiments. The embodiments cited are only used to explain the present application and are not used to limit the scope of the present application.

[0127] In the first step, an N-type silicon wafer with a size of 210 mm × 105 mm is provided, and a single-sided groove is made on the surface of the N-type silicon wafer according to the electrode pattern using a laser, with a groove depth of 15 μm and a groove width of 15 μm, and the grooved N-type silicon wafer is cleaned and dried;

[0128] In the second step, the N-type silicon wafer is subjected to double-sided texturing, double-sided deposition of hydrogenated intrinsic amorphous silicon, and double-sided deposition of doped hydrogenated amorphous silicon in turn; wherein the thickness of the deposited hydrogenated intrinsic amorphous silicon is 10nm, the doped hydrogenated amorphous silicon deposited on the N-side (grooved side) is phosphorus-doped hydrogenated amorphous silicon with a thickness of 30nm, and the doped hydrogenated amorphous silicon deposited on the P-side (ungrooved side) is boron-doped hydrogenated amorphous silicon with a thickness of 40nm;

[0129] The third step is to prepare indium tin oxide on both sides, and prepare a metal electrode with a line width of 40 μm and a line height of 15 μm on the P side by screen printing; wherein the thickness of indium tin oxide deposited on the N side is 100 nm, and the thickness of indium tin oxide deposited on the P side is 80 nm;

[0130] The fourth step is to immerse the silicon wafer in a dilute sulfuric acid solution containing 3% by mass, supplemented by 40KHz ultrasonic oscillation of the solution; use a UV picosecond laser to irradiate the non-groove area of ​​the N-side, with a laser overlap rate of 3% and an irradiation power of 0.05J / cm 2 ;

[0131] Step 5: Use Watts nickel plating solution to deposit a 300nm metal nickel seed layer inside the N-side groove with a current density of 2A / dm 2 , plating time is 2min, plating solution circulation speed: 5L / min;

[0132] A copper metal electrode layer is plated on the seed layer, wherein the plating solution comprises: a mixed solution of copper sulfate, sulfuric acid, sodium chloride, polydisulfide dipropane sulfonate, polyethylene imine alkyl salt and polyethylene glycol, based on the total amount of the plating solution, the concentration of copper sulfate is 100 g / L, the concentration of sulfuric acid is 75 g / L, the concentration of chloride ions in the sodium chloride is 50 mg / L, the concentration of polydisulfide dipropane sulfonate is 10 mg / L, the concentration of polyethylene imine alkyl salt is 50 mg / L, and the concentration of polyethylene glycol is 500 mg / L, and the applied current density during the plating process is 1 A / dm 2 , the plating time is 5min, and the circulation speed of the plating solution is 5L / min;

[0133] In the sixth step, according to the preparation method of the seed layer in the fifth step, a nickel metal protection layer 31 with a thickness of 100 nm is prepared on the electrode layer, and finally the dielectric layer 22 is removed using an acetic acid solution with a mass fraction of 10%.

[0134] On the other hand, an embodiment of the present application further provides a solar cell, the solar cell comprising:

[0135] A semiconductor substrate 10, wherein the semiconductor substrate 10 has a first surface 11 and a second surface opposite to each other, and the first surface 11 has a first region 111 and a second region 112;

[0136] The first surface 11 of the semiconductor substrate 10 has a first conductive layer 21 and a first electrode 30 located in the first region 111 . Along the thickness direction of the semiconductor substrate 10 , the first electrode 30 is located on a side of the first conductive layer 21 away from the semiconductor substrate 10 .

[0137] The first surface 11 of the semiconductor substrate 10 has a second conductive layer 23 located in the second region 112 . Along the thickness direction of the semiconductor substrate 10 , the thickness of the second conductive layer 23 is less than the thickness of the first conductive layer 21 .

[0138] In the process of preparing solar cells, after the first conductive film layer 20 deposited on the first surface 11 of the semiconductor substrate 10 undergoes laser-assisted processing, the portion of the first conductive film layer 20 located in the second region 112 becomes the dielectric layer 22, and the first conductive film layer 20 located in the first region 111 is the first conductive layer 21. The dielectric layer 22 can play a role similar to a mask when preparing the first electrode 30, so that the first electrode 30 is only formed on the first conductive layer 21. Since the conductivity and light transmittance of the dielectric layer 22 are both reduced, after the first electrode 30 is prepared, the dielectric layer 22 can be removed to expose the portion of the first conductive film layer 20 under the dielectric layer 22, which is the second conductive layer 23. This process is equivalent to thinning the first conductive film layer 20 located in the second region 112, so that in the thickness direction of the semiconductor substrate 10, the thickness of the second conductive layer 23 is less than the thickness of the first conductive layer 21.

[0139] In some examples, the solar cell also includes a first hydrogenated amorphous silicon layer and a first doped hydrogenated amorphous silicon layer 40 located on the first side 11 of the semiconductor substrate 10, wherein the first doped hydrogenated amorphous silicon layer 40 is located on a side of the first hydrogenated amorphous silicon layer away from the semiconductor substrate 10, and the first conductive layer 21 and the second conductive layer 23 are both located on a side of the first doped hydrogenated amorphous silicon layer 40 away from the semiconductor substrate 10.

[0140] In some examples, the solar cell also includes a second hydrogenated amorphous silicon layer, a second doped hydrogenated amorphous silicon layer, a second conductive film layer and a second electrode located on the second surface of the semiconductor substrate 10, wherein the second doped hydrogenated amorphous silicon layer is located on a side of the second hydrogenated amorphous silicon layer away from the semiconductor substrate 10, the second conductive film layer is located on a side of the second doped hydrogenated amorphous silicon layer away from the semiconductor substrate 10, and the second electrode is located on a side of the second conductive film layer away from the semiconductor substrate 10.

[0141] On the other hand, an embodiment of the present application further provides a photovoltaic assembly, comprising the solar cell described in any of the above embodiments.

[0142] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0143] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a solar cell, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to each other, the first surface having a first region and a second region; Grooving the first area; forming a first conductive layer in the first region and forming a dielectric layer in the second region; forming a first electrode on a side of the first conductive layer away from the semiconductor substrate by an electroplating process; The dielectric layer is removed.

2. The method for preparing a solar cell according to claim 1, characterized in that: The forming of the first conductive layer in the first region and the forming of the dielectric layer in the second region comprises: forming a first conductive film layer on the first surface of the semiconductor substrate, wherein along the thickness direction of the semiconductor substrate, an orthographic projection of the first conductive film layer on the first surface covers the first region and the second region; In a first solution system, the second region is laser processed and assisted by ultrasonic oscillation, so that the first conductive film layer located in the first region includes a first conductive layer, and at least a portion of the first conductive film layer located in the second region includes a dielectric layer.

3. The method for preparing a solar cell according to claim 2, characterized in that: The pH value of the first solution system ranges from 3 to 5; And / or, the laser irradiation power range of the laser treatment is 0.03 J / cm 2 ~0.07J / cm 2 ; and / or, the laser spot overlap ratio ranges from 2% to 7%; And / or, the ultrasonic frequency range of the ultrasonic oscillation is 40KHz~70KHz.

4. The method for preparing a solar cell according to claim 2, characterized in that: In the first solution system, the second region is subjected to laser treatment and assisted by ultrasonic vibration, so that the first conductive film layer located in the first region includes a first conductive layer, and at least a portion of the first conductive film layer located in the second region includes a dielectric layer, including: At least part of the first conductive film layer located in the second region and away from the semiconductor substrate along the thickness direction of the semiconductor substrate includes a dielectric layer, and at least part of the first conductive film layer located in the second region and close to the semiconductor substrate along the thickness direction of the semiconductor substrate includes a second conductive layer.

5. The method for preparing a solar cell according to claim 2, characterized in that: Along the thickness direction of the semiconductor substrate, the thickness of the first conductive film layer ranges from 50 nm to 100 nm.

6. The method for preparing a solar cell according to any one of claims 1 to 5, characterized in that: The forming of the first electrode on the side of the first conductive layer away from the semiconductor substrate by electroplating process comprises: forming a seed layer on a side of the first conductive layer away from the semiconductor substrate by an electroplating process; An electrode layer is formed on a side of the seed layer facing away from the semiconductor substrate to obtain the first electrode.

7. The method for preparing a solar cell according to any one of claims 1 to 5, characterized in that: The removing the dielectric layer comprises: The dielectric layer is removed by a second solution system.

8. The method for preparing a solar cell according to claim 7, characterized in that: The pH value of the second solution system ranges from 3 to 4.

9. A solar cell, characterized in that: The solar cell comprises: A semiconductor substrate having a first surface and a second surface opposite to each other, wherein the first surface has a first region and a second region; The first surface of the semiconductor substrate has a first conductive layer and a first electrode located in the first region, and along the thickness direction of the semiconductor substrate, the first electrode is located on a side of the first conductive layer away from the semiconductor substrate; A second conductive layer is disposed on the first surface of the semiconductor substrate and is located in the second region. Along the thickness direction of the semiconductor substrate, the thickness of the second conductive layer is less than the thickness of the first conductive layer.

10. A photovoltaic module, characterized in that: Comprising the solar cell according to claim 9.

Images