Composite number length mutual Z-complementary set generation method based on FPGA and communication device

Abstract

The invention discloses a composite number length mutual Z-complementary set generation method based on an FPGA (Field Programmable Gate Array) and a communication device, and belongs to the field of wireless communication. The method comprises the following specific steps: data preparation: randomly taking an initial sequence X with the length of q * p, and setting a twiddle factor sequence W with the same length; cyclic shift: continuously executing p-1 times of q-bit cyclic shift on the sequence X to form a set containing p sequences; and DFT operation: performing DFT operation on the sequence set generated after cyclic shift processing to obtain a new sequence set which is a mutual Z-complementary set. A communication device comprises a data input module, a DFT calculation module and a data output module, and the data input module is responsible for data preparation and execution of cyclic shift; the DFT calculation module is used for carrying out DFT operation on an input sequence; and the data output module outputs the generated mutual Z-complementary set under the control of a specific clock signal. The generated mutual Z-complementary set is suitable for a spatial modulation multiple-input-multiple-output system.

Description

Technical Field

[0001] The invention belongs to the field of wireless communication, and in particular relates to a method for generating a composite long mutual Z-complementary set based on FPGA and a communication device. Background Art

[0002] Cross Z-complementary Set (CZCS) is a specially designed set of sequences, whose notable feature is that the set contains a series of sequences with a specific zero correlation zone (ZCZ). Specifically, if the set G contains M sequences of length L and satisfies the following two conditions: (1) the sum of the non-periodic autocorrelations of all sequences of CZCS has a zero correlation zone of width Z at the time offsets at the front and rear ends; (2) the sum of the non-periodic cross-correlations of all sequences of CZCS has a zero correlation zone of width Z at the time offsets at the rear end, then this set is defined as a cross Z-complementary set, denoted as (M,L,Z)-CZCS.

[0003] Sequence sets with specific correlation properties have been widely used in communication systems to improve link performance. Among them, CZCS, as a training sequence, has shown excellent performance in channel estimation in Space Modulation Multi-input Multi-output (SM-MIMO) systems. Compared with traditional sequences, such as Zadoff-Chu (ZC) sequence, ZCZ sequence, complementary sequence, etc., CZCS has obvious advantages in channel estimation performance.

[0004] The SM-MIMO system combines spatial modulation and multiple-input multiple-output technology. Its core idea is that in a system with multiple antennas, only one transmitting antenna is activated in each time slot. The index of the activated antenna is changed through spatial modulation technology, and the receiving antenna recovers the transmitted data by detecting the index of the activated antenna and the transmitted signal. The combination of these two technologies significantly improves the spectrum efficiency of the system, reduces interference between antennas, and enhances signal reliability.

[0005] SM-MIMO systems have performed well in the field of wireless communications, especially in scenarios that require efficient use of spectrum resources, reduced power consumption, and improved transmission reliability, such as 5G mobile communications, the Internet of Things, Internet of Vehicles, and satellite communications. With the advancement of technology, SM-MIMO systems have made significant progress in theoretical foundations, performance optimization, and practical applications. However, there is still room for improvement in SM-MIMO systems in terms of spectrum efficiency, channel estimation accuracy, hardware complexity, and anti-interference capabilities. By introducing high-quality training sequences, the channel estimation capabilities of SM-MIMO systems in complex and changing channel environments can be significantly enhanced. In SM-MIMO systems, training sequences play a vital role. They provide the receiver with the ability to estimate channel state information, and accurate channel estimation is essential for correctly decoding received signals and achieving efficient data transmission.

[0006] The existing methods for constructing CZCS are limited, and there are many restrictions on the set parameters. For example, the design method using generalized Boolean functions can only produce CZCS of a specific length, number of constituent sequences, and ZCZ length, while the design results using indirect methods depend on the set parameters of the basic sequence. These limitations significantly restrict the scope of application of CZCS. In addition, the current construction method has not yet entered the field of hardware design and only remains at the feasibility verification level at the theoretical level. Therefore, in order to achieve the optimal channel estimation of the SM-MIMO system, it is urgent to explore more flexible and efficient construction methods. These methods should be able to adapt to the requirements of sequences of different lengths and numbers, and simplify the design process to facilitate hardware implementation, thereby improving the practicality of the design. Summary of the invention

[0007] In order to solve the above problems, the present invention provides a composite length CZCS generation method and communication device based on FPGA, which expands the number of sequences in CZCS, provides more length options, and is easier to implement using hardware.

[0008] In order to achieve the above object, the technical solution proposed by the present invention is as follows:

[0009] A method for generating a composite long mutual Z-complementary set based on FPGA, comprising the following steps:

[0010] Step 1: Data preparation. Take an initial sequence X = [x(0), x(1), ..., x(N-1)] of length N = pq, where p and q are non-1 positive integers, and set a rotation factor sequence W = [w(0), w(1), ..., w(N-1)] of the same length.

[0011] Step 2: Circular shift: Starting from sequence X, perform p-1 q-bit circular shifts in succession to form a set of p sequences.

[0012] Step 3: Discrete Fourier Transform (DFT) operation. Perform DFT operation on the sequence set generated after step 2, and the new sequence set obtained is CZCS.

[0013] A further improvement of the technical solution of the present invention is that the length of the initial sequence X in step 1 is a composite number N, and the rotation factor sequence W is a unit modulus complex exponential sequence, wherein n is an integer ranging from 0 to N-1.

[0014] A further improvement of the technical solution of the present invention is that: in the step 1, the real part and the imaginary part of the sequence X and the rotation factor sequence W are respectively integerized and pre-placed in the ROM, and the stored sequence and the corresponding rotation factor sequence are read by using the ROM IP core of the FPGA; ROM IP core 1 is used to read the input sequence, and addr1 is set as the real part input address of the sequence, and addr2 is set as the imaginary part input address of the sequence; ROM IP core 2 is used to read the rotation factor sequence, and addr3 is set as the real part input address of the rotation factor, and addr4 is set as the imaginary part input address of the rotation factor.

[0015] A further improvement of the technical solution of the present invention is that in step 2, the sequence X is circulated left or right by q positions to obtain a new sequence X 1 , and then continue to the sequence X 1 Perform the same cyclic shift to get the sequence X 2 This process is repeated p-1 times, each time shifting the previous shift sequence by q positions. After this operation, a set of p sequences is obtained, denoted as {X,X 1 ,X 2 ,...,X p-1};

[0016] A further improvement of the technical solution of the present invention is that in step 3, DFT is a mathematical method for converting a signal from the time domain to the frequency domain. According to the DFT operation formula, the input sequence set is multiplied and accumulated with the corresponding rotation factor, and the obtained new sequence set is CZCS.

[0017] A further improvement of the technical solution of the present invention is that the rotation factor in step 1 has periodicity, that is, Therefore, when performing DFT operation on a sequence of length N, only N rotation factors need to be stored.

[0018] A further improvement of the technical solution of the present invention is that: considering that when performing time-frequency conversion, all elements in the basic sequence need to participate in the calculation to obtain a sequence element in the DFT sequence, and the sequence is serially input. This means that performing a DFT operation on a sequence requires repeatedly inputting the sequence N times to obtain a frequency domain sequence of length N. Therefore, when performing a DFT operation on each basic sequence in the basic sequence set, the setting of the FPGA input address of the basic sequence and the rotation factor sequence should follow the following principles:

[0019] Basic sequence real part input address: addr1 = (n + t)% N;

[0020] Basic sequence imaginary input address: addr2 = (n + t) % N + N;

[0021] The real part input address of the rotation factor sequence: addr3 = n × k% N;

[0022] The imaginary input address of the rotation factor sequence: addr4 = n × k% N + N;

[0023] Where n represents the index of the base sequence and the rotation factor sequence, n = [0, 1, ..., N-1], t represents the number of bits of the cyclic shift, t = [0, q, ..., (p-1) q], and k represents the index of the DFT sequence, k = [0, 1, ..., N-1]. Their initial values ​​are all 0. After each output, n is incremented by 1. After every N outputs, a sequence element in the DFT sequence is obtained. At this time, k is incremented by 1 and n is reset to zero. 2 After the output, the DFT operation of a sequence is completed. At this time, k returns to zero and t increases by q. 2 After the output, the DFT operation of the entire sequence is completed, and t returns to zero.

[0024] A further improvement of the technical solution of the present invention is that the calculation formula of DFT is:

[0025]

[0026] in

[0027]

[0028] Therefore re(n)=addr1×addr3-addr2×addr4; im(n)=addr2×addr3+addr1×addr4;

[0029] Accumulate N results in the data buffer to get the final result:

[0030]

[0031] A communication device comprising:

[0032] Data input module: responsible for data preparation and circular shift functions, using two dual-port ROMs; the first ROM has a 16-bit width and is used to store the real and imaginary parts of the initial sequence X. Let addr1 be the real part input address of the sequence, and addr2 be the imaginary part input address of the sequence; the second ROM has a 32-bit width and is used to store the real and imaginary parts of the rotation factor sequence. Let addr3 be the real part input address of the rotation factor, and addr4 be the imaginary part input address of the rotation factor; addr1, addr2, addr3, and addr4 all use the system clock clk1.

[0033] DFT calculation module: mainly used to perform DFT operations, consisting of four multipliers, an adder, a subtractor and a data buffer; multiplier 1 is responsible for multiplying the real part of the sequence with the real part of the rotation factor, multiplier 2 multiplies the imaginary part of the sequence with the imaginary part of the rotation factor, multiplier 3 multiplies the imaginary part of the sequence with the real part of the rotation factor, and multiplier 4 multiplies the real part of the sequence with the imaginary part of the rotation factor; all operation units use the system clock clk1.

[0034] Data output module: responsible for the output sequence, consisting of a frequency divider and an output unit. The frequency divider divides the system clock clk1 by N to generate a new output clock clk2. The output unit uses clk2 to output the generated CZCS in serial mode.

[0035] The mutual Z-complementary sets generated by this method can be used as training sequences in SM-MIMO systems to improve the performance of channel estimation. In the SM-MIMO system, the transmitter transmits the training matrix composed of the mutual Z-complementary sets to the receiver. After receiving these training sequences, the receiver estimates the channel state using its zero correlation zone characteristics. Since the mutual Z-complementary sets have excellent zero autocorrelation zone and mutual correlation zone characteristics, they can effectively reduce the mutual interference between signals on different paths even after a certain degree of time delay expansion during the transmission process. This feature significantly improves the accuracy of channel estimation, thereby improving the robustness of the system.

[0036] Due to the adoption of the above technical solution, the technical progress achieved by the present invention is:

[0037] The present invention can obtain a CZCS of the same length by performing cyclic shift and DFT operation processing on any sequence with a composite length, thereby providing more options for sequence lengths.

[0038] The present invention can obtain CZCS with more sequences by performing cyclic shift and DFT operation processing on any sequence with a composite length, thereby providing more selections of set sizes.

[0039] The present invention can obtain CZCS by performing cyclic shift and DFT operation processing on any sequence with a composite length, and provides a simple and feasible method, which is convenient for hardware implementation.

[0040] The present invention realizes the universality of the CZCS generation method by adopting a sequence of any composite length as the design basis. Through simulation verification of the generation module on FPGA, the present invention completes the leap from theoretical design to hardware implementation of CZCS for the first time. The generated CZCS is particularly suitable for SM-MIMO systems. As a training sequence for channel estimation, it has significant advantages such as diverse sequence lengths, a wide range of sequence number choices, low hardware implementation resource usage, and strong practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is an implementation flow chart of the present invention;

[0042] Figure 2 It is a simulation diagram of the distribution of the autocorrelation function calculation results of the final output result of the embodiment and the theoretical value;

[0043] Figure 3 It is a simulation diagram of the distribution of the cross-correlation function calculation results of the final output result of the embodiment and the theoretical value;

[0044] Figure 4 This is a diagram showing the hardware resource usage of an embodiment. DETAILED DESCRIPTION

[0045] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0046] like Figure 1 The figure shows an implementation flow chart of a method for generating a composite long mutual Z-complementary set based on FPGA of the present invention, and the specific implementation method is as follows:

[0047] Step 1: Let the initial sequence X be a ZC sequence of length 10, and the rotation factor sequence in Available

[0048] X=[1.0000+0.0000i, 0.9510-0.3090i, 0.3090-0.9510i, -0.9510-0.3090i, 0.3090+0.9510i,

[0049] 0.0000-1.0000i,0.3090+0.9510i,-0.9510-0.3090i,0.3090-0.9510i,0.9510-0.3090i]W= [1.0000+0.0000i,0.8090-0.5878i,0.3090-0.9510i,-0.3090-0.9510i,-0.8090-0.5878i,

[0050] -1.0000-0.0000i,0.8090+0.5878i,-0.3090+0.9510i,0.3090+0.9510i,0.8090+0.5878i]

[0051] To facilitate processing in hardware, the decimals can be enlarged and rounded before being stored in the file. The real and imaginary parts of the sequence X are enlarged by 2 8 Then round it up and store it in the sequence.mif file, and enlarge the real and imaginary parts of the rotation factor sequence W by 2 respectively. 16 Then round it up and save it into the factor.mif file.

[0052] Available

[0053] ReX=[256,243,79,-243,79,0,79,-243,79,243];

[0054] ImX=[0,-79,-243,-79,243,-256,243,-79,-243,-79];

[0055] ReW=[65536,53020,20252,-20252,-53020,-65536,-53020,-20252,20252,53020];

[0056] ImW=[0,-38521,-62328,-62328,-38521,0,38521,62328,62328,38521].

[0057] Two dual-port ROM IP cores are used to read data in Quartus II. ROM IP core 1 is used to read the real and imaginary parts of the initial sequence X in the sequence.mif file, where addr1 is set as the real part input address of the sequence and addr2 is set as the imaginary part input address of the sequence. ROM IP core 2 is used to read the real and imaginary parts of the rotation factor sequence W in the factor.mif file, where addr3 is set as the real part input address of the rotation factor sequence and addr4 is set as the imaginary part input address of the rotation factor sequence.

[0058] Step 2: Set the shift parameter q = 2, then the number of cyclic shifts is The new sequence X can be obtained by cyclically shifting the initial sequence X to the left by 2 bits. 1 , continue to sequence X 1 Perform the same 2-bit circular left shift to get the sequence X 2 This process is performed 4 times in a row. Each sequence is shifted by 2 bits based on the previous shift sequence. A set of 5 sequences can be obtained, which is recorded as {X,X 1 ,X 2 ,X 3 ,X 4}.

[0059] Available

[0060] Re X=[256,243,79,-243,79,0,79,-243,79,243],

[0061] Re X 1 =[79,-243,79,0,79,-243,79,243,256,243],

[0062] Re X 2 =[79,0,79,-243,79,243,256,243,79,-243],

[0063] Re X 3 =[79,-243,79,243,256,243,79,-243,79,0],

[0064] Re X 4 =[79,243,256,243,79,-243,79,0,79,-243],

[0065] Im X=[0,-79,-243,-79,243,-256,243,-79,-243,-79],

[0066] Im X 1 =[-243,-79,243,-256,243,-79,-243,-79,0,-79],

[0067] Im X 2 =[243,-256,243,-79,-243,-79,0,-79,-243,-79],

[0068] Im X 3=[243,-79,-243,-79,0,-79,-243,-79,243,-256],

[0069] Im X 4 =[-243,-79,0,-79,-243,-79,243,-256,243,-79].

[0070] According to the DFT calculation formula To perform DFT on each sequence in the sequence set, the input addresses of the sequence and rotation factor should be set to:

[0071] Basic sequence real part input address: addr1 = (n + t) % 10;

[0072] Basic sequence imaginary input address: addr2 = (n + t)% 10 + 10;

[0073] The real part input address of the rotation factor sequence: addr3 = n × k% 10;

[0074] The imaginary input address of the rotation factor sequence: addr4 = n × k% 10 + 10;

[0075] Where n represents the index of the sequence, with an initial value of 0, and increases by 1 after each output. When n=10, n returns to zero; t represents the number of bits of the cyclic shift, with an initial value of 0, and increases by 2 after each 100 outputs, that is, after completing the DFT operation of a sequence. When t=10, t returns to zero. k represents the index of the rotation factor sequence, with an initial value of 0, and increases by 1 after each 10 outputs. When k=10, k returns to zero.

[0076] Step 3: Multiply and accumulate the input sequence and the rotation factor to complete the DFT operation of the sequence set. According to the formula

[0077]

[0078] Available

[0079] re(n)=addr1×addr3-addr2×addr4; im(n)=addr2×addr3+addr1×addr4.

[0080] Then, the 10 results are accumulated in the data buffer to get the final result:

[0081]

[0082] We can get:

[0083]

[0084]

[0085] The sequence set S generated above = {s 0 ,s 1 ,s 2 ,s 3 ,s 4} is CZCS, where

[0086]

[0087] Finally, the system clock is divided by 10, and the output clock obtained is used to serially output the generated CZCS.

[0088] This embodiment is simulated and implemented using Verilog language in Quartus II environment, and hardware implementation test is carried out on the development board equipped with EP4CE10F17C8 chip. Finally, the waveform signal and clock signal are observed by Signaltap II tool, the internal signal of FPGA chip is obtained and the output sequence is displayed. It can be observed that the output sequence is the same as the theoretical value.

[0089] like Figure 2 As shown, by comparing the autocorrelation function of the embodiment generated based on FPGA with the theoretical value, it is found that the error is almost zero and can be ignored.

[0090] like Figure 3 As shown, by comparing the cross-correlation function of the embodiment generated based on FPGA with the theoretical value, it is found that the error is almost zero and can be ignored.

[0091] like Figure 4 As shown, in this embodiment, an efficient design method is adopted, which ensures that the usage of logic elements remains at a low level while keeping the number of logic elements basically constant even when the sequence length increases. As the initial sequence length increases, the required memory capacity also increases accordingly. In the experimental setting, the storage resource supported by the EP4CE10F17C8 chip used is 414Kbit, or about 51KB, which allows the maximum sequence length to reach 2048. In view of the fact that the capacity of common embedded memory resources ranges from tens of KB to tens of MB, the sequence length generated by this method can achieve a wider range of lengths according to the type of chip selected. This flexibility enables the design method to adapt to embedded resources of different capacities and meet diverse application requirements.

[0092] A communication device, based on an FPGA composite long mutual Z-complementary set, comprises:

[0093] Data input module: responsible for data preparation and circular shift functions, using two dual-port ROMs; the first ROM has a 16-bit width and is used to store the real and imaginary parts of the initial sequence X. Let addr1 be the real part input address of the sequence, and addr2 be the imaginary part input address of the sequence; the second ROM has a 32-bit width and is used to store the real and imaginary parts of the rotation factor sequence. Let addr3 be the real part input address of the rotation factor, and addr4 be the imaginary part input address of the rotation factor; addr1, addr2, addr3, and addr4 all use the system clock clk1.

[0094] DFT calculation module: mainly used to perform DFT operations, consisting of four multipliers, an adder, a subtractor and a data buffer; multiplier 1 is responsible for multiplying the real part of the sequence with the real part of the rotation factor, multiplier 2 multiplies the imaginary part of the sequence with the imaginary part of the rotation factor, multiplier 3 multiplies the imaginary part of the sequence with the real part of the rotation factor, and multiplier 4 multiplies the real part of the sequence with the imaginary part of the rotation factor; all operation units use the system clock clk1.

[0095] Data output module: responsible for the output sequence, consisting of a frequency divider and an output unit. The frequency divider divides the system clock clk1 by N to generate a new output clock clk2. The output unit uses clk2 to output the generated CZCS in serial mode.

[0096] The mutual Z-complementary set generated by the method of the present application is used as a training sequence in the SM-MIMO system to improve the performance of channel estimation. In SM-MIMO, the transmitter transmits the training matrix composed of CZCS to the receiver. After receiving these training sequences, the receiver uses its excellent zero correlation zone characteristics to estimate the channel state. Even if the signal has undergone a certain degree of delay expansion, it can effectively reduce the mutual interference between signals on different paths, thereby improving the accuracy of channel estimation.

[0097] The above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them. Personnel in the technical field to which the present invention belongs may make various modifications and changes to the specific embodiments described. Therefore, any technical solutions that can be obtained by technicians in the technical field based on the concept of this application through logical analysis, reasoning or limited experiments on the basis of the prior art should be within the scope of protection determined by this application.

Claims

1. A method for generating a composite long mutual Z-complementary set based on FPGA, characterized in that The following steps are involved: Step 1: Data preparation, randomly select an initial sequence X of length q×p, and set a rotation factor sequence W of the same length; Step 2: Circular shift: perform p-1 q-bit circular shifts on sequence X to form a set of p sequences. Step 3: DFT operation: perform DFT operation on the sequence set generated after the processing in step 2, and the new sequence set obtained is the mutual Z-complementary set.

2. The method for generating a composite long mutual Z-complementary set based on FPGA according to claim 1, characterized in that: In step 1, the length of the initial sequence X is a composite number N=pq, and the rotation factor sequence W is a unit modulus complex exponential sequence, W=(w(0), w(1), ..., w(N-1)), where n is an integer ranging from 0 to N-1.

3. The method for generating a composite long mutual Z-complementary set based on FPGA according to claim 2, characterized in that: In step 1, the real and imaginary parts of the sequence X and the rotation factor sequence W are respectively integerized and pre-placed in the ROM, and the stored sequence and the corresponding rotation factor sequence are read using the ROMIP core of the FPGA; ROM IP core 1 is used to read the input sequence, and addr1 is set as the real part input address of the sequence, and addr2 is set as the imaginary part input address of the sequence; ROM IP core 2 is used to read the rotation factor sequence, and addr3 is set as the real part input address of the rotation factor, and addr4 is set as the imaginary part input address of the rotation factor.

4. The method for generating a composite long mutual Z-complementary set based on FPGA according to claim 1, characterized in that: In step 2, the sequence X is circulated left or right by q positions to obtain a new sequence X1, and then the same cyclic shift is performed on the sequence X1 to obtain the sequence X2. This process is repeated p-1 times, and each time the shift sequence is shifted by q positions on the basis of the previous shift sequence. After this operation, a set of p sequences is obtained, which is recorded as {X, X1, X2, ..., X p-1 }.

5. The method for generating composite long mutual Z-complementary sets based on FPGA according to claim 1, characterized in that: In step 3, the input sequence set is multiplied and accumulated with the corresponding rotation factor according to the DFT calculation formula, and the obtained new sequence set is the mutual Z-complementary set.

6. The method for generating a composite long mutual Z-complementary set based on FPGA according to claim 2, characterized in that: The rotation factor in step 1 is periodic, that is, Therefore, when performing DFT operation on a sequence of length N, only N rotation factors need to be stored.

7. The method for generating a composite long mutual Z-complementary set based on FPGA according to claim 3, characterized in that: In step 3, the DFT operation on a sequence needs to be repeated N times to obtain a frequency domain sequence of length N. Therefore, when performing DFT operation on each basic sequence in the basic sequence set, the FPGA input address of the basic sequence and the rotation factor sequence should be set according to the following principles: Basic sequence real part input address: addr1 = (n + t)% N; Basic sequence imaginary input address: addr2 = (n + t) % N + N; The real part input address of the rotation factor sequence: addr3 = n × k% N; The imaginary input address of the rotation factor sequence: addr4 = n × k% N + N; Where n represents the index of the base sequence and the rotation factor sequence, n = [0, 1, ..., N-1], t represents the number of bits of the cyclic shift, t = [0, q, ..., (p-1) q], k represents the index of the DFT sequence, k = [0, 1, ..., N-1], and their initial values ​​are all 0. After each output, n is increased by 1. After every N outputs, a sequence element in the DFT sequence is obtained. At this time, k is increased by 1 and n is reset to zero. Every N 2 After the output, the DFT operation of a sequence is completed. At this time, k returns to zero and t increases by q. 2 After the output, the DFT operation of the entire sequence is completed, and t returns to zero.

8. The method for generating composite long mutual Z-complementary sets based on FPGA according to claim 5, characterized in that: The calculation formula of DFT is: in Therefore, re(n)=addr1×addr3-addr2×addr4; im(n)=addr2×addr3+addr1×addr4; Accumulate N results in the data buffer to get the final result:

9. A communication device, characterized in that FPGA-based composite long-term Z-complementary set, including the following modules: Data input module: responsible for data preparation and circular shift functions, using two dual-port ROMs; the first ROM has a 16-bit width and is used to store the real and imaginary parts of the initial sequence X. Let addr1 be the real part input address of the sequence, and addr2 be the imaginary part input address of the sequence; the second ROM has a 32-bit width and is used to store the real and imaginary parts of the rotation factor sequence. Let addr3 be the real part input address of the rotation factor, and addr4 be the imaginary part input address of the rotation factor; addr1, addr2, addr3, and addr4 all use the system clock clk1; DFT calculation module: mainly used to perform DFT operations, consisting of four multipliers, an adder, a subtractor and a data buffer; multiplier 1 is responsible for multiplying the real part of the sequence with the real part of the rotation factor, multiplier 2 multiplies the imaginary part of the sequence with the imaginary part of the rotation factor, multiplier 3 multiplies the imaginary part of the sequence with the real part of the rotation factor, and multiplier 4 multiplies the real part of the sequence with the imaginary part of the rotation factor; all operation units use the system clock clk1; Data output module: responsible for the output sequence, consisting of a frequency divider and an output unit. The frequency divider divides the system clock clk1 by N to generate a new output clock clk2. The output unit uses clk2 to output the generated mutual Z-complementary set in serial mode.

10. A method for generating a composite long mutual Z-complementary set based on FPGA according to any one of claims 1 to 8, characterized in that: The mutually Z-complementary set generated by the method can be used as a training sequence to enhance the performance of channel estimation in a spatial modulation multiple-input multiple-output (SM-MIMO) system. Specifically, in the SM-MIMO system, the transmitter transmits the training matrix composed of the mutually Z-complementary set to the receiver, and the receiver uses the excellent zero correlation zone characteristics of the training sequence to achieve a more accurate estimation of the system channel state.

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