Link test method, electronic device, storage medium, product and computing device

Abstract

The invention discloses a link test method, electronic equipment, a storage medium, a product and computing equipment, and is applied to the technical field of data transmission. The method comprises the following steps: determining to-be-tested equipment according to a to-be-tested link and a link training trigger condition; when the to-be-tested link finishes executing the link training operation and the link is recovered, determining a target register storing running state parameter information of the to-be-tested link in the to-be-tested device based on a link training trigger condition, and reading the running state parameter information; and when the link to be tested is diagnosed to have no fault according to the running state parameter information, executing the corresponding link training operation again based on the link training triggering condition. According to the method, the problems that related technologies depend on special tools, the starting time is long and the low-probability hardware fault reproduction period is long can be solved, the applicability is high, and the link testing efficiency can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a link testing method, electronic equipment, storage medium, product and computing equipment. Background Art

[0002] PCIe (perIPheral component interconnect express) is the largest interface on a computer motherboard. It is used to connect various components inside a computer, such as network cards, sound cards, discrete graphics cards, video capture cards, etc., so that data can be efficiently transmitted between these components and the processor.

[0003] In order to ensure server performance, related technologies use hardware debugging interfaces and professional software to verify the integrity of PCIe link signals in the laboratory during server development, and test the stability of the link by performing power-on and power-off cycle tests and restart tests on the entire machine. However, this testing method not only relies on special tools and has limited usage scenarios, but also has problems such as long startup time and long reproduction cycle of low-probability hardware failures.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The present invention provides a link testing method, electronic equipment, non-volatile storage medium, computer program product and computing equipment, which are independent of special tools, have strong applicability and can effectively improve link testing efficiency.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions: One aspect of the present invention provides a link testing method, comprising: The device to be tested is determined according to the link to be tested and the link training trigger condition; when the link to be tested completes the link training operation and the link is restored, based on the link training trigger condition, a target register storing the operating status parameter information of the link to be tested in the device to be tested is determined, and the operating status parameter information is read; when it is diagnosed that the link to be tested has no fault according to the operating status parameter information, the corresponding link training operation is performed again based on the link training trigger condition.

[0007] In a first exemplary embodiment, the device to be tested is determined based on the link to be tested and the link training trigger condition, including: obtaining a service module connected to the link to be tested and participating in executing user tasks; when the link training trigger condition is a cold reset or a warm reset, the device to be tested is each service module; when the link training trigger condition is a hot reset, the device to be tested is a service module that does not work at the physical layer.

[0008] In a second exemplary embodiment, based on the link training trigger condition, the target register storing the operating status parameter information of the link to be tested in the tested device is determined, and the operating status parameter information is read, including: when the link training trigger condition is a hot reset, controlling the baseboard management controller to obtain the register of the target business module working at the physical layer through a preset access command to obtain the operating status parameter information of the link to be tested stored in the target business module.

[0009] In a third exemplary embodiment, based on the link training trigger condition, a target register storing the operating status parameter information of the link to be tested in the device to be tested is determined, and the operating status parameter information is read, including: when the link training trigger condition is a cold reset or a warm reset, reading the operating data information of the link to be tested stored in the register of the device to be tested through a sideband signal; obtaining the number of recovery times and the link parameter value from the private register of the device to be tested; and using the operating data information, the number of recovery times and the link parameter value as the operating status parameter information of the link to be tested.

[0010] In a fourth exemplary embodiment, the link to be tested is a PCIe link to be tested, and based on the link training trigger condition, a target register storing operating status parameter information of the link to be tested in the device to be tested is determined, and the operating status parameter information is read, including: when the link training trigger condition is a hot reset, the operating data information of the link to be tested is read from the PCIe configuration space register of the device to be tested; a hardware information acquisition instruction is sent to a baseboard management controller to access a private register of the device to be tested by controlling the baseboard management controller; and the operating data information, the number of recovery times and the link parameter value stored in the private register are used as the operating status parameter information of the link to be tested.

[0011] In a fifth exemplary embodiment, it also includes: by comparing the operating status parameter information and the predicted normal operating status parameters, it is determined that there is a fault in the link to be tested, then an error message is generated, and log data corresponding to the current link training operation process is stored as test log data.

[0012] In a sixth exemplary embodiment, the corresponding link training operation is executed again based on the link training trigger condition, including: when the link training trigger condition is a cold reset, sending a power control signal to the device to be tested to control the device to be tested to perform a power-off and then power-on operation; after the link to be tested is restored, reading the operating status parameter information of the link to be tested under the current link training operation from the target register again, and diagnosing whether the link to be tested has a fault again based on the operating status parameter information, and repeating until a preset fault diagnosis stop condition is reached.

[0013] In a sixth exemplary embodiment, the corresponding link training operation is executed again based on the link training trigger condition, including: when the link training trigger condition is a warm reset, a reset operation signal is sent to the device to be tested to control the device to be tested to perform a reset and then a release reset operation; after the link to be tested is restored, the operating status parameter information of the link to be tested under the current link training operation is read again from the target register, and the link to be tested is diagnosed again based on the operating status parameter information whether there is a fault, and this is repeated until a preset fault diagnosis stop condition is reached.

[0014] In a seventh exemplary embodiment, the corresponding link training operation is executed again based on the link training trigger condition, including: when the link training trigger condition is a hot reset, the target application running under the operating system triggers the hot reset operation by setting the bridge control register of the device to be tested; after the link to be tested is restored, the operating status parameter information of the link to be tested under the current link training operation is read from the target register again, and the link to be tested is diagnosed again based on the operating status parameter information whether there is a fault, and this is repeated until a preset fault diagnosis stop condition is reached.

[0015] The present invention also provides an electronic device, comprising a processor, wherein the processor is used to implement the steps of the link testing method as described in any of the preceding ones when executing a computer program stored in a memory.

[0016] The present invention also provides a non-volatile storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the link testing method as described above are implemented.

[0017] The present invention also provides a computer program product, comprising a computer program / instruction, which implements the steps of the link testing method as described in any of the preceding ones when executed by a processor.

[0018] Finally, the present invention also provides a computing device, which at least includes a server, wherein the server includes a baseboard management controller, a central processing unit, a link training control processor and a first PCIe device; the first PCIe device is connected to the central processing unit via a PCIe bus as a business module for executing user tasks; the central processing unit and the baseboard management controller are located in the same network segment; wherein the baseboard management controller is connected to the first PCIe device and the central processing unit via a sideband signal, and is used to determine the PCIe device to be tested according to the PCIe link to be tested and the first type of link training trigger condition; when the PCIe link to be tested completes the link training operation and the link is restored, the target register storing the operating status parameter information of the PCIe link to be tested in the PCIe device to be tested is determined based on the first type of link training trigger condition, and the operating status parameter information is read; when it is diagnosed that the PCIe link to be tested has no fault according to the operating status parameter information, then Based on the first type of link training trigger condition, the corresponding link training operation is performed again; the first type of link training trigger condition includes cold reset or warm reset; the central processor is used to determine the PCIe device to be tested according to the PCIe link to be tested and the second type of link training trigger condition; when the PCIe link to be tested completes the link training operation and the link is restored, the target register storing the operating status parameter information of the PCIe link to be tested in the PCIe device to be tested is determined based on the second type of link training trigger condition, and the operating status parameter information is read; when it is diagnosed that the PCIe link to be tested has no fault according to the operating status parameter information, the corresponding link training operation is performed again based on the second type of link training trigger condition; the second type of link training trigger condition includes hot reset; the link training control processor is connected to the baseboard management controller, and is used to control the power and reset of the server, and meet the timing requirements of the first PCIe device and the central processor.

[0019] In the first exemplary embodiment, it also includes a network switch and a monitoring end; the network switch is connected to the baseboard management controller through a network port so that the monitoring end can remotely access the baseboard management controller; the monitoring end is used to obtain error data and test log data of the link to be tested during the link training operation from the baseboard management controller.

[0020] In a second exemplary embodiment, the baseboard management controller is also used for: when the link training trigger condition is a cold reset, powering off and powering on the PCIe device to be tested by controlling the register of the link training control processor; correspondingly, the central processing unit is also used for: when the link training trigger condition is a warm reset, resetting and releasing the reset operation on the PCIe device to be tested by controlling the register of the link training control processor.

[0021] The advantage of the technical solution provided by the present invention is that the corresponding link training is performed through different triggering scenarios of link establishment, and after the link is restored, the link stability and signal integrity are tested by performing link fault diagnosis according to the operating status parameter information read from the register. The total link establishment time is in the millisecond level. When the related technology performs link stability testing through power-on and power-off cycle testing and restart testing, the basic input and output system startup and operating system loading time are both in the minute level, so it can avoid the redundant waiting time in the PCIe link testing process of the related technology, especially for low-probability hardware failure problems and test scenarios that rely on long-cycle recurrence problems, greatly reducing the test time, improving the link stability verification efficiency, and effectively improving the link test efficiency. In addition, by performing link fault diagnosis according to the operating status parameter information read from the register after the link is restored, the problem of link training state machine testing relying on special tools is solved, and there is no requirement for the experience and professionalism of the operator. It is not only suitable for the laboratory stage, but also can be used in product testing and operation and maintenance scenarios, and has better applicability.

[0022] In addition, the present invention also provides corresponding electronic devices, non-volatile storage media, computer program products and computing devices for implementing the link testing method, further making the method more practical, and the electronic devices, non-volatile storage media, computer program products and computing devices have corresponding advantages.

[0023] The technical features mentioned above, the technical features to be mentioned below, and the technical features shown separately in the drawings can be arbitrarily combined with each other, as long as the combined technical features are not contradictory. All feasible feature combinations are technical contents clearly recorded in this article. Any of the multiple sub-features contained in the same sentence can be applied independently, and does not have to be applied together with other sub-features. It should be understood that the above general description and the detailed description below are only exemplary and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the present invention or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A schematic diagram of a link testing method provided by the present invention; Figure 2 A schematic diagram of a business module in an exemplary scenario provided by the present invention; Figure 3 A schematic diagram of the hot reset and de-reset process provided by the present invention; Figure 4 A structural diagram of an exemplary implementation of a link testing device provided by the present invention; Figure 5 A structural diagram of an exemplary embodiment of an electronic device provided by the present invention; Figure 6 A structural diagram of an exemplary implementation of a computing device provided by the present invention; Figure 7 A schematic diagram of a framework of a link testing method provided by the present invention in an exemplary application scenario; Figure 8 A flow chart of a link test method triggered by cold reset and warm reset provided by the present invention; Fig. 9 A schematic diagram of a framework of the link testing method provided by the present invention in another exemplary application scenario; Fig.10 A schematic flow chart of a link testing method under hot reset triggering provided by the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. Among them, the term "first" in the specification and the above-mentioned drawings is used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations of the two are intended to cover non-exclusive inclusions. The term "exemplary" means "used as an example, embodiment or illustrative". Any embodiment described here as "exemplary" is not necessarily interpreted as being superior or better than other embodiments.

[0027] With the advancement of high-performance graphics processors and neural network algorithms, artificial intelligence technology has developed rapidly and is widely used in various fields. The realization of artificial intelligence technology depends on a high-performance software and hardware environment, and requires the ability to quickly respond to, analyze, converge, and close the loop of software and hardware failures. PCIe is an interface that connects the graphics processor GPU with other components on the motherboard and is used to transmit data between the GPU and the server system. With the continuous increase in data transmission rates, in order to ensure the reliability of the PCIe link, link training is performed during the initialization of the PCIe link to determine the optimal data transmission parameters. If the link training fails, the server may not work properly. In addition, errors such as parity errors and cyclic redundancy check errors may occur in PCIe communication, which affect the stability and reliability of the server. For example, large models require ultra-large-scale distributed training clusters. If a single graphics processor fails during model training, the previously trained model will fail, which will undoubtedly extend the execution time of the task.

[0028] Related technologies In order to ensure the reliability of the PCIe link, the PCIe link will be tested in the laboratory stage during the server development process, including signal integrity verification, link training state machine switching verification and stability verification. Among them, the signal integrity verification and link training state machine switching verification of the PCIe link are verified by using manufacturer-specific tools. This method not only relies on hardware debugging interfaces and professional software, but also takes a long time and is highly professional. It requires high professional quality of operators and is only applicable to design verification in the laboratory stage. It cannot be used in whole machine scenarios such as production testing and computer room operation and maintenance. The stability verification of the PCIe link is achieved through power on and off cycle testing and restart testing. This method needs to wait for the BIOS (Basic Input Output System) and OS (Operating System) to start during the test process, and the BIOS startup and OS startup take a long time, especially for low-probability hardware failure problems, the reproduction cycle is long, and the corresponding problem solving and regression cycle is even longer.

[0029] In order to solve the problem of the time taken by the traditional power on / off cycle test and restart test in the related technology, and the problem that the link training state machine test relies on special tools and cannot be popularized in production testing and operation and maintenance scenarios, the present invention performs corresponding link training through different triggering scenarios of link establishment, and after the link is restored, the link fault diagnosis is performed according to the operating status parameter information read from the register to achieve the test of the stability and signal integrity of the link. It does not rely on special tools, has strong applicability, and can effectively improve the efficiency of link testing. After introducing the technical scheme of the present invention, various non-limiting embodiments of the present invention are described in detail below. In order to better illustrate the present invention, numerous specific details are given in the specific embodiments below. Those skilled in the art should understand that the present invention can also be implemented without these specific details. In other examples, the methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present invention.

[0030] First see Figure 1 , Figure 1 A flowchart of a link testing method provided in this embodiment may include the following contents: S101: Determine a device to be tested according to a link to be tested and a link training trigger condition.

[0031] Among them, the link is the communication path in the data transmission process, and the link to be tested is the link that needs to detect whether there is a problem in the data communication path between the communication nodes. The link can be based on any bus protocol, including but not limited to the PCIe bus protocol, CAN (Controller Area Network, Controller Area Network Bus), I2C (Inter-Integrated Circuit, Integrated Circuit Bus) protocol. Correspondingly, the link to be tested is a PCIe link to be tested, a CAN link to be tested, and an I2C link to be tested. Link training can ensure the stability and efficiency of high-speed data transmission. Through training, the link can determine the best signal quality and transmission rate, thereby optimizing the data transmission performance. In order to verify the link performance, this embodiment needs to obtain some operating status data during the link training process. Link training is a hardware process controlled by the physical layer. After the computer system or server system is reset, the hardware will automatically start the link training process, and the process is managed by LTSSM (Link Training and Status Machine). The process configures and initializes the port and link of the device to support subsequent data transmission. There are many ways to reset the system at present. According to the different manifestations of link problems under different reset methods, the variables or directions followed by the problems can be obtained. Based on this, the present invention tests the link according to the link training trigger conditions of different devices connected to the link to be tested. According to the different link training trigger conditions, it can be divided into hot reset, warm reset and cold reset. Among them, the hot reset is triggered by the in-band TS (Training Sequence, signal transmission sequence) sequence, and no other hardware signal changes are required. The warm reset triggers the bus port reset through the external PERST_N (global reset signal) signal and re-establishes the link). The cold reset powers off the bus device and then powers it on. The device is completely reset and the firmware is reloaded.

[0032] In this embodiment, the link to be tested refers to a PCIe link that needs to be tested. The link to be tested is connected to multiple business modules that participate in executing the business through a corresponding bus. The business modules include but are not limited to a central processing unit, a bus switch such as a PCIe switch, a retimer, a graphics processor, a network card, and a hard disk. These business modules are connected to the link through a corresponding bus. The link to be tested includes at least two devices to be tested, that is, devices located at both ends of the link to be tested. Since the registers of the devices to be tested connected to the link to be tested store data that can reflect the link status, the methods of reading the registers of the devices are different under different reset modes. This step needs to determine the devices to be read under different link training trigger conditions and define them as devices to be tested. That is, the device to be tested refers to a business module connected to the link to be tested and participating in executing the business, and this business module can directly read the corresponding register data under the corresponding reset mode.

[0033] S102: After the link to be tested completes the link training operation and the link is restored, based on the link training trigger condition, a target register storing the operating status parameter information of the link to be tested in the device to be tested is determined, and the operating status parameter information is read.

[0034] In order to identify whether there is a fault in the link to be tested, it is necessary to obtain relevant data reflecting the status of the link to be tested. The present invention obtains these data by performing a link training operation on the link to be tested. Accordingly, whenever it is detected that the link training operation is completed and the link to be tested is restored, or it is detected that the link to be tested completes the link training operation and the link is restored according to a fixed frequency or a preset triggering method, a register storing the operating status parameter information of the link to be tested is determined. For the convenience of description, it is defined as a target register, and the operating status parameter information of the link to be tested at the current moment, that is, the link training process, is read therefrom. The operating status parameter information includes but is not limited to the bandwidth, rate, recoverable error, unrecoverable error, lane (channel) where the error is located, recovery times, and link parameter values ​​of the link to be tested.

[0035] S103: When it is diagnosed according to the operating status parameter information that the link to be tested has no fault, the corresponding link training operation is performed again based on the link training trigger condition.

[0036] When the operating status parameter information is obtained in the previous step, it is compared with the corresponding data when the link to be tested has no fault, so as to identify that the link to be tested has no fault at the current moment, that is, during this link training process. Exemplarily, the standard value or standard range corresponding to each type of data contained in the operating status parameter information can be pre-set. The operating status parameter information under the standard value or standard range indicates that the current link is running normally. For the convenience of description, it can be defined as a predicted normal operating state parameter, and there is no fault. By comparing the two, it can be quickly identified whether the link to be tested has a fault. When it is determined that the operating status parameter information diagnoses that the link to be tested has no fault, the link to be tested is triggered again according to the link training trigger condition to perform link training, and then jump to execute S102. Exemplarily, when it is determined that the link to be tested has a fault by comparing the operating status parameter information and the predicted normal operating state parameter, an error message is generated, and the log data corresponding to the current link training operation process is stored as test log data. That is to say, when it is determined that the operating status parameter information diagnoses that there is a fault in the link to be tested, an error can be reported and the log data can be exported for subsequent use. If the link to be tested is a PCIe link to be tested, it can be used for subsequent PCIe link fault analysis and PCIe link operation and maintenance recovery.

[0037] In the technical solution provided in this embodiment, corresponding link training is performed through different triggering scenarios of link establishment, and after the link is restored, link fault diagnosis is performed according to the operating status parameter information read from the register to achieve the test of link stability and signal integrity. The total link establishment time is in milliseconds. When the related technology performs link stability testing through power-on and power-off cycle testing and restart testing, the basic input and output system startup and operating system loading time are both in minutes. Therefore, it is possible to avoid the redundant waiting time in the PCIe link testing process of the related technology, especially for low-probability hardware failure problems and test scenarios that rely on long-cycle recurrence problems, greatly reducing the test time, improving the efficiency of link stability verification, and effectively improving the efficiency of link testing. In addition, by performing link fault diagnosis according to the operating status parameter information read from the register after the link is restored, the problem of link training state machine testing relying on special tools is solved, and there is no requirement for the experience and professionalism of the operator. It is not only suitable for the laboratory stage, but also can be used in product testing and operation and maintenance scenarios, and has better applicability.

[0038] In the above embodiment, there is no limitation on how to determine the device to be tested. The present invention also provides an exemplary implementation method, which may include the following contents: Acquire the service modules connected to the link to be tested and participating in executing user tasks; when the link training trigger condition is cold reset or warm reset, the devices to be tested are the service modules; when the link training trigger condition is hot reset, the devices to be tested are service modules that do not work at the physical layer.

[0039] This embodiment determines the device to be tested according to different link training trigger conditions. Figure 2 For example, the central processing unit, PCIe switch, retimer, and graphics processor are business modules, which are interconnected through the PCIe bus and are PCIe devices of the server or computer system. When the link to be tested is the PCIe link between the central processing unit and the PCIe switch, the business modules are the central processing unit and the PCIe switch. In the case of cold reset, warm reset, or hot reset, the device to be tested is the central processing unit and the PCIe switch. When the link to be tested is the PCIe link between the PCIe switch and the graphics retimer processor, the business modules are the PCIe switch, retimer, and graphics processor. Since they work at the physical layer and have no configuration space, they are not visible to the OS. For cold reset or warm reset, the devices to be tested are the PCIe switch, retimer, and graphics processor. For hot reset, the devices to be tested are the PCIe switch and graphics processor.

[0040] As can be seen from the above, this embodiment determines the device to be tested for reading the operating status parameter information according to different resets, which is beneficial to improving the diagnosis accuracy and efficiency of the link.

[0041] In the above embodiment, there is no limitation on how to determine the device to be tested to read the operating status parameter information. The present invention also provides an exemplary implementation method, which may include the following contents: Based on the above embodiment, when the link training trigger condition is a cold reset or a warm reset, the operation data information of the link to be tested stored in the register of the device to be tested is read through the sideband signal; the number of recovery times and the link parameter value are obtained from the private register of the device to be tested; the operation data information, the number of recovery times and the link parameter value are used as the operation status parameter information of the link to be tested. When the link training trigger condition is a hot reset, the operation data information of the link to be tested is read from the PCIe configuration space register of the device to be tested; a hardware information acquisition instruction is sent to the baseboard management controller to access the private register of the device to be tested by controlling the baseboard management controller; the operation data information, the number of recovery times and the link parameter value stored in the private register are used as the operation status parameter information of the link to be tested. In order to ensure accurate diagnosis of the state of the tested PCIe link, for the business module located at the physical layer under hot reset, such as the retimer, the baseboard management controller can be controlled by a preset access command to obtain the register of the target business module working at the physical layer to obtain the operation status parameter information of the link to be tested stored in the target business module. The preset access command may be a pre-set command capable of accessing and controlling the BMC, and the operating status parameter information of the business module is obtained by using an in-band access out-of-band method.

[0042] In this embodiment, the link to be tested is a PCIe link. For cold reset or warm reset, data is read out-of-band. The PCIe device register out-of-band acquisition tool can be pre-integrated to read the register of the device to be tested through the sideband signal, and the basic information of the current link bandwidth, rate, recoverable error, unrecoverable error, lane where the error is located, etc. of the link to be tested is read from the register. If the device to be tested also includes a private register, the number of recovery times and link parameter values ​​are also read from the private register accordingly, and the read basic information and the private information are compared with the preset standard value or standard range to determine whether an error occurs. For hot reset, data is read in-band. The application running on the operating system obtains the PCIe configuration space register of the device to be tested, and reads the basic information of the current link bandwidth, rate, recoverable error, unrecoverable error, lane where the error is located, etc. If the device under test has private registers, the application under the OS can access the BMC through IP (Internet Protocol). The hardware information acquisition instruction can be, for example, an IPMI command. The IPMI command can be sent to the BMC through IP to control the BMC to access the private registers of the device under test and read private information such as the number of recovery times and link parameters therefrom. The read configuration space information and the private information are compared with the preset value to determine whether an error occurs.

[0043] As can be seen from the above, this embodiment uses a matching method based on different reset modes to read data stored in multiple registers for each device connected to the link to be tested, which is beneficial to improving the diagnosis accuracy and efficiency of the link.

[0044] The above embodiment does not limit how to perform the corresponding link training operation again based on the link training trigger condition. Based on the above embodiment, the present invention also provides a link training operation implementation method under different reset conditions, which may include the following contents: When the link training trigger condition is a cold reset, a power control signal is sent to the device under test to control the device under test to perform a power-off and then power-on operation; after the link under test is restored, the operating status parameter information of the link under test under the current link training operation is read from the target register again, and the link under test is diagnosed again based on the operating status parameter information whether there is a fault, and this is repeated until the preset fault diagnosis stop condition is reached.

[0045] When the link training trigger condition is a warm reset, a reset operation signal is sent to the device under test to control the device under test to perform a reset and then a release reset operation; after the link under test is restored, the operating status parameter information of the link under test under the current link training operation is read from the target register again, and the link under test is diagnosed again based on the operating status parameter information whether there is a fault, and this is repeated until the preset fault diagnosis stop condition is reached.

[0046] When the link training trigger condition is a hot reset, the target application running under the operating system triggers a hot reset operation by setting the bridge control register of the link to be tested; after the link to be tested is restored, the operating status parameter information of the link to be tested under the current link training operation is read from the target register again, and the link to be tested is diagnosed again based on the operating status parameter information whether there is a fault, and this is repeated until the preset fault diagnosis stop condition is reached.

[0047] In this embodiment, for cold reset, if the current diagnosis is normal and there is no error, the device to be tested is controlled to be powered off and then powered on, and the operating status parameter information stored in the register of the device to be tested is obtained again after the link is restored, that is, S102-S103 is repeatedly executed until the preset fault diagnosis stop condition is reached, and the preset fault diagnosis stop condition can be, for example, the number of test laps reaches the preset number of laps. For warm reset, if the current diagnosis is normal and there is no error, the device to be tested can be controlled to be reset first, then un-reset, and the operating status parameter information stored in the register of the device to be tested is obtained again after the link is restored, that is, S102-S103 is repeatedly executed until the preset fault diagnosis stop condition is reached. For hot reset, if the current diagnosis is normal and there is no error, the application triggers hot reset by setting the bridge control register of the device to be tested, and the operating status parameter information stored in the register of the device to be tested is obtained again after the PCIe link is restored, that is, S102-S103 is repeatedly executed until the preset fault diagnosis stop condition is reached.

[0048] Exemplarily, the Bridge Control Register is a register used to control and manage the behavior of the PCI (PerIPheral Component Interconnect) bridge. A hot reset can be achieved by first triggering the Bridge Control Register {Bit 6 of Bridge Control Register (Offset 0x3E)}, and the application can write 1 to the Secondary Bus Reset bit in the Bridge Control Register to trigger a hot reset. Use the command setpci -s 00:01.1 3E.B=40 to set the Secondary Bus Reset bit to 1, and then use the lspci command to check whether the modification in the Bridge Control Register is successful. A hot reset is triggered by sending a TS1 ordered set, which is sent simultaneously on all valid channels (Lane) and lasts for at least 2ms. The device under test performs a hot reset after receiving two consecutive TS1 ordered sets. After the hot reset is triggered, if Figure 3Steps ① and ②: The link state machine will first enter the recovery state, then the hot reset state, and finally return to the detection state and restart the link initialization training. Figure 3 Steps ③④⑤⑥⑦⑧: Set the Secondary Bus Reset bit back to 0 through the application to exit the hot reset state. Use the command setpci -s 00:01.1 3E.B=00 to clear the Secondary Bus Reset bit to end the hot reset. After the hot reset is completed, the link state machine will return from the hot reset state to the detection state, and the link will restart the initialization training. Use diagnostic tools such as the lspci command to check the status of the device under test to ensure that the device has resumed normal operation and the link has been successfully reinitialized. If all state machines, hardware logic, port status, and configuration registers of the device under test have specific configurations before reset, it is necessary to ensure that these configurations are restored after the reset so that the device under test can work as expected, ensure the diagnostic accuracy and efficiency of the link, and thus improve the efficiency of link testing.

[0049] As can be seen from the above, this embodiment avoids the invalid time of BIOS startup and OS startup through out-of-band diagnosis, saves link test time, and improves link verification efficiency. The in-band hot reset diagnosis method avoids the reliance on special tools for link training state machine testing, and can be used in product testing and operation and maintenance scenarios. The entire process can be tested in multiple scenarios and multiple laps, increasing the sample size and ensuring the stability and consistency of large-scale server and computer system production.

[0050] The present invention also provides a corresponding device for the link testing method, which further makes the method more practical. Among them, the device can be described from the perspective of functional modules and hardware respectively. The link testing device provided by the present invention is introduced below. The device is used to implement the link testing method provided by the present invention. In this embodiment, the link testing device may include or be divided into one or more program modules, and the one or more program modules are stored in a storage medium and executed by one or more processors to complete the link testing method disclosed in Example 1. The program module referred to in this embodiment refers to a series of computer program instruction segments that can complete specific functions, which is more suitable for describing the execution process of the link testing device in the storage medium than the program itself. The following description will specifically introduce the functions of each program module of this embodiment. The link testing device described below and the link testing method described above can be referenced to each other.

[0051] From the perspective of functional modules, see Figure 4 , Figure 4 The structure diagram of the link test device provided in this embodiment in a specific implementation manner, the device may include: The device determination module 401 is used to determine the device to be tested according to the link to be tested and the link training trigger condition.

[0052] The status data reading module 402 is used to determine the target register storing the operating status parameter information of the link under test in the device under test based on the link training trigger condition after the link under test completes the link training operation and the link is restored, and read the operating status parameter information.

[0053] The link testing module 403 is configured to execute the corresponding link training operation again based on the link training triggering condition when it is diagnosed according to the operation status parameter information that the link to be tested has no fault.

[0054] Exemplarily, in some implementations of this embodiment, the above-mentioned device determination module 401 can also be used to: obtain the service module connected to the link to be tested and involved in executing user tasks; when the link training trigger condition is a cold reset or a warm reset, the device to be tested is each service module; when the link training trigger condition is a hot reset, the device to be tested is a service module that does not work at the physical layer.

[0055] As an illustrative implementation of the above embodiment, the above status data reading module 402 can also be used for: when the link training trigger condition is a hot reset, the baseboard management controller is controlled through a preset access command to obtain the register of the target business module working at the physical layer, so as to obtain the operating status parameter information of the link to be tested stored in the target business module.

[0056] Exemplarily, in some other implementations of this embodiment, the above-mentioned status data reading module 402 can also be used for: when the link training trigger condition is a cold reset or a warm reset, reading the operation data information of the link to be tested stored in the register of the device to be tested through the sideband signal; obtaining the number of recovery times and link parameter values ​​from the private register of the device to be tested; and using the operation data information, the number of recovery times and the link parameter values ​​as the operation status parameter information of the link to be tested.

[0057] Exemplarily, in some other implementations of the present embodiment, the above-mentioned status data reading module 402 can also be used for: when the link training trigger condition is a hot reset, reading the operation data information of the link to be tested from the PCIe configuration space register of the device to be tested; sending a hardware information acquisition instruction to the baseboard management controller to access the private register of the device to be tested by controlling the baseboard management controller; using the operation data information, the number of recovery times stored in the private register and the link parameter value as the operation status parameter information of the link to be tested.

[0058] Exemplarily, in some other implementations of this embodiment, the above-mentioned device may also include a fault diagnosis module, which is used to determine whether there is a fault in the link to be tested by comparing the operating status parameter information and the predicted normal operating status parameters, then generate an error message, and store the log data corresponding to the current link training operation process as test log data.

[0059] Exemplarily, in some other implementations of the present embodiment, the link test module 403 can also be used for: when the link training trigger condition is a cold reset, sending a power control signal to the device to be tested to control the device to be tested to perform a power-off and then power-on operation; after the link to be tested is restored, reading the operating status parameter information of the link to be tested under the current link training operation from the target register again, and diagnosing whether there is a fault in the link to be tested again based on the operating status parameter information, and repeating until the preset fault diagnosis stop condition is reached.

[0060] Exemplarily, in some other implementations of this embodiment, the above-mentioned link test module 403 can also be used for: when the link training trigger condition is a warm reset, sending a reset operation signal to the device to be tested to control the device to be tested to perform an operation of first resetting and then releasing the reset; after the link to be tested is restored, reading the operating status parameter information of the link to be tested under the current link training operation from the target register again, and diagnosing whether there is a fault in the link to be tested again based on the operating status parameter information, and repeating until the preset fault diagnosis stop condition is reached.

[0061] Exemplarily, in some other implementations of this embodiment, the above-mentioned link test module 403 can also be used for: when the link training trigger condition is a hot reset, the target application running under the operating system triggers the hot reset operation by setting the bridge control register of the device to be tested; after the link to be tested is restored, the operating status parameter information of the link to be tested under the current link training operation is read from the target register again, and the link to be tested is diagnosed again based on the operating status parameter information whether there is a fault, and this is repeated until the preset fault diagnosis stop condition is reached.

[0062] The link test device mentioned above is described from the perspective of functional modules. Furthermore, the present invention also provides an electronic device, which is described from the perspective of hardware. Figure 5 The following is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention in one implementation manner. Figure 5 As shown, the electronic device includes a memory 50 for storing a computer program; and a processor 51 for implementing the steps of the link testing method mentioned in any of the above embodiments when executing the computer program.

[0063] Among them, the processor 51 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the processor 51 may also be a controller, a microcontroller, a microprocessor or other data processing chip. The processor 51 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 51 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 51 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 51 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0064] The memory 50 may include one or more computer non-volatile storage media, which may be non-transitory. The memory 50 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the memory 50 may be an internal storage unit of an electronic device, such as a hard disk of a server. In other embodiments, the memory 50 may also be an external storage device of an electronic device, such as a plug-in hard disk equipped on a server, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. Further, the memory 50 may also include both an internal storage unit and an external storage device of the electronic device. The memory 50 may not only be used to store application software and various types of data installed in the electronic device, such as: the code of the program in the process of executing the link test method, etc., but also be used to temporarily store data that has been output or is to be output. In this embodiment, the memory 50 is at least used to store the following computer program 501, wherein, after the computer program is loaded and executed by the processor 51, the relevant steps of the link test method disclosed in any of the aforementioned embodiments can be implemented. In addition, the resources stored in the memory 50 may also include an operating system 502 and data 503, and the storage method may be temporary storage or permanent storage. The operating system 502 may include Windows, Unix, Linux, etc. The data 503 may include but is not limited to data corresponding to the link test result.

[0065] In some embodiments, the electronic device may further include a display screen 52, an input / output interface 53, a communication interface 54 or a network interface, a power supply 55 and a communication bus 56. Among them, the display screen 52 and the input / output interface 53, such as a keyboard, belong to the user interface, and exemplary user interfaces may also include standard wired interfaces, wireless interfaces, etc. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, and an OLED (Organic Light-Emitting Diode) touch device, etc. The display may also be appropriately referred to as a display screen or a display unit, which is used to display information processed in the electronic device and to display a visual user interface. The communication interface 54 may exemplarily include a wired interface and / or a wireless interface, such as a WI-FI interface, a Bluetooth interface, etc., which are generally used to establish a communication connection between the electronic device and other electronic devices. The communication bus 56 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0066] Those skilled in the art will understand that Figure 5 The structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than those shown in the figure, for example, it may also include a sensor 57 for realizing various functions.

[0067] It is understandable that if the link test method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile storage medium. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the relevant technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes but is not limited to: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, multimedia card, card-type memory (such as SD or DX memory, etc.), magnetic memory, removable disk, CD-ROM, magnetic disk or optical disk, etc. Various media that can store program codes. Based on this, the present invention also provides a non-volatile storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the link test method recorded in any of the above embodiments are performed.

[0068] It is understandable that if the link test method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, the computer software product does not need to be stored in a physical storage medium. For example, it can be directly transmitted to a computer or other device with information processing capabilities through a wired network or a wireless network to perform all or part of the steps of the methods of each embodiment of the present invention. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the relevant technology or all or part of the technical solution can be embodied in the form of a software product. Based on this, the present invention also provides a computer program product that stores a computer program. When the computer program is executed by a processor, the steps of the link test method recorded in any of the above embodiments are performed.

[0069] Finally, considering that the PCIe link establishment process of the server is more likely to reproduce the PCIe hardware failure problem, this embodiment targets three triggering scenarios of PCIe link establishment, namely cold reset, warm reset and hot reset, and completes the PCIe link test through the out-of-band diagnosis method of the BMC of the server and the in-band diagnosis method of the CPU, thereby solving the problem that the BIOS startup and OS startup take a long time in the whole system power cycle test and the whole system restart test, and the link training state machine test relies on special tools and cannot be popularized in production testing and operation and maintenance scenarios. The present invention also provides a computing device, which at least includes a server, such as Figure 6 As shown, it may include the following: The server of the present invention at least includes a baseboard management controller 601, namely BMC601, a central processing unit 602, namely CPU602, a link training control processor 603 and a first PCIe device 604. The first PCIe device 604 is connected to the central processing unit 602 through a PCIe bus. As a business module for executing user tasks, the first PCIe device 604 is a PCIe device, such as a hard disk, a network card, a PCIe switch, a retimer and a graphics processor. The server may include multiple PCIe devices. This embodiment takes the first PCIe device 604 and the CPU as two PCIe devices as examples; the central processing unit 602 and the baseboard management controller 601 are located in the same network segment so that the application under the OS can remotely access the BMC through IP. The total link establishment time of the PCIe link is in milliseconds, and the BIOS startup and OS loading are in minutes, avoiding unnecessary waiting time in out-of-band diagnosis. For devices connected to the downstream ports of PCIe switches, firmware loading and link establishment are very fast, with waiting time at the millisecond level, which can be set according to the actual verification value. For PCIe devices attached to the central processor, the waiting time is at the second level, which can be set according to the actual verification value, and is limited by the BIOS startup and PCIe initialization time points.

[0070] In this embodiment, for cold reset and warm reset, a baseboard management controller 601 is used as an execution and control unit. BMC601 can be pre-integrated with an out-of-band acquisition tool for PCIe device registers. The baseboard management controller is connected to the first PCIe device and the central processing unit through a sideband signal, and is used to determine the device to be tested according to the link to be tested and the first type of link training trigger condition; when the link to be tested completes the link training operation and the link is restored, the target register storing the operating status parameter information of the link to be tested in the device to be tested is determined based on the first type of link training trigger condition, and the operating status parameter information is read; when the link to be tested is diagnosed to have no faults based on the operating status parameter information, the corresponding link training operation is performed again based on the first type of link training trigger condition; the first type of link training trigger condition includes cold reset or warm reset. Correspondingly, the baseboard management controller is also used to: when the link training trigger condition is a cold reset, the device to be tested is powered off and powered on by controlling the register of the link training control processor. For hot reset, CPU602 is used as the execution and control unit. When the first PCIe device 604 and CPU602 are started normally and CPU602 has completed OS loading, the central processing unit is used to determine the device to be tested according to the link to be tested and the second type of link training trigger conditions; when the link to be tested completes the link training operation and the link is restored, the target register storing the operating status parameter information of the link to be tested in the device to be tested is determined based on the second type of link training trigger conditions, and the operating status parameter information is read; when the link to be tested is diagnosed to have no faults according to the operating status parameter information, the corresponding link training operation is performed again based on the second type of link training trigger conditions; the second type of link training trigger conditions include hot reset. Correspondingly, the central processing unit is also used to reset and release the device to be tested by controlling the registers of the link training control processor when the link training trigger condition is a warm reset.

[0071] The link training control processor 603 is connected to the baseboard management controller 601, and is used to control the power supply and reset of the server, and meet the timing requirements of the first PCIe device 604 and the central processor 602. The link training control processor 603 can be any device that supports programmable control, such as CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array), which does not affect the implementation of the present invention.

[0072] As can be seen from the above, this embodiment performs corresponding link training through different triggering scenarios of PCIe link establishment of the server, and after the link is restored, the server PCIe link fault diagnosis is performed according to the operating status parameter information read from the register to achieve the stability and signal integrity test of the server PCIe link. The total link establishment time of the server PCIe link is in milliseconds. When the related technology performs link stability test through power-on and power-off cycle test and restart test, the basic input and output system startup and operating system loading time are both in minutes, so it can avoid the redundant waiting time in the PCIe link test process, especially for low-probability hardware failure problems and test scenarios that rely on long-cycle recurrence problems, greatly reducing the test time, improving the efficiency of PCIe link stability verification, and effectively improving the efficiency of PCIe link testing. In addition, by performing PCIe link fault diagnosis according to the operating status parameter information read from the register after the link is restored, the problem of link training state machine test relying on special tools is solved, and there is no requirement for the experience and professionalism of the operator. It is not only suitable for the laboratory stage, but also can be used in product testing and operation and maintenance scenarios, and has better applicability.

[0073] In order to improve the efficiency of link testing, based on the above embodiment, the computing device may also include a network switch and a monitoring end; the network switch is connected to the baseboard management controller through a network port so that the monitoring end can remotely access the baseboard management controller; the monitoring end is used to obtain error data and test log data of the link to be tested during the link training operation from the baseboard management controller.

[0074] In order to make the technical solution of the present invention more clear to those skilled in the art, the present invention takes the link to be tested as a PCIe link, the service module includes a central processing unit, a PCIe switch, a retimer, and a graphics processor, each service module is connected through a PCIe bus, the link training control processor 603 is a CPLD, and the monitoring end is a monitoring computer as an example to illustrate the link testing method, which may include the following contents:

[0075] like Figure 7As shown, for the scenario where the link training trigger condition includes cold reset or warm reset, the baseboard management controller is connected to the central processing unit, PCIe switch, retimer, graphics processor, and CPLD through I2C (Inter-Integrated Circuit). The baseboard management controller integrates the out-of-band access tool of the registers of each PCIe device, that is, the central processing unit, PCIe switch, retimer, and graphics processor. Through this tool, the registers defined in the PCIe specification of different PCIe devices and the private registers defined by different chip manufacturers can be obtained through preset commands. The BMC includes an RGMII (Reduced Gigabit Media Independent Interface) interface, which is connected to the network chip through the interface. The network chip is connected to the network switch through the DMI (Direct Media Interface), and is connected to the monitoring computer through the network switch, so that it can be accessed by the monitoring computer through an IP connection. The CPLD is connected to the power line through a sideband signal to control the power supply of the entire machine and each PCIe device. CPLD controls the platform reset signal of each business module through independent GPIO (General-PurpOSe Input / Output). For easy distinction, the reset signals of the central processing unit, PCIe switch, retimer, and graphics processor can be defined as PERST_N, PERST_SW_N, PERST_RT_N, and PERST_GPU_N respectively. The baseboard management controller accesses the programmable logic device register through I2C to flexibly control the platform reset signal and power supply of the PCIe device. Figure 8As shown, an out-of-band diagnostic script can be stored in the BMC in advance, and the out-of-band diagnostic script can be started to determine the PCIe device to be tested according to the PCIe link to be tested. If the link between the central processor and the PCIe switch is diagnosed, the PCIe devices to be tested are the central processor and the PCIe switch. If the PCIe link between the PCIe switch and the graphics processor is diagnosed, the PCIe devices to be tested are the PCIe switch, the retimer and the graphics processor. The BMC reads the register of the PCIe device to be tested through the sideband signal, and reads the basic information such as the bandwidth, rate, recoverable error, unrecoverable error, and lane where the error is located of the current link; it can also read the number of recovery times and link parameter values ​​from the private register of the PCIe device to be tested. Compare the basic information and private information with the preset predicted normal operating state parameters to determine whether the PCIe link to be tested has an error. For cold reset, if the current PCIe link to be tested is normal and there is no error, the BMC controls the CPLD register through I2C to control the PCIe device to be tested to power off and then power on, wait for the PCIe link to be restored and then obtain the register of the PCIe device to be tested again, and repeat the process until the preset number of cycles is reached. For warm reset, if the PCIe link to be tested is normal and there is no error, the BMC controls the CPLD register through I2C to control the PCIe device to be tested to reset first and then release the reset, wait for the link to be restored and then obtain the register of the PCIe device to be tested again, and repeat the process until the preset number of cycles is reached. If the diagnosis of the current PCIe link to be tested is an error, end the diagnosis, save the test log, and exit the out-of-band diagnosis script; remotely access the BMC through the monitoring computer, view the error information, and export the test log.

[0076] like Fig. 9 As shown, for the scenario where the link training trigger condition includes a hot reset, the baseboard management controller is connected to the central processor, PCIe switch, retimer, and graphics processor through I2C, the central processor is connected to the PCIe switch through the root complex (RootComplex) and the PCIe bus, the downstream port of the PCIe switch is connected to the retimer through the PCIe bus, the retimer is connected to the graphics processor through the PCIe bus, the BMC is connected to the DMI interface of the physical layer through the RGMII interface, the communication lead-out terminal RJ45 is connected to the network switch, and is connected to the monitoring computer through the network switch, so that it can be accessed by the monitoring computer through an IP connection. The central processor is connected to the DMI interface of the network card through USB (Universal Serial Bus) and is connected to the network switch through the communication lead-out terminal RJ45, so that the BMC and the CPU are in the same network segment. When each PCIe device, that is, the central processor, PCIe switch, retimer, and graphics processor are started normally, the BIOS starts the system and completes the OS loading, as shown in Fig.10 As shown, the in-band diagnostic script can be stored in the OS in advance, and the in-band diagnostic script can be started to determine the PCIe device to be tested according to the PCIe link to be tested. If the link between the central processor and the PCIe switch is diagnosed, the PCIe devices to be tested are the central processor and the PCIe switch. If the PCIe link between the PCIe switch and the graphics processor is diagnosed, since the retimer works at the physical layer, there is no configuration space and it is invisible to the OS, the PCIe devices to be tested are the PCIe switch and the graphics processor. The application running in the operating system obtains the PCIe configuration space register of the PCIe device to be tested, and reads the basic information such as the bandwidth, rate, recoverable error, unrecoverable error, and lane where the error is located of the current link; it can also send IPMI commands to the BMC through IP to control the BMC to access the private register of the PCIe device to read the recovery times and link parameter values. The basic information and private information are compared with the preset predicted normal operation status parameters to determine whether the PCIe link to be tested is wrong. If the current PCIe link to be tested is normal and there is no error, the application triggers a hot reset through the set bridge control register, waits for the PCIe link to recover, and then obtains the configuration space register of the PCIe device to be tested again, repeating the process until the preset number of cycles is reached. If the diagnosis of the current PCIe link to be tested is an error, the diagnosis ends, the test log is saved, and the in-band diagnostic script is exited; the BMC is remotely accessed through the monitoring computer, the error information is checked, and the test log is exported.

[0077] From the above, it can be seen that this embodiment completes the PCIe link diagnosis through out-of-band diagnostic scripts and in-band diagnostic scripts, effectively avoiding the invalid time of BIOS startup and OS startup, and also avoiding the problem that the link training state machine test relies on special tools and cannot be popularized in product testing and operation and maintenance scenarios, thereby effectively improving the link testing efficiency.

[0078] The link testing method, electronic device, non-volatile storage medium, computer program product and computing device provided by the present invention are introduced in detail above. The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can refer to each other. The units and algorithm steps of each example described in each disclosed embodiment are executed in electronic hardware or computer software depending on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods for each specific application to implement the described functions, and such implementation should not be considered to exceed the scope of the present invention. Without departing from the principles of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A link testing method, characterized in that: include: Determine the device to be tested according to the link to be tested and the link training trigger condition; After the link to be tested completes the link training operation and the link is restored, based on the link training trigger condition, determining a target register in the device to be tested that stores the operating status parameter information of the link to be tested, and reading the operating status parameter information; When it is diagnosed that the link to be tested has no fault according to the operation status parameter information, the corresponding link training operation is performed again based on the link training trigger condition.

2. The link testing method according to claim 1, characterized in that: Determine the device to be tested based on the link to be tested and the link training trigger conditions, including: Acquire a service module connected to the link to be tested and participating in executing a user task; When the link training trigger condition is a cold reset or a warm reset, the device to be tested is each service module; When the link training trigger condition is a hot reset, the device to be tested is a service module that does not operate at the physical layer.

3. The link testing method according to claim 2, characterized in that: Based on the link training trigger condition, determining a target register in the device to be tested that stores the operating status parameter information of the link to be tested, and reading the operating status parameter information, including: When the link training trigger condition is a hot reset, the baseboard management controller is controlled through a preset access command to obtain the register of the target service module working at the physical layer, so as to obtain the operating status parameter information of the link to be tested stored in the target service module.

4. The link testing method according to claim 1, characterized in that: Based on the link training trigger condition, determining a target register in the device to be tested that stores the operating status parameter information of the link to be tested, and reading the operating status parameter information, including: When the link training trigger condition is a cold reset or a warm reset, reading the operation data information of the link to be tested stored in the register of the device to be tested through a sideband signal; Acquire the number of recovery times and link parameter values ​​from the private register of the device to be tested; The operation data information, the number of recovery times and the link parameter value are used as the operation status parameter information of the link to be tested.

5. The link testing method according to claim 1, characterized in that: The link to be tested is a PCIe link to be tested, and based on the link training trigger condition, a target register storing the operating status parameter information of the link to be tested in the device to be tested is determined, and the operating status parameter information is read, including: When the link training trigger condition is a hot reset, reading the operation data information of the link to be tested from the PCIe configuration space register of the device to be tested; Sending a hardware information acquisition instruction to a baseboard management controller to access a private register of the device to be tested by controlling the baseboard management controller; The operation data information, the number of recovery times stored in the private register, and the link parameter value are used as the operation status parameter information of the link to be tested.

6. The link testing method according to claim 1, characterized in that: Also includes: By comparing the operating status parameter information with the predicted normal operating status parameters, it is determined that the link to be tested has a fault, then an error message is generated, and log data corresponding to the current link training operation process is stored as test log data.

7. The link testing method according to any one of claims 1 to 6, characterized in that: Executing the corresponding link training operation again based on the link training trigger condition includes: When the link training trigger condition is a cold reset, sending a power control signal to the device to be tested to control the device to be tested to perform a power-off and then power-on operation; After the link to be tested is restored, the operating status parameter information of the link to be tested under the current link training operation is read from the target register again, and the link to be tested is diagnosed again based on the operating status parameter information whether there is a fault, and this is repeated until a preset fault diagnosis stop condition is reached.

8. The link testing method according to any one of claims 1 to 6, characterized in that: Executing the corresponding link training operation again based on the link training trigger condition includes: When the link training trigger condition is a warm reset, a reset operation signal is sent to the device to be tested to control the device to be tested to perform an operation of first resetting and then releasing the reset; After the link to be tested is restored, the operating status parameter information of the link to be tested under the current link training operation is read from the target register again, and the link to be tested is diagnosed again based on the operating status parameter information whether there is a fault, and this is repeated until a preset fault diagnosis stop condition is reached.

9. The link testing method according to any one of claims 1 to 6, characterized in that: Executing the corresponding link training operation again based on the link training trigger condition includes: When the link training trigger condition is a hot reset, the target application running under the operating system triggers a hot reset operation by setting a bridge control register of the device to be tested; After the link to be tested is restored, the operating status parameter information of the link to be tested under the current link training operation is read from the target register again, and the link to be tested is diagnosed again based on the operating status parameter information whether there is a fault, and this is repeated until a preset fault diagnosis stop condition is reached.

10. An electronic device, characterized in that: It comprises a processor and a memory, wherein the processor is used to implement the steps of the link testing method according to any one of claims 1 to 9 when executing a computer program stored in the memory.

11. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the link testing method according to any one of claims 1 to 9 are implemented.

12. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the link testing method according to any one of claims 1 to 9 are implemented.

13. A computing device, comprising at least a server, characterized in that: The server includes a baseboard management controller, a central processing unit, a link training control processor and a first PCIe device; The first PCIe device is connected to the central processor via a PCIe bus as a service module for executing user tasks; the central processor and the baseboard management controller are located in the same network segment; Wherein, the baseboard management controller is connected to the first PCIe device and the central processing unit through a sideband signal, and is used to determine the PCIe device to be tested according to the PCIe link to be tested and the first type of link training trigger condition; when the PCIe link to be tested completes the link training operation and the link is restored, the target register storing the operating status parameter information of the PCIe link to be tested in the PCIe device to be tested is determined based on the first type of link training trigger condition, and the operating status parameter information is read; when it is diagnosed that the PCIe link to be tested has no fault according to the operating status parameter information, the corresponding link training operation is performed again based on the first type of link training trigger condition; the first type of link training trigger condition includes a cold reset or a warm reset; The central processor is used to determine the PCIe device to be tested according to the PCIe link to be tested and the second type link training trigger condition; when the PCIe link to be tested completes the link training operation and the link is restored, determine the target register storing the operating status parameter information of the PCIe link to be tested in the PCIe device to be tested based on the second type link training trigger condition, and read the operating status parameter information; when it is diagnosed that the PCIe link to be tested has no fault according to the operating status parameter information, perform the corresponding link training operation again based on the second type link training trigger condition; the second type link training trigger condition includes a hot reset; The link training control processor is connected to the baseboard management controller and is used to control the power supply and reset of the server and meet the timing requirements of the first PCIe device and the central processor.

14. The computing device according to claim 13, characterized in that It also includes network switches and monitoring terminals; The network switch is connected to the baseboard management controller via a network port, so that the monitoring terminal can remotely access the baseboard management controller; The monitoring end is used to obtain error data and test log data of the link to be tested during the link training operation from the baseboard management controller.

15. The computing device according to claim 13, characterized in that The baseboard management controller is also used for: when the link training trigger condition is a cold reset, the power-off operation and the power-on operation of the PCIe device to be tested are performed by controlling the register of the link training control processor; correspondingly, the central processing unit is also used for: when the link training trigger condition is a warm reset, the reset operation and the release-reset operation of the PCIe device to be tested are performed by controlling the register of the link training control processor.

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