Address allocation method, device and system

Abstract

The invention provides an address allocation method, device and system, and relates to the technical field of computers, and the method comprises the steps: sending a control instruction to a target slave device, the control instruction being used for indicating the target slave device to be switched to a working state; the working state is used for indicating the target slave device to respond to communication information of the I2C bus; the target slave device belongs to at least two slave devices; determining a target device address, and sending the target device address to a target slave device in a working state based on a slave device preset device address corresponding to the target slave device; and determining an address allocation result of the target slave device based on a main communication result of communication between the target device address and the target slave device. According to the method and the device, different and unique target device addresses can be allocated to the target slave devices under the condition that hardware design does not need to be changed, repeated conflicts during device address allocation are avoided, and the allocation efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an address allocation method, device and system. Background Art

[0002] The Inter-Integrated Circuit (IIC), also known as the I2C bus, is a bidirectional synchronous serial bus used to transmit status information and control information. When a master device and multiple slave devices are associated in the I2C bus, the master device starts the I2C bus transmission and addresses each slave device to transmit status information and control information. Therefore, each slave device needs to have a unique device address.

[0003] In the prior art, the device address corresponding to each slave device is generally assigned by configuring resistors or firmware during hardware design. However, when the slave devices are external devices and the types of the slave devices are the same, the device addresses of the slave devices assigned by configuring resistors or firmware are the same, and different device addresses cannot be assigned to the same type of slave devices, resulting in repeated conflicts in device addresses. Summary of the invention

[0004] The present invention provides an address allocation method, device and system for solving the defect in the prior art that when device addresses are allocated to slave devices of the same type through configuration resistors or firmware, the allocated device addresses are all the same, resulting in repeated conflicts in the device addresses.

[0005] The present invention provides an address allocation method, which is applied to a master device, wherein the master device is connected to at least two slave devices via an I2C bus; the method comprises: Sending a control instruction to a target slave device, wherein the control instruction is used to instruct the target slave device to switch to a working state; the working state is used to instruct the target slave device to respond to the communication information of the I2C bus; the target slave device belongs to the at least two slave devices; Determine a target device address, and based on a slave device preset device address corresponding to the target slave device, send the target device address to the target slave device in a working state; Based on the master communication result of the target device address and the target slave device, an address allocation result of the target slave device is determined.

[0006] According to the address allocation method provided by the present invention, a GPIO expansion module is provided on the I2C bus, and the GPIO expansion module is respectively connected to the master device and each of the slave devices; The sending of a control instruction to the target slave device comprises: The control instruction is sent to the GPIO expansion module; the GPIO expansion module is used to determine the target slave device from the at least two slave devices and forward the control instruction to the target slave device.

[0007] According to the address allocation method provided by the present invention, the determining the address allocation result of the target slave device based on the master communication result of the target device address communicating with the target slave device comprises: communicating with the target slave device based on the target device address; In a case where the master communication result indicates that a response message of the target slave device is received, determining that the address allocation result of the target slave device is a successful allocation; When the master communication result indicates that the response information of the target slave device is not received, it is determined that the address allocation result of the target slave device is allocation failure.

[0008] According to the address allocation method provided by the present invention, the method further includes: When the address allocation result is successful, associating the target device address with the target slave device, and updating the mark of the target device address as a used address; In the case where the address allocation result is allocation failure, the identification of the target slave device is updated to an address unallocatable state, and the target device address is released.

[0009] The present invention also provides an address allocation method, which is applied to a target slave device, wherein the target slave device belongs to any one of at least two slave devices, and the method comprises: Receive control instructions sent by the main device; Switching the target slave device to a working state based on the control instruction; the working state is used to indicate that the target slave device responds to communication information of the I2C bus; Based on a preset device address of a slave device corresponding to the target slave device, receiving a target device address sent by the master device, and configuring the target device address based on the target device address; A slave communication result with the master device is determined based on the target device address, and the master device is used to determine an address allocation result of the target slave device based on the slave communication result.

[0010] According to the address allocation method provided by the present invention, the receiving control instruction sent by the master device includes: The control instruction sent by the master device and forwarded by the GPIO expansion module is received, wherein the target slave device is determined by the GPIO expansion module from the at least two slave devices, and the GPIO expansion module is arranged on the I2C bus.

[0011] According to the address allocation method provided by the present invention, the determining of the slave communication result with the master device based on the target device address includes: When receiving the communication information sent by the master device based on the target device address, response information is generated, and the slave communication result with the device is determined to be sending the response information to the master device.

[0012] The present invention also provides an address allocation device, which is applied to a master device, wherein the master device is connected to at least two slave devices via an I2C bus; the device comprises: a sending module, configured to send a control instruction to a target slave device, wherein the control instruction is used to instruct the target slave device to switch to a working state; the working state is used to instruct the target slave device to respond to the communication information of the I2C bus; the target slave device belongs to the at least two slave devices; A first determination module is used to determine a target device address, and based on a slave device preset device address corresponding to the target slave device, send the target device address to the target slave device in a working state; The allocation module is used to determine the address allocation result of the target slave device based on the main communication result of the target device address communicating with the target slave device.

[0013] The present invention also provides an address allocation device, which is applied to a target slave device, wherein the target slave device belongs to any one of at least two slave devices, and the device comprises: A first receiving module, used for receiving a control instruction sent by a master device; A state switching module, used for switching the target slave device to a working state based on the control instruction; the working state is used for indicating that the target slave device responds to the communication information of the I2C bus; A second receiving module, configured to receive the target device address sent by the master device based on the preset device address of the slave device corresponding to the target slave device, and configure the target device address based on the target device address; The second determination module is used to determine the slave communication result with the master device based on the target device address, and the master device is used to determine the address allocation result of the target slave device based on the slave communication result.

[0014] The present invention also provides an address allocation system, comprising: a master device, at least two slave devices and a GPIO expansion module, wherein: The master device is connected to each of the slave devices via an I2C bus, the GPIO expansion module is arranged on the I2C bus, a receiving pin of the GPIO expansion module is connected to the master device, and at least two GPIO output pins of the GPIO expansion module are connected to the at least two slave devices in a one-to-one correspondence; The master device is used to execute any one of the address allocation methods described above, and each of the slave devices is used to execute any one of the address allocation methods described above.

[0015] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-mentioned address allocation methods when executing the computer program.

[0016] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the address allocation method described above is implemented.

[0017] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned address allocation methods.

[0018] The address allocation method, device and system provided by the present invention can respond to communication information in an I2C bus by sending a control instruction to a target slave device, instructing the target slave device to switch to a working state through the control instruction, and after the target slave device switches to the working state, sending a determined target device address to the target slave device using a slave device preset device address, and communicating with the target slave device through the target device address, determining the address allocation result of the target slave device through the determined master communication result, and achieving allocation of different and unique target device addresses to each target slave device without changing the hardware design, avoiding repeated conflicts during device address allocation, and improving allocation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 This is one of the flowcharts of the address allocation method provided by the embodiment of the present invention.

[0021] Figure 2 This is the second flowchart of the address allocation method provided by the embodiment of the present invention.

[0022] Figure 3 This is one of the structural diagrams of the address allocation device provided in the embodiment of the present invention.

[0023] Figure 4 This is the second structural diagram of the address allocation device provided in the embodiment of the present invention.

[0024] Figure 5 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention.

[0025] Figure 6 It is a structural diagram of an address allocation system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In view of the problem in the prior art that when assigning device addresses to slave devices of the same type through configuration resistors or firmware, the assigned device addresses are all the same, resulting in repeated device address conflicts, an embodiment of the present invention provides an address assignment method, which is applied to a master device. Figure 1 is one of the flowcharts of the address allocation method provided by the embodiment of the present invention, such as Figure 1 As shown, the master device is connected to at least two slave devices via an I2C bus (Inter-Integrated Circuit, integrated circuit bus); the method includes the following steps 110 to 130.

[0028] Step 110: Send a control instruction to the target slave device, wherein the control instruction is used to instruct the target slave device to switch to a working state; the working state is used to instruct the target slave device to respond to the communication information of the I2C bus; the target slave device belongs to the at least two slave devices.

[0029] Specifically, the embodiment of the present invention is applied to a master device in an address allocation system, the address allocation system includes a master device and at least two slave devices, the master device is connected to the at least two slave devices via an I2C bus. The target slave device is any slave device that is not assigned a device address, and any slave device that is not assigned a device address is in a reset state. When each slave device is in a reset state, even if each slave device is connected to the master device via an I2C bus, it is impossible to respond to the communication information in the I2C bus. When assigning a target device address to a target slave device, the master device may first send a control instruction to the target slave device to control the target slave device to switch from a reset state to a working state. After the target slave device is in a working state, the target slave device may respond to the communication information of the I2C bus, that is, the master device may control the target slave device to access the I2C bus by sending a control instruction to the target slave device, so as to facilitate the assignment of a target device address to the target slave device.

[0030] It should be noted that each time the master device sends a control instruction to a target slave device, after the target slave device switches to the working state, other slave devices that have not been assigned device addresses are still in the reset state, which does not affect the communication process between the master device and the slave devices in the working state. That is, during the address allocation process, the master device can allow a target slave device that needs to be assigned a device address to access the I2C bus, and can also allow a target slave device that needs to be assigned a device address and multiple slave devices that have been assigned device addresses to access the I2C bus. After the target device address of the target slave device is successfully allocated, a new target slave device is determined from other slave devices that have not been assigned device addresses, and then a control instruction is sent to the new target slave device.

[0031] It should be noted that the master device has a master device preset device address, which can be used as a source address or a destination address, and communicates with the target slave device through the I2C bus. In addition, the master device preset device addresses corresponding to the master devices of different address allocation systems can be the same or different. The master devices of different address allocation systems do not communicate with each other through the I2C bus.

[0032] Furthermore, a GPIO expansion module is provided on the I2C bus, and the GPIO expansion module is respectively connected to the master device and each of the slave devices; The sending of a control instruction to the target slave device comprises: The control instruction is sent to the GPIO expansion module; the GPIO expansion module is used to determine the target slave device from the at least two slave devices and forward the control instruction to the target slave device.

[0033] Specifically, since all slave devices to which device addresses are not assigned are in a reset state, the master device cannot send control instructions to the determined target slave device through the I2C bus. Therefore, in an embodiment of the present invention, a GPIO (General-Purpose Input / Output) expansion module is provided on the I2C bus. The GPIO expansion module is communicatively connected to the master device through the I2C bus, but each GPIO output pin of the GPIO expansion module is correspondingly connected to a target pin of each slave device, that is, one GPIO output pin of the GPIO expansion module is correspondingly connected to a target pin of a slave device. The GPIO expansion module includes at least two GPIO output pins. Therefore, the GPIO expansion module can be connected to at least two slave devices.

[0034] The master device can control the target slave device to access the I2C bus through the GPIO expansion module. That is, the master device can send the control instruction to the GPIO expansion module through the I2C bus. After receiving the control instruction, the GPIO expansion module can determine the target output pin from at least two GPIO output pins, thereby determining the target slave device corresponding to the target output pin. Afterwards, the GPIO expansion module can send the received control instruction to the target slave device through the target output pin, and through the hardware transmission method, ensure that the target slave device can receive the control instruction in time, so as to switch to the working state, so as to control the target slave device to access the I2C bus and respond to the subsequent communication information on the I2C bus.

[0035] It should be noted that the target pin in each slave device connected to the GPIO output pin of the GPIO expansion module may include a reset pin or a GPIO input pin of the slave device, which is not limited in the embodiment of the present invention.

[0036] Step 120: determine the target device address, and based on the slave device preset device address corresponding to the target slave device, send the target device address to the target slave device in working state.

[0037] It should be noted that all slave devices that are not assigned device addresses in the same address allocation system have the same slave device preset device address, and the slave device preset device address is different from the master device preset device address corresponding to the master device. The slave device preset device address can be used as a destination address or a source address and communicates with the master device through the I2C bus. In addition, the slave device preset device address is only used to receive the target device address after the target slave device switches to the working state, and does not participate in the subsequent communication with the master device.

[0038] Specifically, after the target slave device switches to the working state, the master device can select any unassigned device address from the device address table as the target device address, and use the slave device preset device address used by all slave devices with unassigned device addresses as the destination address, and send the determined target device address to the target slave device through the I2C bus, so that the target slave device configures the target device address. For example, taking the master device preset device address as 0x55, the slave device preset device address as 0x59, and the target device address as 0x5A as an example, after the target slave device switches to the working state, the master device can use 0x55 as the source address, 0x59 as the destination address, and 0x5A as the data, and send the target device address 0x5A to the target slave device.

[0039] It should be noted that the device address table is a list of device addresses in the master device for managing different slave devices, and the device address table includes allocated device addresses and unallocated device addresses.

[0040] Step 130: Determine an address allocation result of the target slave device based on the master communication result of the target device address communicating with the target slave device.

[0041] Specifically, after the target slave device is configured with the target device address, the master device can communicate with the target slave device through the target device address, and determine the address allocation result of the target slave device through the master communication result between the master device and the target slave device, that is, whether the target device address is allocated successfully is determined by whether the master device can communicate with the target slave device.

[0042] Further, the determining the address allocation result of the target slave device based on the master communication result of the target device address communicating with the target slave device includes: communicating with the target slave device based on the target device address; In a case where the master communication result indicates that a response message of the target slave device is received, determining that the address allocation result of the target slave device is a successful allocation; When the master communication result indicates that the response information of the target slave device is not received, it is determined that the address allocation result of the target slave device is allocation failure.

[0043] Specifically, after the target slave device is configured with the target device address, the master device can use the target device address as the destination address and communicate with the target slave device through the I2C bus. If the master device receives the response information fed back by the target slave device through the I2C bus, it indicates that the target device address corresponding to the target slave device is successfully allocated. If the master device does not receive the response information fed back by the target slave device through the I2C bus, it indicates that the target device address corresponding to the target slave device is failed to be allocated.

[0044] It should be noted that if the master device does not receive the response information fed back by the target slave device within the preset time after communicating with the target slave device through the target device address, it can be determined that the target device address allocation has failed. The preset time can be set based on experience, for example, the preset time can be 1 minute, 3 minutes, 5 minutes, etc., and the embodiment of the present invention does not limit this.

[0045] Furthermore, the method further comprises: When the address allocation result is successful, associating the target device address with the target slave device, and updating the mark of the target device address as a used address; In the case where the address allocation result is allocation failure, the identification of the target slave device is updated to an address unallocatable state, and the target device address is released.

[0046] Specifically, if the target device address is successfully allocated, the master device associates the target slave device and the target device address in the device address table, and updates the mark of the target device address to a used address. The target device address cannot be selected when the device address is allocated next time, so as to avoid repeated conflicts in the device address. If the target device address allocation fails, the master device can update the identification of the target slave device to an unallocated state and notify the GPIO expansion module. Avoid selecting the target device address when determining a new target slave device next time, so as to avoid the state in which the address allocation process has been in an allocation failure, and other slave devices have failed to successfully allocate device addresses. In addition, since the target device address allocation fails, the target device address can be reallocated to other slave devices to which device addresses have not been allocated, so as to avoid wasting address resources.

[0047] The address allocation method provided by the embodiment of the present invention is that the master device sends a control instruction to the target slave device, instructs the target slave device to switch to a working state through the control instruction, and can respond to the communication information in the I2C bus. After the target slave device switches to the working state, the determined target device address is sent to the target slave device using the preset device address of the slave device, and communicates with the target slave device through the target device address. The address allocation result of the target slave device is determined by the determined master communication result. Without changing the hardware design, different and unique target device addresses are allocated to each target slave device, thereby avoiding repeated conflicts during device address allocation and improving allocation efficiency.

[0048] The embodiment of the present invention further provides an address allocation method, which is applied to a target slave device, wherein the target slave device belongs to any one of at least two slave devices. Figure 2 FIG. 2 is a flow chart of the address allocation method provided in an embodiment of the present invention. Figure 2 As shown, the method includes the following steps 210 to 240.

[0049] Step 210: receiving a control instruction sent by a master device; Step 220: Switch the target slave device to a working state based on the control instruction; the working state is used to indicate that the target slave device responds to the communication information of the I2C bus; Step 230: receiving the target device address sent by the master device based on the slave device preset device address corresponding to the target slave device, and configuring the target device address based on the target device address; Step 240: Determine a slave communication result with the master device based on the target device address, wherein the master device is configured to determine an address allocation result of the target slave device based on the slave communication result.

[0050] Specifically, in the initial state, the target slave device is in a reset state. After receiving the control instruction sent by the master device, the target slave device switches from the reset state to the working state to access the I2C bus and respond to the subsequent communication information of the I2C bus. After that, the slave device presets the device address, receives the target device address assigned by the master device, and configures the target device address. After the target device address is configured, the target device address is used as the destination address or source address to communicate with the master device through the I2C bus. Through the slave communication result of the communication with the master device, the auxiliary master device determines the address allocation result of the target slave device, that is, the auxiliary master device determines whether the target device address is successfully allocated.

[0051] Further, the receiving of the control instruction sent by the main device includes: The control instruction sent by the master device and forwarded by the GPIO expansion module is received, wherein the target slave device is determined by the GPIO expansion module from the at least two slave devices, and the GPIO expansion module is arranged on the I2C bus.

[0052] Specifically, a GPIO expansion module is provided on the I2C bus, and the target slave device is connected to the corresponding GPIO output pin in the GPIO expansion module through the target pin. After the master device sends a control instruction to the GPIO expansion module, the target slave device can receive the control instruction forwarded by the GPIO expansion module through the corresponding GPIO output pin through the target pin, thereby switching the target slave device from the reset state to the working state to access the I2C bus and respond to the communication information on the I2C bus.

[0053] Further, the determining the slave communication result with the master device based on the target device address includes: When receiving the communication information sent by the master device based on the target device address, response information is generated, and the slave communication result with the device is determined to be sending the response information to the master device.

[0054] Specifically, after the target slave device is configured with the target device address assigned by the master device, if the target slave device receives the communication information sent by the master device through the I2C bus with the target device address as the destination address, the target slave device can use the target device address as the source address and the master device preset device address corresponding to the master device as the destination address, generate a response message, and send the response message to the master device through the I2C bus, feeding back to the master device that the target device address allocation is successful.

[0055] The address allocation method provided by the embodiment of the present invention is that the slave device receives the control instruction sent by the master device, switches from the reset state to the working state through the control instruction, so as to access the I2C bus and respond to the communication information of the I2C bus. After that, the slave device presets the device address and receives the target device address allocated by the master device. After configuring the target device address, the slave device assists the master device in determining the address allocation result of the target device address through the slave communication result of the communication with the master device. Without changing the hardware design, the allocation of the device address of each target slave device is realized, and the allocated device addresses are not repeated, so that repeated conflicts during the allocation of device addresses are avoided and the allocation efficiency is improved.

[0056] The address allocation device provided by the present invention is described below. The address allocation device described below and the address allocation method described above can be referred to each other.

[0057] An embodiment of the present invention further provides an address allocation device, which is applied to a master device, wherein the master device is connected to at least two slave devices via an I2C bus; Figure 3 FIG. 1 is a schematic diagram of a structure of an address allocation device provided in an embodiment of the present invention. Figure 3 As shown, the address allocation device 300 includes: a sending module 310 , a first determining module 320 and an allocation module 330 .

[0058] The sending module 310 is used to send a control instruction to the target slave device, wherein the control instruction is used to instruct the target slave device to switch to a working state; the working state is used to instruct the target slave device to respond to the communication information of the I2C bus; the target slave device belongs to the at least two slave devices; A first determination module 320 is used to determine a target device address, and based on a slave device preset device address corresponding to the target slave device, send the target device address to the target slave device in a working state; The allocation module 330 is used to determine the address allocation result of the target slave device based on the main communication result of the target device address communicating with the target slave device.

[0059] The address allocation device provided by the embodiment of the present invention can respond to the communication information in the I2C bus by sending a control instruction to the target slave device, instructing the target slave device to switch to a working state through the control instruction. After the target slave device switches to the working state, the determined target device address is sent to the target slave device using the preset device address of the slave device, and communicates with the target slave device through the target device address. The address allocation result of the target slave device is determined by the determined master communication result. Without changing the hardware design, different and unique target device addresses are allocated to each target slave device, thereby avoiding repeated conflicts during device address allocation and improving allocation efficiency.

[0060] Optionally, a GPIO expansion module is provided on the I2C bus, and the GPIO expansion module is respectively connected to the master device and each of the slave devices.

[0061] Optionally, the sending module 310 is specifically configured to: The control instruction is sent to the GPIO expansion module; the GPIO expansion module is used to determine the target slave device from the at least two slave devices and forward the control instruction to the target slave device.

[0062] Optionally, the allocation module 330 is specifically configured to: communicating with the target slave device based on the target device address; In a case where the master communication result indicates that a response message of the target slave device is received, determining that the address allocation result of the target slave device is a successful allocation; When the master communication result indicates that the response information of the target slave device is not received, it is determined that the address allocation result of the target slave device is allocation failure.

[0063] Optionally, the address allocation device 300 further includes an updating module, specifically configured to: When the address allocation result is successful, associating the target device address with the target slave device, and updating the mark of the target device address as a used address; In the case where the address allocation result is allocation failure, the identification of the target slave device is updated to an address unallocatable state, and the target device address is released.

[0064] The embodiment of the present invention further provides an address allocation device, which is applied to a target slave device, wherein the target slave device belongs to any one of at least two slave devices. Figure 4FIG. 2 is a second structural diagram of an address allocation device provided in an embodiment of the present invention. Figure 4 As shown, the address allocation device 400 includes: a first receiving module 410 , a state switching module 420 , a second receiving module 430 and a second determining module 440 .

[0065] A first receiving module 410, configured to receive a control instruction sent by a master device; A state switching module 420, configured to switch the target slave device to a working state based on the control instruction; the working state is used to indicate that the target slave device responds to communication information of the I2C bus; A second receiving module 430 is used to receive the target device address sent by the master device based on the slave device preset device address corresponding to the target slave device, and configure the target device address based on the target device address; The second determination module 440 is configured to determine a slave communication result with the master device based on the target device address, and the master device is configured to determine an address allocation result of the target slave device based on the slave communication result.

[0066] The address allocation device provided by the embodiment of the present invention is that the slave device receives the control instruction sent by the master device, switches from the reset state to the working state through the control instruction, so as to access the I2C bus and respond to the communication information of the I2C bus. After that, the slave device presets the device address and receives the target device address allocated by the master device. After configuring the target device address, the slave device assists the master device in determining the address allocation result of the target device address through the slave communication result of the communication with the master device. Without changing the hardware design, the allocation of the device address of each target slave device is realized, and the allocated device addresses are not repeated, so that repeated conflicts during the allocation of device addresses are avoided and the allocation efficiency is improved.

[0067] Optionally, the first receiving module 410 is specifically configured to: The control instruction sent by the master device and forwarded by the GPIO expansion module is received, wherein the target slave device is determined by the GPIO expansion module from the at least two slave devices, and the GPIO expansion module is arranged on the I2C bus.

[0068] Optionally, the second determining module 440 is specifically configured to: When receiving the communication information sent by the master device based on the target device address, response information is generated, and the slave communication result with the device is determined to be sending the response information to the master device.

[0069] Figure 5 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention, such as Figure 5As shown, the electronic device may include: a processor 510, a communications interface 520, a memory 530 and a communication bus 540, wherein the processor 510, the communications interface 520 and the memory 530 communicate with each other via the communication bus 540. The processor 510 may call the logic instructions in the memory 530 to execute the address allocation method, which includes: Sending a control instruction to a target slave device, wherein the control instruction is used to instruct the target slave device to switch to a working state; the working state is used to instruct the target slave device to respond to the communication information of the I2C bus; the target slave device belongs to the at least two slave devices; Determine a target device address, and based on a slave device preset device address corresponding to the target slave device, send the target device address to the target slave device in a working state; Determine an address allocation result of the target slave device based on a master communication result of the target device address communicating with the target slave device; or,

[0070] Receive control instructions sent by the main device; Switching the target slave device to a working state based on the control instruction; the working state is used to indicate that the target slave device responds to communication information of the I2C bus; Based on a preset device address of a slave device corresponding to the target slave device, receiving a target device address sent by the master device, and configuring the target device address based on the target device address; A slave communication result with the master device is determined based on the target device address, and the master device is used to determine an address allocation result of the target slave device based on the slave communication result.

[0071] In addition, the logic instructions in the above-mentioned memory 530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0072] On the other hand, the present invention further provides a computer program product, the computer program product comprising a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the address allocation method provided by the above methods, the method comprising: Sending a control instruction to a target slave device, wherein the control instruction is used to instruct the target slave device to switch to a working state; the working state is used to instruct the target slave device to respond to the communication information of the I2C bus; the target slave device belongs to the at least two slave devices; Determine a target device address, and based on a slave device preset device address corresponding to the target slave device, send the target device address to the target slave device in a working state; Determine an address allocation result of the target slave device based on a master communication result of the target device address communicating with the target slave device; or,

[0073] Receive control instructions sent by the main device; Switching the target slave device to a working state based on the control instruction; the working state is used to indicate that the target slave device responds to communication information of the I2C bus; Based on a preset device address of a slave device corresponding to the target slave device, receiving a target device address sent by the master device, and configuring the target device address based on the target device address; A slave communication result with the master device is determined based on the target device address, and the master device is used to determine an address allocation result of the target slave device based on the slave communication result.

[0074] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the address allocation method provided by the above methods is implemented, and the method includes: Sending a control instruction to a target slave device, wherein the control instruction is used to instruct the target slave device to switch to a working state; the working state is used to instruct the target slave device to respond to the communication information of the I2C bus; the target slave device belongs to the at least two slave devices; Determine a target device address, and based on a slave device preset device address corresponding to the target slave device, send the target device address to the target slave device in a working state; Determine an address allocation result of the target slave device based on a master communication result of the target device address communicating with the target slave device; or,

[0075] Receive control instructions sent by the main device; Switching the target slave device to a working state based on the control instruction; the working state is used to indicate that the target slave device responds to communication information of the I2C bus; Based on a preset device address of a slave device corresponding to the target slave device, receiving a target device address sent by the master device, and configuring the target device address based on the target device address; A slave communication result with the master device is determined based on the target device address, and the master device is used to determine an address allocation result of the target slave device based on the slave communication result.

[0076] In addition, an embodiment of the present invention further provides an address allocation system. Figure 6 is a schematic diagram of the structure of the address allocation system provided by an embodiment of the present invention, such as Figure 6 As shown, the address allocation system includes: a master device, at least two slave devices and a GPIO expansion module, wherein: The master device is connected to each of the slave devices via an I2C bus, the GPIO expansion module is arranged on the I2C bus, a receiving pin of the GPIO expansion module is connected to the master device, and at least two GPIO output pins of the GPIO expansion module are connected to the at least two slave devices in a one-to-one correspondence; The master device is used to execute any one of the address allocation methods described above, and each of the slave devices is used to execute any one of the address allocation methods described above.

[0077] It should be noted that after the master device sends the control instruction to the GPIO expansion module, the GPIO expansion module can traverse all GPIO output pins, determine the target output pin from all GPIO output pins in order, and thus determine the target slave device corresponding to the target output pin. In addition, the GPIO expansion can also use a no-replacement extraction method to randomly determine the target output pin from all GPIO output pins, as well as the target slave device corresponding to the target output pin.

[0078] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0079] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An address allocation method, characterized in that: Applied to a master device, the master device is connected to at least two slave devices via an I2C bus; the method comprises: Sending a control instruction to a target slave device, wherein the control instruction is used to instruct the target slave device to switch to a working state; the working state is used to instruct the target slave device to respond to the communication information of the I2C bus; the target slave device belongs to the at least two slave devices; Determine a target device address, and based on a slave device preset device address corresponding to the target slave device, send the target device address to the target slave device in a working state; Based on the master communication result of the target device address and the target slave device communication, an address allocation result of the target slave device is determined.

2. The address allocation method according to claim 1, characterized in that: The I2C bus is provided with a GPIO expansion module, and the GPIO expansion module is respectively connected to the master device and each of the slave devices; The sending of a control instruction to the target slave device comprises: The control instruction is sent to the GPIO expansion module; the GPIO expansion module is used to determine the target slave device from the at least two slave devices and forward the control instruction to the target slave device.

3. The address allocation method according to claim 1 or 2, characterized in that: The determining the address allocation result of the target slave device based on the master communication result of the target device address communicating with the target slave device comprises: communicating with the target slave device based on the target device address; In a case where the master communication result indicates that a response message of the target slave device is received, determining that the address allocation result of the target slave device is a successful allocation; When the master communication result indicates that the response information of the target slave device is not received, it is determined that the address allocation result of the target slave device is allocation failure.

4. The address allocation method according to claim 3, characterized in that: The method further comprises: When the address allocation result is successful, associating the target device address with the target slave device, and updating the mark of the target device address as a used address; In the case where the address allocation result is allocation failure, the identification of the target slave device is updated to an address unallocatable state, and the target device address is released.

5. An address allocation method, characterized in that: Applied to a target slave device, the target slave device being any one of at least two slave devices, the method comprises: Receive control instructions sent by the main device; Switching the target slave device to a working state based on the control instruction; the working state is used to indicate that the target slave device responds to communication information of the I2C bus; Based on a preset device address of a slave device corresponding to the target slave device, receiving a target device address sent by the master device, and configuring the target device address based on the target device address; A slave communication result with the master device is determined based on the target device address, and the master device is used to determine an address allocation result of the target slave device based on the slave communication result.

6. The address allocation method according to claim 5, characterized in that: The receiving control instruction sent by the main device includes: The control instruction sent by the master device and forwarded by the GPIO expansion module is received, wherein the target slave device is determined by the GPIO expansion module from the at least two slave devices, and the GPIO expansion module is arranged on the I2C bus.

7. The address allocation method according to claim 5, characterized in that: The determining the slave communication result with the master device based on the target device address includes: When receiving the communication information sent by the master device based on the target device address, response information is generated, and the slave communication result with the device is determined to be sending the response information to the master device.

8. An address allocation device, characterized in that: Applied to a master device, the master device is connected to at least two slave devices via an I2C bus; the device comprises: a sending module, configured to send a control instruction to a target slave device, wherein the control instruction is used to instruct the target slave device to switch to a working state; the working state is used to instruct the target slave device to respond to the communication information of the I2C bus; the target slave device belongs to the at least two slave devices; A first determination module is used to determine a target device address, and based on a slave device preset device address corresponding to the target slave device, send the target device address to the target slave device in a working state; The allocation module is used to determine the address allocation result of the target slave device based on the main communication result of the target device address communicating with the target slave device.

9. An address allocation device, characterized in that: Applied to a target slave device, the target slave device belongs to any one of at least two slave devices, the apparatus comprises: A first receiving module, used for receiving a control instruction sent by a master device; A state switching module, used for switching the target slave device to a working state based on the control instruction; the working state is used for indicating that the target slave device responds to the communication information of the I2C bus; A second receiving module, configured to receive the target device address sent by the master device based on the preset device address of the slave device corresponding to the target slave device, and configure the target device address based on the target device address; The second determination module is used to determine the slave communication result with the master device based on the target device address, and the master device is used to determine the address allocation result of the target slave device based on the slave communication result.

10. An address allocation system, characterized in that: include: A master device, at least two slave devices, and a GPIO expansion module, where: The master device is connected to each of the slave devices via an I2C bus, the GPIO expansion module is arranged on the I2C bus, a receiving pin of the GPIO expansion module is connected to the master device, and at least two GPIO output pins of the GPIO expansion module are connected to the at least two slave devices in a one-to-one correspondence; The master device is used to execute the address allocation method as described in any one of claims 1 to 4, and each of the slave devices is used to execute the address allocation method as described in any one of claims 5 to 7.

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