In-memory computing unit based on all-digital architecture, memory and electronic equipment

Abstract

The invention provides an in-memory computing unit based on an all-digital architecture, a memory and electronic equipment. The in-memory computing unit comprises a first transistor, a second transistor, a first resistive random access memory, a second resistive random access memory, a phase inverter and a summator, the resistance state of the first resistive random access memory and the resistance state of the second resistive random access memory are complementary, and the first transistor and the second transistor are the same in type. According to the invention, the in-memory calculation unit is realized by matching the resistive random access memory with the complementary resistance state with the transistor and the phase inverter and the summator of the all-digital architecture, so that the in-memory calculation unit can complete various in-memory calculation modes, the resource utilization rate of a chip is improved, and the occupied area of the in-memory calculation unit is reduced; compared with the prior art, the full-digital architecture has the advantages that the implementation of a storage chip with higher integration level is facilitated, and meanwhile, compared with in-memory calculation of an analog domain, the full-digital architecture has a more accurate calculation result.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to an in-memory computing unit, memory, and electronic device based on a fully digital architecture. Background Art

[0002] With the development of memory technology and the explosion of data in the information age, implementing a storage-computing integrated architecture is an effective way to improve data processing efficiency and storage efficiency. It is suitable for application scenarios that require large amounts of data processing, such as deep learning, big data analysis and other fields.

[0003] For the current integrated storage and computing architecture, MAC (Multiply-ACCumulate) type in-memory computing and CAM (Content-Addressable Memory) type in-memory computing are the more mainstream research directions in the field of integrated storage and computing. However, currently, in-memory computing is mainly carried out for a single type of computing function, but some research work has also explored multi-functional hybrid computing. However, in this hybrid function computing circuit, the MAC and CAM circuits are still two independent modules, which require more area of ​​the memory chip; some researchers have also proposed combining multiple in-memory computing functions in the same configurable storage array, but in these designs, the CAM storage array is compared in units of rows, and GPCiMs needs to generate calculation results along the vertically connected bit lines. Therefore, additional peripheral circuits are required in each direction, such as independent sensitive amplifiers, which also require additional chip area. Summary of the invention

[0004] The purpose of the embodiments of the present disclosure is to provide an in-memory computing unit, a memory, and an electronic device based on a fully digital architecture, so as to solve the problem of large chip area occupation and low resource utilization in the integrated memory and computing architecture in the prior art.

[0005] The embodiment of the present disclosure adopts the following technical solution: an in-memory computing unit based on a fully digital architecture, comprising: a first transistor, a second transistor, a first resistive memory, a second resistive memory, an inverter and an adder; wherein the resistance state of the first resistive memory is complementary to the resistance state of the second resistive memory, and the first transistor and the second transistor are of the same type; one end of the first resistive memory is connected to the second electrode of the first transistor, the first electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the second transistor is connected to one end of the second resistive memory, the gate of the first transistor and the gate of the second transistor are simultaneously connected to a word line to access a first voltage signal, the other end of the first resistive memory is connected to a bit line to access a second voltage signal, the other end of the second resistive memory is connected to a complementary bit line to access a third voltage signal, the second voltage signal and the third voltage signal have complementary level values, the first electrode of the first transistor leads to an output line, the output line is connected to the input end of the inverter, and the output end of the inverter is connected to the input end of the adder.

[0006] In some embodiments, a threshold of the inverter is half of a voltage difference between the second voltage signal and the third voltage signal.

[0007] In some embodiments, the in-memory computing unit is configured to implement multiplication and addition calculations or content-addressable calculations.

[0008] In some embodiments, when the in-memory computing unit is configured to implement multiplication and addition calculations, the resistance states of the first resistive memory and the second resistive memory are used to characterize a weight value of the multiplication calculation, the first voltage signal is used to characterize input data, and the level value output by the output line is used to characterize the product between the input data and the weight value.

[0009] In some embodiments, when the in-memory computing unit is configured to implement content-addressable computing, the resistance states of the first resistive memory and the second resistive memory are used to characterize the data content stored in the in-memory computing unit, the second voltage signal and the third voltage signal are used to characterize the data to be searched, and when the first voltage signal drives the first transistor and the second transistor to be turned on, the level value output by the output line is used to characterize the matching result between the data content stored in the in-memory computing unit and the data to be searched.

[0010] In some embodiments, both the first transistor and the second transistor are N-type transistors.

[0011] The embodiment of the present disclosure also provides a memory with an in-memory computing function, which includes at least a plurality of memory arrays, each of which includes at least a plurality of in-memory computing units as described above arranged in an array; wherein the gates of the transistors of all the in-memory computing units in the same row in the same memory array are connected to the same word line to access the first voltage signal, the other ends of the first resistive memory of all the in-memory computing units in the same column in the same memory array are connected to the same bit line to access the second voltage signal, the other ends of the second resistive memory of all the in-memory computing units in the same column in the same memory array are connected to the same complementary bit line to access the third voltage signal, and the second voltage signal and the third voltage signal have complementary level values; all the in-memory computing units in the same column in the same memory array share the same output line, each of the output lines is connected to the input end of an inverter, and the output ends of the inverters corresponding to the output lines with the same column number in different memory arrays are connected to the same adder.

[0012] In some embodiments, when the memory is configured to implement in-memory computing, only one word line in each of the memory arrays is turned on at any time.

[0013] In some embodiments, when the memory is configured to implement multiplication and addition calculations, the output of the adder is used to represent the matrix multiplication result of the in-memory computing unit column corresponding to the adder in all the storage arrays; when the memory is configured to implement content-addressed calculations, the output of the adder is used to represent the number of in-memory computing units whose matching results are matched in the in-memory computing unit column corresponding to the adder in all the storage arrays.

[0014] An embodiment of the present disclosure also provides an electronic device, which at least includes the memory as described above.

[0015] The beneficial effects of the disclosed embodiments are as follows: an in-memory computing unit is implemented by using a resistive memory with complementary resistance states in conjunction with transistors and inverters and adders of a fully digital architecture, so that the in-memory computing unit can complete a variety of in-memory computing methods, thereby improving chip resource utilization and reducing the occupied area of ​​the in-memory computing unit, which is conducive to realizing a more integrated memory chip. At the same time, compared with in-memory computing in the analog domain, the fully digital architecture of this embodiment has more accurate calculation results. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 Schematic diagram of a circuit of an in-memory computing unit based on a fully digital architecture in the first embodiment of the present disclosure;

[0018] Figure 2 A circuit diagram of a RRAM storage unit commonly used in the prior art;

[0019] Figure 3 is a circuit diagram of a conventional RRAM CAM unit in the prior art;

[0020] Figure 4 It is a schematic diagram of the structure of a memory with an in-memory computing function in the second embodiment of the present disclosure;

[0021] Figure 5 This is a schematic diagram of a memory performing MAC calculation in the second embodiment of the present disclosure;

[0022] Figure 6 This is a schematic diagram of a memory executing CAM calculation in the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.

[0024] With the development of memory technology and the explosion of data in the information age, implementing a storage-computing integrated architecture is an effective way to improve data processing efficiency and storage efficiency. It is suitable for application scenarios that require large amounts of data processing, such as deep learning, big data analysis and other fields.

[0025] For the current integrated storage and computing architecture, MAC (Multiply-ACCumulate) type in-memory computing and CAM (Content-Addressable Memory) type in-memory computing are the more mainstream research directions in the field of integrated storage and computing. For MAC type computing, it mainly solves data-intensive tensor computing such as neural networks. Taking the computing method in the analog domain as an example, its basic principle is to open multiple bit lines in the memory array to realize multiple parallel inputs, and then the input value and the weight value stored in the array complete the multiplication and addition operation in the analog domain. Finally, the result of the multiplication and addition operation can be read out by the analog output signal in the bit line direction; for CAM type computing, it is currently mainly implemented by SRAM as a storage element, but its high power consumption and area overhead limit the increase in array size.

[0026] However, currently, in-memory computing is mainly carried out for a single type of computing function, but some research work has also explored multi-functional hybrid computing. However, in this hybrid function computing circuit, the MAC and CAM circuits are still two independent modules, which require more area on the memory chip; some researchers have also proposed combining multiple in-memory computing functions in the same configurable memory array, but in these designs, the CAM memory array is compared in units of rows, and GPCiMs needs to generate calculation results along the vertically connected bit lines. Therefore, additional peripheral circuits are required in each direction, such as independent sensitive amplifiers, which also require additional chip area.

[0027] In order to solve the above problems, the first embodiment of the present disclosure provides an in-memory computing unit based on a fully digital architecture, and uses the in-memory computing unit to implement different in-memory computing. Figure 1 The circuit diagram of the in-memory computing unit in this embodiment is shown, which mainly includes a first transistor M1, a second transistor M2, a first resistive memory R1, a second resistive memory R2, an inverter C and an adder ADD, wherein the resistance state of the first resistive memory R1 is complementary to the resistance state of the second resistive memory R2, that is, when R1 is in a high resistance state, R2 is in a low resistance state, and when R1 is in a low resistance state, R2 is in a high resistance state. The first transistor M1 and the second transistor M2 are of the same type. In this embodiment, it is further defined that the first transistor M1 and the second transistor M2 are both N-type transistors.

[0028] Specifically, one end of the first resistive memory R1 is connected to the second electrode of the first transistor M1, the first electrode of the first transistor M1 is connected to the first electrode of the second transistor M2, the second electrode of the second transistor M2 is connected to one end of the second resistive memory R2, the gate of the first transistor M1 and the gate of the second transistor M2 are simultaneously connected to the word line WL to access the first voltage signal, the other end of the first resistive memory R1 is connected to the bit line BL to access the second voltage signal, the other end of the second resistive memory R2 is connected to the complementary bit line BLB to access the third voltage signal, the first electrode of the first transistor M1 is connected to the output line SL, the end of the output line SL is connected to the input end of the inverter C, and the output end of the inverter C is connected to the input end of the adder ADD.

[0029] In this embodiment, the second voltage signal and the third voltage signal have complementary level values, that is, when any one of the second voltage signal and the third voltage signal is at a low level, the other must be at a high level. In some embodiments, 0V can be used to represent a low level and V can be used to represent a high level.

[0030] based on Figure 1 The in-memory computing unit shown, based on the RRAM (resistive random access memory) unit, reuses the RRAM structure and uses the same circuit architecture to implement MAC calculation and CAM calculation respectively, thereby completing the reuse of the in-memory computing unit. The following is a detailed description of the process of the in-memory computing unit completing different types of in-memory calculations in this embodiment.

[0031] In conventional analog-domain-based in-memory computing units, the high / low resistance of RRAM can be used to map the calculation results to different currents. However, since the switching ratio of RRAM is not high, it is difficult to map the calculation results to output voltages. Figure 2 A circuit diagram of a commonly used RRAM storage unit in the prior art is shown. Figure 2 When a voltage is applied to the source terminal (SL) of the transistor, regardless of whether the RRAM is in a high or low resistance state, its output result is close to the SL terminal voltage. The voltage window is small, which can easily lead to misjudgment of the output result.

[0032] This embodiment adopts Figure 1The 2T2R unit structure (i.e., two transistors and two RRAMs) shown is combined with a low threshold inverter and an adder. When performing MAC calculation, the resistance states of the first RRAM R1 and the second RRAM R2 are used to characterize the weight value of this calculation, and the first voltage signal input by WL is used to characterize the valid input data, so that the two transistors are turned on. At this time, the complementary BL and BLB are divided by two RRAM units with different resistance values, so that the output level of SL is close to BL or BLB, that is, the product between the input data and the weight value, and the output voltage window is increased, so that the voltage swing of SL can directly drive the inverter and the adder to output the corresponding calculation result; at the same time, in the process of WL driving the transistor to turn on, one of the two RRAMs is always in a high resistance state, so the DC current between BL and BLB is small, reducing the generation of leakage current.

[0033] Corresponding to CAM calculation, the circuit diagram of the conventional RRAM CAM unit is as follows Figure 3 As shown, when it is working, the storage unit is equivalent to two 1T1R in parallel, and the resistor in the low resistance state has a large conduction current, which causes a large power consumption. When the in-memory calculation unit of this embodiment performs CAM calculation, it uses the second voltage signal and the third voltage signal as input, that is, the data to be searched and stored, and the 2T2R storage unit represents a complementary resistance state, representing the data content stored in the current in-memory calculation unit; when the data is input, the high and low resistance values ​​of the RRAM unit divide the voltage across BL, and combine the level of BL and BLB inputs and the resistance state of R1 and R2 to make the output line SL output a high level or a low level to represent the matching result of the data content stored in the in-memory calculation unit and the data to be searched. In actual implementation, it can be set according to the needs to output a high level of SL to indicate a match in the search content or a low level of SL to indicate a match.

[0034] Specifically, for example, define R1 as high impedance state and R2 as low impedance state to represent data 0, define R1 as low impedance state and R2 as high impedance state to represent data 0, and define BL input 0 and BLB input V to represent the data to be searched as 0, and define BL input V and BLB input 0 to represent the data to be searched as 1. Then, it can be determined that when SL outputs a high level (i.e., V), the data to be searched is consistent with the data stored in the in-memory computing unit. If SL outputs a low level (i.e., 0), the data to be searched is inconsistent with the data stored in the in-memory computing unit, thereby realizing 1-bit CAM calculation. It should be noted that the numerical representation situation and the level value of the matching result defined above are all one of the implementation methods that can be realized, and can also be adjusted during actual implementation. This embodiment does not impose specific restrictions.

[0035] Furthermore, the output line of the in-memory calculation unit is connected to the input end of the inverter C, and the output end of the inverter C is connected to the adder ADD, that is, the inverter C outputs a level value that meets the working range of the adder ADD based on the level of the SL output, and the adder ADD performs subsequent addition processing or counting statistics according to the received level value. It should be noted that, in addition, the inverter C is a low-threshold inverter, and its threshold is one-half of the voltage difference between the second voltage signal and the third voltage signal, that is, V / 2, so that no matter whether the level value of the SL output is a low level close to 0V or a high level close to V, the inverter C can accurately identify it and output the corresponding level value. For example, when the inputs of BL and BLB are (0, 0.5) (i.e., the second voltage signal is 0V and the third voltage signal is 0.5V), the threshold of inverter C is 0.25V. At this time, when the level value output by SL is 0.5V, inverter C determines that the received level value exceeds its threshold value 0.25V, and inverter C outputs a high level. If the level value output by SL is 0, it does not exceed the threshold value of inverter C, and inverter C outputs a low level.

[0036] It should be noted that before performing MAC calculation, the resistance states of the first resistive memory R1 and the second resistive memory R2 of the in-memory computing unit can be adjusted according to the actual requirements of the weight value, as long as the resistance states of the first resistive memory R1 and the second resistive memory R2 are complementary. The resistance state switching method of the resistive memory can refer to the adjustment method of the resistive memory of the conventional RRAM unit, which is not described in this embodiment.

[0037] In actual implementation, the first transistor M1 and the second transistor M2 of the in-memory computing unit are manufactured using a 180nm process, and in order to prevent the interference of SL on the resistance value of RRAM, the voltages of BL and BLB are selected to be 0V and 0.5V, and the inverter and adder circuits can be manufactured using a 28nm process. The above devices can be directly manufactured using conventional processes, and this embodiment will not be described in detail here.

[0038] This embodiment implements the in-memory computing unit by combining a resistive complementary resistive random access memory with a transistor and an inverter and an adder of a fully digital architecture, so that the in-memory computing unit can complete a variety of in-memory computing methods, improve chip resource utilization and reduce the occupied area of ​​the in-memory computing unit, which is conducive to the realization of a more integrated memory chip. At the same time, the fully digital architecture of the embodiment of the present disclosure has more accurate calculation results.

[0039] Based on the same inventive concept, the second embodiment of the present disclosure provides a memory with an in-memory computing function, and its structural diagram is as follows: Figure 4As shown, it includes at least a plurality of storage arrays Array, each storage array includes at least a plurality of in-memory computing units provided in the first embodiment arranged in an array; wherein, Figure 4 As shown, the gates of the transistors of all the in-memory computing units in the same row in the same storage array are connected to the same word line to access the first voltage signal, the other ends of the first resistive memory of all the in-memory computing units in the same column in the same storage array are connected to the same bit line to access the second voltage signal, the other ends of the second resistive memory of all the in-memory computing units in the same column in the same storage array are connected to the same complementary bit line to access the third voltage signal, the second voltage signal and the third voltage signal have complementary level values, all the in-memory computing units in the same column in the same storage array share the same output line, each of the output lines is connected to the input end of the inverter, and the output ends of the inverters corresponding to the output lines with the same column number in different storage arrays are connected to the same adder.

[0040] When performing MAC calculation, if Figure 5 As shown, the memory includes 10 memory arrays, each of which has 64 WLs, corresponding to 64 rows of in-memory computing units. Activation represents the input activation value, and the WL line corresponding to the bit with a value of 1 in the activation value is turned on, indicating valid input data. When the value is 0, no matter what the weight value is, the final product is 0, so only the WL corresponding to the value 1 is required to perform matrix multiplication. The resistance state of the resistive memory in the in-memory computing units of different memory arrays is used to characterize different weight values ​​Weight. When the corresponding WL is turned on, SL outputs the product of Activation and Weight to the adder, and the adder sums the multiplication results of different computing unit rows and the multiplication results of different memory arrays to obtain the final calculation result of the matrix multiplication operation, summation result.

[0041] When performing CAM calculations, Figure 6As shown, the memory also includes 10 storage arrays, each storage array has 64 WLs, m+1 in-memory computing unit columns, that is, there are a total of m+1 BL, BLB pairs, key data represents the data to be searched, hashcode represents the data content stored in the in-memory computing unit, when the WL is turned on, combined with the second voltage signal and the third voltage signal level, the resistance value of the resistive memory in the in-memory computing unit is matched and the matching result is output to the adder, and the adder counts the matching result of the current in-memory computing unit in different storage arrays at the same time. For example, corresponding to 10 bits of data to be searched, when the number of in-memory computing units that have successfully matched counted by the adder is 10, it is determined that the data to be searched is stored in the current in-memory computing unit, and the CAM calculation is completed.

[0042] In in-memory computing, the opening and closing of WL and BL (BLB) directly affects the efficiency and power consumption of computing. In order to improve the energy efficiency of the overall system, only one WL is opened for each storage array during MAC and CAM calculations to avoid DC power consumption between units. In this way, the number of opened WLs can be reduced to a certain extent, avoiding potential DC power consumption problems, thereby improving the overall computing efficiency.

[0043] In addition, the memory should also include peripheral circuits (not shown in the figure) for inputting signals to word lines, bit lines, and complementary bit lines, which may specifically include word line driving circuits, bit lines, and complementary bit line driving circuits, and may further include resistive write circuits of resistive memory, etc. The driving methods of word lines, bit lines, and complementary bit lines implemented by the above-mentioned peripheral circuits can be directly implemented by referring to conventional driving circuits, and this embodiment will not be described in detail here.

[0044] This embodiment realizes the in-memory computing unit through the combination of resistive complementary resistive random access memory and transistors, so that the in-memory computing unit can complete a variety of in-memory computing methods, improve the resource utilization of the chip and reduce the occupied area of ​​the in-memory computing unit, which is conducive to the realization of a more integrated memory chip. At the same time, the in-memory computing unit of the embodiment of the present disclosure realizes in-memory computing based on a fully digital method. Compared with the in-memory computing in the analog domain, the fully digital architecture has more accurate computing results.

[0045] Based on the same inventive concept, the third embodiment of the present disclosure provides an electronic device, which should at least include the memory with in-memory computing function provided in the second embodiment of the present disclosure, and when performing data processing, it can be combined with actual data processing needs to perform MAC calculations or CAM calculations to achieve memory structure reuse, meet multiple computing needs, and save memory space and chip area.

[0046] In actual implementation, the electronic device may include multiple memories with in-memory computing functions provided in the second embodiment of the present disclosure, and dynamically adjust the type of calculation currently performed by each memory according to the data processing volume and current processing requirements to maximize resource utilization and improve data processing efficiency.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An in-memory computing unit based on a fully digital architecture, characterized in that: include: A first transistor, a second transistor, a first resistive memory, a second resistive memory, an inverter and an adder; wherein, The resistance state of the first resistive memory is complementary to the resistance state of the second resistive memory, and the first transistor and the second transistor are of the same type; One end of the first resistive memory is connected to the second electrode of the first transistor, the first electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the second transistor is connected to one end of the second resistive memory, the gate of the first transistor and the gate of the second transistor are simultaneously connected to a word line to access a first voltage signal, the other end of the first resistive memory is connected to a bit line to access a second voltage signal, the other end of the second resistive memory is connected to a complementary bit line to access a third voltage signal, the second voltage signal and the third voltage signal have complementary level values, the first electrode of the first transistor leads to an output line, the output line is connected to an input end of an inverter, and the output end of the inverter is connected to an input end of an adder.

2. The in-memory computing unit according to claim 1, characterized in that: A threshold of the inverter is half of a voltage difference between the second voltage signal and the third voltage signal.

3. The in-memory computing unit according to claim 1, characterized in that: The in-memory computing unit is configured to implement multiplication and addition calculations or content-addressable calculations.

4. The in-memory computing unit according to claim 3, characterized in that: When the in-memory computing unit is configured to implement multiplication and addition calculations, the resistance states of the first resistive memory and the second resistive memory are used to characterize a weight value of the multiplication calculation, the first voltage signal is used to characterize input data, and the level value output by the output line is used to characterize the product between the input data and the weight value.

5. The in-memory computing unit according to claim 3, characterized in that: When the in-memory computing unit is configured to implement content-addressable computing, the resistance states of the first resistive memory and the second resistive memory are used to characterize the data content stored in the in-memory computing unit, the second voltage signal and the third voltage signal are used to characterize the data to be searched, and when the first voltage signal drives the first transistor and the second transistor to be turned on, the level value output by the output line is used to characterize the matching result between the data content stored in the in-memory computing unit and the data to be searched.

6. The in-memory computing unit according to any one of claims 1 to 5, characterized in that: The first transistor and the second transistor are both N-type transistors.

7. A memory with in-memory computing function, characterized in that: At least comprising a plurality of storage arrays, each of the storage arrays comprising at least a plurality of in-memory computing units as claimed in any one of claims 1 to 6 arranged in an array; Among them, the gates of the transistors of all the in-memory computing units located in the same row in the same storage array are connected to the same word line to access the first voltage signal, the other ends of the first resistive memory of all the in-memory computing units located in the same column in the same storage array are connected to the same bit line to access the second voltage signal, and the other ends of the second resistive memory of all the in-memory computing units located in the same column in the same storage array are connected to the same complementary bit line to access the third voltage signal, and the second voltage signal and the third voltage signal have complementary level values; all the in-memory computing units located in the same column in the same storage array share the same output line, each of the output lines is connected to the input end of the inverter, and the output ends of the inverters corresponding to the output lines with the same column number in different storage arrays are connected to the same adder.

8. The memory according to claim 7, characterized in that: When the memory is configured to implement in-memory computing, only one word line in each of the memory arrays is turned on at any time.

9. The memory according to claim 7, characterized in that: In the case where the memory is configured to implement multiplication and addition calculations, the output of the adder is used to represent the matrix multiplication result of the in-memory computing unit columns corresponding to the adder in all the storage arrays; In the case where the memory is configured to implement content-addressable computing, the output of the adder is used to represent the number of in-memory computing units with matching results in the in-memory computing unit columns corresponding to the adder in all the storage arrays.

10. An electronic device, characterized in that: At least comprising the memory as claimed in any one of claims 7 to 9.

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