Junction Field Effect Transistor Device And Method Of Manufacturing The Same
By forming a well with different conductivity types and a first top layer in the junction field effect transistor device, and forming a plurality of first well grooves in the well, the problem of junction breakdown voltage limit of the traditional device is solved, and the effect of high breakdown voltage and miniaturization is achieved.
Patent Information
- Application Number
- CN202311127688.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-09
- Filing Date
- 2023-09-04
- Publication Date
- 2025-02-25
AI Technical Summary
Traditional junction field effect transistor devices have problems with junction breakdown voltage limitation, resulting in reduced performance or damage, and the device size is difficult to reduce.
By forming a well with different conductivity types and a first top layer in the substrate, and forming a plurality of first well grooves in the well, the second conductivity type doping concentration of the first well groove is lower than the second conductivity type doping concentration of the well, a plurality of sources or drains and gates are provided to form a junction field effect transistor device.
Reducing the threshold voltage, increasing the breakdown voltage, and shortening the channel length and the distance between the drain and the gate, thereby reducing the size of the device.
Smart Images
Figure CN119521733A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to semiconductor manufacturing technology, and more particularly to a junction field effect transistor device and a manufacturing method thereof. Background Art
[0002] Semiconductor devices have been widely used in various electronic products, such as personal computers, mobile phones, digital cameras and other electronic devices. As the size of semiconductor devices shrinks, the difficulty of manufacturing semiconductor devices has also increased significantly. Defects may occur during the process of semiconductor devices, and these defects may cause the performance of the device to be reduced or damaged. For example, a junction gate field-effect transistor (JFET) device is a semiconductor device that controls the flow of channel current by changing the electric field. It can be divided into two types: N-channel and P-channel. Traditional junction field effect transistor devices have the problem of junction breakdown voltage limitation. Therefore, it is necessary to continuously improve the junction field effect transistor device and its manufacturing method to increase the breakdown voltage and reduce the size of the device. Summary of the invention
[0003] According to some embodiments of the present invention, a junction field effect transistor device is provided. The junction field effect transistor device includes a substrate having a first conductivity type; a well buried in the substrate and having a second conductivity type, the second conductivity type being different from the first conductivity type; a first top layer buried in the well and having the first conductivity type; a plurality of source electrodes or drain electrodes disposed on the top surface of the well; a first isolation structure adjacent to one of the source electrodes or drain electrodes; a gate electrode disposed on the top surface of the first top layer; and a plurality of first well trenches disposed below the gate electrode, wherein the second conductivity type doping concentration of the first well trenches is lower than the second conductivity type doping concentration of the well electrode.
[0004] According to some other embodiments of the present invention, a method for manufacturing a junction field effect transistor device is provided. The method for manufacturing the junction field effect transistor device includes forming a well in a substrate, wherein the substrate has a first conductivity type and the well has a second conductivity type, the second conductivity type being different from the first conductivity type; forming a first top layer in the well, wherein the first top layer has the first conductivity type; implanting the well with a dopant having the first conductivity type to form a plurality of first well grooves, wherein the second conductivity type dopant concentration of the first well grooves is lower than the second conductivity type dopant concentration of the well; forming an isolation structure on the top surface of the first top layer; forming a plurality of source electrodes or drain electrodes on the top surface of the well; and forming a gate electrode above the first well groove to cover the first well groove.
[0005] The junction field effect transistor device provided by the embodiment of the present invention has multiple wells and top layers arranged below the channel region and the drift region, which can reduce the threshold voltage, increase the breakdown voltage, and shorten the channel length and the distance between the drain and the gate (the length of the drift region), thereby reducing the size of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] By the following detailed description in conjunction with the accompanying drawings, the aspects of the embodiments of the present invention can be better understood. It should be emphasized that, according to standard practices in the industry, many components are not drawn to scale. In fact, in order to clearly discuss, the sizes of various components may be arbitrarily increased or reduced.
[0007] Figures 1 to 8 Cross-sectional views are shown of various stages in the fabrication of a junction field effect transistor device according to some embodiments of the present invention.
[0008] Reference numerals:
[0009] 100: Junction field effect transistor device
[0010] 102: Substrate
[0011] 104: Epitaxial layer
[0012] 106: Trap
[0013] 108: First top floor
[0014] 110: Second top floor
[0015] 112: First well slot
[0016] 114: Second well slot
[0017] 116,118: Isolation structure
[0018] 120: Gate field plate
[0019] 122: Source or drain field plate
[0020] 124,126: source or drain
[0021] 128: Doping area
[0022] 130: Gate
[0023] D1,D2,D3: Depth
[0024] S1,S2: Spacing
[0025] W1,W2: Width DETAILED DESCRIPTION
[0026] Some embodiments are summarized below so that those skilled in the art can more easily understand the present invention. However, these embodiments are only examples and are not intended to limit the present invention. It is understood that those skilled in the art can adjust the embodiments described below as needed, such as changing the process sequence and / or including more or fewer steps than described herein, and these adjustments do not exceed the scope of the present invention.
[0027] In addition, other elements may be added on the basis of the embodiments described below. For example, the description of "forming a second element on a first element" or "forming a second element above a first element" may include an embodiment in which the first element is in direct contact with the second element, and may also include an embodiment in which there are other elements between the first element and the second element so that the first element and the second element are not in direct contact, and the upper and lower relationship between the first element and the second element may change as the device is operated or used in different orientations. In addition, the present invention may repeat reference numbers and / or letters in different embodiments. This repetition is for simplicity and clarity, and is not used to indicate the relationship between the different embodiments discussed.
[0028] According to some embodiments of the present invention, a junction field effect transistor device and a method for manufacturing the same are described below. According to an embodiment of the present invention, the junction field effect transistor device includes a plurality of well slots and a top layer, which can achieve a high breakdown voltage and a high drive current, and can shorten the channel length and the distance between the drain and the gate, thereby reducing the size of the device.
[0029] Figures 1 to 8 Some embodiments of the present invention depict cross-sectional views of various stages of forming a junction field effect transistor device 100. Additional components may be added to the junction field effect transistor device 100. For different embodiments, some components described below may be replaced or eliminated. To simplify the diagram, only a portion of the junction field effect transistor device 100 is depicted.
[0030] Reference Figure 1 , providing a substrate 102. The substrate 102 may use any substrate material suitable for a junction field effect transistor device. For example, the material of the substrate 102 may include an element or a compound, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, germanium, silicon carbide, gallium arsenide, zinc oxide, indium phosphide, similar materials, or a combination thereof. The substrate 102 may be a bulk substrate or a composite substrate formed of different materials. The substrate 102 may include a semiconductor-on-insulator (SOI) substrate formed by disposing a semiconductor material on an insulating layer. In one embodiment, the substrate 102 includes an epitaxial layer 104.
[0031] The substrate 102 may be doped with a P-type or N-type dopant. For example, the P-type dopant may be boron, boron difluoride (BF 2 ), gallium or a combination thereof, and the N-type dopant may be phosphorus, arsenic or a combination thereof. The substrate 102 and the epitaxial layer 104 have the same conductivity type.
[0032] One or more semiconductor devices (including active devices and / or passive devices) may be pre-formed on the substrate 102. To simplify the diagram, only a flat substrate 102 is shown here. In the description of the present invention, the term "substrate" may include devices formed on a semiconductor wafer and various coatings covering the semiconductor wafer.
[0033] According to some embodiments, substrate 102 includes a well 106. The conductivity type of well 106 may be different from the conductivity type of substrate 102. According to some embodiments, substrate 102 and epitaxial layer 104 are P-type, well 106 is N-type, and the formed junction field effect transistor device 100 is N-type. In other embodiments, substrate 102 and epitaxial layer 104 are N-type, well 106 is P-type, and the formed junction field effect transistor device 100 is P-type.
[0034] The well 106 may be formed by an ion implantation process using a patterned mask layer over the substrate 102. For example, the mask layer may include a photoresist, such as a positive photoresist or a negative photoresist. In some embodiments, the mask layer may include a hard mask and may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, similar materials, or a combination of the foregoing. The mask layer may be a single layer or a multilayer structure. The formation of the mask layer may include a deposition process, a photolithography process, other appropriate processes, or a combination of the foregoing. In some embodiments, the deposition process includes spin coating, chemical vapor deposition, atomic layer deposition, similar processes, or a combination of the foregoing. For example, the photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask lithography, exposure, post-exposure baking (PEB), development, cleaning, drying (e.g., hard baking), other appropriate processes, or a combination of the foregoing.
[0035] Then, according to some embodiments, Figure 2 As shown, a first top layer 108 and a second top layer 110 are formed in the well 106 to adjust the threshold voltage (V th) and drift region, thereby maintaining a high breakdown voltage. The first top layer 108 and the second top layer 110 can be formed by an ion implantation process using a patterned mask layer over the substrate 102. In some embodiments, the first top layer 108 and the second top layer 110 are formed respectively using different patterned mask layers. The second top layer 110 can be formed after the first top layer 108 is formed. Alternatively, the first top layer 108 can be formed after the second top layer 110 is formed. In other embodiments, the first top layer 108 and the second top layer 110 can be formed simultaneously.
[0036] The conductivity type of the first top layer 108 and the second top layer 110 may be different from the conductivity type of the well 106. For example, in an N-type junction field effect transistor, the first top layer 108 and the second top layer 110 are P-type. The first top layer 108 and the second top layer 110 may have the same or different doping concentrations. For example, the doping concentration of the first top layer 108 may be about 2.5E12cm 2 to about 3E15 cm 2 , and the doping concentration of the second top layer 110 may be about 2.5E12 cm 2 to about 5E12 cm 2 .
[0037] In some embodiments, the first top layer 108 and the second top layer 110 are separated by a portion of the well 106. Figure 2 As shown, the width of the second top layer 110 may be greater than the width of the first top layer 108 .
[0038] The depths of the first top layer 108 and the second top layer 110 may be the same or different. The depths of the first top layer 108 and the second top layer 110 may be adjusted to obtain a desired threshold voltage. For example, the ratio of the depth D1 of the well 106 to the depth D2 of the first top layer 108 may be about 2 to about 3, and the ratio of the depth D1 of the well 106 to the depth D3 of the first top layer 108 may be about 2 to about 3.
[0039] Then, according to some embodiments, Figure 3 As shown, a plurality of first well trenches 112 and a plurality of second well trenches 114 are formed in the well 106 to adjust the threshold voltage and the drift region, thereby maintaining a high breakdown voltage. The first well trenches 112 and the second well trenches 114 can pass through the bottom surfaces of the first top layer 108 and the second top layer 110, respectively, and extend to the bottom surface of the well 106.
[0040] The conductivity type of the first well 112 and the second well 114 may be the same as the conductivity type of the well 106, but the dopant concentration of the first well 112 and the second well 114 is lower than the dopant concentration of the well 106. In some embodiments, in an N-type junction field effect transistor, the first well 112 and the second well 114 are N-type. The first well 112 and the second well 114 may be formed by an ion implantation process using a patterned mask layer over the substrate 102. According to some embodiments, dopants of a different conductivity type from the well 106 are implanted into the places where the first well 112 and the second well 114 are to be formed, for example, P-type dopants may be implanted into the N-type well 106 to reduce the dopant concentration of these regions.
[0041] The first well 112 and the second well 114 may have the same or different dopant concentrations. The dopant concentrations of the first well 112 and the second well 114 may be adjusted to obtain a desired threshold voltage. For example, the dopant concentration of the first well 112 is about 2E12 cm 2 to about 2.7E12 cm 2 , and the doping concentration of the second well 114 is about 2E12cm 2 to about 2.7E12 cm 2 .
[0042] The number of the second wells 114 may be greater than the number of the first wells 112, but is not limited to the number in the figure. The first wells 112 and the second wells 114 may have the same or different spacings and / or widths. The spacing S1 between the first wells 112 may be about 1 μm to about 3 μm, and the spacing S2 between the second wells 114 may be about 1 μm to about 3 μm. The width W1 of one of the first wells 112 may be about 1 μm to about 2 μm, and the width W2 of one of the second wells 114 may be about 1 μm to about 2 μm.
[0043] Then, according to some embodiments, Figure 4 As shown, a plurality of isolation structures 116, 118 are formed on the top surface of the substrate 102. In some embodiments, the isolation structures 116, 118 include local oxidation of silicon (LOCOS) isolation structures, and a portion of the isolation structures 116, 118 is embedded in the substrate 102. In other embodiments, the isolation structures 116, 118 include shallow trench isolation (STI) structures.
[0044] In some embodiments, the isolation structures 116 and 118 are made of silicon oxide, silicon nitride, silicon oxynitride, similar materials, or a combination thereof. In some embodiments, the formation of the isolation structures 116 and 118 may include a thermal oxidation process, a chemical vapor deposition (CVD) process, a similar process, or a combination thereof. The formation of the isolation structures 116 and 118 may be performed by etching a plurality of trenches in the substrate 102 using an etching process, and then filling the trenches with the material of the epitaxial layer 104 using a chemical vapor deposition process.
[0045] like Figure 4 As shown, the isolation structure 116 may cover an edge of the first top layer 108. The isolation structure 118 may extend over the entire second top layer 110 and cover both edges of the second top layer 110 and the top surface of the second well 114. In some embodiments, the depth of the isolation structures 116 and 118 in the substrate 102 is less than the depth of the first top layer 108 and the second top layer 110.
[0046] Then, according to some embodiments, Figure 5 As shown, a gate field plate 120 and one or more source or drain field plates 122 are formed on the top surface of the substrate 102 to maintain a high breakdown voltage. In some embodiments, the materials of the gate field plate 120 and the source or drain field plate 122 are deposited on the top surface of the substrate 102, and then an etching process is performed to simultaneously form the gate field plate 120 and the source or drain field plate 122. In other embodiments, the gate field plate 120 and the source or drain field plate 122 are formed separately in different processes.
[0047] The material of the gate field plate 120 and the source or drain field plate 122 may include polysilicon or any suitable conductive material. The deposition process may include a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, an atomic layer deposition process, a similar process, or a combination of the foregoing. The etching process may include a dry etching process, a wet etching process, or a combination of the foregoing. For example, the dry etching process may include reactive ion etching (RIE), inductively-coupled plasma (ICP) etching, neutral beam etching (NBE), a similar etching process, or a combination of the foregoing. For example, the wet etching process may use any suitable etchant, such as hydrofluoric acid, ammonium hydroxide, or a similar material.
[0048] like Figure 5As shown, the gate field plate 120 may extend from above the first top layer 108 to above the second top layer 110 and cover an edge of the isolation structure 118. The source or drain field plates 122 may include four as shown, but may also include more or less.
[0049] Then, according to some embodiments, Figure 6 As shown, source or drain 124, 126, such as source or drain 124 and source or drain 126, are formed on the top surface of well 106. In some embodiments, source or drain 124, 126 are formed by one ion implantation process. In other embodiments, source or drain 124, 126 are formed separately in different processes.
[0050] The source or drain 124, 126 may have the same conductivity type and may be the same conductivity type as the well 106. For example, in an N-type junction field effect transistor, the source or drain 124, 126 is N-type. The doping concentration of the source or source or drain 124, 126 may be higher than the doping concentration of the well 106.
[0051] Then, according to some embodiments, Figure 7 As shown, a doped region 128 and a gate 130 are formed on the top surface of the substrate 102. The gate 130 can be formed on the top surface of the first top layer 108 and can cover the top surface of the first well 112. In some embodiments, the doped region 128 and the gate 130 are formed by a single ion implantation process. In other embodiments, the doped region 128 and the gate 130 are formed separately in different processes.
[0052] The doping region 128 and the gate 130 may have the same conductivity type and may be different from the conductivity type of the well 106. For example, in an N-type junction field effect transistor, the doping region 128 and the gate 130 are P-type. The doping concentration of the doping region 128 may be higher than the doping concentration of the substrate 102. The doping concentration of the gate 130 may be higher than the doping concentration of the first top layer 108.
[0053] Although the source or drain 124, 126 is formed first, and then the doped region 128 and the gate 130 are formed, the present invention is not limited thereto, and the process sequence can be adjusted. For example, the doped region 128 and the gate 130 can be formed first, and then the source or drain 124, 126 can be formed.
[0054] Then, according to some embodiments, Figure 8As shown, interconnect structures are formed to connect to the source or drain 124, 126, the doped region 128 and the gate 130, respectively, and form the junction field effect transistor device 100. Some interconnect structures are electrically connected to the gate 130 and the gate field plate 120, and some interconnect structures are electrically connected to one of the source or drain (for example, 126) and the source or drain field plate 122.
[0055] In summary, the junction field effect transistor device provided by the embodiment of the present invention has multiple wells and top layers arranged below the channel region and the drift region, which can reduce the threshold voltage, increase the breakdown voltage, and shorten the channel length and the distance between the drain and the gate (the length of the drift region), thereby reducing the size of the device. In addition, according to some embodiments, a field plate electrically connected to one of the source or drain or the gate is arranged above the drift region to maintain a high breakdown voltage.
[0056] The above summarizes the components of several embodiments so that those with ordinary knowledge in the art can better understand the various aspects of the embodiments of the present invention. Those with ordinary knowledge in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the embodiments of the present invention, and they can make various changes, substitutions and adjustments without violating the spirit and scope of the embodiments of the present invention.
Claims
1. A junction field effect transistor device, characterized in that: include: a substrate having a first conductivity type; a well buried in the substrate and having a second conductivity type, the second conductivity type being different from the first conductivity type; a first top layer, buried in the well and having the first conductivity type; A plurality of source electrodes or drain electrodes are disposed on a top surface of the well; as well as a first isolation structure adjacent to one of the source or the drain; A gate is disposed on a top surface of the first top layer; A plurality of first wells are arranged below the gate, wherein the second conductive type doping concentration of the first wells is lower than the second conductive type doping concentration of the well.
2. The junction field effect transistor device according to claim 1, characterized in that The first well passes through the first top layer.
3. The junction field effect transistor device according to claim 1, characterized in that Also includes: A second top layer is disposed below the first isolation structure and has the first conductivity type, wherein the first top layer and the second top layer are separated by a distance.
4. The junction field effect transistor device according to claim 1, wherein: Also includes: A gate field plate extends from the top surface of the first top layer to a top surface of the first isolation structure.
5. The junction field effect transistor device according to claim 4, characterized in that The gate field plate is adjacent to the gate.
6. The junction field effect transistor device according to claim 1, wherein: Also includes: A source or drain field plate is disposed on a top surface of the first isolation structure and is electrically connected to one of the source or drain.
7. The junction field effect transistor device according to claim 1, wherein: Also includes: A plurality of second wells are disposed below the first isolation structure, wherein the second conductive type doping concentration of the second wells is lower than the second conductive type doping concentration of the well.
8. The junction field effect transistor device according to claim 1, wherein: Also includes: A second isolation structure is disposed between one of the source or drain and the gate and straddles an edge of the first top layer.
9. The junction field effect transistor device according to claim 1, wherein: The interval between the first wells is 1 μm to 3 μm.
10. The junction field effect transistor device according to claim 1, wherein: A width of one of the first wells is 1 μm to 2 μm.
11. A method for manufacturing a junction field effect transistor device, characterized in that: include: forming a well in a substrate, wherein the substrate has a first conductivity type and the well has a second conductivity type, the second conductivity type being different from the first conductivity type; forming a first top layer in the well, wherein the first top layer has the first conductivity type; Implanting the well with a dopant of the first conductivity type to form a plurality of first well trenches, wherein the dopant concentration of the second conductivity type in the first well trenches is lower than the dopant concentration of the second conductivity type in the well; forming an isolation structure on a top surface of the first top layer; forming a plurality of source electrodes or drain electrodes on a top surface of the well; as well as A gate is formed above the first well trench to cover the first well trench.
12. The method for manufacturing a junction field effect transistor device according to claim 11, wherein: Also includes: Before forming the isolation structure, a second top layer is formed in the well, wherein the second top layer has the first conductivity type and is spaced apart from the first top layer by a distance.
13. The method for manufacturing a junction field effect transistor device according to claim 12, wherein: Also includes: Before forming the isolation structure, a plurality of second well trenches are formed in the well through the second top layer, wherein the second conductive type doping concentration of the second well trenches is lower than the second conductive type doping concentration of the well.
14. The method for manufacturing a junction field effect transistor device according to claim 11, wherein: Also includes: A plurality of field plates are formed above the isolation structure, wherein the field plates are electrically connected to the gate and one of the source or drain, respectively.
15. The method for manufacturing a junction field effect transistor device according to claim 14, wherein: One of the field plates covers an edge of the isolation structure and an edge of the first top layer.
16. The method for manufacturing a junction field effect transistor device according to claim 11, wherein: The second conductivity type doping concentration of the first well is 5E12 cm 2 to 3E15 cm 2 , and the second conductivity type doping concentration of the well is 5E12 cm 2 to 3E15 cm 2 .
17. The method for manufacturing a junction field effect transistor device according to claim 11, wherein: The gate has the first conductivity type, and the first conductivity type doping concentration of the gate is higher than the first conductivity type doping concentration of the first top layer.
18. The method for manufacturing a junction field effect transistor device according to claim 17, wherein: The first conductivity type doping concentration of the first top layer is 2.5E12 cm 2 to 3E12 cm 2 .
19. The method for manufacturing a junction field effect transistor device according to claim 11, wherein: Also includes: Before forming the well, an epitaxial layer is formed in the substrate, wherein the epitaxial layer has the first conductivity type.
20. The method for manufacturing a junction field effect transistor device according to claim 11, wherein: Also includes: A doping region is formed in the substrate, wherein the first conductivity type doping concentration of the doping region is higher than the first conductivity type doping concentration of the substrate.