Fully differential margin amplifier adopting negative feedback network

Abstract

The invention discloses a fully-differential margin amplifier adopting a negative feedback network. The fully-differential margin amplifier comprises a two-stage fully-differential operational amplifier, a common-mode signal amplification circuit, a sampling network and the negative feedback network, wherein the sampling network is connected in series with the two-stage fully differential operational amplifier; the negative feedback network is connected in parallel with the two-stage fully differential operational amplifier; and the common-mode signal amplification circuit is connected in parallel with the first-stage operational amplifier of the two-stage fully differential operational amplifier. According to the fully-differential margin amplifier, the open-loop direct-current gain can reach more than 85 dB, the closed-loop bandwidth can reach more than 15 GHz, and the problem that an existing fully-differential margin amplifier is insufficient in open-loop direct-current gain and closed-loop bandwidth is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of high-speed and high-precision A / D converter design, and in particular relates to a full differential residual amplifier using a negative feedback network. Background Art

[0002] A / D converters that can complete analog-to-digital conversion are key components in modern electronic systems. A / D converters with sampling rates above GHz and resolutions above 12 bits are widely used in radar, wireless communications and other fields. The pipeline architecture can achieve high sampling rates and resolutions at the same time, and is the mainstream architecture for high-speed and high-precision A / D converters.

[0003] The interstage margin amplifier is one of the key modules of the pipeline A / D converter. Its gain and bandwidth restrict the improvement of sampling accuracy and speed. The traditional interstage op amp is a two-stage fully differential common source amplifier structure. Each stage has a local common-mode negative feedback circuit to stabilize the common-mode level. The common-mode negative feedback circuit has a negative impact on the gain and bandwidth of the amplifier. As the conversion accuracy exceeds 12bit and the sampling rate enters the gigahertz range, the A / D converter has higher and higher requirements for the gain and bandwidth of the interstage op amp, usually requiring an open-loop DC gain of more than 80dB and a closed-loop bandwidth of more than 5GHz. However, as the manufacturing process reaches 28nm and below, the problem of insufficient intrinsic gain of the device becomes more and more prominent, making it difficult for the open-loop gain of the op amp to reach the target value; in addition, when the sampling rate of the pipeline A / D converter continues to rise, the bandwidth requirements for the margin amplifier increase significantly.

[0004] In order to solve the problem of insufficient gain of the residual amplifier, the current high-speed and high-precision A / D converter generally adopts digital calibration. The calibration algorithm can estimate the actual gain of the current op amp and calibrate it in the digital domain. However, the actual gain of the op amp will change with the change of the output amplitude. When the output amplitude is large, the gain of the op amp is low, and the gain error estimated by the calibration algorithm is also large. In order to alleviate this problem, on the one hand, a high-order calibration algorithm can be used to estimate a more accurate gain under different output amplitudes, but the cost is that the calibration algorithm is more complex, the convergence time and hardware overhead will also be greater; on the other hand, the common-mode negative feedback circuit of the residual amplifier can be started to reduce its influence on the gain, improve the gain of the op amp itself, and thus improve the calibration accuracy. In order to solve the problem of insufficient bandwidth of the residual amplifier, on the one hand, a lower node process can be used, but it will cause further reduction of gain and increase of cost; on the other hand, the common-mode negative feedback circuit of the residual amplifier can be started to reduce its influence on the bandwidth. Summary of the invention

[0005] The technology of the present invention solves the problem: Overcoming the shortcomings of the prior art, providing a fully differential margin amplifier using a negative feedback network, aiming to solve the problems of insufficient open-loop DC gain and closed-loop bandwidth of the existing fully differential margin amplifier, and enabling the open-loop DC gain to reach above 85dB and the closed-loop bandwidth to reach above 15GHz.

[0006] In order to solve the above technical problems, the present invention discloses a fully differential margin amplifier using a negative feedback network, comprising: a two-stage fully differential operational amplifier, a common-mode signal amplifying circuit, a sampling network and a negative feedback network; wherein the sampling network is connected in series with the two-stage fully differential operational amplifier; the negative feedback network is connected in parallel to the two-stage fully differential operational amplifier; and the common-mode signal amplifying circuit is connected in parallel to the first-stage operational amplifier of the two-stage fully differential operational amplifier.

[0007] In the fully differential residual amplifier using a negative feedback network, the sampling network is used to convert the sampled signal V INP and signal V INM Output to two-stage fully differential op amp; two-stage fully differential op amp, used to INP and signal V INM Amplify and finally output signal V OP2 and V OM2 signal; common mode signal amplifier circuit, used for signal V OM2 and signal V OP2 The negative feedback network is used to amplify the common-mode component of the signal V OM2 and signal V OP2 Feedback to the input of the two-stage fully differential op amp; where the signal V INP is a positive input signal, signal V INM For negative input signal, signal V INP and signal V INM is a complementary differential signal; signal V OP2 is a positive output signal, signal V OM2 is a negative output signal, signal V OP2 and V OM2 The signals are complementary differential signals.

[0008] In the fully differential residual amplifier using a negative feedback network, the sampling network includes: a first sampling switch, a second sampling switch, a third sampling switch, a fourth sampling switch, a first sampling capacitor, a second sampling capacitor and a fifth sampling switch; wherein the first sampling switch is connected across the reference level V REF and negative sampling node S1; the second sampling switch is connected across the signal V INM and negative sampling node S1; the third sampling switch is connected across the signal V INP and positive sampling node S2; the fourth sampling switch is connected across the reference level V REFand positive sampling node S2; the first sampling capacitor is connected across the negative sampling node S1 and the positive summing node A1; the second sampling capacitor is connected across the positive sampling node S2 and the negative summing node A2; and the five sampling switches are connected across the positive summing node A1 and the negative summing node A2.

[0009] In the fully differential residual amplifier using a negative feedback network, the two-stage fully differential operational amplifier is a two-stage fully differential operational amplifier using Miller compensation, including: a first-stage operational amplifier, a second-stage operational amplifier, a first Miller compensation capacitor, and a second Miller compensation capacitor; wherein the positive input terminal of the first-stage operational amplifier is connected to the negative summing node A2, the negative input terminal is connected to the positive summing node A1, the positive output terminal is connected to the positive input terminal of the second-stage operational amplifier, and the negative output terminal is connected to the negative input terminal of the second-stage operational amplifier; the positive output terminal of the second-stage operational amplifier is connected to the secondary negative output node V' OM2 , the negative output terminal is connected to the secondary positive output node V' OP2 ; The first Miller compensation capacitor is connected across the negative input terminal and the positive output terminal of the second stage operational amplifier; and the second Miller compensation capacitor is connected across the positive input terminal and the negative output terminal of the second stage operational amplifier.

[0010] In the fully differential residual amplifier using the negative feedback network, the negative feedback network includes: a first feedback capacitor, a first feedback switch, a second feedback switch, a second feedback capacitor and a third feedback switch; wherein the first feedback capacitor and the first feedback switch are connected in parallel across the positive summing node A1 and the secondary negative output node V' OM2 The second feedback capacitor and the second feedback switch are connected in parallel across the negative summing node A2 and the secondary positive output node V' OP2 ; The third feedback switch is connected across the secondary negative output node V' OM2 and the secondary positive output node V' OP2 .

[0011] In the above-mentioned fully differential residual amplifier using a negative feedback network, the common-mode signal amplification circuit includes: a first PMOS tube, a first NMOS tube, a second PMOS tube and a second NMOS tube; wherein the gate of the first PMOS tube is connected to the positive summing node A1, the source is connected to the source of the second PMOS tube, the source of the first NMOS tube and the source of the second NMOS tube, and the drain is grounded; the gate of the first NMOS tube is connected to the bias level V B , the drain is connected to the negative output node V' OM1 The gate of the second PMOS tube is connected to the negative summing node A2, and the drain is grounded; the gate of the second NMOS tube is connected to the bias level V B , the drain is connected to the positive output node V' OP1 .

[0012] In the fully differential residual amplifier using the negative feedback network, the second sampling switch, the third sampling switch, the fifth sampling switch, the first feedback switch, the second feedback switch and the third feedback switch are driven by the clock signal control; in which, when the clock signal When the clock signal is high, the second sampling switch, the third sampling switch, the fifth sampling switch, the first feedback switch, the second feedback switch and the third feedback switch are closed; when the clock signal When it is at a low level, the second sampling switch, the third sampling switch, the fifth sampling switch, the first feedback switch, the second feedback switch and the third feedback switch are disconnected.

[0013] In the fully differential residual amplifier using the negative feedback network, the first sampling switch and the fourth sampling switch are driven by the clock signal control; in which, when the clock signal When the clock signal is high, the first sampling switch and the fourth sampling switch are closed; When it is at a low level, the first sampling switch and the fourth sampling switch are disconnected.

[0014] In the fully differential margin amplifier using the negative feedback network, the clock signal and clock signal is: a square wave signal with a phase difference of 180 degrees.

[0015] In the above-mentioned fully differential margin amplifier using a negative feedback network, the fully differential margin amplifier includes two working stages:

[0016] Reset phase: When in the reset phase, the signal V INP and signal V INM The data is collected on the sampling network, the positive summing node A1 and the negative summing node A2 are short-circuited, and the secondary negative output node V' OM2 The positive output node V' OP2 Short circuit; the fully differential margin amplifier does not work;

[0017] Amplification stage: When in the amplification stage, the signal V sampled by the sampling network INP and signal V INM The signal V is amplified by two-stage fully differential op amps. OM2 and signal V OP2 ; Signal V OM2 and signal V OP2 The common-mode signal component is fed back to the input of the two-stage fully differential op amp through the negative feedback network, and the common-mode negative feedback is formed through the common-mode signal amplification circuit to stabilize the common-mode output level; wherein, in the amplification stage, the voltage at the positive summing node A1 is the signal V INM With V REFThe signal after the difference is recorded as X signal; the voltage at the negative summing node A2 is V INP With V REF The signal after difference is recorded as Y signal; the differential mode components of the X signal and the Y signal cancel each other out at the source of the first PMOS tube and the second PMOS tube, and there is no amplification effect; the common mode components of the X signal and the Y signal are transmitted to the source of the first PMOS tube and the second PMOS tube, and after being amplified by the common gate amplifier composed of the first NMOS tube and the second NMOS tube, they are transmitted to the output node of the first stage of the two-stage full differential operational amplifier to complete the amplification of the common mode signal.

[0018] The present invention has the following advantages:

[0019] (1) The present invention discloses a fully differential residual amplifier using a negative feedback network. A common-mode signal amplification circuit is connected in parallel to the first stage of the residual amplifier. The common-mode signal amplification circuit has the function of amplifying only the common-mode signal. Part of the original circuit is reused to form a common-mode negative feedback loop, which converts the traditional local common-mode negative feedback into global common-mode negative feedback, thereby simplifying the circuit structure.

[0020] (2) The present invention discloses a fully differential residual amplifier using a negative feedback network. By removing the two common-mode negative feedback circuits of the first and second stages of the traditional residual amplifier, the parasitic capacitance of the first and second stage output ends of the residual amplifier is reduced, the output resistance of the first and second stage output ends of the residual amplifier is increased, and the negative impact of the common-mode negative feedback circuit on the open-loop DC gain and closed-loop bandwidth is reduced, thereby improving the gain and bandwidth.

[0021] (3) The present invention discloses a fully differential residual amplifier using a negative feedback network, which can be applied to high-speed and high-precision A / D converters with sampling rates ranging from hundreds of megahertz to gigahertz, providing technical support for the next step of developing high-speed and high-precision A / D converters with higher conversion bit numbers and sampling rates and higher performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the principle of a fully differential margin amplifier using a negative feedback network in an embodiment of the present invention;

[0023] Figure 2 It is a schematic diagram of the principle of a common-mode signal amplification circuit in an embodiment of the present invention;

[0024] Figure 3 is a waveform diagram of a clock signal in an embodiment of the present invention;

[0025] Figure 4 It is a performance simulation schematic diagram of a fully differential margin amplifier using a negative feedback network in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments disclosed in the present invention will be further described in detail below with reference to the accompanying drawings.

[0027] The present invention proposes a fully differential residual amplifier using a novel negative feedback network for high-speed and high-precision A / D converters with a resolution of 10 to 14 bits and a sampling rate of hundreds of megahertz to gigahertz, which can make the open-loop DC gain reach more than 85dB and the closed-loop bandwidth reach more than 15GHz.

[0028] like Figure 1 As shown, in this embodiment, the fully differential residue amplifier using a negative feedback network includes: a two-stage fully differential operational amplifier 10, a common-mode signal amplifying circuit 20, a sampling network 30 and a negative feedback network 40. The sampling network 30 is connected in series with the two-stage fully differential operational amplifier 10; the negative feedback network 40 is connected in parallel with the two-stage fully differential operational amplifier 10; and the common-mode signal amplifying circuit 20 is connected in parallel with the first-stage operational amplifier 101 of the two-stage fully differential operational amplifier 10.

[0029] In this embodiment, the sampling network 30 is used to convert the sampled signal V INP and signal V INM Output to the two-stage fully differential operational amplifier 10; the two-stage fully differential operational amplifier 10 is used to INP and signal V INM Amplify and finally output signal V OP2 and V OM2 signal; common mode signal amplifier circuit 20, used for signal V OM2 and signal V OP2 The negative feedback network 40 is used to amplify the common mode component of the signal V OM2 and signal V OP2 is fed back to the input of the two-stage fully differential op amp 10; wherein the signal V INP is a positive input signal, signal V INM For negative input signal, signal V INP and signal V INM is a complementary differential signal; signal V OP2 is a positive output signal, signal V OM2 is a negative output signal, signal V OP2 and V OM2 The signals are complementary differential signals.

[0030] In this embodiment, the sampling network 30 includes: a first sampling switch 301, a second sampling switch 302, a third sampling switch 303, a fourth sampling switch 304, a first sampling capacitor 305, a second sampling capacitor 306 and a fifth sampling switch 307. The first sampling switch 301 is connected to the reference voltage V REFand negative sampling node S1; the second sampling switch 302 is connected across the signal V INM and negative sampling node S1; the third sampling switch 303 is connected across the signal V INP and the positive sampling node S2; the fourth sampling switch 304 is connected across the reference level V REF and positive sampling node S2; the first sampling capacitor 305 is connected across the negative sampling node S1 and the positive summing node A1; the second sampling capacitor 306 is connected across the positive sampling node S2 and the negative summing node A2; the five sampling switches 307 are connected across the positive summing node A1 and the negative summing node A2.

[0031] In this embodiment, the two-stage fully differential operational amplifier 10 is a two-stage fully differential operational amplifier using Miller compensation, including: a first-stage operational amplifier 101, a second-stage operational amplifier 102, a first Miller compensation capacitor 103, and a second Miller compensation capacitor 104. Among them, the positive input terminal of the first-stage operational amplifier 101 is connected to the negative summing node A2, the negative input terminal is connected to the positive summing node A1, the positive output terminal is connected to the positive input terminal of the second-stage operational amplifier 102, and the negative output terminal is connected to the negative input terminal of the second-stage operational amplifier 102; the positive output terminal of the second-stage operational amplifier 102 is connected to the secondary negative output node V' OM2 , the negative output terminal is connected to the secondary positive output node V' OP2 ; The first Miller compensation capacitor 103 is connected across the negative input terminal and the positive output terminal of the second stage operational amplifier 102; and the second Miller compensation capacitor 104 is connected across the positive input terminal and the negative output terminal of the second stage operational amplifier 102.

[0032] In this embodiment, the negative feedback network 40 includes: a first feedback capacitor 401, a first feedback switch 402, a second feedback switch 403, a second feedback capacitor 404 and a third feedback switch 405. The first feedback capacitor 401 and the first feedback switch 402 are connected in parallel and connected across the positive summing node A1 and the secondary negative output node V' OM2 The second feedback capacitor 404 and the second feedback switch 403 are connected in parallel across the negative summing node A2 and the secondary positive output node V' OP2 The third feedback switch 405 is connected across the secondary negative output node V' OM2 and the secondary positive output node V' OP2 .

[0033] In this embodiment, if Figure 2As shown, the common mode signal amplifier circuit 20 includes: a first PMOS transistor 201, a first NMOS transistor 202, a second PMOS transistor 203 and a second NMOS transistor 204. The gate of the first PMOS transistor 201 is connected to the positive summing node A1, the source is connected to the source of the second PMOS transistor 203, the source of the first NMOS transistor 202 and the source of the second NMOS transistor 204, and the drain is grounded; the gate of the first NMOS transistor 202 is connected to the bias level V B , the drain is connected to the negative output node V' OM1 The gate of the second PMOS tube 203 is connected to the negative summing node A2, and the drain is grounded; the gate of the second NMOS tube 204 is connected to the bias level V B , the drain is connected to the positive output node V' OP1 .

[0034] In this embodiment, the second sampling switch 302, the third sampling switch 303, the fifth sampling switch 307, the first feedback switch 402, the second feedback switch 403 and the third feedback switch 405 are controlled by the clock signal Control; when the clock signal When the clock signal is high, the second sampling switch 302, the third sampling switch 303, the fifth sampling switch 307, the first feedback switch 402, the second feedback switch 403 and the third feedback switch 405 are closed; When the clock signal is low, the second sampling switch 302, the third sampling switch 303, the fifth sampling switch 307, the first feedback switch 402, the second feedback switch 403 and the third feedback switch 405 are disconnected. Control; when the clock signal When the clock signal is high, the first sampling switch 301 and the fourth sampling switch 304 are closed; When is at a low level, the first sampling switch 301 and the fourth sampling switch 304 are disconnected. Figure 3 As shown, the clock signal and clock signal is: a square wave signal with a phase difference of 180 degrees.

[0035] In this embodiment, the fully differential residue amplifier includes two working stages:

[0036] Reset phase: When in the reset phase, the signal V INP and signal V INM is collected on the sampling network 30, the positive summing node A1 and the negative summing node A2 are short-circuited, and the secondary negative output node V' OM2 The positive output node V' OP2 Shorted; fully differential headroom amplifier does not work.

[0037] Amplification stage: When in the amplification stage, the signal V sampled by the sampling network 30 is INP and signal V INM The signal V is amplified by two-stage fully differential op amp 10. OM2 and signal V OP2 ; Signal V OM2 and signal V OP2 The common-mode signal component of is fed back to the input of the two-stage fully differential operational amplifier 10 through the negative feedback network 40, and forms a common-mode negative feedback through the common-mode signal amplification circuit 20 to stabilize the common-mode output level; wherein, in the amplification stage, the voltage at the positive summing node A1 is the signal V INM With V REF The signal after the difference is recorded as X signal; the voltage at the negative summing node A2 is V INP With V REF The signal after difference is recorded as Y signal; the differential mode components of the X signal and the Y signal cancel each other out at the source of the first PMOS transistor 201 and the second PMOS transistor 203, and there is no amplification effect; the common mode components of the X signal and the Y signal are transmitted to the source of the first PMOS transistor 201 and the second PMOS transistor 203, and after being amplified by the common gate amplifier composed of the first NMOS transistor 202 and the second NMOS transistor 204, they are transmitted to the output node of the first stage operational amplifier 101 of the two-stage full differential operational amplifier 10, thereby completing the amplification of the common mode signal.

[0038] The performance simulation results of a fully differential margin amplifier of the present invention are as follows: Figure 4 The open-loop DC gain is 86.5dB and the closed-loop bandwidth is 16.0GHz.

[0039] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

[0040] The contents not described in detail in the specification of the present invention belong to the common knowledge of the professionals in this field.

Claims

1. A fully differential margin amplifier using a negative feedback network, characterized in that: include: A two-stage fully differential operational amplifier (10), a common-mode signal amplifying circuit (20), a sampling network (30) and a negative feedback network (40); wherein the sampling network (30) is connected in series with the two-stage fully differential operational amplifier (10); the negative feedback network (40) is connected in parallel with the two-stage fully differential operational amplifier (10); and the common-mode signal amplifying circuit (20) is connected in parallel with the first-stage operational amplifier (101) of the two-stage fully differential operational amplifier (10).

2. The fully differential margin amplifier using a negative feedback network according to claim 1, characterized in that: The sampling network (30) is used to convert the sampled signal V INP and signal V INM Output to the two-stage fully differential operational amplifier (10); the two-stage fully differential operational amplifier (10) is used to INP and signal V INM Amplify and finally output signal V OP2 and V OM2 signal; a common-mode signal amplifying circuit (20) for a signal V OM2 and signal V OP2 The negative feedback network (40) is used to amplify the common mode component of the signal V OM2 and signal V OP2 is fed back to the input of the two-stage fully differential operational amplifier (10); wherein the signal V INP is a positive input signal, signal V INM For negative input signal, signal V INP and signal V INM is a complementary differential signal; signal V OP2 is a positive output signal, signal V OM2 is a negative output signal, signal V OP2 and V OM2 The signals are complementary differential signals.

3. The fully differential margin amplifier using a negative feedback network according to claim 2, characterized in that: The sampling network (30) comprises: a first sampling switch (301), a second sampling switch (302), a third sampling switch (303), a fourth sampling switch (304), a first sampling capacitor (305), a second sampling capacitor (306) and a fifth sampling switch (307); wherein the first sampling switch (301) is connected across a reference level V REF and negative sampling node S1; the second sampling switch (302) is connected across the signal V INM and negative sampling node S1; the third sampling switch (303) is connected across the signal V INP and the positive sampling node S2; the fourth sampling switch (304) is connected across the reference level V REF and positive sampling node S2; a first sampling capacitor (305) is connected across the negative sampling node S1 and the positive summing node A1; a second sampling capacitor (306) is connected across the positive sampling node S2 and the negative summing node A2; and a five sampling switch (307) is connected across the positive summing node A1 and the negative summing node A2.

4. The fully differential margin amplifier using a negative feedback network according to claim 3, characterized in that: The two-stage fully differential operational amplifier (10) is a two-stage fully differential operational amplifier using Miller compensation, comprising: a first-stage operational amplifier (101), a second-stage operational amplifier (102), a first Miller compensation capacitor (103), and a second Miller compensation capacitor (104); wherein the positive input terminal of the first-stage operational amplifier (101) is connected to a negative summing node A2, the negative input terminal is connected to a positive summing node A1, the positive output terminal is connected to a positive input terminal of the second-stage operational amplifier (102), and the negative output terminal is connected to a negative input terminal of the second-stage operational amplifier (102); the positive output terminal of the second-stage operational amplifier (102) is connected to a secondary negative output node V' OM2 , the negative output terminal is connected to the secondary positive output node V' OP2 ; a first Miller compensation capacitor (103) is connected across the negative input terminal and the positive output terminal of the second stage operational amplifier (102); and a second Miller compensation capacitor (104) is connected across the positive input terminal and the negative output terminal of the second stage operational amplifier (102).

5. The fully differential margin amplifier using a negative feedback network according to claim 4, characterized in that: A negative feedback network (40) comprises: a first feedback capacitor (401), a first feedback switch (402), a second feedback switch (403), a second feedback capacitor (404) and a third feedback switch (405); wherein the first feedback capacitor (401) and the first feedback switch (402) are connected in parallel and then connected across a positive summing node A1 and a secondary negative output node V' OM2 The second feedback capacitor (404) and the second feedback switch (403) are connected in parallel and then connected across the negative summing node A2 and the secondary positive output node V' OP2 The third feedback switch (405) is connected across the secondary negative output node V' OM2 and the secondary positive output node V' OP2 .

6. The fully differential margin amplifier using a negative feedback network according to claim 5, characterized in that: A common-mode signal amplifying circuit (20) comprises: a first PMOS tube (201), a first NMOS tube (202), a second PMOS tube (203) and a second NMOS tube (204); wherein the gate of the first PMOS tube (201) is connected to a positive summing node A1, the source is connected to the source of the second PMOS tube (203), the source of the first NMOS tube (202) and the source of the second NMOS tube (204), and the drain is grounded; the gate of the first NMOS tube (202) is connected to a bias level V B , the drain is connected to the negative output node V' OM1 The gate of the second PMOS tube (203) is connected to the negative summing node A2, and the drain is grounded; the gate of the second NMOS tube (204) is connected to the bias level V B , the drain is connected to the positive output node V' OP1 .

7. The fully differential margin amplifier using a negative feedback network according to claim 6, characterized in that: The second sampling switch (302), the third sampling switch (303), the fifth sampling switch (307), the first feedback switch (402), the second feedback switch (403) and the third feedback switch (405) are driven by the clock signal control; where the clock signal When the clock signal is high, the second sampling switch (302), the third sampling switch (303), the fifth sampling switch (307), the first feedback switch (402), the second feedback switch (403) and the third feedback switch (405) are closed; When it is at a low level, the second sampling switch (302), the third sampling switch (303), the fifth sampling switch (307), the first feedback switch (402), the second feedback switch (403) and the third feedback switch (405) are disconnected.

8. The fully differential margin amplifier using a negative feedback network according to claim 7, characterized in that: The first sampling switch (301) and the fourth sampling switch (304) are driven by a clock signal control; where the clock signal When the clock signal is high, the first sampling switch (301) and the fourth sampling switch (304) are closed; When it is at a low level, the first sampling switch (301) and the fourth sampling switch (304) are disconnected.

9. The fully differential margin amplifier using a negative feedback network according to claim 8, characterized in that: Clock signal and clock signal is: a square wave signal with a phase difference of 180 degrees.

10. The fully differential margin amplifier using a negative feedback network according to claim 6, characterized in that: The fully differential margin amplifier consists of two operating stages: Reset phase: When in the reset phase, the signal V INP and signal V INM is collected on the sampling network (30), the positive summing node A1 and the negative summing node A2 are short-circuited, and the secondary negative output node V' OM2 The positive output node V' OP2 Short circuit; the fully differential margin amplifier does not work; Amplification stage: When in the amplification stage, the signal V sampled by the sampling network (30) INP and signal V INM The signal V is amplified by two-stage fully differential op amp (10). OM2 and signal V OP2 ; Signal V OM2 and signal V OP2 The common-mode signal component is fed back to the input end of the two-stage fully differential operational amplifier (10) through the negative feedback network (40), and forms common-mode negative feedback through the common-mode signal amplification circuit (20) to stabilize the common-mode output level; wherein, in the amplification stage, the voltage at the positive summing node A1 is the signal V INM With V REF The signal after the difference is recorded as X signal; the voltage at the negative summing node A2 is V INP With V REF The signal after difference is recorded as Y signal; the differential mode components of the X signal and the Y signal cancel each other out at the source electrodes of the first PMOS tube (201) and the second PMOS tube (203), and no amplification effect occurs; the common mode components of the X signal and the Y signal are transmitted to the source electrodes of the first PMOS tube (201) and the second PMOS tube (203), and after being amplified by a common gate amplifier composed of a first NMOS tube (202) and a second NMOS tube (204), are transmitted to the output node of the first stage operational amplifier (101) of the two-stage fully differential operational amplifier (10), thereby completing the amplification of the common mode signal.

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