Flexible and configurable system clock processing system
Through a flexible and configurable system clock processing system, the multi-clock source and phase-locking loop chip are used to realize the flexible configuration and stable transmission of clock frequency of functional modules in complex electronic devices, solving the problems of clock frequency requirements and anti-interference, and improving the System stability and bit error rate reduction effect.
Patent Information
- Application Number
- CN202323562777.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-26
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2033-12-26
AI Technical Summary
Functional boards or functional modules in complex electronic equipment and testing fields require different clock frequencies, low jitter and high stability clocks, and suppress power noise interference to reduce bit error rates in high-speed serial links.
Design a flexible and configurable system clock processing system, including the main control board, clock source module, phase lock loop chip and buffer, adopt multi-clock source selection, processed through FPGA or CPU chip, and use TCXO or OCXO crystal oscillator as The on-board clock source is used to realize the transmission and configuration of clock signals through phase-locked loops and buffers, supporting differential lines or coaxial lines transmission, realizing clock return comparison to monitor clock status.
Achieve multi-clock source selection, flexible clock frequency configuration, up to 1.25Ghz, avoid clock jitter caused by interference, support different clock status monitoring, meet the clock requirements of multi-function modules, improve system stability and anti-interference ability.
Smart Images
Figure CN222167497U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field related to electronic systems or electronic testing systems, and in particular to a flexible and configurable system clock processing system. Background Art
[0002] In the field of complex electronic equipment or electronic testing, there are various functional boards or functional modules that require different clock frequencies or the same clock frequency, or require variable clock frequencies, and sometimes require the same source clock frequency for the functional boards or functional modules to be tested. The clock also needs to have low jitter, high stability, and be able to suppress the interference of power supply noise (PSNR) and reduce the bit error rate (BER) in high-speed serial links.
[0003] In view of the above-mentioned defects, the designers have actively carried out research and innovation in order to create a flexible and configurable system clock processing system to make it more valuable for industrial use. Utility Model Content
[0004] In order to solve the above technical problems, the purpose of the utility model is to provide a flexible and configurable system clock processing system.
[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:
[0006] A flexible and configurable system clock processing system includes a plurality of functional modules arranged in parallel, wherein the functional modules include a main control board, an output link and a functional board or a functional module;
[0007] The main control board includes a main control board chip, a clock source module and a phase-locked loop chip, and the function board or function module includes a plurality of function boards arranged in parallel;
[0008] The clock source module includes the main control board chip clock source, onboard clock source and external input clock source;
[0009] After the external input clock source enters the phase-locked loop chip, it is transmitted to the external input clock source of another functional module through the buffer;
[0010] The clock source of the main control board chip and the onboard clock source enter the phase-locked loop chip, are processed by the main control board chip, and are transmitted to the functional board through the action of the buffer and the output link.
[0011] As a further improvement of the present invention, the main control board chip is an FPGA chip, and its model is Xilinx KU or Xilinx VU.
[0012] As a further improvement of the present invention, the main control board chip is a CPU chip, and its model is Xilinx KU or Xilinx VU.
[0013] As a further improvement of the utility model, the onboard clock source is a TCXO crystal oscillator or an XO crystal oscillator or an OCXO constant temperature crystal oscillator.
[0014] As a further improvement of the present invention, the phase-locked loop chip is a LMK5B12204 chip.
[0015] As a further improvement of the present invention, the buffer has a built-in clock buffer chip, and the model of the clock buffer chip is SN65LVDS116.
[0016] As a further improvement of the present invention, the output link adopts a fully shielded mode and uses differential lines to transmit the clock signal.
[0017] As a further improvement of the present invention, the function board or function module adopts a signal backplane to transmit differential signals, and a 350mV low-amplitude differential signal technology differential clock transmission is adopted during the transmission process.
[0018] As a further improvement of the present invention, the functional module for extended testing is connected to the SMA coaxial connector port of the main control board using a coaxial cable.
[0019] By means of the above solution, the utility model has at least the following advantages:
[0020] The utility model has multiple clock sources to choose from, and the clock sources are flexible and have a wide range (1HZ~800Mhz).
[0021] The output clock of the utility model is controllable, up to 1.25Ghz, and different clock frequencies can be flexibly configured.
[0022] The output clock transmission links of the utility model all adopt differential line transmission or coaxial line transmission, thus avoiding clock jitter caused by various interferences.
[0023] The utility model supports clock return comparison and can monitor the states of two groups of different clocks.
[0024] The above description is only an overview of the technical solution of the utility model. In order to more clearly understand the technical means of the utility model and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the utility model in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the utility model and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying creative work.
[0026] Figure 1 It is a schematic diagram of the principle of a flexible and configurable system clock processing system of the utility model;
[0027] Figure 2 It is a structural block diagram of a specific embodiment of the utility model.
[0028] The meanings of the various reference numerals in the figures are as follows.
[0029] Main control board chip 1, onboard clock source 2, external input clock source 3, phase-locked loop chip 4, buffer 5, function board 6. DETAILED DESCRIPTION
[0030] The following is a further detailed description of the specific implementation of the present invention in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.
[0031] In order to make the technical personnel in the technical field better understand the scheme of the utility model, the technical scheme in the embodiment of the utility model will be clearly and completely described below in combination with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, rather than all the embodiments. The components of the embodiment of the utility model usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiment of the utility model provided in the drawings is not intended to limit the scope of the utility model for protection, but only represents the selected embodiment of the utility model. Based on the embodiment of the utility model, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the utility model.
[0032] Example
[0033] like Figure 1-2 As shown,
[0034] A flexible and configurable system clock processing system includes a plurality of functional modules arranged in parallel, wherein the functional modules include a main control board, an output link and a functional board or a functional module;
[0035] The main control board includes a main control board chip 1, a clock source module and a phase-locked loop chip 4, and the function board or function module includes a plurality of function boards 6 arranged in parallel;
[0036] The clock source module includes the main control board chip clock source, onboard clock source 2 and external input clock source 3;
[0037] After the external input clock source 3 enters the phase-locked loop chip 4, it is transmitted to the external input clock source 3 of another functional module through the action of the buffer 5;
[0038] The main control board chip clock source and the onboard clock source 2 enter the phase-locked loop chip 4 and are processed by the main control board chip 1 and transmitted to the functional board 6 through the action of the buffer 5 and the output link.
[0039] Preferably, the main control board chip 1 is an FPGA chip, and its model is Xilinx KU or Xilinx VU.
[0040] Preferably, the main control board chip 1 is a CPU chip, and its model is Xilinx KU or Xilinx VU.
[0041] Preferably, the onboard clock source 2 is a TCXO crystal oscillator or an XO crystal oscillator or an OCXO constant temperature crystal oscillator.
[0042] Preferably, the phase-locked loop chip 4 is a LMK5B12204 chip.
[0043] Preferably, the buffer 5 has a built-in clock buffer chip, the model of the clock buffer chip is SN65LVDS116, and the output clock capability can reach 400Mhz.
[0044] Preferably, the output link adopts a fully shielded manner and uses differential lines to transmit the clock signal.
[0045] Preferably, the functional board or functional module uses a signal backplane to transmit differential signals, and a 350mV low-amplitude differential signal technology and differential clock transmission are used during the transmission process.
[0046] Preferably, the functional module for the extended test is connected to the SMA coaxial connector port of the main control board using a coaxial cable.
[0047] The utility model provides a method of selecting an external clock, an internal clock, or an internal high-precision TCXO crystal oscillator as a clock source, and then using it through different functional boards or functional modules of a PLL (phase-locked loop chip 4). The phase-locked loop chip 4 uses the LMK5B12204 chip of TI (Texas Instruments) to realize an ultra-low jitter network synchronization clock with two frequency domains; after the main control board chip 1 such as a CPU (central processing unit) or FPGA (programmable logic controller) flexibly configures the phase-locked loop chip 4, four different frequency outputs can be realized, and the output can also be configured to be a clock of the same frequency. Or different clocks can be configured according to needs for use by the functional boards or functional modules of the subsequent stages.
[0048] The utility model realizes the non-interruption switching of the same source configurable clocks with different output frequencies, the input clock can be a wide range clock of 1HZ to 800MHZ; the 10Mhz to 100Mhz clock source provided by the TCXO crystal oscillator or the XO crystal oscillator OCXO constant temperature crystal oscillator can also be used, the clock source can be a single-ended input clock source, and the clock source can also be a differential input clock source.
[0049] The output clock can be divided into four groups, and each group can be configured to use the same frequency or different frequencies according to requirements, with a maximum output clock frequency of 1.25Ghz.
[0050] 1. The specific structure diagram is as above Figure 2 As shown, the complete clock processing circuit is divided into a main control board, an output link and a functional board or functional module and other functional modules. The main control board completes all clock generation and processing except external input, and fans out to each functional board 6 through a buffer 5. The functional board or functional module can be single or multiple, supporting up to 16 functional boards or functional modules. Other functional modules may be an extended test unit that completes the test in parallel with the main functional module.
[0051] 2. Clock Source
[0052] The clock sources are divided into the main control board chip clock source, onboard clock source 2 and external input clock source 3.
[0053] The onboard clock source generally uses a TCXO crystal oscillator or an XO crystal oscillator or an OCXO constant temperature crystal oscillator to generate a relatively stable, low temperature drift clock frequency. Generally speaking, for ease of control and simplicity of circuits, using a lower frequency clock source will reduce PCB (printed circuit board) requirements and save costs. Generally, a crystal oscillator below 25MHZ is used.
[0054] 3. Clock switching method
[0055] Software-controlled switching mode: The clock switching mode can be controlled by the software in the main control board chip 1, and the user can use the client software to initiate a selection to control which clock source to use.
[0056] Hardware control switching method: The clock source can also be connected to the main control board chip 1 for input selection by arranging a hardware switch on the device panel or other parts of the device; the switch is connected to the IO interrupt input terminal of the main control board chip 1. When the main control board chip 1 reads this selection, it sends an instruction to control the clock selection circuit to make a choice between different clock sources.
[0057] 4. Clock Output
[0058] The clock output circuit uses a professional high-speed clock fan-out chip with fully differential output, which can maximize the line transmission efficiency and transmission quality and avoid various interferences.
[0059] 5. Output Link
[0060] The output link adopts a fully shielded method and uses differential lines to transmit clock signals to reduce clock jitter; it includes using the main control board to insert into the signal backplane and then connecting to the functional board or functional module through the signal backplane. The connector used also supports differential transmission and has a grounding shielding function.
[0061] 6. Clock Return Comparison
[0062] Clock return comparison means that the configured clock returns a clock signal to the main control board chip 1. This clock signal is used for detection, monitoring and comparison to determine whether the clock configuration information is correct.
[0063] 7. Clock User Terminal
[0064] The clock using end includes a functional board or functional module and an external extended test functional unit module. The functional board or functional module can use a signal backplane to transmit differential signal connections. During the transmission process, 350mV LVDS (low amplitude differential signal technology) differential clock transmission is used; the extended test functional unit module is connected to the SMA (coaxial connector) port of the main control board using a coaxial cable, as shown in the following example. Figure 1 shown.
[0065] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly referring to the number of technical features indicated. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.
[0066] In the description of the present utility model, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the utility model can be understood through specific circumstances.
[0067] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the technical principle of the present invention, and these improvements and modifications should also be regarded as within the protection scope of the present invention.
Claims
1. A flexible and configurable system clock processing system, comprising a plurality of functional modules arranged in parallel, wherein the functional modules include a main control board, an output link and a functional board or a functional module; Features: The main control board comprises a main control board chip (1), a clock source module and a phase-locked loop chip (4); the functional board or functional module comprises a plurality of functional boards (6) arranged in parallel; The clock source module comprises a main control board chip clock source, an onboard clock source (2) and an external input clock source (3); After the external input clock source (3) enters the phase-locked loop chip (4), it is transmitted to the external input clock source (3) of another functional module through the action of the buffer (5); The main control board chip clock source and the onboard clock source (2) enter the phase-locked loop chip (4), are processed by the main control board chip (1), and are transmitted to the functional board card (6) through the action of the buffer (5) and the output link.
2. A flexible and configurable system clock processing system as claimed in claim 1, characterized in that: The main control board chip (1) is an FPGA chip, and its model is Xilinx KU or Xilinx VU.
3. A flexible and configurable system clock processing system as claimed in claim 1, characterized in that: The main control board chip (1) is a CPU chip, and its model is Xilinx KU or Xilinx VU.
4. A flexible and configurable system clock processing system as claimed in claim 1, characterized in that: The onboard clock source (2) is a TCXO crystal oscillator or an XO crystal oscillator or an OCXO constant temperature crystal oscillator.
5. A flexible and configurable system clock processing system as claimed in claim 1, characterized in that: The phase-locked loop chip (4) is a LMK5B12204 chip.
6. A flexible and configurable system clock processing system as claimed in claim 1, characterized in that: The buffer (5) has a built-in clock buffer chip, and the model of the clock buffer chip is SN65LVDS116.
7. A flexible and configurable system clock processing system as claimed in claim 1, characterized in that: The output link adopts a fully shielded mode and uses differential lines to transmit clock signals.
8. A flexible and configurable system clock processing system as claimed in claim 1, characterized in that: The functional board or functional module uses a signal backplane to transmit differential signals, and uses a 350mV low-amplitude differential signal technology and differential clock transmission during the transmission process.
9. A flexible and configurable system clock processing system as claimed in claim 1, characterized in that: The functional module for the extended test is connected to the SMA coaxial connector port of the main control board using a coaxial cable.