2b / cycle successive approximation analog-to-digital converter with double comparators

Abstract

The utility model discloses a 2b / cycle successive approximation analog-to-digital converter of double comparators. The digital-to-analog converter comprises a DAC module, a comparator module, a recoding module and a successive approximation logic module, the DAC module comprises a main DAC capacitor array and an auxiliary DAC capacitor array, the main DAC capacitor array comprises a main quantization capacitor and a main C0 capacitor, the auxiliary DAC capacitor array adopts a differential structure to generate reference voltage, the auxiliary DAC capacitor array comprises an auxiliary capacitor and an auxiliary C0 capacitor, and the auxiliary C0 capacitor is used for generating reference voltage. The comparator module is composed of a comparator CMP1, a comparator CMP2 and two NOR gates, the comparator CMP1 is connected with the main DAC capacitor array, and the comparator CMP2 is connected with the main DAC capacitor array. The SAR ADC has the advantages of playing an important role in improving the linearity of the ADC, reducing the power consumption and the area of the SAR ADC, ensuring the stability of an asynchronous time sequence, having higher linearity and lower power consumption, realizing analog-to-digital conversion of high-speed data, and improving the conversion accuracy.

Description

Technical Field

[0001] The utility model relates to a high-speed data converter, in particular to a 2b / cycle successive approximation analog-to-digital converter with double comparators. Background Art

[0002] In the field of digital signal processing and electronic measurement, analog-to-digital converters (ADCs) play a vital role. Successive approximation register (SAR) ADCs are favored for their simple structure and low power consumption. However, with the increasing requirements for data processing speed in modern electronic systems, the limitations of traditional SAR ADCs in conversion speed have gradually become prominent, becoming a key factor restricting the expansion of its application range. The 2b / cycle ADC came into being in this context. It can simultaneously determine two digital codes in each quantization cycle, thereby significantly improving the conversion rate. For an N-bit ADC, after adopting the 2b / cycle technology, only N / 2 cycles are needed to complete the entire quantization process, which means that its conversion speed is doubled compared to the traditional SAR ADC. The 2b / cycle SAR ADC under this technical background not only maintains the advantages of low power consumption and high precision of SAR ADC, but also greatly improves the conversion efficiency by reducing the required quantization cycle, making it more suitable for high-speed signal processing occasions.

[0003] The 2b / cycle SAR ADC requires two DACs, a main DAC for sampling and quantizing the input signal, and an auxiliary DAC for generating the three reference voltages required for quantization comparison. In addition, at least three comparators are required to compare the three reference voltages with the residual signal generated by the main DAC. The output of these comparators is a thermometer code, which is then converted into a binary code to complete the quantization of two bits per cycle. However, the mismatch between different comparators will affect the linearity of the entire ADC, and the three comparators will increase the power consumption of the overall circuit. Summary of the invention

[0004] The technical problem to be solved by the utility model is to provide a 2b / cycle successive approximation analog-to-digital converter with dual comparators having higher linearity and lower power consumption.

[0005] In order to solve the above technical problems, a 2b / cycle successive approximation analog-to-digital converter using a dual comparator of a new model is disclosed, comprising a DAC module, a comparator module, a recoding module and a successive approximation logic module, wherein the DAC module comprises a main DAC capacitor array and an auxiliary DAC capacitor array, wherein the main DAC capacitor array comprises 2N-2 main quantization capacitors and a main C0 capacitor for matching an input signal range with a quantization range, wherein the upper plate of the main quantization capacitor is connected to an input signal, and the lower plate of the main quantization capacitor is connected to a DAC signal with a cut margin, wherein the auxiliary DAC capacitor array adopts a differential structure for generating a reference voltage, and the auxiliary DAC capacitor array comprises a main DAC capacitor array and an auxiliary DAC capacitor array, wherein the main DAC capacitor array comprises a main quantization capacitor array and an auxiliary DAC capacitor array, wherein the main quantization capacitor array comprises a main C0 capacitor for matching an input signal range with a quantization range, wherein the upper plate of the main quantization capacitor is connected to an input signal, and the lower plate of the main quantization capacitor is connected to a DAC signal with a cut margin, wherein the auxiliary DAC capacitor array adopts a differential structure for generating a reference voltage, and the auxiliary DAC capacitor array comprises a main DAC capacitor array and an auxiliary DAC capacitor array, wherein the main quantization capacitor array comprises a main quantization ... The capacitor array includes 2N-2 auxiliary capacitors and an auxiliary C0 capacitor for adjusting the size of the reference voltage. The upper plate of the auxiliary DAC capacitor array is connected to the input reference voltage. The other side array of the auxiliary DAC capacitor array generates the reference DAC voltage that needs to be compared next time. The comparator module is composed of comparator CMP1, comparator CMP2 and two NOR gates. Comparator CMP1 is connected to the main DAC capacitor array and is used to compare the residual signal on the main DAC capacitor array with the low reference voltage. Comparator CMP2 is connected to the main DAC capacitor array and is used to compare the residual signal on the main DAC capacitor array with the high reference voltage.

[0006] The comparator CMP1 and the comparator CMP2 are both four-input comparators, and the four-input comparator is connected to a clock CLKC. The first stage of the four-input comparator adopts a four-input dynamic pre-amplifier, the second stage is an inverter, and the third stage is a latch structure. When the clock CLKC is at a low level, the output ends of the comparator CMP1 and the comparator CMP2 both output 1; when the clock CLKC flips to a high level, one end of the four-input comparator outputs a high level, and the other end outputs a low level.

[0007] The outputs of the comparator CMP1 and the comparator CMP2 are both connected to the 1-bit TDC and can determine the difference between the differential input signal and the high reference voltage and the low reference voltage according to the comparison time of the comparator CMP1 and the comparator CMP2, and finally obtain a 3-bit thermometer code.

[0008] The clock CLKC is composed of a two-input NAND gate and a three-input NOR gate and can generate an asynchronous clock from the outputs CMPP2 and CMPN2 of the 1-bit TDC.

[0009] The successive approximation logic module is connected to the comparison module and can directly generate a control signal for switching the main CDAC and auxiliary DAC switch arrays according to the 3-bit thermometer code generated by the comparison module.

[0010] The successive approximation logic module has two dynamic control logic units and can use output nodes P and N to control the bottom plate of the capacitor array after the dynamic control logic units Outp and Outn are valid; P and N of one dynamic control logic unit are respectively connected to the outputs CMPP2 and CMPN2 of the 1-bit TDC, and P and N of the other dynamic control logic unit are respectively connected to the outputs CMPN1 and CMPP3 of two four-input comparators.

[0011] The re-encoding module is connected to the comparator CMP1 and the comparator CMP2 via the successive approximation logic module and can be used to re-encode the 3-bit thermometer code generated by the comparator CMP1, the comparator CMP2 and the 1-bit TDC to obtain the corresponding binary digital code.

[0012] The advantages of the utility model are:

[0013] The converter uses only two comparators to obtain a 3-bit thermometer code. Compared with the traditional 2b / cycle SAR ADC, the reduction in the number of comparators plays an important role in improving the linearity of the ADC and reduces the power consumption and area of ​​the SAR ADC by reducing one comparator. At the same time, the stability of the asynchronous timing is guaranteed, and it has higher linearity and lower power consumption. Through the cleverly designed circuit structure, the converter can effectively realize the analog-to-digital conversion of high-speed data and improve the accuracy of the conversion without increasing the complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic diagram of the architecture of a 2b / cycle successive approximation analog-to-digital converter with dual comparators of the utility model;

[0015] Figure 2 It is a schematic diagram of the main CDAC array structure in the utility model;

[0016] Figure 3 It is a schematic diagram of the auxiliary CDAC array structure in the utility model;

[0017] Figure 4 It is a schematic diagram of the structure of a four-input comparator in the utility model;

[0018] Figure 5 This is a schematic diagram of a 1-bit TDC in the present utility model;

[0019] Figure 6 This is the asynchronous clock logic circuit diagram of the utility model;

[0020] Figure 7 It is a schematic diagram of the successive approximation logic module in the utility model;

[0021] Figure 8It is a circuit diagram of the re-encoding module in the utility model. DETAILED DESCRIPTION

[0022] The following is a further detailed description of the 2b / cycle successive approximation analog-to-digital converter with dual comparators of the present invention in conjunction with the accompanying drawings and specific implementations.

[0023] As shown in the figure, the 2b / cycle successive approximation analog-to-digital converter of the dual comparator of the utility model includes a DAC module, a comparator module, a recoding module and a successive approximation logic module. The DAC module includes a main DAC capacitor array and an auxiliary DAC capacitor array. Figure 2 As shown, the main DAC capacitor array includes 2N-2 main quantization capacitors (numbered C1p, C2p, C3p, ..., CN-1p and C1n, C2n, C3n, ..., CN-1n in descending order according to weight, where N is the number of bits of the analog-to-digital converter) and a main C0 capacitor for matching the input signal range with the quantization range. The upper plate of the main quantization capacitor is connected to the input signal through a gate voltage bootstrap switch, and the lower plate of the main quantization capacitor is connected to the DAC signal of the cut margin, as shown in FIG. Figure 3 As shown, the auxiliary DAC capacitor array (single-sided capacitor array) adopts a differential structure to generate a reference voltage. The auxiliary DAC capacitor array includes 2N-2 auxiliary capacitors (numbered C1p, C2p, C3p, ..., CN-1p and C1n, C2n, C3n, ..., CN-1n in descending order according to weight) and an auxiliary C0 capacitor for adjusting the size of the reference voltage. The upper plate of the auxiliary DAC capacitor array is connected to the input reference voltage (the reference voltage V FS / 2), the other side of the auxiliary DAC capacitor array switches the switch array to generate the reference DAC voltage that needs to be compared next time. In the sampling phase, the input signal is sampled to the top plate of CDAC (main DAC capacitor array) through the gate voltage bootstrap switch S1 and the gate voltage bootstrap switch S2, and the bottom plate is connected to the high reference voltage and the low reference voltage respectively through the switch. In the sampling phase of the auxiliary DAC (auxiliary DAC capacitor array), the differential reference voltage V FS / 4 is sampled on the top plate. When the sampling phase is over, the first comparison is performed directly without switching the bottom plate switches of the main DAC array and the auxiliary DAC array. The comparator module is composed of a comparator CMP1, a comparator CMP2 and two NOR gates. The comparator CMP1 is connected to the main DAC capacitor array and is used to compare the residual signal on the main DAC capacitor array with the low reference voltage (-V F The comparator CMP2 is connected to the main DAC capacitor array and is used to compare the residual signal on the main DAC capacitor array with the high reference voltage (V FS / 2) for comparison, a 1-bit TDC is composed of two NOR gates. Two comparators and a 1-bit TDC can generate a 3-bit thermometer code.

[0024] Furthermore, the comparator CMP1 and the comparator CMP2 are both four-input comparators, the four-input comparator is connected to the clock CLKC, the first stage of the four-input comparator adopts a four-input dynamic pre-amplifier, the second stage is an inverter, and the third stage is a latch structure and can reset the comparator CMP1 and the comparator CMP2 when the clock CLKC is at a low level, so that the output ends of the comparator CMP1 and the comparator CMP2 both output 1; when the clock CLKC flips to a high level, the four-input comparator compares the input signal voltage (Vip-Vin) with the reference voltage, and after amplification by the first stage pre-amplifier, the latch is latched according to the inputs of the first two stages, so that one end of the four-input comparator outputs a high level and the other end outputs a low level,

[0025] When Vip-Vin=Vrefn-Vrefp, it is the threshold value of the four-input comparator. The traditional 2b / cycle SAR ADC uses three comparators to make the input signal on the top plate of the main DAC and +V FS / 2,0,-V FS / 2, the two comparators of the comparator module of the utility model compare the input signal on the top plate of the main DAC with +V FS / 2, -V FS / 2 for comparison.

[0026] like Figure 5 As shown in FIG. 1 , the outputs of comparator CMP1 and comparator CMP2 are both connected to a 1-bit TDC. Since the larger the difference between the differential input signal and the reference voltage, the shorter the comparison time, the difference between the differential input signal and +V can be determined based on the comparison time of comparator CMP1 and comparator CMP2. FS / 2 and -V FS / 2 the difference, and finally a 3-bit thermometer code is obtained, and a comparator can be omitted, reducing the power consumption of the overall SAR ADC. When reset, the outputs of the two comparators are both high, and the outputs of both ends of the 1-bit TDC are 1.

[0027] In a 2b / cycle SAR ADC, only the differential input signal needs to be compared with a high reference voltage (V FS / 2) and a low reference voltage (-V FS / 2) for comparison, so only one V needs to be generated in the auxiliary DAC before each comparison. FS / 2 differential reference voltage. When the difference between Vip-Vin and Vrefn-Vrefp is larger, the equivalent transconductance of the comparator input to the tube is larger, and the comparison time is shorter. The outputs of the two comparators are connected to a 1-bit TDC composed of two NOR gates to obtain a 3-bit thermometer code; for example, when the input signal is [V FS / 2,V FS ] interval, CMPN1 outputs 0, CMPP3 outputs 1, and the P-terminal output of the 1-bit TDC is high, and the thermometer code 111 can be obtained; when the input signal is in [0, V FS / 2] interval, the two comparator outputs CMPP3 and CMPN1 are low, but due to the differential input signal and -V FS / 2 is larger, CMPN1 will drop faster than CMPP3, the two NOR gates will have positive feedback, CMPP2 output is high level, CMPN2 output is low level, and the generated thermometer code is 011; when the input signal is in [-V FS / 2,0] interval, the outputs of the two comparators CMPP3 and CMPN1 are low, but due to the differential input signal and V FS / 2 is larger, CMPP3 will drop faster than CMPN1, the two NOR gates will have positive feedback, CMPP2 output is low level, CMPN2 output is high level, and the generated thermometer code is 001; when the input signal is in [-V FS , -V FS / 2] interval, CMPP3 output is low level, CMPN1 output is high level, it can be obtained that CMPP2 output is low level, CMPN2 output is high level, and the thermometer code 000 can be obtained.

[0028] Further, Figure 6The asynchronous clock logic circuit is shown. The clock CLKC is composed of a two-input NAND gate and a three-input NOR gate and can generate an asynchronous clock from the outputs CMPP2 and CMPN2 of a 1-bit TDC. The traditional 2b / cycle SAR ADC uses three comparators. The comparison time of different comparators is completely inconsistent each time, which cannot guarantee the stability of the asynchronous clock and increases the complexity of the circuit. In the above circuit structure, CMPP2 and CMPN2 must be generated through a simple logic gate after the comparison between comparators CMP1 and CMP2 is completed. Therefore, CMPP2 and CMPN2 ensure that the asynchronous clock will not flip until the thermometer code is completely established. In the reset stage, CMPP2 and CMPN2 are both high level. At this time, the NAND gate output is low level, and the Valid signal is high level. When the SAR ADC completes a comparison, one end of a TDC outputs a high level and the other end outputs a low level. At this time, the NAND gate outputs a high level and the Valid signal is low level. The input terminals of the three-input NOR gate are respectively connected to the sampling clock CLKS, the comparison completion flag signal RDY and the output signal of the NAND gate to generate an asynchronous clock CLKC signal of the comparator.

[0029] Furthermore, if Figure 7 As shown, the successive approximation logic module is connected to the comparison module and can directly generate a control signal for switching the main CDAC and auxiliary DAC switch arrays according to the 3-bit thermometer code generated by the comparison module, without first converting the thermometer code to binary code, so as to achieve a faster quantization speed.

[0030] Furthermore, the SAR ADC implements the process of successive approximation under the control of the SAR logic. The SAR logic circuit directly uses the 3-bit thermometer code generated by the comparison module to generate the control signal to switch the capacitor array and latch the control signal. When all conversions are completed, all control signals are latched and the thermometer code is converted into binary code and output uniformly. The power consumption of digital circuits based on traditional SAR control logic is still very significant. In order to reduce the power consumption of digital circuits,

[0031] like Figure 7As shown, since two binary codes need to be converted for each comparison, two dynamic control logic units are required for each comparison. For this reason, the successive approximation logic module has two dynamic control logic units. During the sampling phase, the input D is at a low level, and the outputs P and N of the dynamic control logic unit are reset to zero, and the node Q is also discharged to the ground. When the input D changes from low to high, CLKi is pulled down to the ground. Since the two-digit code is quantized in each comparison cycle, when the dynamic control logic units Outp and Outn are valid, the output nodes P and N are used to control the bottom plate of the capacitor array. The P and N of one dynamic control logic unit are connected to the outputs CMPP2 and CMPN2 of a TDC, respectively, and the P and N of the other dynamic control logic unit are connected to the outputs CMPN1 and CMPP3 of two four-input comparators, respectively. The Valid signal is generated by the output of a TDC and the negative operation. At the same time, when the falling edge of the Valid signal arrives, the output Q is pulled up to VDD, indicating that this conversion is completed. The P and N of the dynamic logic control unit control the switch switching of the bottom plate of the reference voltage DAC through AND operation. The outputs P1~Pn and N1~Nn of the dynamic control logic unit generate control signals through the combinational logic circuit to control the capacitor drive switch to switch the capacitor in the DAC array, completing the successive approximation process.

[0032] In the example of quantization of a 2b / cycle SAR ADC, a 3-bit thermometer code can be generated by two comparators and a 1-bit TDC. The input signal is sampled to the top plate of the main CDAC through the gate voltage bootstrap switch. After sampling, there is no need to switch the bottom plate switch array. The first conversion process is directly performed. The generated 3-bit thermometer code is directly used to control the switching of the switch array to prepare for the next conversion.

[0033] The outputs CMPP2 and CMPN2 of the 1-bit TDC control the bottom plate switch array control signals P2, N2, P4, N4, ... of the main CDAC by the successive approximation logic unit; the outputs CMPP1 and CMPN3 of the two comparators control the bottom plate switch array control signals P1, N1, P3, N3, ... of the main CDAC by the successive approximation logic unit. The switch array control signals RP1, RP2, RP3, ... of the reference voltage DAC are generated by P2 / N2, P4 / N4, P6 / N6, ..., and the subsequent conversion is completed according to the above bottom plate switch array switching method.

[0034] Furthermore, if Figure 8As shown, the re-encoding module is connected to the comparator CMP1 and the comparator CMP2 through a logic circuit. The re-encoding module is used to re-encode the 3-bit thermometer code generated by the two comparators and the 1-bit TDC to obtain the corresponding binary digital code. The re-encoding module can generate a binary code according to the Pi and Ni signals output by the dynamic control logic unit and obtain the final binary digital code through unified latching. The first group of dynamic control logic units outputs P1, P2, N1 and N2. The second bit D2 in the two-bit binary code can be obtained from P2. P1 and N1 are subjected to an OR-N operation, and then the output result is subjected to an XOR operation with P2 to obtain the first bit D1 in the two-bit binary code, completing the encoding of a group of two-bit binary codes. Similarly, the conversion of other binary codes is completed, and the final binary digital code is obtained through unified latching.

[0035] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. A 2b / cycle successive approximation analog-to-digital converter with dual comparators, comprising a DAC module, a comparator module, a recoding module and a successive approximation logic module, characterized in that: The DAC module includes a main DAC capacitor array and an auxiliary DAC capacitor array. The main DAC capacitor array includes 2N-2 main quantization capacitors and a main C0 capacitor for matching the input signal range with the quantization range. The upper plate of the main quantization capacitor is connected to the input signal, and the lower plate of the main quantization capacitor is connected to the DAC signal of the cut margin. The auxiliary DAC capacitor array adopts a differential structure to generate a reference voltage. The auxiliary DAC capacitor array includes 2N-2 auxiliary capacitors and an auxiliary C0 capacitor for adjusting the size of the reference voltage. The upper plate of the auxiliary DAC capacitor array is connected to the input reference voltage, and the other side array of the auxiliary DAC capacitor array generates a reference DAC voltage to be compared next time. The comparator module consists of a comparator CMP1, a comparator CMP2 and two NOR gates. The comparator CMP1 is connected to the main DAC capacitor array and is used to compare the margin signal on the main DAC capacitor array with a low reference voltage. The comparator CMP2 is connected to the main DAC capacitor array and is used to compare the margin signal on the main DAC capacitor array with a high reference voltage.

2. The 2b / cycle successive approximation analog-to-digital converter of dual comparators according to claim 1, characterized in that: The comparator CMP1 and the comparator CMP2 are both four-input comparators, and the four-input comparator is connected to a clock CLKC. The first stage of the four-input comparator adopts a four-input dynamic pre-amplifier, the second stage is an inverter, and the third stage is a latch structure. When the clock CLKC is at a low level, the output ends of the comparator CMP1 and the comparator CMP2 both output 1; when the clock CLKC flips to a high level, one end of the four-input comparator outputs a high level, and the other end outputs a low level.

3. The 2b / cycle successive approximation analog-to-digital converter of dual comparators according to claim 2, characterized in that: The outputs of the comparator CMP1 and the comparator CMP2 are both connected to the 1-bit TDC and can determine the difference between the differential input signal and the high reference voltage and the low reference voltage according to the comparison time of the comparator CMP1 and the comparator CMP2, and finally obtain a 3-bit thermometer code.

4. The 2b / cycle successive approximation analog-to-digital converter of dual comparators according to claim 3, characterized in that: The clock CLKC is composed of a two-input NAND gate and a three-input NOR gate and can generate an asynchronous clock from the outputs CMPP2 and CMPN2 of the 1-bit TDC.

5. The 2b / cycle successive approximation analog-to-digital converter of dual comparators according to claim 4, characterized in that: The successive approximation logic module is connected to the comparison module and can directly generate a control signal for switching the main CDAC and auxiliary DAC switch arrays according to the 3-bit thermometer code generated by the comparison module.

6. The 2b / cycle successive approximation analog-to-digital converter of dual comparators according to claim 5, characterized in that: The successive approximation logic module has two dynamic control logic units and can use output nodes P and N to control the bottom plate of the capacitor array after the dynamic control logic units Outp and Outn are valid; P and N of one dynamic control logic unit are respectively connected to the outputs CMPP2 and CMPN2 of the 1-bit TDC, and P and N of the other dynamic control logic unit are respectively connected to the outputs CMPN1 and CMPP3 of two four-input comparators.

7. The 2b / cycle successive approximation analog-to-digital converter of dual comparators according to claim 6, characterized in that: The re-encoding module is connected to the comparator CMP1 and the comparator CMP2 via the successive approximation logic module and can be used to re-encode the 3-bit thermometer code generated by the comparator CMP1, the comparator CMP2 and the 1-bit TDC to obtain the corresponding binary digital code.

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