Hybrid passivated back contact cell

Abstract

The utility model discloses a hybrid passivation back contact cell. The cell comprises a silicon wafer; the heterostructure comprises a first passivation layer which is at least stacked on the first region and a first microcrystalline silicon layer which is fully or partially doped; the first electrode structure is located on the first microcrystalline silicon layer in the heterostructure; the first passivation structure comprises a tunneling oxide layer and a doped polycrystalline silicon layer which are stacked on the second region; the second electrode structure is located on the doped polycrystalline silicon layer in the first passivation structure; the second passivation structure comprises a second passivation layer at least stacked on the first surface and a second microcrystalline silicon layer which is fully or partially doped, the crystallization rate of the second microcrystalline silicon layer is larger than that of the first microcrystalline silicon layer, and the doping type of the second microcrystalline silicon layer is opposite to that of the first microcrystalline silicon layer. According to the utility model, good passivation and tunneling contact performance can be realized, and the electrical performance and the photoelectric conversion efficiency of the cell are significantly improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of solar energy, and in particular relates to a hybrid passivation back contact (HTBC) battery. Background Art

[0002] Silicon heterojunction solar cells have achieved record efficiencies, especially in solar cells combined with back contacts. Nevertheless, the passivation contacts of amorphous silicon thin films still suffer from parasitic absorption and series resistance losses. Microcrystalline silicon is an alternative to doped amorphous silicon. By exploiting the indirect nature of the crystalline silicon bandgap, the microcrystalline silicon contact layer has higher transparency and charge transport capabilities than the amorphous contact layer while maintaining superior passivation quality. Therefore, it achieves a good compromise between passivation quality and reducing parasitic absorption of more transparent materials. Although a sufficiently thin high crystalline layer can reduce parasitic absorption, high crystallinity does not necessarily mean better conductivity. On the contrary, it will also lead to high contact resistivity with transparent conductive oxides, resulting in efficiency loss.

[0003] The prior art does not propose an effective design for the microcrystalline silicon layer, especially for the back contact cell structure.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a hybrid passivated back contact battery. Utility Model Content

[0005] In view of this, an object of the present invention is to provide a hybrid passivated back contact cell to improve the photoelectric conversion efficiency.

[0006] In order to achieve the above purpose, the technical solution provided by an embodiment of the present utility model is as follows:

[0007] A hybrid passivated back contact battery, comprising:

[0008] The silicon wafer comprises a first surface and a second surface arranged opposite to each other, wherein the second surface comprises a first region and a second region, and an area of ​​the first region is larger than an area of ​​the second region;

[0009] A heterogeneous structure, comprising at least a first passivation layer stacked on the first region and a first microcrystalline silicon layer that is fully or partially doped;

[0010] A first electrode structure is located on the first microcrystalline silicon layer in the heterostructure;

[0011] A first passivation structure includes a tunneling oxide layer and a doped polysilicon layer stacked on the second region;

[0012] a second electrode structure, located on the doped polysilicon layer in the first passivation structure;

[0013] The second passivation structure includes at least a second passivation layer stacked on the first surface and a fully or partially doped second microcrystalline silicon layer, the crystallization rate of the second microcrystalline silicon layer is greater than the crystallization rate of the first microcrystalline silicon layer, and the doping type of the second microcrystalline silicon layer is opposite to the doping type of the first microcrystalline silicon layer.

[0014] In one embodiment, the crystallization rate of the first microcrystalline silicon layer is 62% to 69%; and / or,

[0015] The crystallization rate of the second microcrystalline silicon layer is 70% to 78%.

[0016] In one embodiment, the first microcrystalline silicon layer includes a first inner microcrystalline silicon layer, a first middle microcrystalline silicon layer and a first outer microcrystalline silicon layer sequentially stacked on the first passivation layer, the first inner microcrystalline silicon layer is an intrinsic microcrystalline silicon layer, and the first middle microcrystalline silicon layer and the first outer microcrystalline silicon layer are doped microcrystalline silicon layers.

[0017] In one embodiment, the thickness of the first microcrystalline silicon layer is 25 nm to 40 nm; and / or,

[0018] The thickness of the first inner microcrystalline silicon layer is 1 nm to 5 nm; and / or,

[0019] The thickness of the first microcrystalline silicon layer is 20 nm to 28 nm; and / or,

[0020] The thickness of the first outer microcrystalline silicon layer is 4 nm to 7 nm; and / or,

[0021] The doping concentration of the first microcrystalline silicon layer is 1E17 cm -3 ~1E19cm -3 and / or,

[0022] The doping concentration of the first outer microcrystalline silicon layer is 1E19 cm -3 ~1E20cm -3 .

[0023] In one embodiment, the second microcrystalline silicon layer includes a seed layer and a second outer microcrystalline silicon layer sequentially stacked on the second passivation layer, the seed layer and the second outer microcrystalline silicon layer are both hydrogen-containing doped microcrystalline silicon layers, and the hydrogen content in the seed layer is greater than the hydrogen content in the second outer microcrystalline silicon layer.

[0024] In one embodiment, the thickness of the second microcrystalline silicon layer is 29 nm to 40 nm; and / or,

[0025] The thickness of the seed layer is 2nm to 5nm; and / or,

[0026] The thickness of the second outer microcrystalline silicon layer is 27 nm to 35 nm; and / or,

[0027] The doping concentration of the second outer microcrystalline silicon layer is 1E17 cm -3 ~1E19cm -3 .

[0028] In one embodiment, the first passivation layer and / or the second passivation layer comprises an intrinsic hydrogenated amorphous silicon layer; and / or,

[0029] The thickness of the first passivation layer is 4.5 nm to 6 nm; and / or,

[0030] The thickness of the second passivation layer is 5 nm to 7 nm; and / or,

[0031] The tunneling oxide layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0032] The thickness of the tunnel oxide layer is 1 nm to 2 nm; and / or,

[0033] The thickness of the doped polysilicon layer is 120nm to 200nm; and / or,

[0034] The doping concentration of the doped polysilicon layer is 1E21cm -3 ~1E22cm -3 and / or,

[0035] An anti-reflection layer is further stacked on the second microcrystalline silicon layer, and the anti-reflection layer includes a combination of one or more of a SiNx layer, a SiNxOy layer, and a TCO layer.

[0036] In one embodiment, the first passivation layer and the first microcrystalline silicon layer are stacked on the first passivation structure on the entire first region and part of the second region, and an electrode window not covered by the first passivation layer and the first microcrystalline silicon layer is formed on the doped polysilicon layer.

[0037] In one embodiment, the first electrode structure includes a first TCO layer and a first electrode, the first TCO layer is at least located on the first microcrystalline silicon layer in the first region, and the first electrode is in electrical contact with the first TCO layer;

[0038] The second electrode structure comprises a second TCO layer and a second electrode, wherein the second TCO layer is at least located in the electrode window on the second region, and the second electrode is in electrical contact with the second TCO layer;

[0039] The first TCO layer and the second TCO layer are electrically isolated from each other through an isolation groove.

[0040] In one embodiment, the silicon wafer is a doped silicon wafer, the doping type of the first microcrystalline silicon layer is opposite to the doping type of the silicon wafer, and the doping type of the second microcrystalline silicon layer and the doped polycrystalline silicon layer is the same as the doping type of the silicon wafer; and / or,

[0041] The silicon wafer is an N-type doped silicon wafer; and / or,

[0042] The first surface is a pyramid structure velvet surface or a polished surface; and / or,

[0043] The first area is a pyramid structure velvet surface or a polished surface; and / or,

[0044] The second area is a pyramid structure velvet surface or a polished surface.

[0045] The utility model has the following beneficial effects:

[0046] The front and back sides of the HTBC battery of the utility model use microcrystalline silicon layers to replace the amorphous silicon layers in the prior art, and the crystallization rate range of the front and back microcrystalline silicon layers is controlled, so as to achieve good passivation and tunneling contact performance, and significantly improve the electrical performance and photoelectric conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 This is a schematic diagram of the structure of a HTBC battery in a specific embodiment of the utility model;

[0049] Figure 2 This is a schematic diagram of the structure of the heterostructure on the first region of the second surface of the HTBC battery in a specific embodiment of the utility model;

[0050] Figure 3 It is a schematic structural diagram of a second passivation structure on the first surface of a HTBC battery in a specific embodiment of the utility model;

[0051] Figures 4a to 4j The figure is a process flow chart for preparing HTBC battery in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0053] In the present utility model, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0054] The utility model discloses a hybrid passivation back contact battery (ie, HTBC battery), comprising:

[0055] The silicon wafer comprises a first surface and a second surface arranged opposite to each other, wherein the second surface comprises a first region and a second region;

[0056] A heterogeneous structure, comprising at least a first passivation layer stacked on the first region and a first microcrystalline silicon layer that is fully or partially doped;

[0057] A first electrode structure is located on the first microcrystalline silicon layer in the heterostructure;

[0058] A first passivation structure includes a tunneling oxide layer and a doped polysilicon layer stacked on the second region;

[0059] a second electrode structure, located on the doped polysilicon layer in the first passivation structure;

[0060] A second passivation structure includes at least a second passivation layer stacked on the first surface and a fully or partially doped second microcrystalline silicon layer, wherein the doping type of the second microcrystalline silicon layer is opposite to the doping type of the first microcrystalline silicon layer;

[0061] The crystallization rate of the second microcrystalline silicon layer is greater than the crystallization rate of the first microcrystalline silicon layer.

[0062] Preferably, the crystallization rate of the first microcrystalline silicon layer is 62% to 69%, and the crystallization rate of the second microcrystalline silicon layer is 70% to 78%.

[0063] The present invention is further described below in conjunction with specific embodiments.

[0064] Ginseng Figure 1 As shown, the HTBC battery in a specific embodiment of the utility model includes:

[0065] A silicon wafer 10, which is a doped silicon wafer, comprises a first surface S1 and a second surface which are arranged opposite to each other, wherein the second surface comprises a first region S21 and a second region S22, and an area of ​​the first region S21 is larger than an area of ​​the second region S22;

[0066] A heterogeneous structure, comprising a first passivation layer 21 stacked at least on the first region S21 and a first microcrystalline silicon layer 22 at least partially doped, wherein the doping type of the first microcrystalline silicon layer 22 is opposite to the doping type of the silicon wafer 10;

[0067] A first electrode structure, located on the first microcrystalline silicon layer 22 in the heterostructure;

[0068] The first passivation structure includes a tunneling oxide layer 31 and a doped polysilicon layer 32 stacked on the second region S22, wherein the doping type of the doped polysilicon layer 32 is the same as the doping type of the silicon wafer 10;

[0069] A second electrode structure is located on the doped polysilicon layer 32 in the first passivation structure, and the first electrode structure is electrically isolated from the second electrode structure by an isolation trench 70;

[0070] The second passivation structure includes a second passivation layer 41 stacked at least on the first surface S1 of the silicon wafer and a second microcrystalline silicon layer 42 that is at least partially doped. The crystallization rate of the second microcrystalline silicon layer 42 is greater than the crystallization rate of the first microcrystalline silicon layer 22, and the doping type of the second microcrystalline silicon layer is opposite to the doping type of the first microcrystalline silicon layer.

[0071] Exemplarily, the silicon wafer 10 in this embodiment is illustrated by taking an N-type silicon wafer (i.e., N-type doping) as an example. The doping type of the first microcrystalline silicon layer 22 is opposite to the doping type of the silicon wafer 10, which is P-type doping (such as boron doping, etc.), and the doping type of the doped polycrystalline silicon layer 32 is the same as the doping type of the silicon wafer 10, which is N-type doping (such as phosphorus doping, etc.).

[0072] In this embodiment, the first region S21 is a back-emitting region (P-Emitter), and the area of ​​the first region S21 is 70% to 95% of the area of ​​the second surface. Preferably, the area of ​​the first region S21 is 80% to 85% of the area of ​​the second surface.

[0073] Furthermore, in the heterostructure of this embodiment, the first passivation layer 21 is an intrinsic hydrogenated amorphous silicon layer with a thickness of 4.5nm-6nm; the first microcrystalline silicon layer 22 is partially P-type doped with a thickness of 25nm-40nm, and the overall crystallization rate is 62%-69%.

[0074] Combination Figure 2 As shown, the first microcrystalline silicon layer 22 in this embodiment includes a first inner microcrystalline silicon layer 221, a first middle microcrystalline silicon layer 222 and a first outer microcrystalline silicon layer 223 sequentially stacked on the first passivation layer, the first inner microcrystalline silicon layer 221 is an intrinsic microcrystalline silicon layer, the first middle microcrystalline silicon layer 222 and the first outer microcrystalline silicon layer 223 are P-type doped microcrystalline silicon layers. Preferably:

[0075] The thickness of the first inner microcrystalline silicon layer 221 is 1 nm to 5 nm;

[0076] The thickness of the first medium microcrystalline silicon layer 222 is 20 nm to 28 nm, and the doping concentration is 1E17 cm -3 ~1E19cm -3 ;

[0077] The thickness of the first outer microcrystalline silicon layer 223 is 4 nm to 7 nm, and the doping concentration is 1E19 cm -3 ~1E20cm -3 .

[0078] In this embodiment, the second region S22 is a back field passivation region (n-BSF). In the first passivation structure, the tunneling oxide layer 31 is a combination of any one or more of a silicon oxide layer (SiOx) and a silicon oxynitride layer (SiNxOy), with a thickness of 1nm to 2nm. The doped polysilicon layer 32 is N-type doped, with a thickness of 120nm to 200nm and a doping concentration of 1E21cm -3 ~1E22cm -3 .

[0079] Preferably, the first passivation layer 21 and the first microcrystalline silicon layer 22 of the present embodiment are stacked on the first passivation structure of the entire first region S21 and part of the second region S22 , and an electrode window not covered by the first passivation layer 21 and the first microcrystalline silicon layer 22 is formed on the doped polysilicon layer 32 .

[0080] In addition, the first electrode structure in the present embodiment includes a first TCO layer 51 and a first electrode 61, the first TCO layer is at least located on the first microcrystalline silicon layer 22 in the first region S21, and the first electrode is in electrical contact with the first TCO layer, and the second electrode structure includes a second TCO layer 52 and a second electrode 62, the second TCO layer 52 is at least located in the electrode window in the second region S22, and the second electrode 62 is in electrical contact with the second TCO layer 52. The first TCO layer 51 and the second TCO layer 52 are electrically isolated by the isolation groove 70.

[0081] Specifically, the TCO (transparent conductive oxide) layer may be one or more of ITO, AZO, IWO, etc. The first electrode 61 and the second electrode 62 are metal grid line electrodes, and the material thereof may be Ag or Ag / Cu alloy.

[0082] The isolation groove 70 in this embodiment is formed on the second region S22. The first TCO layer 51 and the second TCO layer 52 can be isolated by setting the isolation groove to avoid short circuit between the two electrodes. The depth of the isolation groove is greater than or equal to the thickness of the TCO layer, and the width is 20μm to 100μm. In other embodiments, the isolation groove 70 can also be formed on the first region S21, or partially formed on the first region S21 and partially formed on the second region S22. The isolation effect is the same and will not be described here.

[0083] Furthermore, an insulating layer (not shown) is formed in all or part of the isolation groove 70, and the isolation effect can be further improved by the provision of the insulating layer. In this embodiment, the isolation groove 70 extends to the surface of the first microcrystalline silicon layer 22, and an extremely thin (about 1 nm thick) natural oxide layer (i.e., silicon oxide layer) is formed on the bottom wall and sidewall of the isolation groove.

[0084] In this embodiment, the first surface S1 is a front surface field (FSF), and the second passivation structure thereon includes a second passivation layer 41 stacked on the first surface S1 and a partially doped second microcrystalline silicon layer 42 .

[0085] In this embodiment, the second passivation layer 41 is an intrinsic hydrogenated amorphous silicon layer with a thickness of 5 nm to 7 nm.

[0086] Furthermore, in the present embodiment, the second microcrystalline silicon layer 42 is N-type doped, has a thickness of 29 nm to 40 nm, and an overall crystallization rate of 70% to 78%.

[0087] Combination Figure 3 As shown, the second microcrystalline silicon layer 42 in this embodiment includes a seed layer 421 and a second outer microcrystalline silicon layer 422 sequentially stacked on the second passivation layer 41, and the seed layer 421 and the second outer microcrystalline silicon layer 422 are both doped microcrystalline silicon layers containing hydrogen (H), and the hydrogen content in the seed layer 421 is greater than the hydrogen content in the second outer microcrystalline silicon layer. Preferably:

[0088] The thickness of the seed layer 421 is 2 nm to 5 nm;

[0089] The thickness of the second outer microcrystalline silicon layer 422 is 27 nm to 35 nm, and the doping concentration is 1E17 cm -3 ~1E19cm -3 .

[0090] Furthermore, an anti-reflection layer 43 is deposited on the second microcrystalline silicon layer 42 . The anti-reflection layer 43 includes a combination of one or more of a TCO layer, a SiNx layer, a SiNxOy layer, etc., and is preferably a SiNx layer.

[0091] For example, in this embodiment, the first surface S1 and the first area S21 are pyramid-structured velvet surfaces, and the light trapping effect is improved by the pyramid velvet structure, and the second area S22 is a polished surface. In other embodiments, the first surface S1 and the first area S21 may also be polished surfaces, and the second area S22 may also be a pyramid velvet structure, which will not be described one by one here.

[0092] The front and back sides of the HTBC battery of the utility model both adopt passivation structures to reduce the surface recombination rate, and the first area and the second area of ​​the back side respectively adopt the passivation structures of the HJT battery and the TOPCon battery, which have good passivation effects and can improve the photoelectric conversion efficiency.

[0093] Ginseng Figures 4a to 4j As shown, a method for preparing a HTBC battery in a specific embodiment of the utility model comprises the following steps:

[0094] 1. Ginseng Figure 4a As shown, a silicon wafer 10 is provided. The silicon wafer is an N-type silicon wafer, including a first surface S1 and a second surface arranged opposite to each other. The second surface includes a first region S21 and a second region S22, and the area of ​​the first region S21 is larger than that of the second region S22.

[0095] In this embodiment, the first surface S1 of the silicon wafer is the front surface field (FSF), the first area S21 in the second surface is the back emission area (P-Emitter), the second area S22 is the back field passivation area (n-BSF), and the area of ​​the first area S21 is 70% to 95% of the area of ​​the second surface, preferably 80% to 85%.

[0096] Illustratively, in this embodiment, the front and back sides of the silicon wafer are first polished in a tank cleaning machine using a polishing liquid (such as a NaOH solution) to form a smooth surface.

[0097] 2. Ginseng Figure 4b As shown, a tunnel oxide layer 31 and a doped polysilicon layer 32 are sequentially deposited on the second surface by a PECVD (plasma enhanced chemical vapor deposition) process.

[0098] Exemplarily, the tunneling oxide layer 31 is a silicon dioxide layer with a thickness of 1 nm to 2 nm, and the doped polysilicon layer 32 is a phosphorus-doped polysilicon layer with a thickness of 120 nm to 200 nm and a doping concentration of 1E21 cm -3 ~1E22cm -3 .

[0099] Then, the doped polysilicon layer is annealed in an annealing furnace at a temperature of 1050° C. for 1500 seconds. Meanwhile, a first mask 80 can be formed on the surface of the doped polysilicon layer 32 , and the mask is a PSG (phosphorus silicon glass) mask.

[0100] In other embodiments, the first mask 80 may also be a mask deposited separately by a PECVD process, such as any one of a SINx mask, a SiNxOy mask, and a SiOx mask, etc., as a mask for subsequent processes.

[0101] 3. Ginseng Figure 4c As shown, the first mask 80 on the first region S21 is patterned and opened, and the tunnel oxide layer 31 and the doped polysilicon layer 32 on the first region S21 are removed.

[0102] The patterned film opening can be performed by using a laser process to completely remove the tunneling oxide layer 31 and the doped polysilicon layer 32 on the first region S21 .

[0103] 4. Ginseng Figure 4d As shown, the first mask 80 on the second surface of the silicon wafer is removed.

[0104] In this embodiment, in a chain cleaning machine, the back side of the silicon wafer after the laser process is placed in a hydrofluoric acid solution to remove the PSG mask on the back side of the silicon wafer.

[0105] Preferably, in this embodiment, in a texturing cleaning machine, the first area S21 of the second surface of the silicon wafer and the first surface S1 are processed by an alkali (such as NaOH solution) texturing process to form a pyramid texture surface structure with a pyramid size of 0.5 μm to 5 μm.

[0106] 5. Ginseng Figure 4e As shown, a first passivation layer 21 and a first microcrystalline silicon layer 22 are sequentially deposited on the second surface of the silicon wafer by a PECVD (plasma enhanced chemical vapor deposition) process, and a second passivation layer 41 and a second microcrystalline silicon layer 42 are sequentially deposited on the first surface of the silicon wafer.

[0107] The deposition process of the first passivation layer 21 , the first microcrystalline silicon layer 22 , the second passivation layer 41 and the second microcrystalline silicon layer 42 is the key process of the present invention, and the deposition of each layer is described in detail below.

[0108] 5.1. The deposition process of the first passivation layer 21 is specifically as follows:

[0109] Using the PECVD process, silane and hydrogen are introduced, the silane flow rate is 500sccm~700sccm, the hydrogen flow rate is 800sccm~1000sccm, and an amorphous silicon layer is deposited on the first surface of the silicon wafer. The deposition temperature is 200℃~210℃, the deposition time is 50s~65s, the deposition thickness is 5nm~7nm, the pressure in the PECVD chamber is 0.5Torr~0.6Torr, and the deposition power is 300W~500W.

[0110] 5.2. The deposition process of the first microcrystalline silicon layer 22 is specifically as follows:

[0111] The pressure in the PECVD chamber is controlled to be 3 Torr to 5 Torr, and the deposition power is controlled to be 4000W to 7000W.

[0112] 5.21. Deposit a first inner microcrystalline silicon layer on the first passivation layer, wherein the first inner microcrystalline silicon layer is an intrinsic microcrystalline silicon layer.

[0113] Using the PECVD process, silane, hydrogen and carbon dioxide are introduced, the flow ratio of silane to hydrogen is (6-8): (2500-2900), and the first inner microcrystalline silicon layer is deposited on the first passivation layer. The deposition temperature is 158°C-162°C, the deposition time is 18s-22s, and the thickness is 1nm-3nm.

[0114] Exemplarily, the silane flow rate is 60 sccm to 80 sccm, the hydrogen flow rate is 25000 sccm to 29000 sccm, and the carbon dioxide flow rate is 15 sccm to 20 sccm.

[0115] 5.22. Deposit a first middle microcrystalline silicon layer on the first inner microcrystalline silicon layer, wherein the first middle microcrystalline silicon layer is P-type doped.

[0116] A PECVD process is adopted to introduce borane, silane, hydrogen and carbon dioxide, and the flow ratio of borane, silane and hydrogen is (3-3.8): (6-8): (2500-2900), and a boron-doped first middle microcrystalline silicon layer is deposited on the first inner microcrystalline silicon layer. The deposition temperature is 158°C-162°C, the deposition time is 155s-165s, the thickness is 20nm-24nm, and the boron doping concentration is 1E17cm -3 ~1E19cm -3 .

[0117] Exemplarily, the borane flow rate is 30 sccm to 38 sccm, the silane flow rate is 60 sccm to 80 sccm, the hydrogen flow rate is 25000 sccm to 29000 sccm, and the carbon dioxide flow rate is 15 sccm to 20 sccm.

[0118] 5.23. Depositing a first outer microcrystalline silicon layer on the first middle microcrystalline silicon layer, wherein the first middle microcrystalline silicon layer is P-type doped.

[0119] A PECVD process is used to introduce borane, silane, hydrogen and carbon dioxide, with a flow ratio of borane, silane and hydrogen of (6.5-7.5): (6-8): (2500-2900), and a boron-doped first outer microcrystalline silicon layer is deposited on the first middle microcrystalline silicon layer. The deposition temperature is 170°C-175°C, the deposition time is 65s-75s, the thickness is 5nm-7nm, and the boron doping concentration is 1E19cm-3 ~1E20cm -3 .

[0120] Exemplarily, the borane flow rate is 65 sccm to 75 sccm, the silane flow rate is 60 sccm to 80 sccm, the hydrogen flow rate is 25000 sccm to 29000 sccm, and the carbon dioxide flow rate is 15 sccm to 20 sccm.

[0121] Through the above deposition process, the overall crystallization rate of the first microcrystalline silicon layer can be controlled to be 62% to 69%.

[0122] 5.3. The deposition process of the second passivation layer 41 is specifically as follows:

[0123] Using the PECVD process, silane and hydrogen are introduced, the silane flow rate is 500sccm~700sccm, the hydrogen flow rate is 800sccm~1000sccm, and an amorphous silicon layer is deposited on the second surface of the silicon wafer. The deposition temperature is 190℃~205℃, the deposition time is 80s~100s, the deposition thickness is 4.5nm~6nm, the pressure in the PECVD chamber is 0.5Torr~0.6Torr, and the deposition power is 150W~300W.

[0124] 5.4. The deposition process of the second microcrystalline silicon layer 42 is specifically as follows:

[0125] The pressure in the PECVD chamber is controlled to be 3 Torr to 5 Torr, and the deposition power is controlled to be 3000 W to 5000 W.

[0126] 5.41. Deposit a seed layer on the second passivation layer.

[0127] Using the PECVD process, phosphine, silane, hydrogen and carbon dioxide are introduced, the flow rate of silane to hydrogen is 1: (700-900), and a seed layer is deposited on the second passivation layer. The deposition temperature is 190°C-205°C, the deposition time is 10s-25s, and the thickness is 2nnm-5nm.

[0128] Illustratively, the phosphine flow rate is 1 sccm to 5 sccm, the silane flow rate is 25 sccm to 35 sccm, the hydrogen flow rate is 22000 sccm to 28000 sccm, and the carbon dioxide flow rate is 10 sccm to 20 sccm.

[0129] 5.42. Deposit a second outer microcrystalline silicon layer on the seed layer, wherein the second outer microcrystalline silicon layer is a doped microcrystalline silicon layer.

[0130] Using the PECVD process, phosphine, silane, hydrogen and carbon dioxide are introduced, the flow rate of silane to hydrogen is 1: (350-380), and the second outer microcrystalline silicon layer is deposited on the seed layer. The deposition temperature is 190°C-205°C, the deposition time is 260s-300s, and the thickness is 27nm-35nm.

[0131] Illustratively, the phosphine flow rate is 150 sccm to 200 sccm, the silane flow rate is 40 sccm to 50 sccm, the hydrogen flow rate is 15000 sccm to 17000 sccm, and the carbon dioxide flow rate is 50 sccm to 60 sccm.

[0132] Through the above deposition process, the overall crystallization rate of the second microcrystalline silicon layer can be controlled to be 70% to 78%.

[0133] It should be understood that the utility model does not limit the deposition order of the first passivation layer 21 and the first microcrystalline silicon layer 22 and the deposition order of the second passivation layer 41 and the second microcrystalline silicon layer 42. The first passivation layer 21 and the first microcrystalline silicon layer 22 on the back side can be deposited first, and then the second passivation layer 41 and the second microcrystalline silicon layer 42 on the front side can be deposited. Alternatively, the second passivation layer 41 and the second microcrystalline silicon layer 42 on the front side can be deposited first, and then the first passivation layer 21 and the first microcrystalline silicon layer 22 on the back side can be deposited. Alternatively, the first passivation layer 21 and the second passivation layer 41 on the front and back sides can be deposited at the same time, and then the first microcrystalline silicon layer 22 on the back side and the second microcrystalline silicon layer 42 on the front side can be deposited separately.

[0134] 6. Ginseng Figure 4f As shown, the anti-reflection layer 43 is continuously deposited at low temperature on the first surface S1 of the silicon wafer by using a tubular PECVD or PVD device.

[0135] Exemplarily, the anti-reflection layer 43 in this embodiment is a SiNx layer, and may also be a TCO layer in other embodiments.

[0136] 7. Ginseng Figure 4g As shown, a portion of the first passivation layer 21 and the first microcrystalline silicon layer 22 on the second region S22 is removed to form an electrode window 23 .

[0137] The patterned film opening can be performed by laser technology, at least to the surface of the doped polysilicon layer 32, to ensure that the doped polysilicon layer 32 below the electrode window 23 is exposed.

[0138] 8. Ginseng Figure 4h As shown, in a PVD (physical vapor deposition) device, a TCO layer 50 is formed in the first microcrystalline silicon layer 22 and the electrode window 23 .

[0139] 9. Ginseng Figure 4iAs shown, part of the TCO layer on the first area S21 and / or the second area S22 is removed, and an electrically isolated first TCO layer 51 and a second TCO layer 52 are formed in the first microcrystalline silicon layer and the electrode window. The first TCO layer 51 and the second TCO layer 52 are electrically isolated by an isolation groove 70 formed by a laser process.

[0140] 10. Ginseng Figure 4j As shown, a first electrode 61 electrically contacting the first TCO layer is prepared on the first TCO layer 51 , and a second electrode 62 electrically contacting the second TCO layer is prepared on the second TCO layer 52 .

[0141] Preferably, the metal electrode (the first electrode 61 or the second electrode 62) is prepared by screen printing using a conductive paste, wherein the conductive paste is a low-temperature silver paste or a silver-copper paste, and the curing temperature is 190°C to 220°C.

[0142] In addition, the anti-reflection layer in this embodiment includes a combination of one or more of a TCO layer, a SiNx layer, and a SiNxOy layer. If the anti-reflection layer is a TCO layer, the preparation of the layer can be carried out in the same process as the preparation of the back TCO layer; if the anti-reflection layer is a SiNx layer or a SiNxOy layer, an additional process is required, but the anti-reflection effect of the SiNx layer or the SiNxOy layer is better than that of the TCO layer.

[0143] In the prior art, the contact of the amorphous silicon layer will produce parasitic absorption and series resistance loss. The microcrystalline silicon layer can replace the doped amorphous silicon layer in the prior art. Although a sufficiently thin high crystalline layer can reduce parasitic absorption, a high crystallinity does not necessarily mean better conductivity. On the contrary, it will also lead to a higher contact resistivity with the transparent conductive oxide layer (TCO), resulting in a loss of photoelectric conversion efficiency. The prior art only emphasizes crystallinity and ignores the impact of contact resistivity.

[0144] The utility model replaces the doped amorphous silicon layer on the front and back sides of the battery with a microcrystalline silicon layer through process improvements and in combination with the characteristics of the HTBC battery, and controls the crystallization rate of the front and back sides through the process to improve the photoelectric performance of the battery.

[0145] In a pair of proportions and multiple embodiments, the pressure in the PECVD chamber is controlled to be 5 Torr, the deposition power is 5000 W, and borane (B2H6), silane (SiH4), hydrogen (H2) and carbon dioxide (CO2) are introduced to prepare a microcrystalline silicon layer with an inner, middle and outer three-layer structure. The silane flow rate is 70 sccm, the hydrogen flow rate is 27000 sccm, and the CO2 flow rate is 18 sccm.

[0146] Among them, the deposition temperature of the comparative example is 175°C, the deposition temperature of the inner and middle microcrystalline silicon layers in each embodiment is 160°C, the deposition temperature of the outer microcrystalline silicon layer is 173°C, and the inner microcrystalline silicon layer is not doped with borane, the deposition time is 18s~22s, the middle microcrystalline silicon layer is introduced with low borane flow rate of 30sccm~38sccm, the deposition time is 155s~165s, the outer microcrystalline silicon layer is doped with high borane flow rate of 65sccm~75sccm, and the deposition time is 45s~52s.

[0147] The crystallization rate and electrical properties corresponding to different borane flow rates and deposition thicknesses are shown in the following table:

[0148]

[0149] It can be seen that the crystallization rate of the inner microcrystalline silicon layer can be improved by lowering the deposition temperature of the inner microcrystalline silicon layer and not doping with borane. The high borane doping of the outer microcrystalline silicon layer can improve the contact performance with TCO. The crystallization rate of the overall microcrystalline silicon layer is controlled to be 62% to 69%, which can significantly improve the photoelectric conversion efficiency of the battery (0.7% to 0.19%). At the same time, the dark conductivity of the film is also significantly improved.

[0150] In another comparative example and multiple embodiments, the pressure in the PECVD chamber is controlled to be 4 Torr, the deposition power is 5000 W, and phosphine (PH3), silane (SiH4), hydrogen (H2) and carbon dioxide (CO2) are introduced to prepare the second microcrystalline silicon layer. In the comparative example, the seed layer is not deposited, and each embodiment first deposits the seed layer. In the deposition process of the seed layer, the flow rates of phosphine, silane and hydrogen are 3 sccm, 30 sccm and 25000 sccm respectively.

[0151] In the process of depositing the second outer microcrystalline silicon layer, the flow rate of silane and hydrogen is 1: (350-380), the flow rate of phosphine is 350 sccm, the deposition temperature is 200° C., the deposition time is 280 s, and the deposition thickness is 30 nm.

[0152] The crystallization rate and electrical properties corresponding to different flow ratios of phosphine, silane and hydrogen are shown in the following table:

[0153]

[0154] In other embodiments, the flow rate of silane and hydrogen in the seed layer deposition process can be controlled to be 1:(700~900), and the flow rate of silane and hydrogen in the second outer microcrystalline silicon layer deposition process can be controlled to be 1:(350~380). Through the growth of the seed layer and the high hydrogen dilution ratio of the outer layer, the overall crystallization rate of the second microcrystalline silicon layer is controlled to be 70%~78%, which can significantly improve the photoelectric conversion efficiency of the battery (0.7%~0.14%). At the same time, the increase in the crystallinity of the thin film can reduce the parasitic absorption on the front side, and the current can also be significantly improved.

[0155] It can be seen from the above technical solutions that the utility model has the following beneficial effects:

[0156] The front and back sides of the HTBC battery of the utility model use microcrystalline silicon layers to replace the amorphous silicon layers in the prior art, and the crystallization rate range of the front and back microcrystalline silicon layers is controlled, so as to achieve good passivation and tunneling contact performance, and significantly improve the electrical performance and photoelectric conversion efficiency of the battery.

[0157] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

[0158] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A hybrid passivated back contact cell, characterized in that: The battery comprises: The silicon wafer comprises a first surface and a second surface arranged opposite to each other, wherein the second surface comprises a first region and a second region, and an area of ​​the first region is larger than an area of ​​the second region; A heterogeneous structure, comprising at least a first passivation layer stacked on the first region and a first microcrystalline silicon layer that is fully or partially doped; A first electrode structure is located on the first microcrystalline silicon layer in the heterostructure; A first passivation structure includes a tunneling oxide layer and a doped polysilicon layer stacked on the second region; a second electrode structure, located on the doped polysilicon layer in the first passivation structure; The second passivation structure includes at least a second passivation layer stacked on the first surface and a fully or partially doped second microcrystalline silicon layer, the crystallization rate of the second microcrystalline silicon layer is greater than the crystallization rate of the first microcrystalline silicon layer, and the doping type of the second microcrystalline silicon layer is opposite to the doping type of the first microcrystalline silicon layer.

2. The hybrid passivated back contact cell according to claim 1, characterized in that: The crystallization rate of the first microcrystalline silicon layer is 62% to 69%; and / or, The crystallization rate of the second microcrystalline silicon layer is 70% to 78%.

3. The hybrid passivated back contact cell according to claim 1, characterized in that: The first microcrystalline silicon layer includes a first inner microcrystalline silicon layer, a first middle microcrystalline silicon layer and a first outer microcrystalline silicon layer sequentially stacked on the first passivation layer, the first inner microcrystalline silicon layer is an intrinsic microcrystalline silicon layer, and the first middle microcrystalline silicon layer and the first outer microcrystalline silicon layer are doped microcrystalline silicon layers.

4. The hybrid passivated back contact cell according to claim 3, characterized in that: The thickness of the first microcrystalline silicon layer is 25 nm to 40 nm; and / or, The thickness of the first inner microcrystalline silicon layer is 1 nm to 5 nm; and / or, The thickness of the first microcrystalline silicon layer is 20 nm to 28 nm; and / or, The thickness of the first outer microcrystalline silicon layer is 4 nm to 7 nm.

5. The hybrid passivated back contact cell according to claim 1, characterized in that: The second microcrystalline silicon layer includes a seed layer and a second outer microcrystalline silicon layer sequentially stacked on the second passivation layer.

6. The hybrid passivated back contact cell according to claim 5, characterized in that: The thickness of the second microcrystalline silicon layer is 29 nm to 40 nm; and / or, The thickness of the seed layer is 2nm to 5nm; and / or, The thickness of the second outer microcrystalline silicon layer is 27 nm to 35 nm.

7. The hybrid passivated back contact cell according to claim 1, characterized in that: The first passivation layer and / or the second passivation layer comprises an intrinsic hydrogenated amorphous silicon layer; and / or, The thickness of the first passivation layer is 4.5 nm to 6 nm; and / or, The thickness of the second passivation layer is 5 nm to 7 nm; and / or, The tunneling oxide layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or, The thickness of the tunnel oxide layer is 1 nm to 2 nm; and / or, The thickness of the doped polysilicon layer is 120nm to 200nm; and / or, An anti-reflection layer is further stacked on the second microcrystalline silicon layer, and the anti-reflection layer includes a combination of one or more of a SiNx layer, a SiNxOy layer, and a TCO layer.

8. The hybrid passivated back contact cell according to claim 1, characterized in that: The first passivation layer and the first microcrystalline silicon layer are stacked on the first passivation structure of the entire first region and a portion of the second region, and an electrode window not covered by the first passivation layer and the first microcrystalline silicon layer is formed on the doped polysilicon layer.

9. The hybrid passivated back contact cell according to claim 8, characterized in that: The first electrode structure includes a first TCO layer and a first electrode, the first TCO layer is at least located on the first microcrystalline silicon layer in the first region, and the first electrode is in electrical contact with the first TCO layer; The second electrode structure comprises a second TCO layer and a second electrode, wherein the second TCO layer is at least located in the electrode window on the second region, and the second electrode is in electrical contact with the second TCO layer; The first TCO layer and the second TCO layer are electrically isolated from each other through an isolation groove.

10. The hybrid passivated back contact cell according to claim 1, characterized in that: The silicon wafer is a doped silicon wafer, the doping type of the first microcrystalline silicon layer is opposite to the doping type of the silicon wafer, and the doping types of the second microcrystalline silicon layer and the doped polycrystalline silicon layer are the same as the doping type of the silicon wafer; and / or, The silicon wafer is an N-type doped silicon wafer; and / or, The first surface is a pyramid structure velvet surface or a polished surface; and / or, The first area is a pyramid structure velvet surface or a polished surface; and / or, The second area is a pyramid structure velvet surface or a polished surface.

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