Semiconductor circuit for arithmetic processing and arithmetic processing method
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[First Embodiment]
A first embodiment is an application of the present invention to a semiconductor circuit for arithmetic processing for adding data. In the first embodiment, a binary SD (signed digit) number system is used as a redundant base n number system. The binary SD number system is one redundant number system, and permits numbers of redundant value called “−1”, that were not available originally, for binary numbers comprised of combinations of “0's” and “1's”. An example of an arithmetic rule using this binary SD number system is shown in table 1. In the following description, for example, when data “010” is represented in the binary SD number system this data is shown as “010”SD, while when data “010” is being represented in the binary system the data is shown as “010”B. Also, data “2” being represented in the decimal system is shown as “2”D. TABLE 1A−101B−1−1 · 0−1 · 10 · 0 0 ·−10−1 · 1 0 · 00 · 1 0 ·−11 ·−11 0 · 0 0 · 11 · 0 1 ·−1
In table 1, the two characters ...
Example
[Second Embodiment]
In the second embodiment, the adder 1 and the adder 2 of the first embodiment are implemented as described in the following. Specifically, because of this two digit binary, comprising combinations of “0” and “1”, is used. According to two digit binary there are four combinations of “0” and “1”. In the second embodiment, “0” in the binary SD number system is expressed two ways in binary. Accordingly, “1”, “0” and “−1” in the binary SD number system is expressed as follows in binary. “−1” in binary SD . . . [11]B “0” in binary SD . . . [00]B, [10]B “1” in binary SD . . . [01]B.
Using binary SD “1”, “0” and “−1” expressed in this way means the adder 1 becomes as follows. For example, in the case of data a1 of “0” and data a2 of “−1”, data a1 being a value of [00]B and data a2 being a value of [11]B are input to the adder 1.
Inside the adder 1, if binary SD representation is used, the additional result is “−1”. In this case, In accordance with table 2, the value o...
Example
[Third Embodiment]
In the third embodiment, the adder 1 and the adder 2 of the first embodiment have the following structure.
Specifically, the adder shown in FIG. 4 is used as the adder 1. The adder 101 in FIG. 4 is comprised of neuron MOS inverters 101A-101C made using neuron MOS (Metal Oxide Silicon) transistors and inverters 101D-101F.
The neuron MOS inverters 101A-101C are sequentially connected.
The output of the neuron MOS inverter 101A is connected to the of the neuron MOS inverter 101C and to the inverter 101F, the output of the neuron MOS inverter 101B is connected to the of the neuron MOS inverter 101C and to the inverter 101E, and the output of the neuron MOS inverter 101C is connected to the inverter 101D.
Data a4 and data a5 comprising 2 bits correspond to the data a1 and data a2 in FIG. 1. A digit of a number in the redundant number system is represented by data a4 and data a5. Data a4 and data a5 can not be implements using an electrical signal being transmitted...
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