Multi-phase clock division

Abstract

Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.

Description

BACKGROUNDField of the Present Disclosure[0001]Embodiments of the present disclosure relate generally to the field of semiconductor devices. More specifically, embodiments of the present disclosure relate to using a multi-phase clock when the starting phase is unknown.Description of Related Art[0002]Semiconductor devices (e.g., memory devices) often utilize clocks to perform functions. As frequency speeds increase, it may be helpful to divide a fast clock into multiple phases for internal use of a portion (e.g., dynamic random-access memory (DRAM). However, by dividing the clock into multiple phases, it may be unknown which starting phase first receives a first incoming clock for the clock. Variable write preamble lengths may also cause incorrect bit counting in a phase of the multiple phases when write preamble lengths change from a default length.[0003]Embodiments of the present disclosure may be directed to one or more of the problems set forth above.BRIEF DESCRIPTION OF DRAWINGS...

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