A delay phase-locked loop circuit with start-up control function

A start-up control, voltage-controlled delay technology, applied in the direction of automatic power control, electrical components, etc., can solve the problems of complex second-order low-pass filter, etc., to achieve the effect of increasing the chip area and speeding up the locking speed

CN104601166BActive Publication Date: 2017-08-25PEKING UNIV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Publication Date
2017-08-25

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Abstract

The invention discloses a delay phase-locked loop circuit with a start-up control function, comprising a phase detection sub-circuit, a voltage-controlled delay chain, a first-order filter capacitor and a start-up control sub-circuit; the start-up control sub-circuit initializes a control voltage, The control voltage falls within the adjustment range of the delay control voltage of the voltage-controlled delay chain; the phase detection sub-circuit unit adjusts the control voltage according to the phase relationship between the reference clock and the feedback clock of the voltage-controlled delay chain. The value of the voltage; the adjusted control voltage is filtered by the first-order filter capacitor and used as the delay control voltage of the voltage-controlled delay chain to control the voltage-controlled delay chain. The circuit of the present invention sets a suitable control voltage at the beginning of the circuit operation, so that the time delay of the voltage-controlled delay chain to the reference clock is half of its adjustment range, fully utilizes the delay range provided by the voltage-controlled delay chain, and speeds up The locking speed of the whole system is improved, and at the same time, the present invention does not significantly increase the chip area.
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Description

technical field

[0001] The invention relates to the technical field of a delay phase-locked loop, and more specifically relates to a delay phase-locked loop circuit with a start-up control function. Background technique

[0002] As the demand for chip performance continues to increase, on-chip clock distribution quality and clock delay become more and more important, and the requirements for suppressing clock skew and jitter are getting higher and higher. However, increases in clock frequency and circuit integration make it more difficult to reduce clock skew and jitter, whether the jitter is internal or from substrate or power supply noise. Traditional clock trees cannot maintain precise synchronization of on-chip high-speed clocks. In microprocessors, memory interfaces, and communication chips, a phase-locked loop (Phase Locked Loop, PLL) and a delay phase-locked loop (DLL) are generally used to implement clock synchronization.

[0003] Among them, PLL is a high-level sy...

Examples

Embodiment Construction

[0024] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but should not be used to limit the scope of the present invention.

[0025] figure 1 It is a schematic structural diagram of a delay phase-locked loop circuit with a start-up control function of a preferred embodiment of the present invention; the delay phase-locked loop circuit with a start-up control function includes a phase detection sub-circuit, a voltage-controlled delay A time chain, a first-order filter capacitor, and a start-up control subcircuit; the start-up control subcircuit initializes a control voltage, and the control voltage falls within the adjustment range of the delay control voltage of the voltage-controlled delay chain; the phase The detection sub-circuit unit adjusts the value of the control voltage according to the phase of the reference clock and the ...