Heterogeneous multi-core programmable system and memory configuration thereof as well as programming method of computing unit

Abstract

The invention relates to a heterogeneous multi-core programmable system implemented in a single FPGA (Field Programmable Gate Array) chip and a memory configuration method of the heterogeneous multi-core programmable system as well as a programming method of a computing unit. The heterogeneous multi-core programmable system comprises a host, multiple computing units, and an external DDR (Data Direction Register) memory which serves a system memory configuration shared by the multiple computing units, wherein a storage space is distributed in each computing unit; and each storage space is used for storing data and an instruction which correspond to each computing unit. The memory configuration method comprises the following steps: the host distributes the corresponding storage spaces to all the computing units in the external DDR memory according to computing tasks configured by all the computing units, and further divides each storage space into two symmetric regions. According to the heterogeneous multi-core programmable system and the memory configuration method, the data and instruction memories of the computing units are all distributed to the external DDR memory, so that the phenomenon of insufficient storage capacity for the instructions and the data due to lack of storage resources in the chip can be avoided; and meanwhile, the memory distribution has the advantages of flexibility, high efficiency and reliability.

Description

technical field

[0001] The present invention relates to the field of heterogeneous multi-core programmable systems, and mainly relates to a design method, memory allocation, programming model design and implementation of a heterogeneous multi-core programmable system in a single Field Programmable Gate Array (FPGA, Field-Programmable Gate Array) chip. Open Computing Language (OpenCL, Open Computing Language) support, more specifically, relates to a heterogeneous multi-core programmable system implemented in a single FPGA chip and its memory configuration method and computing unit programming method. Background technique

[0002] The heterogeneous multi-core programmable system integrates multiple core processors with different structures, functions, power consumption, and computing performance on a single chip. Through task analysis and core scheduling, different tasks are assigned to the corresponding cores, so that each Each core is used to the best of its ability. This or...

Examples

Embodiment Construction

[0052] The present invention conceives a heterogeneous multi-core programmable system implemented in a single FPGA chip, which uses two CPUs with different architectures to implement a host and multiple computing units. The host is responsible for task allocation and result processing, and multiple computing units are responsible for parallel processing tasks. The task of the computing unit is configurable online, and the task of single instruction multiple data or multiple instruction multiple data can be realized.

[0053] In the present invention, a dynamically configurable local data and instruction memory is realized by using the internal data and instruction buffer of the computing unit + the external DDR memory. This not only provides enough data and instruction storage space for each computing unit, but also does not slow down the speed of accessing storage.

[0054] On the basis of the programming and compiling model independently proposed by the present invention, t...

technical field

[0001] The present invention relates to the field of heterogeneous multi-core programmable systems, and mainly relates to a design method, memory allocation, programming model design and implementation of a heterogeneous multi-core programmable system in a single Field Programmable Gate Array (FPGA, Field-Programmable Gate Array) chip. Open Computing Language (OpenCL, Open Computing Language) support, more specifically, relates to a heterogeneous multi-core programmable system implemented in a single FPGA chip and its memory configuration method and computing unit programming method. Background technique

[0002] The heterogeneous multi-core programmable system integrates multiple core processors with different structures, functions, power consumption, and computing performance on a single chip. Through task analysis and core scheduling, different tasks are assigned to the corresponding cores, so that each Each core is used to the best of its ability. This or...

Examples

Embodiment Construction

[0052] The present invention conceives a heterogeneous multi-core programmable system implemented in a single FPGA chip, which uses two CPUs with different architectures to implement a host and multiple computing units. The host is responsible for task allocation and result processing, and multiple computing units are responsible for parallel processing tasks. The task of the computing unit is configurable online, and the task of single instruction multiple data or multiple instruction multiple data can be realized.

[0053] In the present invention, a dynamically configurable local data and instruction memory is realized by using the internal data and instruction buffer of the computing unit + the external DDR memory. This not only provides enough data and instruction storage space for each computing unit, but also does not slow down the speed of accessing storage.

[0054] On the basis of the programming and compiling model independently proposed by the present invention, t...

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