Resistor element and method for manufacturing the same

Abstract

Provided are a resistor element and a manufacturing method thereof that can reduce the chip size and the number of bonding wires. The resistor element comprises: a semiconductor substrate; a first insulating film disposed on the semiconductor substrate; a resistor layer disposed on the first insulating film; a second insulating film disposed to cover the first insulating film and the resistor layer; a first electrode disposed on the second insulating film and electrically connected to the resistor layer; a relay wiring disposed on the second insulating film and separated from the first electrode, having a resistor layer connection terminal electrically connected to the resistor layer and a substrate connection terminal ohmically connected to the semiconductor substrate; and a second electrode disposed under the semiconductor substrate, wherein a resistor body is provided between the first electrode and the second electrode.

Description

Technical Field

[0001] The present invention relates to a resistor element and a method for manufacturing the same. Background Art

[0002] As a resistor element for semiconductor devices such as semiconductor integrated circuits (ICs), a resistor element is known in which an insulating layer is provided on a silicon substrate and a thin film resistor layer is provided on the insulating layer (see Patent Document 1). In the resistor element described in Patent Document 1, two electrodes are connected to the opposing sides of the resistor layer, and aluminum thin wires are bonded to the two electrodes.

[0003] In the resistor element described in Patent Document 1, two electrodes connected to the opposing sides of the resistor layer are located on the upper surface side of the resistor layer. Therefore, the chip size becomes large, and two bonding wires connected to the two electrodes are required.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 8-306861 Summary of the invention

[0005] Problem that the invention aims to solve

[0006] In view of the above problems, an object of the present invention is to provide a resistor element and a method for manufacturing the resistor element that can reduce the chip size and the number of bonding wires.

[0007] Solutions for solving problems

[0008] The main purpose of one embodiment of the present invention is a resistor element comprising: (a) a semiconductor substrate; (b) a first insulating film, which is arranged on the semiconductor substrate; (c) a resistor layer, which is arranged on the first insulating film; (d) a second insulating film, which is arranged to cover the first insulating film and the resistor layer; (e) a first electrode, which is arranged on the second insulating film and is electrically connected to the resistor layer; (f) a relay wiring, which is arranged on the second insulating film and separated from the first electrode, and has a resistor layer connection terminal electrically connected to the resistor layer and a substrate connection terminal ohmically connected to the semiconductor substrate; and (g) a second electrode, which is arranged under the semiconductor substrate, wherein a resistor body is between the first electrode and the second electrode.

[0009] The main purpose of other embodiments of the present invention is a method for manufacturing a resistor element, comprising the following steps: (a) forming a first insulating film on a semiconductor substrate; (b) forming a resistor layer on the first insulating film; (c) forming a second insulating film in a manner covering the first insulating film and the resistor layer; (d) opening a first contact hole on the second insulating film for exposing the resistor layer, a second contact hole for exposing the resistor layer at a position separated from the first contact hole, and a third contact hole for exposing a portion of the upper surface of the semiconductor substrate at a position separated from the first contact hole and the second contact hole; (e) forming a first electrode electrically connected to the resistor layer by means of the first contact hole; (f) forming a relay wiring electrically connected to the resistor layer by means of the second contact hole and ohmically connected to the semiconductor substrate by means of the third contact hole; and (g) forming a second electrode under the semiconductor substrate, wherein a resistor body is set between the first electrode and the second electrode.

[0010] Effects of the Invention

[0011] According to the present invention, it is possible to provide a resistor element and a method for manufacturing the resistor element that can reduce the chip size and the number of bonding wires. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a cross-sectional view showing an example of a resistor element according to an embodiment of the present invention.

[0013] Figure 2 It is a graph showing the relationship between the temperature coefficient of doped polysilicon and the dose.

[0014] Figure 3 It is a plan view showing an example of a resistor element according to an embodiment of the present invention.

[0015] Figure 4 It is a cross-sectional view to which an equivalent circuit is added of a resistor element according to an embodiment of the present invention.

[0016] Figure 5 (a) and Figure 5 (b) is an equivalent circuit of the resistor element according to the embodiment of the present invention.

[0017] Figure 6 It is a plan view showing an example of the contact arrangement of the resistor element according to the embodiment of the present invention.

[0018] Figure 7 It is a plan view showing another example of the contact arrangement of the resistor element according to the embodiment of the present invention.

[0019] Figure 8It is a plan view showing another example of the contact arrangement of the resistor element according to the embodiment of the present invention.

[0020] Fig. 9 It is a circuit diagram showing an application example of the resistance element according to the embodiment of the present invention.

[0021] Fig.10 The diagram is a cross-sectional view of a process for explaining an example of a method for manufacturing a resistor element according to an embodiment of the present invention.

[0022] Fig.11 This is a further description of an example of a method for manufacturing a resistor element according to an embodiment of the present invention. Fig.10 A cross-sectional view of the subsequent process.

[0023] Fig.12 This is a further description of an example of a method for manufacturing a resistor element according to an embodiment of the present invention. Fig.11 A cross-sectional view of the subsequent process.

[0024] Fig.13 This is a further description of an example of a method for manufacturing a resistor element according to an embodiment of the present invention. Fig.12 A cross-sectional view of the subsequent process.

[0025] Fig.14 This is a further description of an example of a method for manufacturing a resistor element according to an embodiment of the present invention. Fig.13 A cross-sectional view of the subsequent process.

[0026] Fig.15 This is a further description of an example of a method for manufacturing a resistor element according to an embodiment of the present invention. Fig.14 A cross-sectional view of the subsequent process.

[0027] Fig.16 This is a further description of an example of a method for manufacturing a resistor element according to an embodiment of the present invention. Fig.15 A cross-sectional view of the subsequent process.

[0028] Fig.17 This is a further description of an example of a method for manufacturing a resistor element according to an embodiment of the present invention. Fig.16 A cross-sectional view of the subsequent process.

[0029] Fig.18 This is a further description of an example of a method for manufacturing a resistor element according to an embodiment of the present invention. Fig.17 A cross-sectional view of the subsequent process.

[0030] Fig.19 This is a further description of an example of a method for manufacturing a resistor element according to an embodiment of the present invention. Fig.18A cross-sectional view of the subsequent process.

[0031] Fig. 20 This is a cross-sectional view showing an example of a resistor element according to a first modified example of the embodiment of the present invention.

[0032] Fig.21 It is a cross-sectional view showing an example of a resistor element according to a second modified example of the embodiment of the present invention.

[0033] Description of Reference Numerals

[0034] 1: semiconductor substrate; 2, 2a, 2b, 2c: first insulating film; 3: doped polysilicon layer; 3a, 3b: resistor layer; 3c, 3d, 3e: auxiliary film; 4: second insulating film; 5: metal film; 5a, 5b, 5e: first electrode; 5c, 5f, 5g: relay wiring; 5d: guard ring layer; 6a, 6b, 6c, 6d, 6e, 6f, 6g, 6h, 6i: contact area; 7: protective film; 7a, 7b: opening; 9 : second electrode; 31: first end; 32: second end; 4a, 4b, 4c, 4d, 4e, 4f, 4g: contact hole; 61, 61a, 61b, 61c, 61d: first outer contact; 62a, 62b, 62c, 62d: first inner contact; 63a, 63b, 63c, 63d: second inner contact; 64, 64a, 64b, 64c, 64d: second outer contact; 101, 102: terminals. DETAILED DESCRIPTION

[0035] Hereinafter, the embodiments of the present invention will be described with reference to the accompanying drawings. In the description of the accompanying drawings, the same or similar parts are marked with the same or similar marks, and repeated descriptions are omitted. However, the accompanying drawings are schematic, and there are situations where the relationship between the thickness and the plane size, the ratio of the thickness of each layer, etc. are different from the actual situation. In addition, the drawings may also contain parts with different size relationships and ratios. In addition, the embodiments shown below are used to illustrate the devices and methods used to concretize the technical ideas of the present invention. The materials, shapes, structures, configurations, etc. of the structural components in the technical ideas of the present invention are not specifically the materials, shapes, structures, configurations described below. In addition, the definitions of directions such as up and down in the following description are only for the convenience of explanation and do not limit the technical ideas of the present invention. For example, if the object is rotated 90° for observation, the up and down are converted to left and right, and if the object is rotated 180° for observation, the up and down are reversed, which is self-evident.

[0036] like Figure 1As shown, the resistor element according to the embodiment of the present invention includes a semiconductor substrate 1 with a low resistivity, first insulating films 2a and 2b disposed on the semiconductor substrate 1, and thin film resistor layers 3a and 3b disposed on the first insulating films 2a and 2b. The resistor element is used as a gate resistor of an insulated gate bipolar transistor (IGBT), for example.

[0037] The thickness of the semiconductor substrate 1 is, for example, about 350 μm. As the semiconductor substrate 1, a low-resistivity substrate such as a silicon substrate to which n-type impurities are added at a high concentration can be used. Preferably, the resistance component of the semiconductor substrate 1 is small to a level that can be ignored compared with the resistance component of the resistance layers 3a and 3b. That is, preferably, the resistance component of the semiconductor substrate 1 is less than 1 / 100 of the resistance component of the resistance layers 3a and 3b. The resistivity of the semiconductor substrate 1 can also be, for example, about 2 mΩ·cm to 60 mΩ·cm. In addition, as the semiconductor substrate 1, a silicon substrate to which p-type impurities are added at a high concentration or a semiconductor substrate other than silicon can also be used.

[0038] As the first insulating films 2a and 2b, a silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film), or a composite film thereof can be used. As the first insulating films 2a and 2b, an insulating film (TEOS film) generated by a chemical vapor growth (CVD) method using tetraethoxysilane (TEOS) gas of an organic silicon compound can also be used. The thickness of the first insulating films 2a and 2b is, for example, about 800 nm. The parasitic capacitance can be reduced by making the first insulating films 2a and 2b thicker.

[0039] The thickness of the resistor layers 3a and 3b is, for example, about 500 nm, and the surface resistance of the resistor layers 3a and 3b is, for example, about 150 Ω / □. Figure 1 depth direction) and length ( Figure 1 The resistance value of the resistor layers 3a and 3b is controlled by adjusting the resistance of the resistor layers 3a and 3b. For example, n-type doped polysilicon can be used as the resistor layers 3a and 3b. n-type doped polysilicon can be formed by ion implanting n-type impurities such as phosphorus (P) into polysilicon and adding polysilicon to the deposition using a CVD device.

[0040] Preferably, the temperature coefficient of the resistor layers 3a and 3b is less than 0 ppm / °C (in other words, the temperature coefficient of the resistor layers 3a and 3b is 0, or the resistor layers 3a and 3b have a negative temperature coefficient). Thus, the increase in the resistance value during high temperature operation can be suppressed. For example, when the resistor element involved in the embodiment of the present invention is applied to the gate resistor of the IGBT, the loss when the IGBT is turned on can be suppressed. The temperature coefficient of doped polysilicon can be controlled by adjusting the dose when ion implantation of impurities into polysilicon, etc. Figure 2 The relationship between the temperature coefficient and the dose of n-type doped polysilicon formed by phosphorus (P) ion implantation is shown in Figure 2. For example, if the dose is set to 7.0×10 15 cm -2 If the temperature coefficient of doped polysilicon is less than 0 ppm / °C, the temperature coefficient of doped polysilicon can be reduced to less than 0 ppm / °C. In addition, the temperature coefficient of the resistor layers 3a and 3b is not necessarily limited to less than 0 ppm / °C, and the resistor layers 3a and 3b may have a positive temperature coefficient.

[0041] In addition, the resistance layers 3a and 3b may also be p-type doped polysilicon. It is also possible to form p-type doped polysilicon by ion implantation of p-type impurities such as boron (B) into polysilicon. The resistance layers 3a and 3b are not limited to doped polysilicon, but may also be films of transition metal nitrides such as tantalum nitride (TaNx), or laminated films of high melting point metal films laminated in the order of chromium (Cr)-nickel (Ni)-manganese (Mn). For the resistance layers 3a and 3b, thin films of silver palladium (AgPd), ruthenium oxide (RuO2), etc. may also be used. In addition, although Figure 1 Although the structure shown is different, the resistance layers 3 a and 3 b can also be realized by using a p-type diffusion layer or an n-type diffusion layer formed on the surface of the semiconductor.

[0042] The second insulating film (interlayer insulating film) 4 is configured to cover the first insulating films 2a, 2b and the resistance layers 3a, 3b. The thickness of the second insulating film 4 is, for example, about 1500nm. As the second insulating film 4, a silicon oxide film (SiO2 film) not containing phosphorus (P) and boron (B), a silicon oxide film (PSG film) added with phosphorus, a silicon oxide film (BSG film) added with boron, a silicon oxide film (BPSG film) added with phosphorus and boron, or a silicon nitride film (Si3N4 film) can be used as the so-called "NSG film", or a composite film obtained by combining multiple of them. For example, the second insulating film 4 can be composed of a composite film formed by stacking a NSG film of about 770nm and a PSG film of about 650nm. The NSG film has the function of suppressing resistance deviation. In addition, the PSG film has the function of ensuring the strength of wire bonding.

[0043] A pair of first electrodes (surface electrodes) 5a, 5b and a relay wiring 5c ​​are arranged on the second insulating film 4. The first electrode 5a on one side is located above the first insulating film 2a, and the horizontal position of the end of the first electrode 5a on one side overlaps with one end of the resistor layer 3a in the depth direction. The first electrode 5b on the other side is located above the first insulating film 2b, and the horizontal position of the end of the first electrode 5b on the other side overlaps with one end of the resistor layer 3b in the depth direction. The relay wiring 5c ​​is arranged from above the first insulating film 2a to above the first insulating film 2b in a manner sandwiched between the pair of first electrodes 5a, 5b.

[0044] The first electrode 5a on one side is connected to one end of the resistor layer 3a via the contact area 6a. The other end of the resistor layer 3a is connected to the resistor layer connection terminal as one end (first end) of the relay wiring 5c ​​via the contact area 6b. The first electrode 5b on the other side is connected to one end of the resistor layer 3b via the contact area 6c. The other end of the resistor layer 3b is connected to the resistor layer connection terminal as the other end (second end) of the relay wiring 5c ​​via the contact area 6d. The substrate connection terminal as the other end (third end) of the relay wiring 5c ​​is ohmically connected to the semiconductor substrate 1 with low contact resistance via the contact area 6e. The second electrode 9 is provided on the back side of the semiconductor substrate 1. That is, the resistor layers 3a and 3b are connected in series with the semiconductor substrate 1 via the relay wiring 5c, realizing a longitudinal resistor element in which the resistor body is set between the first electrode 5a on one side and the second electrode 9.

[0045] The thickness of a pair of first electrodes 5a, 5b and relay wiring 5c ​​is, for example, about 3 μm. For example, a pair of first electrodes 5a, 5b and relay wiring 5c ​​can be formed by a stacked film of titanium / titanium nitride (Ti / TiN) of about 120 nm as a barrier metal, aluminum-silicon (Al-Si) of about 3 μm, and TiN / Ti of about 45 nm as an anti-reflection film. Al-Si can also be replaced by Al alloys such as Al, Al-Cu-Si, and Al-Cu. A pair of first electrodes 5a, 5b respectively constitute electrode pads. A bonding wire (not shown) with a diameter of about 300 μm formed of a metal such as aluminum (Al) is connected to the pair of first electrodes 5a, 5b.

[0046] Furthermore, a guard ring layer 5d is disposed on the second insulating film 4. The guard ring layer 5d is disposed in a ring shape on the outer peripheral portion of the chip constituting the resistor element involved in the embodiment of the present invention. The guard ring layer 5d is connected to the semiconductor substrate 1 via the contact areas 6f and 6g. The guard ring layer 5d is formed of the same material as the pair of first electrodes 5a and 5b and the relay wiring 5c. The guard ring layer 5d has a function of preventing moisture from intruding from the side of the chip.

[0047] A protective film (passivation film) 7 is disposed on the pair of first electrodes 5a, 5b, the relay wiring 5c, and the guard ring layer 5d. The protective film 7 can be composed of, for example, a composite film in which a TEOS film, a Si3N4 film, and a polyimide film are stacked in sequence. Openings 7a, 7b are provided on the protective film 7. The portions of the pair of first electrodes 5a, 5b exposed from the openings 7a, 7b become pad regions to which bonding wires can be connected.

[0048] exist Figure 3 FIG. 2 is a top view of a resistor element according to an embodiment of the present invention. Figure 3 The cross-sectional view obtained by observing the AA direction is Figure 1 Corresponding. The resistor element according to the embodiment of the present invention has, for example, a rectangular planar pattern whose long side is in the direction in which the pair of first electrodes 5a, 5b and the relay wiring 5c ​​are arranged. The chip size of the resistor element according to the embodiment of the present invention is, for example, about 2.8 mm×2.5 mm. Figure 3 As shown, the first electrode 5a disposed on the left side is a rectangular planar pattern with a length of L1 and a width of W1, and the first electrode 5b disposed on the right side is also similar. The first electrode 5a on one side and the first electrode 5b on the other side are disposed with a spacing of S1 and parallel to each other. For example, the length L1 of a pair of first electrodes 5a and 5b is about 2.0 mm, the width W1 is about 0.9 mm, and the spacing S1 is about 0.5 mm or more. Figure 3 As shown, the resistance layers 3a, 3b and the relay wiring 5c ​​also have, for example, Figure 3 A rectangular plane pattern with the up-down direction as the long side direction.

[0049] The rectangular plane pattern of the relay wiring 5c ​​is set on the straight line L2 passing through the center C1 of the chip. Moreover, the resistance layers 3a, 3b, a pair of first electrodes 5a, 5b and the relay wiring 5c ​​are set in the plane pattern to be line symmetrical with respect to the straight line L2 passing through the center C1 of the chip. That is, the plane pattern of the resistance layers 3a, 3b, a pair of first electrodes 5a, 5b and the relay wiring 5c ​​is 180° rotationally symmetrical with respect to the center C1 of the chip. As a result, when installing the resistance element involved in the embodiment of the present invention, it can also be rotated 180° for use, and the assembly operation becomes easy.

[0050] like Figure 1As shown, a second electrode (back electrode) 9 is arranged on the lower surface of the semiconductor substrate 1. For example, the second electrode 9 can be formed by a single-layer film formed of gold (Au) or a metal film formed by stacking titanium (Ti), nickel (Ni), and gold (Au) in this order. The outermost layer of the second electrode 9 can be formed of a weldable material. The second electrode 9 is fixed to a metal plate (not shown) or the like by welding or the like.

[0051] Figure 4 Yes Figure 1 The figure shows a cross-sectional structure of the resistor element according to the embodiment of the present invention on the left side and an equivalent circuit thereof. The first electrode 5a on one side is connected to the terminal 101, and the second electrode 9 is connected to the terminal 102. A parasitic capacitor C is formed under the first electrode 5a on one side with the first insulating film 2a and the second insulating film 4 as dielectrics. pad A parasitic capacitor C is formed under the resistance layer 3a with the first insulating film 2a as a dielectric. poly The parasitic capacitance C between the end of the first electrode 5a and the end of the relay wiring 5c ​​(resistance layer connection terminal) using the protective film 7 as a dielectric layer is pmm Small, so can be ignored.

[0052] exist Figure 5 (a) indicates Figure 4 The equivalent circuit shown is as follows. The parasitic capacitance C under the resistance layer 3a with the first insulating film 2a as the dielectric poly The resistance R of the resistance layer 3a poly Connect in parallel. pad and parasitic capacitance C poly Taken together Figure 5 As shown in (b) of para When the parasitic capacitance C para The impedance ratio of the chip resistor R poly When low, the parasitic capacitance C para The current I C Therefore, it is necessary to calculate the parasitic capacitance C para , to confirm the required cutoff frequency. The conditions for suppressing oscillation are as follows: the current I flowing through the chip PAD Roughly equal to the current flowing through the chip resistor R poly The current component I R The formula of the low-pass filter is as follows:

[0053] f c =1 / (2πC para R poly )……(1)

[0054] Here, f cis the oscillation frequency. Formula (1) can be transformed into Formula (2).

[0055] C para =1 / (2πf c R poly )……(2)

[0056] By substituting the oscillation frequency f into equation (2) c , the parasitic capacitance C can be calculated para By setting the calculated parasitic capacitance C para The following can ensure that the current flowing through the chip resistor R poly The current component I R The parasitic capacitance C can be controlled by adjusting the thickness of the first insulating film 2a and the second insulating film 4. para .

[0057] Next, refer to Figure 6 to Figure 8 To illustrate and Figure 1 The contact configuration corresponding to the contact area 6a, 6b for connecting the resistor layer 3a to the first electrode 5a and the relay wiring 5c ​​is shown. Figure 6 to Figure 8 In the description, the focus is on the resistor layer 3a, but the same structure can also be adopted for the contact configuration of the contact areas 6c and 6d for connecting the other first electrode 5b and relay wiring 5c ​​to the resistor layer 3b.

[0058] exist Figure 6 to Figure 8 In the description, the measured Figure 3 The length L1 of the planar pattern of the first electrode 5a defined in the embodiment is defined as the "resistor width direction", and the direction in which the width W1 is measured is defined as the "resistor length direction". Figure 7 The main direction of the current component flowing in the resistor layer 3a is shown by the dashed arrow in FIG. Figure 3 The interval S1 shown is also measured along the resistor length direction. That is, the "resistor length direction" refers to the main direction of current flow that determines the resistance value of the resistor layer 3a from a macroscopic point of view. Figure 6 The current component indicated by the dotted arrow also has an angular deviation, but when decomposed into vector components, the current component flowing along the length direction of the resistor is larger in total.

[0059] like Figure 6As shown, first outer contacts 61a to 61d and first inner contacts 62a to 62d are arranged on the side of one end (first end) 31 of the resistor layer 3a, respectively. A plurality of first inner contacts 62a to 62d are arranged periodically in the resistor width direction. A plurality of first outer contacts 61a to 61d are arranged periodically in the resistor width direction in parallel with the first inner contacts 62a to 62d. The arrangement positions of the first inner contacts 62a to 62d and the arrangement positions of the first outer contacts 61a to 61d are staggered in a lattice (checkered pattern) so as not to overlap each other when compared in the resistor width direction.

[0060] The second outer contacts 64a to 64d and the second inner contacts 63a to 63d are arranged on the other end (second end) 32 of the resistor layer 3a facing the first end 31 along the resistor length direction. The second inner contacts 63a to 63d are arranged periodically in the resistor width direction. The second outer contacts 64a to 64d are arranged periodically in the resistor width direction in parallel with the second inner contacts 63a to 63d. The arrangement positions of the second inner contacts 63a to 63d and the arrangement positions of the second outer contacts 64a to 64d are staggered in a lattice (checkered pattern) so as not to overlap each other when compared in the resistor width direction.

[0061] The arrangement positions of the first inner contacts 62a to 62d and the arrangement positions of the second inner contacts 63a to 63d are staggered so as not to overlap each other in the comparison in the resistor width direction. When viewed along the resistor length direction, the arrangement positions of the first inner contacts 62a to 62d are opposite to the arrangement positions of the second outer contacts 64a to 64d via the gaps of the second inner contacts 63a to 63d. The arrangement positions of the second inner contacts 63a to 63d are opposite to the arrangement positions of the first outer contacts 61a to 61d via the gaps of the first inner contacts 62a to 62d.

[0062] exist Figure 6 In the example, the gap between the second inner contacts 63a to 63d and the length in the resistor width direction of the second outer contacts 64a to 64d are the same, but they may be different from each other. For example, Figure 6 The gap between the second inner contacts 63a to 63d is narrow, and the arrangement positions of the first inner contacts 62a to 62d and the arrangement positions of the second outer contacts 64a to 64d are respectively opposed to each other. Figure 6The second inner contacts 63a to 63d are shown to have wide gaps, and there is a region in the resistor length direction where neither the second inner contacts 63a to 63d nor the second outer contacts 64a to 64d exist.

[0063] Similarly, the example shows the case where the gap between the first inner contacts 62a to 62d and the length of the first outer contacts 61a to 61d in the resistor width direction are the same, but they may be different from each other. For example, Figure 6 The gap between the first inner contacts 62a to 62d is narrow, and the arrangement positions of the second inner contacts 63a to 63d are respectively opposed to a part of the arrangement positions of the first outer contacts 61a to 61d. Figure 6 The first inner contacts 62a to 62d are shown with wide gaps, and there is a region in the resistor length direction where neither the first inner contacts 62a to 62d nor the first outer contacts 61a to 61d exist.

[0064] Preferably, the distance D1 in the direction of the resistance length between the first inner contacts 62a to 62d and the second outer contacts 64a to 64d is equal to the distance D2 in the direction of the resistance length between the second inner contacts 63a to 63d and the first outer contacts 61a to 61d. In addition, the distance D1 and the distance D2 may not necessarily be equal. For example, the distance D1 may be greater than the distance D2, or the distance D1 may be less than the distance D2. In addition, in each pair of the first inner contacts 62a to 62d and the second outer contacts 64a to 64d, the distance D1 may be the same as or different from each other. In addition, in each pair of the second inner contacts 63a to 63d and the first outer contacts 61a to 61d, the distance D2 may be the same as or different from each other.

[0065] Alternatively, it can be, Figure 7 As shown in the contact configuration, when viewed along the resistor length direction, the first inner contacts 62a to 62d and the first outer contacts 61a to 61d on the first end 31 side are arranged so that their positions in the resistor width direction overlap each other. Alternatively, when comparing their positions along the resistor length direction, the second inner contacts 63a to 63d and the second outer contacts 64a to 64d may be arranged so that their positions in the resistor width direction overlap each other. When compared in the resistor length direction, the first inner contacts 62a to 62d and the second inner contacts 63a to 63d are arranged so that their positions in the resistor width direction overlap each other.

[0066] exist Figure 7In the contact configuration shown, the arrangement positions of the first inner contacts 62a to 62d in the resistance width direction and the arrangement positions of the second inner contacts 63a to 63d in the resistance width direction are spaced apart and face each other in the resistance length direction. However, the arrangement positions of the second outer contacts 64a to 64d in the resistance width direction are concealed outside the arrangement positions of the second inner contacts 63a to 63d in the resistance width direction. In addition, the arrangement positions of the first outer contacts 61a to 61d in the resistance width direction are concealed outside the arrangement positions of the first inner contacts 62a to 62d in the resistance width direction. In this case, as Figure 7 As indicated by the dotted arrows in FIG. 1 , the current component flowing through the resistor layer 3a is non-uniform, and current concentration is likely to occur near the first inner contacts 62a to 62d and the second inner contacts 63a to 63d where the intervals in the resistor length direction are smallest.

[0067] In contrast, according to Figure 6 The contact configuration shown can increase the effective contact area. Figure 6 By making the current component of each contact point uniform as shown by the dotted arrow in the figure, it is possible to prevent the current concentration at the contact point. Therefore, it is possible to realize a resistor with less variation in resistance value and strong surge resistance.

[0068] In addition, if Figure 8 As shown, the first outer contact 61 and the second outer contact 64 may also be a linear pattern (line pattern) extending in the resistor width direction. Figure 6 The contact configuration shown is the same. When viewed in the resistor length direction, the arrangement position of each of the first inner contacts 62a to 62d in the resistor width direction faces a portion of the second outer contact 64 via the gap between the second inner contacts 63a to 63d. When viewed in the resistor length direction, the arrangement position of each of the second inner contacts 63a to 63d in the resistor width direction faces a portion of the first outer contact 61 via the gap between the first inner contacts 62a to 62d.

[0069] according to Figure 8 The contact configuration shown, with Figure 6 The contact configuration shown can also increase the effective contact area, make the current component of each contact uniform, and prevent the current concentration at the contact. Therefore, it is possible to realize a resistor with less variation in resistance value and strong surge resistance.

[0070] like Fig. 9As shown, the resistor element involved in the embodiment of the present invention can be applied to an inverter module 100 that drives a three-phase motor composed of, for example, a u-phase, a v-phase, and a w-phase. The inverter module 100 includes: power semiconductor devices TR1, TR2, TR3, and TR4 that drive the u-phase; power semiconductor devices TR5, TR6, TR7, and TR8 that drive the v-phase; and power semiconductor devices TR9, TR10, TR11, and TR12 that drive the w-phase. The power semiconductor devices TR1 to TR12 are respectively connected to freewheeling diodes (not shown). The power semiconductor devices TR1 to TR12 can all use IGBTs, and in order to suppress the oscillation phenomenon during switching, gate resistors R1 to R12 are connected to the gate electrodes of each IGBT.

[0071] The resistor elements according to the embodiment of the present invention can be used as a pair of gate resistors R1 and R2, a pair of gate resistors R3 and R4, a pair of gate resistors R5 and R6, a pair of gate resistors R7 and R8, a pair of gate resistors R9 and R10, and a pair of gate resistors R11 and R12. For example, Figure 1 The resistor layers 3a and 3b shown correspond to the gate resistors R1 and R2. The gate resistors R1 and R2 are connected to the gate electrodes of the power semiconductor devices TR1 and TR2 on one side thereof. Figure 1 The terminals on the side of the pair of first electrodes 5a and 5b shown correspond to each other. In addition, the gate resistors R1 and R2 are connected to the gate electrodes of the power semiconductor devices TR1 and TR2 on the opposite sides thereof. Figure 1 The terminals on the second electrode 9 side are shown to correspond.

[0072] According to the resistor element involved in the embodiment of the present invention, the resistor layer connection terminal as one end of the relay wiring 5c ​​is connected to the resistor layers 3a and 3b, and the substrate connection terminal as the other end of the relay wiring 5c ​​is ohmically connected to the semiconductor substrate 1 with low resistivity with low contact resistance, thereby forming a resistor element with a vertical structure. Therefore, there is one pad area for each resistor layer 3a and 3b, which is respectively composed of a pair of first electrodes 5a and 5b on the upper surface side connected to the resistor layers 3a and 3b. Therefore, the number of bonding wires for each resistor layer 3a and 3b is 1, and the number of bonding wires can be reduced compared with the horizontal resistor element. In addition, compared with the horizontal resistor element, the occupied area of ​​the pad area on the upper surface side can be reduced, so the chip size can be reduced.

[0073] Next, refer to Figure 10 to Figure 19The method for manufacturing a resistor element described below is an example, and it is obvious that the method for manufacturing a resistor element described below is an example, and can be realized by various other manufacturing methods including its modified examples as long as it is within the scope of the subject matter described in the claims.

[0074] First, a semiconductor substrate 1 such as a silicon substrate to which n-type impurities are added at a high concentration is prepared. Fig.10 As shown, a first insulating film 2 such as a TEOS film is deposited on a semiconductor substrate 1 by a low pressure (LP) CVD method or the like. In addition, the first insulating film 2 can also be formed by the following composite film: after a thermal oxide film is formed by a thermal oxidation method, an insulating film is deposited on the thermal oxide film by a CVD method or the like, and the thermal oxide film and the deposited insulating film are stacked to obtain the composite film. Next, a photoresist film is coated on the first insulating film 2, and the photoresist film is patterned using photolithography technology. The patterned photoresist film is used as an etching mask, and a portion of the first insulating film 2 is selectively removed by dry etching such as reactive ion etching (RIE). Thereafter, the photoresist film is removed. As a result, as shown in FIG. Fig.11 As shown, first insulating films 2a and 2b are formed on a portion of a semiconductor substrate 1.

[0075] Next, a non-doped polysilicon layer is formed on the semiconductor substrate 1 and the first insulating films 2a and 2b by CVD or the like. Then, ions of n-type impurities such as phosphorus (P) are implanted into the polysilicon layer. For example, an acceleration voltage of 80 keV and a dose of 6.0×10 15 cm -2 Phosphorus (P) ions are implanted to the following extent. Then, the implanted ions are activated by heat treatment, so that Fig.12 As shown in FIG. 1 , a doped polysilicon layer 3 to which n-type impurities are added at a high concentration is formed. Next, a photoresist film is applied on the doped polysilicon layer 3, and the photoresist film is patterned using a photolithography technique. The patterned photoresist film is used as an etching mask to selectively remove a portion of the doped polysilicon layer 3 by RIE or the like. Thereafter, the photoresist film is removed. As a result, as shown in FIG. Fig.13 As shown, resistance layers 3a and 3b are formed on the first insulating films 2a and 2b, respectively.

[0076] Then, if Fig.14As shown, the second insulating film 4 is deposited in a manner covering the first insulating films 2a, 2b and the resistance layers 3a, 3b. For example, the NSG film and the PSG film can be deposited in sequence by a CVD method or the like to form the second insulating film 4 from a composite film formed by stacking the NSG film and the PSG film. Next, a photoresist film is applied on the second insulating film 4, and the photoresist film is patterned using a photolithography technique. The patterned photoresist film is used as an etching mask to selectively remove a portion of the second insulating film 4 by RIE or the like. Thereafter, the photoresist film is removed. As a result, as shown in FIG. Fig.15 As shown, a first contact hole 4a on one side, a second contact hole 4b on one side, a first contact hole 4c on the other side, a second contact hole 4d on the other side, and a third contact hole 4e are formed on the second insulating film 4. At the same time, a fourth contact hole 4f on one side and a fourth contact hole 4g ​​on the other side are also formed on the second insulating film 4.

[0077] Then, if Fig.16 As shown, a metal film 5 is deposited on the second insulating film 4 by vacuum evaporation or sputtering to fill the contact holes 4a to 4g. For example, the metal film 5 can be formed by sequentially depositing Ti / TiN, Al-Si, and TiN / Ti by CVD. Next, a photoresist film is applied on the metal film 5, and the photoresist film is patterned by photolithography. The patterned photoresist film is used as an etching mask to selectively remove a portion of the metal film 5. As a result, as shown in FIG. Fig.17 As shown, a pair of first electrodes 5 a and 5 b , a relay wiring 5 c , and a guard ring layer 5 d are formed on the second insulating film 4 .

[0078] At this time, a contact region 6a is formed to connect the first electrode 5a of one side to the resistor layer 3a by means of the first contact hole 4a of one side, and a contact region 6b is formed to connect the relay wiring 5c ​​to the resistor layer 3a by means of the second contact hole 4b of one side. In addition, a contact region 6e is formed to connect the relay wiring 5c ​​to the semiconductor substrate 1 by means of the third contact hole 4e. Furthermore, a contact region 6c is formed to connect the first electrode 5b of the other side to the resistor layer 3b by means of the first contact hole 4c of the other side, and a contact region 6d is formed to connect the relay wiring 5c ​​to the resistor layer 3b by means of the second contact hole 4d of the other side. Furthermore, contact regions 6f and 6g are formed to connect the guard ring layer 5d to the semiconductor substrate 1 by means of the fourth contact hole 4f of one side and the fourth contact hole 4g ​​of the other side.

[0079] Then, if Fig.18As shown in FIG. 1 , a protective film 7 is formed on a pair of first electrodes 5a, 5b, a relay wiring 5c, and a guard ring layer 5d. For example, a TEOS film and a Si3N4 film are sequentially deposited by a plasma CVD method, and a polyimide film is applied, thereby forming a protective film 7 formed of a TEOS film, a Si3N4 film, and a polyimide film. Next, a photoresist film is applied on the protective film 7, and the photoresist film is patterned using a photolithography technique. The patterned photoresist film is used as an etching mask to selectively remove a portion of the protective film 7. As a result, as shown in FIG. Fig.19 As shown, openings 7a and 7b are formed in the protective film 7, and the pair of first electrodes 5a and 5b exposed in the openings 7a and 7b serve as pad regions.

[0080] Next, the lower surface of the semiconductor substrate 1 is polished by chemical mechanical polishing (CMP) or the like to reduce the thickness of the semiconductor substrate 1 to about 350 μm. Then, the second electrode 9 is formed on the lower surface of the semiconductor substrate 1 by vacuum evaporation or sputtering. Figure 1 The resistor elements shown are formed into a large number of chip regions in a matrix shape, and then cut into pieces to separate the chip regions into Figure 1 A chip of a resistor element is shown.

[0081] According to the method for manufacturing a resistor element according to the embodiment of the present invention, it is possible to reduce the chip size and easily realize a resistor element in which the number of bonding wires can be reduced.

[0082] (First Modification)

[0083] like Fig. 20 As shown, the resistor element according to the first modified example of the embodiment of the present invention is Figure 1 The resistor element according to the embodiment of the present invention shown is different in that auxiliary films 3c and 3d in a floating state in potential are arranged on first insulating films 2a and 2b separately from resistor layers 3a and 3b.

[0084] The auxiliary film 3c is disposed below the first electrode 5a on one side and is separated from the resistor layer 3a. The auxiliary film 3d is disposed below the first electrode 5b on the other side and is separated from the resistor layer 3b. The auxiliary films 3c and 3d are formed of the same material as the resistor layers 3a and 3b, such as n-type doped polysilicon, and have the same thickness as the resistor layers 3a and 3b. The auxiliary films 3c and 3d have, for example, a rectangular planar pattern. Other structures of the resistor element according to the first variant of the embodiment of the present invention are the same as those of the resistor element 3a and 3b. Figure 1 The resistor elements involved in the illustrated embodiments of the present invention are the same, and therefore duplicate descriptions are omitted.

[0085] According to the resistor element involved in the first modified example of the embodiment of the present invention, the auxiliary films 3c and 3d in a floating state in potential are arranged on the first insulating films 2a and 2b, thereby reducing the parasitic capacitance under the pair of first electrodes 5a and 5b in the same manner as when the thickness of the first insulating films 2a and 2b is increased. As a result, the reduction in total resistance corresponding to the reduction in impedance during high-frequency operation can be suppressed, and the oscillation phenomenon can be suppressed.

[0086] The manufacturing method of the resistor element according to the first modified example of the embodiment of the present invention is as follows: Fig.13 In the process shown, the auxiliary films 3c and 3d are formed while the resistor layers 3a and 3b are formed by selectively removing the doped polysilicon layer 3. The other processes of the method for manufacturing a resistor element according to the first variant of the embodiment of the present invention are the same as those of the method for manufacturing a resistor element according to the embodiment of the present invention, and therefore repeated descriptions are omitted.

[0087] (Second Modification)

[0088] In the resistor element according to the embodiment of the present invention, the following structure is exemplified: Figure 1 As shown, a plurality of first insulating films 2a, 2b, resistance layers 3a, 3b and first electrodes 5a, 5b are provided, and a relay wiring 5c ​​is electrically connected to the other ends of the plurality of resistance layers 3a, 3b. Fig.21 As shown, the resistance element involved in the second variant of the embodiment of the present invention is different from the resistance element involved in the embodiment of the present invention in that a plurality of resistance layers 3a, 3b and relay wirings 5f, 5g are provided, and a first electrode 5e is electrically connected to one end of the plurality of resistance layers 3a, 3b, respectively.

[0089] An auxiliary film 3e that is in a floating state in terms of potential is provided on the first insulating film 2c in a manner sandwiched between the resistor layers 3a and 3b, separated from the resistor layers 3a and 3b. The auxiliary film 3e is formed of the same material as the resistor layers 3a and 3b, such as n-type doped polysilicon, and has the same thickness as the resistor layers 3a and 3b. The auxiliary film 3e has, for example, a rectangular planar pattern. A first electrode 5e is disposed at the center of the chip on the second insulating film 4. In addition, a pair of relay wirings 5f and 5g are disposed on the second insulating film 4 in a manner sandwiching the first electrode 5e. One end of the first electrode 5e overlaps with one end of the resistor layer 3a in the depth direction, and the other end of the first electrode 5e overlaps with one end of the resistor layer 3b in the depth direction. One end of the relay wiring 5f on one side overlaps with the other end of the resistor layer 3a in the depth direction. One end of the relay wiring 5g on the other side overlaps with the other end of the resistor layer 3b in the depth direction.

[0090] The first electrode 5e is connected to one end of the resistor layer 3a via the contact region 6b. The other end of the resistor layer 3a is connected to the resistor layer connection terminal at one end of the relay wiring 5f as one side via the contact region 6a. The substrate connection terminal at the other end of the relay wiring 5f as one side is ohmically connected to the semiconductor substrate 1 via the contact region 6h. The first electrode 5e is also connected to one end of the resistor layer 3b via the contact region 6d. The other end of the resistor layer 3b is connected to the resistor layer connection terminal at one end of the relay wiring 5g as the other side via the contact region 6c. The substrate connection terminal at the other end of the relay wiring 5g as the other side is ohmically connected to the semiconductor substrate 1 via the contact region 6i.

[0091] That is, the resistor layers 3a and 3b are connected in series to the semiconductor substrate 1 via a pair of relay wirings 5f and 5g, thereby realizing a vertical resistor element in which the resistor body is provided between the first electrode 5e and the second electrode 9. Figure 1 The resistor elements involved in the illustrated embodiments of the present invention are the same, and therefore duplicate descriptions are omitted.

[0092] According to the second variant of the embodiment of the present invention, the resistor element is connected in series with the semiconductor substrate 1 by means of a pair of relay wirings 5f and 5g, and a resistor body is set between the first electrode 5e and the second electrode 9. Therefore, there is one pad area formed by the first electrode 5e on the upper surface side connected to the resistor layers 3a and 3b. Therefore, the number of bonding wires is one, and the number of bonding wires can be reduced compared to the horizontal resistor element. In addition, compared to the horizontal resistor element, the occupied area of ​​the pad area on the upper surface side can be reduced, so the chip size can be reduced.

[0093] Furthermore, by disposing the auxiliary film 3e in a floating potential on the first insulating film 2c, the parasitic capacitance can be reduced in the same manner as when the thickness of the first insulating film 2c is increased. This can suppress the reduction in total resistance corresponding to the impedance reduction during high-frequency operation, and can suppress oscillation.

[0094] Regarding a method for manufacturing a resistor element according to a second modification example of an embodiment of the present invention, Fig.13In the process shown, the auxiliary film 3e is formed while the resistance layers 3a and 3b are formed by selectively removing the doped polysilicon layer 3. In addition, in the resistor element involved in the second variant of the embodiment of the present invention, the configuration positions and numbers of the first insulating film 2c, the resistance layers 3a and 3b, the first electrode 5e, the pair of relay wirings 5f and 5g, etc. are different from those of the resistor element involved in the embodiment of the present invention. However, it can be manufactured by the same method as the manufacturing method of the resistor element involved in the second variant of the embodiment of the present invention, so repeated description is omitted.

[0095] (Other Embodiments)

[0096] As described above, the present invention is described by the embodiments, but it should not be understood that the description and drawings constituting part of the present disclosure are used to limit the present invention. Based on the present disclosure, various alternative embodiments, examples, and application techniques should be clear to those skilled in the art.

[0097] For example, as a resistor element according to an embodiment of the present invention, Figure 1 , a structure in which two resistor layers 3a and 3b are provided on one chip is illustrated, but only one resistor layer may be provided on one chip. Figure 1 The structure of the right side of the resistor element shown includes the first insulating film 2b, the resistor layer 3b, and the first electrode 5b on the other side. Fig. 20 The structure of the right side of the resistor element shown includes the first insulating film 2b, the resistor layer 3b, the other first electrode 5b, and the auxiliary film 3d. Fig.21 The structure shown on the right side of the resistor element includes a resistor layer 3b and another relay wiring 5g. In addition, three or more resistor layers may be provided on one chip.

[0098] In addition, the resistor element according to the embodiment of the present invention is exemplified as follows. Fig. 9 Although the resistors are used as gate resistors R1 to R12 as shown, the application is not limited to gate resistors R1 to R12. The resistor element according to the embodiment of the present invention can be used as a resistor element of various ICs.

Claims

1. A resistor element, characterized in that: have: Semiconductor substrate; A first insulating film, which is disposed on the semiconductor substrate; a resistance layer disposed on the first insulating film; a second insulating film arranged to cover the first insulating film and the resistance layer; a first electrode, which is disposed on the second insulating film and is electrically connected to the resistance layer; a relay wiring, which is provided on the second insulating film and is separated from the first electrode, and has a resistance layer connection terminal electrically connected to the resistance layer and a substrate connection terminal ohmically connected to the semiconductor substrate; as well as A second electrode is disposed under the semiconductor substrate, Wherein, a resistor is provided between the first electrode and the second electrode. A protective film is disposed on the first electrode and the relay wiring, an opening is provided in the protective film, and a portion of the first electrode exposed from the opening serves as a pad region to which a bonding wire can be connected.

2. A resistor element, characterized in that: have: Semiconductor substrate; A first insulating film, which is disposed on the semiconductor substrate; a resistance layer disposed on the first insulating film; a second insulating film arranged to cover the first insulating film and the resistance layer; a first electrode, which is disposed on the second insulating film and is electrically connected to the resistance layer; a relay wiring, which is provided on the second insulating film and is separated from the first electrode, and has a resistance layer connection terminal electrically connected to the resistance layer and a substrate connection terminal ohmically connected to a position away from the end of the semiconductor substrate; as well as A second electrode is disposed under the semiconductor substrate, Wherein, a resistor is provided between the first electrode and the second electrode. The resistance component of the semiconductor substrate is 1 / 100 or less of the resistance component of the resistance layer.

3. The resistor element according to claim 1 or 2, characterized in that: The device further includes an auxiliary film in a floating potential state, the auxiliary film being provided below the first electrode on the first insulating film and separated from the resistance layer, and the auxiliary film being formed of the same material as the resistance layer.

4. The resistor element according to claim 1 or 2, characterized in that: The first insulating film, the resistance layer and the first electrode are each provided with a plurality of The relay wiring is provided so as to be sandwiched between the plurality of the first electrodes, and has a plurality of the resistance layer connection terminals corresponding to the plurality of the resistance layers.

5. The resistor element according to claim 4, characterized in that The rectangular planar pattern of the relay wiring is arranged on a straight line passing through the center of the chip, The rectangular planar patterns of the plurality of the resistance layers and the plurality of the first electrodes are arranged to be line-symmetrical with respect to the straight line.

6. The resistor element according to claim 1 or 2, characterized in that: The resistance layer and the relay wiring are both provided in plurality, The first electrode is provided so as to be sandwiched between the plurality of relay wirings and is electrically connected to each of the plurality of resistance layers.

7. The resistor element according to claim 1 or 2, characterized in that: The resistance layer is connected to the first electrode via a first contact hole formed in the second insulating film. The resistance layer and the second electrode are connected via a second contact hole formed in the second insulating film at a position separated from the first contact hole.

8. The resistor element according to claim 7, characterized in that The planar pattern of the resistor layer is formed by a rectangular shape defining a resistor length direction and a resistor width direction orthogonal to the resistor length direction.

9. The resistor element according to claim 8, characterized in that The planar pattern of the resistor layer has a length in the resistor width direction longer than a length in the resistor length direction.

10. The resistor element according to claim 8 or 9, characterized in that: The first contact hole comprises: A first outer contact is disposed at one end side of the resistor layer defined along the length direction of the resistor; and a first inner contact disposed at a position closer to the center in the resistor length direction than the first outer contact; The second contact hole comprises: A second outer contact is arranged at the other end side of the resistor layer defined along the length direction of the resistor; and a second inner contact disposed at a position closer to the center in the resistor length direction than the second outer contact; In the comparison in the length direction of the resistor, The configuration position of the first inner contact is offset from the configuration position of the second inner contact. The first inner contact faces at least a portion of the second outer contact, The second inner contact faces at least a portion of the first outer contact.

11. The resistor element according to claim 10, characterized in that The distance between the first inner contact and the second outer contact is equal to the distance between the second inner contact and the first outer contact.

12. The resistor element according to claim 10, characterized in that The first inner contact, the second inner contact, the first outer contact, and the second outer contact are arranged in plurality in the resistor width direction. In the comparison in the length direction of the resistor, The arrangement position of the first inner contact in the resistor width direction is staggered from the arrangement position of the second inner contact in the resistor width direction. The arrangement position of the first inner contact in the resistor width direction faces the arrangement position of the second outer contact in the resistor width direction. The arrangement position of the second inner contact in the resistor width direction faces the arrangement position of the first outer contact in the resistor width direction.

13. The resistor element according to claim 10, characterized in that The first inner contact and the second inner contact are arranged in a plurality in the resistor width direction. In the comparison in the length direction of the resistor, The arrangement position of the first inner contact in the resistor width direction is staggered from the arrangement position of the second inner contact in the resistor width direction. The arrangement position of the first inner contact in the resistor width direction faces a portion of the second outer contact in a line pattern extending in the resistor width direction. The arrangement position of the second inner contact in the resistor width direction faces a portion of the first outer contact in a line pattern extending in the resistor width direction.

14. A method for manufacturing a resistor element, characterized in that: Including the following processes: forming a first insulating film on a semiconductor substrate; forming a resistance layer on the first insulating film; forming a second insulating film so as to cover the first insulating film and the resistance layer; On the second insulating film, a first contact hole for exposing the resistance layer, a second contact hole for exposing the resistance layer at a position separated from the first contact hole, and a third contact hole for exposing a portion of the upper surface of the semiconductor substrate at a position separated from the first contact hole and the second contact hole are formed; forming a first electrode electrically connected to the resistance layer via the first contact hole; forming a relay wiring electrically connected to the resistance layer via the second contact hole and ohmically connected to the semiconductor substrate via the third contact hole; as well as forming a second electrode under the semiconductor substrate, A resistor is provided between the first electrode and the second electrode. A protective film is disposed on the first electrode and the relay wiring, an opening is provided in the protective film, and a portion of the first electrode exposed from the opening serves as a pad region to which a bonding wire can be connected.

15. A method for manufacturing a resistor element, characterized in that: Including the following processes: forming a first insulating film on a semiconductor substrate; forming a resistance layer on the first insulating film; forming a second insulating film so as to cover the first insulating film and the resistance layer; On the second insulating film, a first contact hole for exposing the resistance layer, a second contact hole for exposing the resistance layer at a position separated from the first contact hole, and a third contact hole for exposing a portion of the upper surface of the semiconductor substrate at a position separated from the first contact hole and the second contact hole are formed; forming a first electrode electrically connected to the resistance layer via the first contact hole; forming a relay wiring electrically connected to the resistance layer via the second contact hole and ohmically connected to a position of the semiconductor substrate away from the end via the third contact hole; as well as forming a second electrode under the semiconductor substrate, A resistor is provided between the first electrode and the second electrode. The resistance component of the semiconductor substrate is 1 / 100 or less of the resistance component of the resistance layer.

16. The method for manufacturing a resistor element according to claim 14 or 15, characterized in that: At the same time as the resistance layer is formed, an auxiliary film is formed on the first insulating film below the first electrode, separated from the resistance layer and in a floating potential state. The auxiliary film is formed of the same material as the resistance layer.

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