Control circuit and control method

Abstract

This invention discloses a control circuit and control method. The control circuit includes a discharge control circuit for acquiring an input voltage sampling signal and sending a signal to the discharge circuit to control the discharge circuit to turn on at a predetermined time before the arrival of the valley position of the input voltage sampling signal. It also sends a signal to the discharge circuit to control the discharge circuit to turn off at a predetermined time before the end of the valley position or at a predetermined time after the end of the valley position. The control circuit and control method proposed in this invention can greatly reduce the system losses caused by the discharge current. The reduction in system losses is particularly significant under light load or no-load conditions. This invention can reduce no-load standby losses while improving the chip's load-carrying capacity. The circuit designed in this invention is simple and reliable; the delay time can be set according to actual conditions, offering high flexibility.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits and relates to a control circuit, and in particular to a power supply control circuit and a control method. Background Art

[0002] Figure 1-1 For a schematic diagram of an existing power circuit, please refer to Figure 1-1 , the input AC voltage is passed through the rectifier diodes D1 and D2 to obtain the input voltage sampling signal Va. Ideally, Va is a steamed wave after the sine wave is trimmed, and the voltage at the bottom is zero (such as Figure 2 In fact, due to the existence of parasitic capacitor C1, the voltage Va cannot be completely discharged, so the valley bottom position is raised (as shown in the upper half of the waveform). Figure 2 As shown in the lower half of the waveform), the voltage Va cannot truly reflect the voltage value of the input voltage Vac.

[0003] Figure 1-2 For the circuit diagram of another existing power circuit, please refer to Figure 1-2 Since the second capacitor C2 is relatively small and the circuit itself requires that the voltage of the second capacitor C2 present an ideal steamed bun wave, when lightly loaded or unloaded, the bottom position of the waveform of the second capacitor C2 cannot be pulled down to near zero potential.

[0004] In order to make the Va waveform close to the ideal steamed bun wave, it is necessary to add an appropriate discharge circuit to Va, such as Figure 1-1 , Figure 1-2 As shown in the figure. Due to the existence of the discharge current, the system will increase certain losses, especially when it is lightly loaded or no-loaded, the increased losses of the system are more obvious, and the no-load losses are difficult to meet the energy efficiency requirements. In addition, the discharge circuit will also cause the chip to heat up, limiting the maximum load capacity of the chip.

[0005] In view of this, there is an urgent need to design a discharge circuit control method to overcome the above-mentioned defects of the existing discharge circuit control method. Summary of the invention

[0006] The present invention provides a control circuit and a control method, which can greatly reduce the opening time of a discharge circuit, significantly reduce the loss, reduce the circuit no-load loss, and improve the circuit load capacity.

[0007] To solve the above technical problem, according to one aspect of the present invention, the following technical solution is adopted:

[0008] A control circuit, the control circuit comprising a discharge control circuit, the discharge control circuit comprising a first comparator U1 and a timer;

[0009] The first comparator U1 is used to obtain an input voltage sampling signal, and output a first level signal when the input voltage sampling signal is greater than a first reference voltage;

[0010] The timer is coupled to the first comparator U1, and is used to start timing when receiving the first level signal, and output an opening signal after a preset time, and the opening signal is used to control the discharge circuit to discharge current; the timer is used to send a signal to the discharge circuit to control the discharge circuit to shut down before or after the valley position of the input voltage sampling signal ends.

[0011] As an implementation manner of the present invention, the timer includes a second comparator U2 for controlling the length of the preset time.

[0012] As an implementation mode of the present invention, the timer includes a first switch tube Q1, a first current source I1, a first capacitor C1, and a second comparator U2;

[0013] The inverting input terminal of the first comparator U1 is coupled to the input voltage sampling signal Va0, the non-inverting input terminal of the first comparator U1 is coupled to the first reference voltage Vth, and the output terminal of the first comparator U1 is coupled to the gate of the first switch tube Q1;

[0014] The output of the first current source I1 is respectively coupled to the drain of the first switch tube Q1, the first end of the first capacitor C1, and the non-inverting input end of the second comparator U2; the inverting input end of the second comparator U2 is coupled to the second reference voltage V-; the output end of the second comparator U2 is coupled to the discharge circuit; the source of the first switch tube Q1 and the second end of the first capacitor C1 are respectively grounded.

[0015] As an implementation mode of the present invention, the first comparator U1 compares the input voltage sampling signal Va0 with the first reference voltage Vth. When the input voltage sampling signal Va0 is greater than the first reference voltage Vth, the first comparator U1 outputs a low level, the first switch tube Q1 is turned off, and the first current source I1 charges the first capacitor C1.

[0016] The second comparator compares the voltage V+ of the first capacitor C1 with the second reference voltage V-. When the voltage V+ of the first capacitor C1 is greater than the second reference voltage V-, the discharge circuit is turned on, and the input voltage sampling signal Va0 is discharged to the ground through the set second current source Ib.

[0017] As an implementation manner of the present invention, the control circuit further includes a discharge circuit; the discharge circuit includes a second current source Ib and a second switch tube Q2; the output of the second current source Ib is coupled to the second switch tube Q2.

[0018] As an embodiment of the present invention, the control circuit further includes a timer delay time acquisition unit, which determines the timer delay time according to the frequency of the input voltage sampling signal and sends the acquired data to the discharge control circuit;

[0019] The control circuit also includes an AC frequency sampling circuit, which is used to obtain the frequency of the input voltage sampling signal Va0; the AC frequency sampling circuit is connected to the timer delay time acquisition unit, and the timer delay time acquisition unit determines the timer delay time according to the received frequency of the input voltage sampling signal Va0.

[0020] As an implementation mode of the present invention, if the input voltage sampling signal Va0 is a fixed input frequency, or the frequency variation range is less than the set value, the timer delay time acquisition unit sets the counter delay time to the first time;

[0021] If the frequency change of the input voltage sampling signal Va0 is greater than the set value, the timer delay time acquisition unit determines the frequency of the input voltage sampling signal Va0 by peak voltage sampling, and adjusts the value of the second reference voltage V- according to the frequency so that the timer delay time meets the set requirements.

[0022] As an implementation mode of the present invention, the AC frequency sampling circuit includes: a third comparator U3, a D flip-flop, a third current source Ia, a first switch S1, a second switch S2, a second capacitor C2, and an average voltage generating module;

[0023] The inverting input terminal of the third comparator U3 is coupled to the input voltage sampling signal Va0, the non-inverting input terminal of the third comparator U3 is coupled to the third reference voltage Vb, and the output terminal of the third comparator U3 is coupled to the first terminal dk of the D flip-flop;

[0024] The second terminal Q of the D flip-flop is coupled to the first switch S1, and sends a control signal to the first switch S1 to control the on and off of the first switch S1; the third terminal The first terminal and the fourth terminal D are respectively coupled to the second switch S2, and send a control signal to the second switch S2 to control the second switch S2 to be turned on or off;

[0025] The output of the third current source Ia is coupled to the first end of the first switch S1, and the second end of the first switch S1 is respectively coupled to the first end of the second switch S2, the first end of the second capacitor C2, and the first end of the average voltage generating module; the second end of the average voltage generating module is the second reference voltage V-, and the voltage change of the first end of the second capacitor C2 is averaged to obtain the second reference voltage V-.

[0026] A control method, the control method comprising:

[0027] Obtain input voltage sampling signal;

[0028] Comparing the acquired input voltage sampling signal with a first reference voltage, and outputting a first level signal when the input voltage sampling signal is greater than the first reference voltage;

[0029] When the first level signal is received, timing starts, and an on signal is output after a preset time, wherein the on signal is used to control the discharge circuit to discharge current; before or after the valley position of the input voltage sampling signal ends, a signal for controlling the discharge circuit to shut down is sent to the discharge circuit.

[0030] As an embodiment of the present invention, the control method includes: comparing the input voltage sampling signal Va0 with the first reference voltage Vth, when the input voltage sampling signal Va0 is greater than the first reference voltage Vth, the first comparator U1 outputs a low level, the first switch tube Q1 is turned off, and the first capacitor C1 is charged through the first current source I1;

[0031] The voltage V+ of the first capacitor C1 is compared with the second reference voltage V-. When the voltage V+ of the first capacitor C1 is greater than the second reference voltage V-, the discharge circuit is turned on, and the input voltage sampling signal Va0 is discharged to the ground through the set second current source Ib.

[0032] As an implementation manner of the present invention, the control method includes: acquiring the frequency of the input voltage sampling signal Va0, and determining the timer delay time according to the frequency of the input voltage sampling signal Va0.

[0033] As an implementation mode of the present invention, if the input voltage sampling signal Va0 is a fixed input frequency, or the frequency variation range is less than the set value, the counter delay time is set to the first time;

[0034] If the frequency change of the input voltage sampling signal Va0 is greater than the set value, the frequency of the input voltage sampling signal Va0 is determined by peak voltage sampling, and the value of the second reference voltage V- is adjusted according to the frequency so that the timer delay time meets the set requirements.

[0035] As an embodiment of the present invention, the control method includes: comparing the input voltage sampling signal Va0 with the third reference voltage Vb to generate a square wave signal, sampling the rising edge signal through a D trigger, the output high level time of the D trigger is the sampled AC input cycle, during the period when the Q end of the D trigger outputs a high level, the first switch S1 is turned on, the second switch S2 is turned off, the third current source Ia charges the second capacitor C2, and the maximum voltage VC2max reached by the second capacitor C2 represents the length of the input cycle of the input voltage sampling signal Va0; transmitting the average value of VC2max to the second reference voltage V-, that is, the inverting input end of the second comparator U2, through the sampling and holding signal; when the AC cycle is longer, VC2max is larger, and the corresponding second reference voltage V- is larger, so that the timer delay time td is longer, and adaptive control of the delay time is achieved.

[0036] The beneficial effects of the present invention are: the control circuit and control method proposed in the present invention can greatly reduce the system loss caused by the discharge current. Especially when light load or no load, the loss added to the system is reduced significantly; the present invention can reduce no-load standby loss and improve the chip load capacity. The circuit designed by the present invention is simple and reliable; the present invention can set the delay time according to the actual situation, and has greater flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1-1 The invention is a circuit diagram of an existing power circuit.

[0038] Figure 1-2 The figure is a circuit diagram of another existing electrical circuit.

[0039] Figure 2 It is the waveform diagram of Va under ideal and actual conditions of the existing power circuit.

[0040] Figure 3 FIG. 4 is a circuit diagram of a control circuit in an embodiment of the present invention.

[0041] Figure 4 1 is a waveform diagram of relevant points in the control circuit in one embodiment of the present invention.

[0042] Figure 5 FIG. 4 is a circuit diagram of an AC frequency sampling circuit in an embodiment of the present invention.

[0043] Figure 6 1 is a waveform diagram of relevant points in an AC frequency sampling circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0046] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments. The same or similar prior art means and some technical features in the embodiments are mutually replaced within the scope of the present invention.

[0047] The term "coupling" or connection in the specification includes both direct connection and indirect connection, such as connection through some active devices, passive devices or electrically conductive media; it may also include connection through other active devices or passive devices known to those skilled in the art on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits.

[0048] In addition, the “input voltage sampling signal” in the specification may be a voltage signal obtained after rectification of the AC voltage, or may be a voltage-divided signal thereof.

[0049] The present invention discloses a control circuit, which includes a discharge control circuit, which is used to obtain an input voltage sampling signal, and send a signal for controlling the discharge circuit to be turned on to the discharge circuit at a set time before the valley bottom position of the input voltage sampling signal arrives, and send a signal for controlling the discharge circuit to be turned off to the discharge circuit at a set time before the valley bottom position of the input voltage sampling signal ends or a set time after the valley bottom position ends.

[0050] In one embodiment of the present invention, the discharge control circuit includes a first comparator U1 and a timer; the first comparator U1 is used to obtain an input voltage sampling signal, and when the input voltage sampling signal is greater than a first reference voltage, outputs a first level signal; the timer is coupled to the first comparator U1, and is used to start timing when receiving the first level signal, and output an opening signal after a preset time, and the opening signal is used to control the discharge circuit to discharge current; the timer is used to send a signal to the discharge circuit to control the discharge circuit to shut down before or after the valley position of the input voltage sampling signal ends.

[0051] In one embodiment of the present invention, the timer includes a second comparator U2 for controlling the length of the preset time.

[0052] Figure 3 is a circuit diagram of a control circuit in one embodiment of the present invention; please refer to Figure 3In one embodiment of the present invention, the discharge control circuit includes a first comparator U1 and a timer 10. The first input terminal of the first comparator U1 is coupled to the input voltage sampling signal, the second input terminal of the first comparator U1 is coupled to the first reference voltage, and the output terminal of the first comparator U1 is coupled to the timer 10. The first comparator U1 is used to compare the input voltage sampling signal with the first reference voltage, and feed back the comparison result to the timer 10; the timer 10 outputs a signal for controlling the discharge circuit to be turned on or off according to the comparison result of the first comparator U1.

[0053] In one embodiment of the present invention, the timer includes a first switch tube Q1, a first current source I1, a first capacitor C1, and a second comparator U2. The inverting input terminal of the first comparator U1 is coupled to Va0 (in one embodiment of the present invention, Va0 is a voltage-divided signal of the input voltage sampling signal Va), the non-inverting input terminal of the first comparator U1 is coupled to the first reference voltage Vth, and the output terminal of the first comparator U1 is coupled to the gate of the first switch tube Q1. The output of the first current source I1 is respectively coupled to the drain of the first switch tube Q1, the first end of the first capacitor C1, and the non-inverting input terminal of the second comparator U2, the inverting input terminal of the second comparator U2 is coupled to the second reference voltage V-, and the output terminal of the second comparator U2 is coupled to the discharge circuit; the source of the first switch tube Q1 and the second end of the first capacitor C1 are respectively grounded.

[0054] In one embodiment of the present invention, the first comparator U1 compares the voltage-divided signal Va0 with the first reference voltage Vth. When Va0 is greater than the first reference voltage Vth, the first comparator U1 outputs a low level, the first switch tube Q1 is turned off, and the timer charges the first capacitor C1 through the first current source I1; the second comparator compares the voltage V+ of the first capacitor C1 with the second reference voltage V-. When the voltage V+ of the first capacitor C1 is greater than the second reference voltage V-, the discharge circuit is turned on, and the input voltage sampling signal Va is discharged to the ground through the set second current source Ib.

[0055] Figure 4 : is a waveform diagram of each relevant point in the control circuit in one embodiment of the present invention; the waveform of each relevant point in the control circuit is as shown in FIG. Figure 4 By selecting a suitable first reference voltage Vth, a first capacitor C1, a first current source I1 and a second reference voltage V-value, the discharge circuit can be turned on or off at a predetermined time point.

[0056] Please continue reading Figure 3In one embodiment of the present invention, the control circuit further includes a discharge circuit 20; the discharge circuit 20 includes a second current source Ib and a second switch tube Q2; the output of the second current source Ib is coupled to the second switch tube Q2. In one embodiment of the present invention, the output end of the second comparator U2 is coupled to the gate of the second switch tube Q2, the input of the second current source Ib is coupled to the input voltage sampling signal Va, the output of the second current source Ib is coupled to the drain of the second switch tube Q2, and the source of the second switch tube Q2 is grounded.

[0057] In one embodiment of the present invention, Figure 4 The selection of the counter td time can be determined according to specific requirements: (1) If the input voltage sampling signal Va is a fixed input frequency, or the frequency variation range is less than the set value, the timer delay time acquisition unit sets the counter delay time to the first time. For example, when the AC input is 50Hz, the half-wave period is 10ms, and the appropriate system parameters are used. Figure 4 In the example, the counter td time is 8ms. This solution is simple and reliable to implement. (2) If the frequency change of the input voltage sampling signal Va is greater than the set value, the frequency of the input voltage sampling signal Va is determined by peak voltage sampling, and the value of the second reference voltage V- is adjusted according to the frequency so that the timer delay time meets the set requirements.

[0058] In an embodiment of the present invention, the control circuit further includes a timer delay time acquisition unit, which determines the timer delay time according to the frequency of the input voltage sampling signal and sends the acquired data to the discharge control circuit.

[0059] Figure 5 is a circuit diagram of an AC frequency sampling circuit in one embodiment of the present invention; please refer to Figure 5 In one embodiment of the present invention, the control circuit further includes an AC frequency sampling circuit, which is used to obtain the frequency of the input voltage sampling signal Va; the AC frequency sampling circuit is connected to the timer delay time acquisition unit, and the timer delay time acquisition unit determines the timer delay time according to the frequency of the received input voltage sampling signal Va; the AC frequency sampling circuit includes: a third comparator U3, a D trigger, a third current source Ia, a first switch S1, a second switch S2, a second capacitor C2, and an average voltage generation module 30.

[0060] The inverting input terminal of the third comparator U3 is coupled to the voltage division signal Va0, the non-inverting input terminal of the third comparator U3 is coupled to the third reference voltage Vb, and the output terminal of the third comparator U3 is coupled to the first terminal dk of the D flip-flop. The second terminal Q of the D flip-flop is coupled to the first switch S1, and a control signal for controlling the on and off of the first switch S1 is sent to the first switch S1; the third terminal of the D flip-flop The output of the third current source Ia is coupled to the first end of the first switch S1, and the second end of the first switch S1 is coupled to the first end of the second switch S2, the first end of the second capacitor C2, and the first end of the average voltage generating module 30; the second end of the second switch S2 and the second end of the second capacitor C2 are grounded respectively.

[0061] In one embodiment of the present invention, the average voltage generating module 30 includes a third switch S3, a fourth switch S4, a third resistor R3, a third capacitor C3, a fourth capacitor C4, and a fourth diode D4. The cathode of the fourth diode D4 is respectively coupled to the first end of the third switch S3, the first end of the third capacitor C3, and the first end of the fourth switch S4; the second end of the third switch S3 and the second end of the third capacitor C3 are respectively grounded; the second end of the fourth switch S4 is coupled to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is grounded.

[0062] In one embodiment of the present invention, regarding the implementation method of sampling AC frequency: Figure 5 As shown, Va0 (the voltage signal of the input voltage VAC sampled by Va0) is compared with the third reference voltage Vb to generate a square wave signal. The rising edge signal is sampled by the D flip-flop. The output high level time of the D flip-flop is the sampled AC input cycle. During the period when the Q end of the D flip-flop outputs a high level, the first switch S1 is turned on, the second switch S2 is turned off, and the third current source Ia charges the second capacitor C2. The maximum voltage VC2max reached by the second capacitor C2 represents the length of the input cycle of the input voltage sampling signal Va. The average value of VC2max is transmitted to the second reference voltage V- through the relevant sampling and holding signal, that is, Figure 3 The inverting input terminal of the second comparator U2 in the circuit. When the AC cycle is longer, VC2max is larger, and the corresponding second reference voltage V- is larger, so that the timer delay time td is longer, and adaptive control of the delay time is achieved; the relevant waveform is as follows Figure 6 shown.

[0063] The present invention also discloses a control method, which includes: obtaining an input voltage sampling signal, sending a signal to control the discharge circuit to be turned on at a set time before the valley bottom position of the input voltage sampling signal arrives; sending a signal to control the discharge circuit to be turned off at a set time before the valley bottom position of the input voltage sampling signal ends or at a set time after the valley bottom position ends.

[0064] In an embodiment of the present invention, the control method includes: comparing an input voltage sampling signal with a first reference voltage, and feeding back the comparison result to a timer; the timer outputs a signal for controlling the discharge circuit to be turned on or off according to the comparison result.

[0065] In one embodiment of the present invention, the control method includes: obtaining an input voltage sampling signal; comparing the obtained input voltage sampling signal with a first reference voltage, and outputting a first level signal when the input voltage sampling signal is greater than the first reference voltage; starting timing when the first level signal is received, and outputting an opening signal after a preset time, the opening signal being used to control the discharge circuit to discharge current; sending a signal to the discharge circuit to control the discharge circuit to shut down before or after the valley position of the input voltage sampling signal ends.

[0066] In one embodiment of the present invention, the control method includes: comparing the input voltage sampling signal Va0 with the first reference voltage Vth, when the input voltage sampling signal Va0 is greater than the first reference voltage Vth, the first comparator U1 outputs a low level, the first switch tube Q1 is turned off, and the first capacitor C1 is charged through the first current source I1; comparing the voltage V+ of the first capacitor C1 with the second reference voltage V-, when the voltage V+ of the first capacitor C1 is greater than the second reference voltage V-, the discharge circuit is turned on, and the AC signal Va is discharged to the ground through the set second current source Ib.

[0067] In one embodiment of the present invention, the control method includes: comparing the input voltage sampling signal Va0 with the third reference voltage Vb to generate a square wave signal, sampling the rising edge signal through a D trigger, the output high level time of the D trigger is the sampled AC input cycle, during the period when the Q end of the D trigger outputs a high level, the first switch S1 is turned on, the second switch S2 is turned off, the third current source Ia charges the second capacitor C2, and the maximum voltage VC2max reached by the second capacitor C2 represents the length of the AC signal input cycle; transmitting the average value of VC2max to the second reference voltage V-, that is, the inverting input terminal of the second comparator U2, through the sampling and holding signal; when the AC cycle is longer, VC2max is larger, and the corresponding second reference voltage V- is larger, so that the timer delay time td is longer, and adaptive control of the delay time is achieved.

[0068] In one embodiment of the present invention, the control method includes: obtaining the frequency of the input voltage sampling signal Va, and determining the timer delay time according to the frequency of the input voltage sampling signal Va. (1) If the input voltage sampling signal Va (i.e., the input voltage AC signal) is a fixed input frequency, or the frequency variation range is less than the set value, the timer delay time acquisition unit sets the counter delay time to the first time. For example, when the AC input is 50Hz, the half-wave period is 10ms, and the appropriate system parameters are used. Figure 4 In the example, the counter td time is 8ms. This solution is simple and reliable to implement. (2) If the frequency change of the input voltage sampling signal Va is greater than the set value, the frequency of the input voltage sampling signal Va is determined by peak voltage sampling, and the value of the second reference voltage V- is adjusted according to the frequency so that the timer delay time meets the set requirements.

[0069] In one embodiment of the present invention, the control method is implemented by a control circuit; the composition of the control circuit can refer to the description of each of the above embodiments.

[0070] In one embodiment of the present invention, the voltage-divided signal Va0 is compared with the first reference voltage Vth. When Va0 is greater than the first reference voltage Vth, the first comparator U1 outputs a low level, the first switch tube Q1 is turned off, and the first capacitor C1 is charged through the first current source I1. The voltage V+ of the first capacitor C1 is compared with the second reference voltage V-. When the voltage V+ of the first capacitor C1 is greater than the second reference voltage V-, the discharge circuit is turned on, and the input voltage sampling signal Va is discharged to the ground through the set second current source Ib.

[0071] In one embodiment of the present invention, the control method includes the step of adjusting the timer delay time according to AC frequency sampling, specifically including: comparing the voltage division signal Va0 with the third reference voltage Vb to generate a square wave signal, sampling the rising edge signal through the D flip-flop, the output high level time of the D flip-flop is the sampled AC input cycle, during the period when the Q end of the D flip-flop outputs a high level, the first switch S1 is turned on, the second switch S2 is turned off, the third current source Ia charges the second capacitor C2, and the maximum voltage VC2max reached by the second capacitor C2 represents the length of the input cycle of the input voltage sampling signal Va; the average value of VC2max is transmitted to the second reference voltage V-, that is, the inverting input terminal of the second comparator U2 through the relevant sampling and holding signal; when the AC cycle is longer, VC2max is larger, and the corresponding second reference voltage V- is larger, so that the timer delay time td is longer, and adaptive control of the delay time is achieved.

[0072] In summary, the control circuit and control method proposed in the present invention can greatly reduce the system loss caused by the discharge current. Especially when lightly loaded or unloaded, the system loss reduction is particularly obvious; the present invention can reduce the no-load standby loss and improve the chip load capacity. The circuit designed by the present invention is simple and reliable; the present invention can set the delay time according to the actual situation, which is more flexible.

[0073] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] The description and application of the present invention here are illustrative and are not intended to limit the scope of the present invention to the above-described embodiments. The deformation and changes of the embodiments disclosed here are possible, and the replacement of the embodiments and the various components equivalent to those of ordinary skill in the art are well known. It should be clear to those skilled in the art that the present invention can be realized in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential characteristics of the present invention. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A control circuit, characterized in that: The control circuit includes a discharge control circuit, and the discharge control circuit includes a first comparator U1 and a timer; The first comparator U1 is used to obtain an input voltage sampling signal, and output a first level signal when the input voltage sampling signal is greater than a first reference voltage; The input voltage sampling signal is a pulsating waveform signal obtained after full-wave rectification of the AC voltage signal; The timer is coupled to the first comparator U1, and is used to start timing when receiving the first level signal, and output an on signal after a preset time, and the on signal is used to control the discharge circuit to discharge current; the timer is used to send a signal to the discharge circuit to control the discharge circuit to shut down before or after the valley position of the input voltage sampling signal ends; The control circuit further includes a timer delay time acquisition unit, which determines the timer delay time according to the frequency of the input voltage sampling signal and sends the acquired data to the discharge control circuit; the delay time is the preset time; The control circuit further includes an AC frequency sampling circuit, which is used to obtain the frequency of the input voltage sampling signal Va0; the AC frequency sampling circuit is connected to the timer delay time acquisition unit, and the timer delay time acquisition unit determines the timer delay time according to the received frequency of the input voltage sampling signal Va0; If the input voltage sampling signal Va0 is a fixed input frequency, or the frequency variation range is less than the set value, the timer delay time acquisition unit sets the counter delay time to the first time; If the frequency change of the input voltage sampling signal Va0 is greater than the set value, the timer delay time acquisition unit determines the frequency of the input voltage sampling signal Va0 by peak voltage sampling, and adjusts the value of the second reference voltage V- according to the frequency, so that the timer delay time meets the set requirements; When the AC cycle is longer, the value of the second reference voltage V- is larger, which makes the timer delay time td longer.

2. The control circuit according to claim 1, characterized in that: The timer includes a second comparator U2, and the second comparator U2 is used to control the length of the preset time.

3. The control circuit according to claim 1, characterized in that: The timer includes a first switch tube Q1, a first current source I1, a first capacitor C1, and a second comparator U2; The inverting input terminal of the first comparator U1 is coupled to the input voltage sampling signal Va0, the non-inverting input terminal of the first comparator U1 is coupled to the first reference voltage Vth, and the output terminal of the first comparator U1 is coupled to the gate of the first switch tube Q1; The output of the first current source I1 is respectively coupled to the drain of the first switch tube Q1, the first end of the first capacitor C1, and the non-inverting input end of the second comparator U2; the inverting input end of the second comparator U2 is coupled to the second reference voltage V-; the output end of the second comparator U2 is coupled to the discharge circuit; the source of the first switch tube Q1 and the second end of the first capacitor C1 are respectively grounded.

4. The control circuit according to claim 3, characterized in that: The first comparator U1 compares the input voltage sampling signal Va0 with the first reference voltage Vth. When the input voltage sampling signal Va0 is greater than the first reference voltage Vth, the first comparator U1 outputs a low level, the first switch tube Q1 is turned off, and the first current source I1 charges the first capacitor C1. The second comparator U2 compares the voltage V+ of the first capacitor C1 with the second reference voltage V-. When the voltage V+ of the first capacitor C1 is greater than the second reference voltage V-, the discharge circuit is turned on, and the input voltage sampling signal Va0 is discharged to the ground through the set second current source Ib.

5. The control circuit according to any one of claims 1 to 4, characterized in that: The control circuit further includes a discharge circuit; the discharge circuit includes a second current source Ib and a second switch tube Q2; the output of the second current source Ib is coupled to the second switch tube Q2.

6. The control circuit according to claim 1, characterized in that: The AC frequency sampling circuit includes: a third comparator U3, a D trigger, a third current source Ia, a first switch S1, a second switch S2, a second capacitor C2, and an average voltage generation module; The inverting input terminal of the third comparator U3 is coupled to the input voltage sampling signal Va0, the non-inverting input terminal of the third comparator U3 is coupled to the third reference voltage Vb, and the output terminal of the third comparator U3 is coupled to the first terminal dk of the D flip-flop; The second terminal Q of the D flip-flop is coupled to the first switch S1, and sends a control signal to the first switch S1 to control the on and off of the first switch S1; the third terminal Q and the fourth terminal D of the D flip-flop are respectively coupled to the second switch S2, and send a control signal to the second switch S2 to control the on and off of the second switch S2; The output of the third current source Ia is coupled to the first end of the first switch S1, and the second end of the first switch S1 is respectively coupled to the first end of the second switch S2, the first end of the second capacitor C2, and the first end of the average voltage generating module; the second end of the average voltage generating module is the second reference voltage V-, and the voltage change of the first end of the second capacitor C2 is averaged to obtain the second reference voltage V-.

7. A control method, characterized in that: The control method comprises: Acquire an input voltage sampling signal; the input voltage sampling signal is a pulsating waveform signal obtained after full-wave rectification of the AC voltage signal; Comparing the acquired input voltage sampling signal with a first reference voltage, and outputting a first level signal when the input voltage sampling signal is greater than the first reference voltage; When the first level signal is received, timing is started, and an opening signal is output after a preset time, wherein the opening signal is used to control the discharge circuit to discharge current; before or after the valley position of the input voltage sampling signal ends, a signal for controlling the discharge circuit to shut down is sent to the discharge circuit; The control method comprises: obtaining the frequency of the input voltage sampling signal Va0, and determining the delay time of the timer according to the frequency of the input voltage sampling signal Va0; the delay time is the preset time; If the input voltage sampling signal Va0 is a fixed input frequency, or the frequency variation range is less than the set value, the timer delay time acquisition unit sets the counter delay time to the first time; If the frequency change of the input voltage sampling signal Va0 is greater than the set value, the timer delay time acquisition unit determines the frequency of the input voltage sampling signal Va0 by peak voltage sampling, and adjusts the value of the second reference voltage V- according to the frequency, so that the timer delay time meets the set requirements; When the AC cycle is longer, the value of the second reference voltage V- is larger, which makes the timer delay time td longer.

8. The control method according to claim 7, characterized in that: The control method comprises: comparing the input voltage sampling signal Va0 with the first reference voltage Vth, when the input voltage sampling signal Va0 is greater than the first reference voltage Vth, the first comparator U1 outputs a low level, the first switch tube Q1 is turned off, and the first capacitor C1 is charged through the first current source I1; The voltage V+ of the first capacitor C1 is compared with the second reference voltage V-. When the voltage V+ of the first capacitor C1 is greater than the second reference voltage V-, the discharge circuit is turned on, and the input voltage sampling signal Va0 is discharged to the ground through the set second current source Ib.

9. The control method according to claim 8, characterized in that: The control method includes: comparing the input voltage sampling signal Va0 with the third reference voltage Vb to generate a square wave signal, sampling the rising edge signal through a D trigger, the output high level time of the D trigger is the sampled AC input cycle, during the period when the Q end of the D trigger outputs a high level, the first switch S1 is turned on, the second switch S2 is turned off, the third current source Ia charges the second capacitor C2, and the maximum voltage VC2max reached by the second capacitor C2 represents the length of the input cycle of the input voltage sampling signal Va0; transmitting the average value of VC2max to the second reference voltage V-, that is, the inverting input end of the second comparator U2, through the sampling and holding signal; when the AC cycle is longer, VC2max is larger, and the corresponding second reference voltage V- is larger, so that the timer delay time td is longer, and adaptive control of the delay time is achieved.

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