Delay Control Circuit for Asynchronous Successive Approximation Analog-to-Digital Converter

Abstract

The present invention discloses a delay control circuit of an asynchronous successive approximation analog-to-digital converter, comprising: a phase-locked loop correction circuit and a delay chain circuit, wherein the phase-locked loop correction circuit comprises a voltage-controlled oscillator, and the phase-locked loop correction circuit provides a first control voltage of the voltage-controlled oscillator; the delay chain circuit comprises: a delay chain composed of N-stage first delay units cascaded; a multiplexer respectively connected to the output end of each first delay unit in the delay chain; an input end connected to the first control voltage, and an output end connected to the first buffer of each first delay unit; a first capacitor having one end connected to the ground and the other end connected to the output end of the first buffer. After the first control voltage passes through the first buffer and the first capacitor, a second control voltage is generated, which is respectively used to control the delay time of each first delay unit. The operating speed of the ADC can be increased, the linearity and signal-to-noise ratio of the ADC can be improved, and the yield rate of mass-produced chips can be increased.

Description

Technical Field

[0001] The invention relates to the field of data conversion integrated circuits, and in particular to a delay control circuit of an asynchronous SAR-ADC (successive approximation analog-digital converter). Background Art

[0002] Successive approximation analog-to-digital converter (SAR-ADC) has the characteristics of simple structure, low power consumption, small area and easy integration. It is widely used in the field of medium precision (8-16 bits) and medium speed (<150Msps).

[0003] Conventional SAR-ADC clock control is synchronous, that is, an external clock is connected, and each step of sampling, conversion, storage, and output in the chip is defined by the external clock. The accuracy of the external clock must match the sampling accuracy of the SAR-ADC. In addition to ensuring the purity of the clock source, it is also necessary to be very careful about the noise from the clock to each link inside the chip. In addition, the high-speed clock frequency requires the logic gates in the chip to have a strong driving capability, which means a lot of power consumption. For high-speed SAR-ADC, it is very uneconomical and difficult to use synchronous control to achieve a speed of more than 100MS / s and an accuracy of more than 10 bits.

[0004] Asynchronous clock control is the most important system-level solution for speeding up SAR-ADC in recent years. SAR-ADC has some characteristics. For example, sampling requires high clock accuracy, but conversion has almost no requirements for clock accuracy, which just provides space for asynchronous clock to play its advantages. The pulses required by the control circuit are generated by itself. Asynchronous clock control abandons the frequency division operation of the synchronous clock, and instead uses an external clock with the same sampling frequency to divide the clock into two stages: sampling and conversion. During conversion, the system has no requirements for the edge of the operating clock. The conversion is made into an asynchronous trigger, and the comparator is used to trigger the SAR logic. The SAR logic drives the digital-to-analog conversion array (DAC Array) to complete N comparisons. Finally, the N data that are completed in sequence but not aligned with the clock are output in a synchronous manner.

[0005] The basic structure of asynchronous SAR-ADC is as follows Figure 2 As shown, the external clock signal passes through the clock generation circuit to generate the sampling clock CLK sample. After the sampling clock samples the input differential signals INP and INN, they are compared by a high-speed comparator, and the Ready signal is generated through XOR and input into a high-speed digital circuit composed of a multi-phase clock generator and successive approximation logic. On the one hand, a clock signal is generated to provide a comparison clock to the comparator through a delay chain, and on the other hand, the SAR-ADC switch capacitor array (digital-analog conversion array, DAC Array) is controlled through a DAC (digital-analog conversion) control circuit. The reference voltage of the DAC is generated by an external reference source (BG) through a reference voltage buffer (VREF BUF). The delay loop of the entire asynchronous SAR-ADC consists of a comparator, an XOR gate, a multi-phase clock generation circuit, and a delay chain. Since the delays of other circuits are basically fixed, the adjustment of the delay time of the delay chain becomes the only controllable factor.

[0006] Traditional asynchronous SAR-ADC delay control circuit such as Figure 3 As shown, VIN is used as the input signal of the delay chain. The multiplexer (MUXN×1) selects one of the taps of the N delay units (DELAY) as the output signal VOUT. Since the delay time of the delay chain changes with the process angle, voltage and temperature (PVT), the delay time may even change by more than twice under different PVT change conditions. A larger delay time can increase the DAC's stabilization time, thereby improving the overall performance of the ADC, but it may cause the loss of the last few comparison pulses of the ADC, affecting the mass production yield of the ADC. A smaller delay time will cause the performance of the ADC to deteriorate. Summary of the invention

[0007] The object of the present invention is to provide a delay control circuit of an asynchronous successive approximation analog-to-digital converter, which can increase the operating speed of the ADC, improve the linearity and signal-to-noise ratio (SNR) of the ADC, and increase the yield of mass-produced chips.

[0008] The technical solution to achieve the above purpose is:

[0009] A delay control circuit of an asynchronous successive approximation analog-to-digital converter comprises: a phase-locked loop correction circuit and a delay chain circuit, wherein:

[0010] The phase-locked loop correction circuit includes a voltage-controlled oscillator, and the phase-locked loop correction circuit provides a first control voltage of the voltage-controlled oscillator;

[0011] The delay chain circuit comprises:

[0012] A delay chain formed by cascading N stages of first delay units; N ≥ 2 and is a positive integer;

[0013] A multiplexer connected to the output end of each first delay unit in the delay chain respectively;

[0014] An input terminal is connected to the first control voltage, and an output terminal is connected to a first buffer of each of the first delay units; (BUF) and

[0015] One end is grounded, and the other end is connected to a first capacitor at an output end of the first buffer;

[0016] The first control voltage, after passing through the first buffer and the first capacitor, generates a second control voltage for controlling the delay time of each of the first delay units.

[0017] Preferably, the phase-locked loop correction circuit further includes: a phase frequency detector (PFD), a charge pump (CP), a loop filter (LPF), a first inverter and an M divider, wherein:

[0018] The frequency detector and phase detector receive a reference frequency;

[0019] The output end of the frequency and phase detector is connected to the input end of the charge pump;

[0020] The output end of the charge pump is connected to the loop filter and the voltage controlled oscillator;

[0021] The loop filter generates the first control voltage and supplies it to the voltage controlled oscillator;

[0022] The output end of the voltage-controlled oscillator is connected to the input end of the phase frequency detector through the first inverter and the M frequency divider in sequence.

[0023] Preferably, the voltage-controlled oscillator comprises: N stages of second delay units cascaded to each other, and a third delay unit cascaded to the last stage of the second delay unit and outputting feedback to the first stage of the second delay unit; N≥2 and is a positive integer;

[0024] The delay time of the second delay unit is twice the delay time of the third delay unit;

[0025] The first control voltage is supplied to each of the second delay unit and the third delay unit respectively.

[0026] Preferably, the first delay unit and the second delay unit have the same structure, both consisting of two stages of controllable inverters in cascade; the third delay unit includes a single stage of controllable inverter;

[0027] The voltage-controlled oscillator and the delay chain circuit both further include: an error amplifier (EA), a first PMOS tube, a first resistor, a second PMOS tube and a first NMOS tube, wherein a first input terminal of the error amplifier is connected to the first control voltage or the second control voltage, a second input terminal is grounded through the first resistor, and an output terminal is connected to the gate of the first PMOS tube and the gate of the second PMOS tube;

[0028] The source of the first PMOS tube is connected to a power supply, and the drain is grounded through the first resistor;

[0029] The source of the second PMOS tube is connected to a power supply, and the drain is connected to the drain of the first NMOS tube;

[0030] The drain of the first NMOS tube is connected to the gate of the first NMOS tube;

[0031] The source of the first NMOS tube is grounded;

[0032] The gate of the second PMOS tube and the gate of the first NMOS tube are respectively connected to each of the first delay units or each of the second delay unit and the third delay unit;

[0033] The delay chain circuit further includes a second buffer connected to the output end of the multiplexer.

[0034] Preferably, the first delay unit and the second delay unit have the same structure, both consisting of two stages of differential inverters in cascade connection; the third delay unit includes a single stage of differential inverter;

[0035] The voltage-controlled oscillator and the delay chain circuit both further include: a double-to-single circuit for converting the differential signal output by the third delay unit or the differential signal output by the multiplexer into a single-channel signal;

[0036] The delay chain circuit further includes: a third buffer connected to the output end of the double-to-single circuit.

[0037] Preferably, the controllable inverter comprises: a third PMOS tube, a fourth PMOS tube, a second NMOS tube and a third NMOS tube, wherein:

[0038] The source of the third PMOS tube is connected to a power supply, the drain is connected to the source of the fourth PMOS tube, and the gate is connected to the gate of the second PMOS tube;

[0039] The connected end of the drain of the fourth PMOS tube and the drain of the second NMOS tube serves as an output end;

[0040] The connecting end of the gate of the fourth PMOS tube and the gate of the second NMOS tube is used as an input end;

[0041] The source of the third NMOS tube is grounded, the drain is connected to the source of the second NMOS tube, and the gate is connected to the gate of the first NMOS tube.

[0042] Preferably, the differential inverter comprises: a variable capacitor, a fifth PMOS transistor, a sixth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor, wherein:

[0043] The control terminal of the variable capacitor is connected to the first control voltage or the second control voltage;

[0044] The source electrodes of the fifth PMOS tube and the sixth PMOS tube are respectively connected to a power source;

[0045] The source electrodes of the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube and the seventh NMOS tube are respectively grounded;

[0046] The connected end of the gate of the fifth PMOS tube and the gate of the fourth NMOS tube serves as an input end;

[0047] The connecting end of the gate of the sixth PMOS tube and the gate of the seventh NMOS tube serves as another input end;

[0048] The drain of the fifth PMOS tube, the drain of the fourth NMOS tube, the drain of the fifth NMOS tube, the gate of the sixth NMOS tube and the first end of the variable capacitor are connected, and the connected ends serve as an output end;

[0049] The drain of the sixth PMOS tube, the drain of the seventh NMOS tube, the gate of the fifth NMOS tube, the drain of the sixth NMOS tube and the second end of the variable capacitor are connected, and the connected end serves as another output end.

[0050] Preferably, the double-to-single circuit comprises: a seventh PMOS tube, an eighth PMOS tube, an eighth NMOS tube and a ninth NMOS tube, wherein:

[0051] The source of the seventh PMOS tube is connected to a power supply, the drain is connected to the drain of the eighth NMOS tube, and the gate is connected to the gate of the eighth PMOS tube and the drain of the seventh PMOS tube;

[0052] The source of the eighth PMOS tube is connected to a power supply;

[0053] The connected end of the drain of the eighth PMOS tube and the drain of the ninth NMOS tube serves as an output end;

[0054] The source electrodes of the eighth NMOS tube and the ninth NMOS tube are respectively grounded;

[0055] The gate of the eighth NMOS tube and the gate of the ninth NMOS tube serve as two input terminals.

[0056] The beneficial effects of the present invention are as follows: the present invention uses a phase-locked loop to automatically correct the delay time of the delay control circuit in real time, thereby reducing the variation of the comparison clock generated by the asynchronous SAR-ADC delay loop with process angle, voltage and temperature (PVT). Therefore, in large-scale mass production, the variation of the ADC conversion time can be greatly reduced, thereby leaving enough margin for the settling time of the capacitor digital-to-analog conversion array (CDAC) in the ADC. The present invention can increase the operating speed of the asynchronous SAR-ADC, improve the linearity and signal-to-noise ratio of the ADC, and increase the yield of mass-produced chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a delay control circuit of an asynchronous successive approximation analog-to-digital converter in the present invention;

[0058] Figure 2 This is a basic structural diagram of an asynchronous SAR-ADC;

[0059] Figure 3 It is a circuit diagram of a delay control circuit of an asynchronous SAR-ADC in the prior art;

[0060] Figure 4 is a circuit diagram of a phase-locked loop correction circuit in the present invention;

[0061] Figure 5 is a circuit diagram of an embodiment of a voltage-controlled oscillator in the present invention;

[0062] Figure 6 is a circuit diagram of an embodiment of a delay chain circuit in the present invention;

[0063] Figure 7 is a circuit diagram of a second embodiment of a voltage-controlled oscillator in the present invention;

[0064] Figure 8 It is a circuit diagram of a second embodiment of a delay chain circuit in the present invention. DETAILED DESCRIPTION

[0065] The present invention will be further described below in conjunction with the accompanying drawings.

[0066] See also Figure 1 The delay control circuit of the asynchronous successive approximation analog-to-digital converter of the present invention includes: a phase-locked loop (PLL) correction circuit and a delay chain circuit.

[0067] The phase-locked loop correction circuit comprises a voltage-controlled oscillator 11 , and the phase-locked loop correction circuit provides a first control voltage VC for the voltage-controlled oscillator 11 .

[0068] The delay chain circuit includes: a delay chain, a multiplexer 22, a first buffer 23 and a first capacitor C1. The delay chain is composed of N stages of first delay units 21 cascaded, N≥2, and is a positive integer. The multiplexer 22 is respectively connected to the output ends of each first delay unit 21 in the delay chain. That is: the multiplexer 22 selects one path from the taps of the N first delay units 21 as the output signal VOUT. The input end of the first buffer 23 is connected to the first control voltage VC, and the output end is connected to each first delay unit 21. One end of the first capacitor C1 is grounded, and the other end is connected to the output end of the first buffer 23. Among them, the first control voltage VC generates a second control voltage VTRIM for controlling the delay time of each first delay unit 21 after passing through the first buffer 23 and the first capacitor C1. The first capacitor C1 can filter out high-frequency glitches from the phase-locked loop correction circuit.

[0069] like Figure 4 As shown, the phase-locked loop correction circuit further includes: a phase frequency detector 12 , a charge pump 13 , a loop filter 14 , a first inverter 15 and an M frequency divider 16 .

[0070] The frequency detector 12 receives the reference frequency FREF. The output of the frequency detector 12 is connected to the input of the charge pump 13. The output of the charge pump 13 is connected to the loop filter 14 and the voltage controlled oscillator 11. The loop filter 14 generates a first control voltage VC and supplies it to the voltage controlled oscillator 11. The output of the voltage controlled oscillator 11 is connected to the input of the frequency detector 12 through the first inverter 15 and the M frequency divider 16 in sequence.

[0071] Specifically, the voltage controlled oscillator 11 includes: N stages of second delay units 17 cascaded with each other, and a third delay unit 18 cascaded with the last stage of second delay units 17 and outputting feedback to the first stage of second delay units 17; N ≥ 2, and is a positive integer. The delay time of the second delay unit 17 is twice the delay time of the third delay unit 18. The first control voltage VC is supplied to each second delay unit 17 and the third delay unit 18 respectively.

[0072] If the delay unit in the delay chain circuit and the delay unit in the phase-locked loop correction circuit are the same circuit, the clock period of the voltage-controlled oscillator 11 (VCO) in the phase-locked loop correction circuit is proportional to the total delay time of the delay chain. Since the reference voltage of the phase-locked loop comes from a stable clock source outside the chip, the frequency period of the voltage-controlled oscillator 11 in the PLL does not change with PVT, and the total delay time in the delay chain circuit does not change with PVT. Once the phase-locked loop is locked, the oscillation frequency of the voltage-controlled oscillator 11 is equal to M times the external reference frequency and does not change with PVT. The oscillation period of the voltage-controlled oscillator 11 is proportional to the delay of the N-stage delay unit. The locked voltage of the PLL will be taken out to control the delay unit of the delay chain circuit.

[0073] like Figure 5 and Figure 6 As shown, the first delay unit 21 and the second delay unit 17 have the same structure, both of which are composed of two stages of controllable inverters in cascade; the third delay unit 18 includes one stage of controllable inverter.

[0074] The voltage-controlled oscillator 11 and the delay chain circuit also include: an error amplifier 31, a first PMOS transistor PM1, a first resistor R1, a second PMOS transistor PM2 and a first NMOS transistor NM1. The first input terminal of the error amplifier 31 is connected to the first control voltage VC or the second control voltage VTRIM, the second input terminal is grounded through the first resistor R1, and the output terminal is connected to the gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2. The source of the first PMOS transistor PM1 is connected to the power supply, and the drain is grounded through the first resistor R1. The source of the second PMOS transistor PM2 is connected to the power supply, and the drain is connected to the drain of the first NMOS transistor NM1. The drain of the first NMOS transistor NM1 is connected to the gate of the first NMOS transistor NM1. The source of the first NMOS transistor NM1 is grounded. The gate of the second PMOS transistor PM2 and the gate of the first NMOS transistor NM1 are respectively connected to each first delay unit 21 or each second delay unit 17 and the third delay unit 18;

[0075] The delay chain circuit further includes a second buffer 32 connected to the output end of the multiplexer 22 .

[0076] The first control voltage VC or the second control voltage VTRIM generates a controllable current VC / R on the first resistor R1 through the error amplifier 31 and the first PMOS transistor PM1. This current is mirrored to each first delay unit 21 or the second delay unit 17 and the third delay unit 18 through the second PMOS transistor PM2 and the first NMOS transistor NM1.

[0077] In this embodiment, the controllable inverter includes: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a second NMOS transistor NM2 and a third NMOS transistor NM3.

[0078] The source of the third PMOS tube PM3 is connected to the power supply, the drain is connected to the source of the fourth PMOS tube PM4, and the gate is connected to the gate of the second PMOS tube PM2. The connecting end of the drain of the fourth PMOS tube PM4 and the drain of the second NMOS tube NM2 is used as an output end. The connecting end of the gate of the fourth PMOS tube PM4 and the gate of the second NMOS tube NM2 is used as an input end. The source of the third NMOS tube NM3 is grounded, the drain is connected to the source of the second NMOS tube NM2, and the gate is connected to the gate of the first NMOS tube NM1.

[0079] In the first delay unit 21 or the second delay unit 17, the two fourth PMOS transistors PM4 and the two second NMOS transistors NM2 form a delay buffer, and the two third PMOS transistors PM3 and the two third NMOS transistors NM3 are controlled by controllable mirror current to change the oscillation frequency through charging and discharging. Figure 5 In the embodiment, the N-stage second delay unit 17 is connected to the third delay unit 18, and the output is fed back to the input of the first-stage second delay unit 17 to form an odd-order ring oscillation circuit. Finally, the output of this circuit is output through the first inverter 15 to output the VCO signal to the frequency divider circuit of the PLL. Figure 6 In, with Figure 5 The delay units have the same structure. Then, the N-stage first delay units 21 delay the input signal, and the multiplexer 22 selects one tap from the N first delay units 21 and reshapes it through the second buffer 32 as the output signal VOUT.

[0080] like Figure 7 and Figure 8 As shown, the first delay unit 21 and the second delay unit 17 have the same structure, both of which are composed of two stages of differential inverters in cascade connection; the third delay unit 18 includes one stage of differential inverter.

[0081] The voltage controlled oscillator 11 and the delay chain circuit both further include: a double-to-single circuit 41 for converting the differential signal output by the third delay unit 18 or the differential signal output by the multiplexer 22 into a single signal.

[0082] The delay chain circuit further includes a third buffer 42 connected to the output end of the double-to-single circuit 41 .

[0083] The differential inverter includes: a variable capacitor C2, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6 and a seventh NMOS transistor NM7.

[0084] The control terminal of the variable capacitor C2 is connected to the first control voltage VC or the second control voltage VTRIM. The source of the fifth PMOS tube PM5 and the sixth PMOS tube PM6 are connected to the power supply. The source of the fourth NMOS tube NM4, the fifth NMOS tube NM5, the sixth NMOS tube NM6 and the seventh NMOS tube NM7 are grounded. The gate of the fifth PMOS tube PM5 and the gate of the fourth NMOS tube NM4 are connected as an input terminal. The gate of the sixth PMOS tube PM6 and the gate of the seventh NMOS tube NM7 are connected as another input terminal. The drain of the fifth PMOS tube PM5, the drain of the fourth NMOS tube NM4, the drain of the fifth NMOS tube NM5, the gate of the sixth NMOS tube NM6 and the first end of the variable capacitor C2 are connected, and the connected ends are used as an output terminal.

[0085] The drain of the sixth PMOS transistor PM6, the drain of the seventh NMOS transistor NM7, the gate of the fifth NMOS transistor NM5, the drain of the sixth NMOS transistor NM6 and the second end of the variable capacitor C2 are connected, and the connected end serves as another output end.

[0086] The double-to-single circuit 41 includes: a seventh PMOS tube PM7, an eighth PMOS tube PM8, an eighth NMOS tube NM8 and a ninth NMOS tube NM9. The source of the seventh PMOS tube PM7 is connected to the power supply, the drain is connected to the drain of the eighth NMOS tube NM8, and the gate is connected to the gate of the eighth PMOS tube PM8 and the drain of the seventh PMOS tube PM7. The source of the eighth PMOS tube PM8 is connected to the power supply. The connecting end of the drain of the eighth PMOS tube PM8 and the drain of the ninth NMOS tube NM9 is used as an output end. The source of the eighth NMOS tube NM8 and the ninth NMOS tube NM9 is grounded. The gate of the eighth NMOS tube NM8 and the gate of the ninth NMOS tube NM9 are used as two input ends.

[0087] The first control voltage VC or the second control voltage VTRIM controls the output capacitance load of the first delay unit 21 or the second delay unit 17 through two variable capacitors C2. The fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the fourth NMOS transistor NM4, and the seventh NMOS transistor NM7 form a differential inverter, and the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 form a latch to regenerate and amplify the output voltage. The oscillation frequency is changed by adjusting the variable capacitor C2 in each stage of the circuit. Figure 7In the circuit, the N-stage second delay unit 17 and the third delay unit 18 are cascaded, and the output is fed back to the input of the first-stage second delay unit 17 to form an odd-order ring oscillation circuit. Finally, the output of this circuit is converted from a differential signal to a single-channel signal through a double-to-single circuit 41, and the VCO signal is output to the frequency divider circuit of the PLL through the first inverter 15. In the double-to-single circuit 41, the two input terminals receive two high-frequency voltage signals with opposite phases, respectively, convert them into currents, add them at the output stage and convert them into voltages. Figure 8 In, with Figure 7 The delay unit structure is the same. The input signal VIN generates an inverted signal through an inverter, and is input to the differential delay link together with its own signal. The N-stage cascaded first delay unit 21 delays the input signal, and the multiplexer 22 selects a differential signal from the taps of the N first delay units 21, outputs it to the double-to-single circuit 41, and then is shaped by the third buffer 42 as the output signal VOUT.

[0088] The present invention is implemented under CMOS technology. Since the PLL circuit is only used to generate a DC correction voltage instead of a high-frequency clock, it can be completed with a smaller area and power consumption. Compared with the traditional technology, the present invention uses a high-frequency phase-locked loop to automatically correct the delay time of the delay link, increase the operating speed of the ADC, improve the linearity and signal-to-noise ratio of the ADC, and increase the yield of mass-produced chips.

[0089] The above embodiments are only used to illustrate the present invention, rather than to limit the present invention. Those skilled in the relevant technical field may make various changes or modifications without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions should also belong to the scope of the present invention and should be defined by the claims.

Claims

1. A delay control circuit for an asynchronous successive approximation analog-to-digital converter, characterized in that: include: Phase-locked loop correction circuit and delay chain circuit, wherein, The phase-locked loop correction circuit includes a voltage-controlled oscillator, and the phase-locked loop correction circuit provides a first control voltage of the voltage-controlled oscillator; The delay chain circuit comprises: A delay chain formed by cascading N stages of first delay units; N ≥ 2 and is a positive integer; A multiplexer connected to the output end of each first delay unit in the delay chain respectively; An input terminal is connected to the first control voltage, and an output terminal is connected to the first buffer of each of the first delay units; and One end is grounded, and the other end is connected to a first capacitor at an output end of the first buffer; The first control voltage, after passing through the first buffer and the first capacitor, generates a second control voltage for controlling the delay time of each of the first delay units.

2. The delay control circuit of the asynchronous successive approximation analog-to-digital converter according to claim 1, characterized in that: The phase-locked loop correction circuit further includes: a phase frequency detector, a charge pump, a loop filter, a first inverter and an M frequency divider, wherein: The frequency detector and phase detector receive a reference frequency; The output end of the frequency and phase detector is connected to the input end of the charge pump; The output end of the charge pump is connected to the loop filter and the voltage controlled oscillator; The loop filter generates the first control voltage and supplies it to the voltage controlled oscillator; The output end of the voltage-controlled oscillator is connected to the input end of the phase frequency detector through the first inverter and the M frequency divider in sequence.

3. The delay control circuit of the asynchronous successive approximation analog-to-digital converter according to claim 2, characterized in that: The voltage-controlled oscillator comprises: N stages of second delay units cascaded with each other, and a third delay unit cascaded with the last stage of second delay units and outputting feedback to the first stage of second delay units; N≥2 and is a positive integer; The delay time of the second delay unit is twice the delay time of the third delay unit; The first control voltage is supplied to each of the second delay unit and the third delay unit respectively.

4. The delay control circuit of the asynchronous successive approximation analog-to-digital converter according to claim 3, characterized in that: The first delay unit and the second delay unit have the same structure, both consisting of two stages of controllable inverters in cascade connection; the third delay unit includes a single stage of controllable inverter; The voltage-controlled oscillator and the delay chain circuit both further include: an error amplifier, a first PMOS tube, a first resistor, a second PMOS tube and a first NMOS tube, wherein a first input terminal of the error amplifier is connected to the first control voltage or the second control voltage, a second input terminal is grounded through the first resistor, and an output terminal is connected to the gate of the first PMOS tube and the gate of the second PMOS tube; The source of the first PMOS tube is connected to a power supply, and the drain is grounded through the first resistor; The source of the second PMOS tube is connected to a power supply, and the drain is connected to the drain of the first NMOS tube; The drain of the first NMOS tube is connected to the gate of the first NMOS tube; The source of the first NMOS tube is grounded; The gate of the second PMOS tube and the gate of the first NMOS tube are respectively connected to each of the first delay units or each of the second delay unit and the third delay unit; The delay chain circuit further includes a second buffer connected to the output end of the multiplexer.

5. The delay control circuit of the asynchronous successive approximation analog-to-digital converter according to claim 3, characterized in that: The first delay unit and the second delay unit have the same structure, both consisting of two stages of differential inverters in cascade connection; the third delay unit includes a single stage of differential inverter; The voltage-controlled oscillator and the delay chain circuit both further include: a double-to-single circuit for converting the differential signal output by the third delay unit or the differential signal output by the multiplexer into a single-channel signal; The delay chain circuit further includes: a third buffer connected to the output end of the double-to-single circuit.

6. The delay control circuit of the asynchronous successive approximation analog-to-digital converter according to claim 4, characterized in that: The controllable inverter includes: a third PMOS tube, a fourth PMOS tube, a second NMOS tube and a third NMOS tube, wherein: The source of the third PMOS tube is connected to a power supply, the drain is connected to the source of the fourth PMOS tube, and the gate is connected to the gate of the second PMOS tube; The connected end of the drain of the fourth PMOS tube and the drain of the second NMOS tube serves as an output end; The connecting end of the gate of the fourth PMOS tube and the gate of the second NMOS tube is used as an input end; The source of the third NMOS tube is grounded, the drain is connected to the source of the second NMOS tube, and the gate is connected to the gate of the first NMOS tube.

7. The delay control circuit of the asynchronous successive approximation analog-to-digital converter according to claim 5, characterized in that: The differential inverter includes: a variable capacitor, a fifth PMOS transistor, a sixth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor, wherein: The control terminal of the variable capacitor is connected to the first control voltage or the second control voltage; The source electrodes of the fifth PMOS tube and the sixth PMOS tube are respectively connected to a power source; The source electrodes of the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube and the seventh NMOS tube are respectively grounded; The connected end of the gate of the fifth PMOS tube and the gate of the fourth NMOS tube serves as an input end; The connecting end of the gate of the sixth PMOS tube and the gate of the seventh NMOS tube serves as another input end; The drain of the fifth PMOS tube, the drain of the fourth NMOS tube, the drain of the fifth NMOS tube, the gate of the sixth NMOS tube and the first end of the variable capacitor are connected, and the connected end serves as an output end; The drain of the sixth PMOS tube, the drain of the seventh NMOS tube, the gate of the fifth NMOS tube, the drain of the sixth NMOS tube and the second end of the variable capacitor are connected, and the connected end serves as another output end.

8. The delay control circuit of the asynchronous successive approximation analog-to-digital converter according to claim 5, characterized in that: The double-to-single circuit includes: a seventh PMOS tube, an eighth PMOS tube, an eighth NMOS tube and a ninth NMOS tube, wherein: The source of the seventh PMOS tube is connected to a power supply, the drain is connected to the drain of the eighth NMOS tube, and the gate is connected to the gate of the eighth PMOS tube and the drain of the seventh PMOS tube; The source of the eighth PMOS tube is connected to a power supply; The connected end of the drain of the eighth PMOS tube and the drain of the ninth NMOS tube serves as an output end; The source electrodes of the eighth NMOS tube and the ninth NMOS tube are respectively grounded; The gate of the eighth NMOS tube and the gate of the ninth NMOS tube serve as two input terminals.

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