Heterojunction solar cell and method for manufacturing the same

Abstract

The present invention relates to a method for manufacturing a heterojunction solar cell and a heterojunction solar cell. The heterojunction solar cell comprises a single crystal silicon wafer, a tunneling layer, an N-type passivation layer, a P-type passivation layer and a light-transmitting conductive layer. The tunneling layer is arranged on the bottom surface of the single crystal silicon wafer; the N-type passivation layer is arranged on the bottom surface of the tunneling layer; the P-type passivation layer is arranged on the top surface of the single crystal silicon wafer; and the light-transmitting conductive layer is arranged on the top surface of the P-type passivation layer. In the present invention, the two technologies of passivation contact and heterojunction are combined, which not only retains the low-cost characteristics of passivation contact but also has the advantages of high efficiency and simple process of heterojunction cells. In addition, in the preparation process of the present invention, doped polycrystalline silicon is first prepared on the bottom surface of the single crystal silicon wafer and then an amorphous silicon film is prepared on the top surface, thereby effectively avoiding the problem of phosphorus plating on the bottom surface to the top surface, causing the battery to short-circuit or fail.

Description

Technical Field

[0001] The present invention relates to the field of energy, and in particular to a heterojunction solar cell and a manufacturing method thereof. Background Art

[0002] With the accelerated consumption of conventional fossil energy such as coal, oil and natural gas, the ecological environment is deteriorating, especially the increasingly severe global climate change caused by greenhouse gas emissions, and the sustainable development of human society has been seriously threatened. Countries around the world have formulated their own energy development strategies to cope with the limited resources of conventional fossil energy and the environmental problems caused by its development and utilization. Solar energy has become one of the most important renewable energy sources due to its reliability, safety, extensiveness, longevity, environmental protection and sufficient resources, and is expected to become the main pillar of global electricity supply in the future.

[0003] In the new round of energy transformation, my country's photovoltaic industry has grown into a strategic emerging industry with international competitive advantages. However, the development of the photovoltaic industry still faces many problems and challenges. Conversion efficiency and reliability are the biggest technical obstacles to the development of the photovoltaic industry, while cost control and scale have formed economic constraints.

[0004] At present, heterojunction solar cells are known as the next generation of ultra-high efficiency solar cell technology with the greatest industrialization potential due to a series of advantages such as high conversion efficiency, short manufacturing process, thin silicon wafers, low temperature coefficient, no light-induced degradation, double-sided power generation and high double-sided rate. However, it is also difficult to achieve large-scale development of solar cell technology: on the one hand, the manufacturing cost of heterojunction solar cells is relatively high, and on the other hand, when solar cells are packaged using conventional packaging technology, the stability of the tension of the welding ribbon is difficult to control, and some solar cells cannot adopt the high-temperature welding process of traditional crystalline silicon cells, and require low-temperature welding process and low-temperature materials, so the packaging process is more difficult.

[0005] In order to compensate for the above defects, other high-efficiency crystalline silicon solar cells can be used instead of heterojunction solar cells in some scenarios.

[0006] In recent years, various new crystalline silicon technologies have emerged one after another. Currently, PERC solar cells are the main ones in the market, and the mainstream production efficiency can exceed 22%. However, the conversion efficiency of PERC solar cells will be subject to more restrictions. At present, a new type of passivation contact structure can increase the cell conversion efficiency to more than 23% by superimposing 2-3 processes on the existing PERC technology. Passivation contact technology is increasingly favored by the market and various research institutions due to its strong compatibility with existing PERC technology.

[0007] On the one hand, the existing passivation contact technology for ordinary crystalline silicon solar cells is based on first preparing a silicon dioxide tunneling layer on the back of the N-crystalline silicon and then preparing an N-type polysilicon passivation film. However, the process of depositing the doped polysilicon film can easily cause the PN junction on the front to be plated around, resulting in a short circuit or failure of the battery, and an additional cleaning process is required.

[0008] On the other hand, although the existing heterojunction technology has a simple preparation process, the equipment cost for manufacturing amorphous silicon thin films is high, and the corresponding transparent conductive films are expensive, which hinders the industrial development of these two technologies.

[0009] Therefore, it is necessary to provide a novel heterojunction solar cell and a method for manufacturing the same to at least partially solve the above problems. Summary of the invention

[0010] The purpose of the present invention is to provide a heterojunction solar cell with a passivation contact structure and a method for manufacturing the same, which combines the two technologies of passivation contact and heterojunction, retaining the low-cost characteristics of the passivation contact while also having the advantages of high efficiency and simple process of the heterojunction cell.

[0011] Furthermore, in the preparation process of the present invention, doped polysilicon is first prepared on the bottom surface of the single crystal silicon wafer and then an amorphous silicon film is prepared on the top surface, thereby effectively avoiding the problem of phosphorus from the bottom surface being plated around to the top surface, causing battery short circuit or failure.

[0012] At the same time, the heterojunction solar cell provided by the present invention is highly compatible with the traditional P-type PERC cell and has practical application prospects; the heterojunction solar cell sheet provided by the present invention has a relatively simple structure and is easy to produce and manufacture, and the manufacturing method provided by the present invention has a simple process route and is easy to implement.

[0013] According to one aspect of the present invention, a heterojunction solar cell is provided, the heterojunction solar cell comprising a substrate sheet and grid lines arranged on the top surface and the bottom surface of the substrate sheet, the substrate sheet comprising:

[0014] Monocrystalline silicon wafer;

[0015] A tunneling layer, wherein the tunneling layer is disposed on the bottom surface of the single crystal silicon wafer;

[0016] An N-type passivation layer, the N-type passivation layer being disposed on the bottom surface of the tunneling layer;

[0017] A P-type passivation layer, the P-type passivation layer being disposed on the top surface of the single crystal silicon wafer;

[0018] A light-transmitting conductive layer is disposed on the top surface of the amorphous silicon thin film layer.

[0019] In one embodiment, the P-type passivation layer includes an intrinsic thin film layer disposed on the top surface of the single crystal silicon wafer and a P-type thin film layer disposed on the top surface of the intrinsic thin film layer.

[0020] In one embodiment, the intrinsic thin film layer is one of an intrinsic amorphous silicon thin film layer, an intrinsic microcrystalline silicon thin film layer and an intrinsic nanosilicon thin film layer, and the P-type thin film layer is one of a P-type amorphous silicon thin film layer, a P-type microcrystalline silicon thin film layer and a P-type nanosilicon thin film layer.

[0021] In one embodiment, the N-type passivation layer includes at least one of doped polysilicon, doped silicon carbide, and doped silicon oxide.

[0022] In one embodiment, the thickness of the P-type amorphous silicon thin film layer is 2nm-40nm.

[0023] In one embodiment, an anti-reflection film is further included on the bottom surface of the N-type passivation layer.

[0024] In one embodiment, the anti-reflection film is a silicon nitride anti-reflection film or a silicon oxynitride anti-reflection film, and the thickness of the anti-reflection film is 70nm-200nm.

[0025] In one embodiment, the tunneling layer is a silicon dioxide tunneling layer, and the thickness of the silicon dioxide tunneling layer is 0.8 nm-3 nm.

[0026] In one embodiment, the light-transmitting conductive layer includes at least one of an indium tin oxide layer, a tungsten-doped indium oxide layer, an indium zinc oxide layer, and a zinc aluminum oxide layer.

[0027] In one embodiment, the thickness of the N-type passivation layer is 20 nm-300 nm.

[0028] In one embodiment, the light-transmitting conductive layer is a multi-layer structure, each of the light-transmitting conductive layers is stacked on the top surface of the amorphous silicon thin film layer, and the light transmittance of each of the light-transmitting conductive layers increases gradually in the direction from the amorphous silicon thin film layer to the top side gate line of the substrate.

[0029] Another aspect of the present invention provides a manufacturing method for manufacturing a heterojunction solar cell, the method comprising providing a substrate sheet and applying grid lines on the top surface and the bottom surface of the substrate sheet, the step of providing the substrate sheet sequentially comprising the following steps:

[0030] Setting a single crystal silicon wafer;

[0031] Disposing a tunneling layer on the bottom surface of the single crystal silicon wafer;

[0032] Disposing an N-type passivation layer on the bottom surface of the silicon dioxide tunneling layer;

[0033] Etching the edge and top surface of the single crystal silicon wafer to remove phosphorus thereon;

[0034] Disposing a P-type passivation layer on the top surface of the single crystal silicon wafer;

[0035] A light-transmitting conductive layer is disposed on the P-type passivation layer.

[0036] In one embodiment, the single crystal silicon wafer is a P-type silicon wafer or an N-type silicon wafer, and the step of setting the single crystal silicon wafer includes: cleaning and texturing the single crystal silicon wafer with a sodium hydroxide or potassium hydroxide solution to remove metal ions on its surface and cut the damaged layer and form a pyramid texture surface on its surface.

[0037] In one embodiment, the step of providing a P-type passivation layer on the top surface of the single crystal silicon wafer comprises:

[0038] Disposing an intrinsic thin film layer on the top surface of the single crystal silicon wafer, wherein the intrinsic thin film layer is one of an intrinsic amorphous silicon thin film layer, an intrinsic microcrystalline silicon thin film layer and an intrinsic nano silicon thin film layer;

[0039] A P-type thin film layer is disposed on the top surface of the intrinsic thin film layer, and the P-type thin film layer is one of a P-type amorphous silicon thin film layer, a P-type microcrystalline silicon thin film layer, and a P-type nano-silicon thin film layer.

[0040] In one embodiment, the step of setting the P-type passivation layer includes: preparing the P-type passivation layer using at least one of an LPCVD method, a PECVD method, an ion implantation method, a thermal diffusion method, an ALD method, a thermal oxidation method, and an evaporation method, and making the thickness of the P-type passivation layer 2nm-40nm.

[0041] In one embodiment, the step of etching the edge and top surface of the single crystal silicon wafer is achieved by chemical wet etching and / or dry etching method.

[0042] In one embodiment, the method further comprises the following step: disposing an anti-reflection film on the bottom surface of the N-type passivation layer.

[0043] In one embodiment, the anti-reflection film is a silicon nitride anti-reflection film or a silicon oxynitride anti-reflection film, and the anti-reflection film is disposed by a PECVD method, and the thickness of the anti-reflection film is formed to be 70nm-200nm.

[0044] In one embodiment, the tunneling layer is a silicon dioxide tunneling layer, and the step of providing the silicon dioxide tunneling layer includes: preparing the silicon dioxide tunneling layer by at least one of thermal oxidation, ozone, wet oxidation and ALD methods, so that the thickness of the silicon dioxide tunneling layer is 0.8nm-3nm.

[0045] In one embodiment, the step of providing a light-transmitting conductive layer is achieved by magnetron sputtering or ordinary physical plating, and the light-transmitting conductive layer includes at least one of an indium tin oxide layer, a tungsten-doped indium oxide layer, an indium zinc oxide layer, and a zinc aluminum oxide layer.

[0046] In one embodiment, the step of setting the N-type passivation layer includes: preparing the N-type passivation layer using at least one of an LPCVD method, a PECVD method, an ion implantation method, a thermal diffusion method, an ALD method, a thermal oxidation method, and an evaporation method, so that the thickness of the N-type passivation layer is 20nm-300nm.

[0047] The present invention combines the two technologies of passivation contact and heterojunction, which not only retains the low-cost characteristics of passivation contact but also has the advantages of high efficiency and simple process of heterojunction cells. In addition, in the preparation process, the doped polysilicon on the bottom surface of the single-crystal silicon wafer is first prepared, and then the amorphous silicon film on the top surface is prepared, so as to effectively avoid the problem of phosphorus from the bottom surface being plated to the top surface, causing the battery to short-circuit or fail. At the same time, the heterojunction solar cell provided by the present invention is highly compatible with the traditional P-type PERC cell and has practical application prospects; the heterojunction solar cell provided by the present invention has a relatively simple structure and is easy to produce and manufacture, and the manufacturing method provided by the present invention has a simple process route and is easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to better understand the above and other purposes, features, advantages and functions of the present invention, reference may be made to the preferred embodiments shown in the accompanying drawings. The same reference numerals in the accompanying drawings refer to the same components. It should be understood by those skilled in the art that the accompanying drawings are intended to schematically illustrate the preferred embodiments of the present invention and have no limiting effect on the scope of the present invention, and the components in the drawings are not drawn to scale.

[0049] Figure 1 A top view of a heterojunction solar cell according to a preferred embodiment of the present invention;

[0050] Figure 2 for Figure 1 A schematic diagram showing a cross-sectional view taken along line AA rotated 90° clockwise.

[0051] Figure 3 The figure is a flow chart of a manufacturing method according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0052] Now, with reference to the accompanying drawings, the specific embodiments of the present invention are described in detail. What is described here is only the preferred embodiment of the present invention, and those skilled in the art can think of other ways to implement the present invention based on the preferred embodiment, and the other ways also fall within the scope of the present invention.

[0053] The invention provides a heterojunction solar cell sheet and a manufacturing method thereof. Figure 1 FIG. 2 shows a schematic diagram of a heterojunction solar cell according to a preferred embodiment of the present invention. Figure 3 A schematic diagram of the manufacturing method.

[0054] like Figure 1 As shown, the solar cell 1 includes a substrate and grid lines arranged on the top and bottom surfaces of the substrate. Figure 2 The substrate includes a single crystal silicon wafer 2, an intrinsic amorphous silicon thin film layer 3, a P-type amorphous silicon thin film layer 4, a tunneling layer 6, an N-type passivation layer 7 and a light-transmitting conductive layer 10. The gate line includes a secondary gate line and a main gate line, which can be made of one or more metals such as silver, gold, copper, aluminum, and nickel. Figure 2 , a top-side auxiliary grid line 8 located on the top side of the substrate sheet and a bottom-side auxiliary grid line 9 located on the bottom side of the substrate sheet are shown.

[0055] Among them, the single crystal silicon wafer 2 can be a P-type silicon wafer or an N-type silicon wafer, and the thickness of the single crystal silicon wafer 2 is 100μm-220μm. The intrinsic amorphous silicon film layer 3 and the P-type amorphous silicon film layer 4 on the top surface of the single crystal silicon wafer 2 together form a P-type passivation layer in this embodiment, but in other embodiments not shown, the P-type passivation layer may also include other structures in addition to the intrinsic amorphous silicon film layer and the P-type amorphous silicon film layer. In addition, in other embodiments not shown, the intrinsic amorphous silicon film layer 3 can be replaced by an intrinsic microcrystalline silicon film layer or an intrinsic nanosilicon film layer; the P-type amorphous silicon film layer 4 can be replaced by a P-type microcrystalline silicon film layer or a P-type nanosilicon film layer. Preferably, in this embodiment, the thickness of the P-type passivation layer is approximately 2nm-40nm.

[0056] The light-transmitting conductive layer 10 is located on the top surface of the P-type amorphous silicon thin film layer 4. Preferably, the light-transmitting conductive layer 10 includes at least one of an indium tin oxide layer, a tungsten-doped indium oxide layer, an indium zinc oxide layer, and a zinc aluminum oxide layer, that is, the light-transmitting conductive layer 10 can be a single layer or a stack of an indium tin oxide layer, a tungsten-doped indium oxide layer, an indium zinc oxide layer, and a zinc aluminum oxide layer.

[0057] Preferably, the light-transmitting conductive layer may be a multilayer structure, wherein a plurality of light-transmitting conductive layers are stacked on the top surface of the P-type amorphous silicon thin film layer 4, and the light transmittance of each of the light-transmitting conductive layers increases in the direction from the P-type amorphous silicon thin film layer 4 to the top side auxiliary grid line 8. Such a configuration can improve the carrier shift rate, light transmittance and conductivity of the heterojunction solar cell, avoid the occurrence of problems such as low fill factor and low open-circuit current, and enable the heterojunction solar cell to have a higher photoelectric conversion rate.

[0058] The tunneling layer 6 is disposed on the bottom surface of the single crystal silicon wafer 2. In this embodiment, the tunneling layer 6 is a silicon dioxide tunneling layer. Preferably, the thickness of the tunneling layer 6 is approximately 0.8 nm-3 nm.

[0059] The N-type passivation layer 7 is disposed on the bottom surface of the tunneling layer 6, and the N-type passivation layer 7 is a boron-doped passivation layer, which can protect the tunneling layer 6 and can provide a passivation effect on the heterojunction solar cell 1. The N-type passivation layer 7 is preferably a boron-doped polysilicon passivation layer, a silicon carbide passivation layer or a silicon oxide passivation layer. Alternatively, the N-type passivation layer 7 can also be a boron-doped amorphous silicon passivation layer or a boron-doped microcrystalline silicon passivation layer. The thickness of the N-type passivation layer 7 can be, for example, 20nm-300nm.

[0060] Preferably, an anti-reflection film 5 may be further provided on the bottom surface of the N-type passivation layer 7. The anti-reflection film 5 may be made of, for example, silicon nitride or silicon oxynitride, and the thickness of the anti-reflection film 5 may be, for example, 70 nm-200 nm.

[0061] On the other hand, this embodiment also provides a method for manufacturing a heterojunction solar cell 1. Figure 3 The method comprises the following steps S1 to S5 in sequence.

[0062] S1 is a pre-processing step. This step also includes sub-steps S11 and S12 ( Figure 3 not shown).

[0063] S11 is a step of setting a single crystal silicon wafer. In this step, the single crystal silicon wafer can be cleaned and textured with a sodium hydroxide or potassium hydroxide solution to remove metal ions and cutting damage layers on the surface of the single crystal silicon wafer and form a pyramid texture surface, the size of which is, for example, 1 μm-10 μm.

[0064] S12 is a step of providing a tunneling layer on the bottom surface of the single crystal silicon wafer, and the tunneling layer may be a silicon dioxide tunneling layer. This step may be implemented by a PECVD method, an ALD method, an LPCVD method, a thermal oxidation method, an evaporation method or a PEALD method, and the tunneling layer may be provided to have a thickness of 0.8 nm to 3 nm.

[0065] S2 is a step of setting a boron-doped N-type passivation layer on the bottom surface of the tunneling layer. This step is implemented by at least one of an LPCVD method, a PECVD method, an ion implantation method, a thermal diffusion method, an ALD method, a thermal oxidation method, and an evaporation method, and the N-type passivation layer 7 is set to have a thickness of 20nm-300nm. Preferably, a boron-doped polysilicon thin film layer can be set as the N-type passivation layer, or a boron-doped amorphous silicon thin film layer or a boron-doped microcrystalline thin film layer can be set as the N-type passivation layer.

[0066] S3 is a step of etching the edge and top surface of the single crystal silicon wafer 2. This step can remove the phosphorus plated on the edge and top surface of the single crystal silicon wafer 2 by dry or wet method. This step can be implemented by chemical wet and / or dry etching method.

[0067] S4 is a step of providing a P-type passivation layer on the top surface of the single crystal silicon wafer. This step also includes sub-steps S41 and S42 ( Figure 3 S41 is a step of providing an intrinsic amorphous silicon thin film layer (or an intrinsic microcrystalline silicon thin film layer or an intrinsic nano-silicon thin film layer) on the top surface of the single crystal silicon wafer. S42 is a step of providing a P-type amorphous silicon thin film layer (or a P-type microcrystalline silicon thin film layer or a P-type nano-silicon thin film layer) on the top surface of the intrinsic amorphous silicon thin film layer, in which the P-type amorphous silicon thin film layer is prepared by at least one of an LPCVD method, a PECVD method, an ion implantation method, a thermal diffusion method, an ALD method, a thermal oxidation method, and an evaporation method, and the thickness of the P-type passivation layer is 2nm-40nm.

[0068] S5 is a subsequent processing step, which may include sub-steps S51, S52 and S53 (not shown in FIG. 3).

[0069] S51 is a step of providing an anti-reflection film on the bottom surface of the N-type passivation layer. This step may include: providing a silicon nitride anti-reflection film by using a PECVD method, and forming the silicon nitride anti-reflection film to a thickness of 70 nm to 200 nm.

[0070] S52 is a step of providing a light-transmitting conductive layer. The step of providing a light-transmitting conductive layer is implemented by magnetron sputtering or ordinary physical plating, and the light-transmitting conductive layer includes at least one of an indium tin oxide layer, a tungsten-doped indium oxide layer, an indium zinc oxide layer, and a zinc aluminum oxide layer.

[0071] S53 is, for example, a step of printing grid lines, or a step of printing electrodes. In this step, the main grid lines and the auxiliary grid lines can be printed on the top and bottom surfaces of the substrate sheet using one or more of silver, gold, copper, aluminum, and nickel. Figure 2 The gate lines shown in FIG. 1 are auxiliary gate lines.

[0072] In the structure and method of the present invention, the two technologies of passivation contact and heterojunction are combined, which not only retains the low-cost characteristics of passivation contact but also has the advantages of high efficiency and simple process of heterojunction batteries.

[0073] Furthermore, in the preparation process, doped polysilicon is first prepared on the bottom surface of the single crystal silicon wafer and then an amorphous silicon film is prepared on the top surface, thereby effectively avoiding the problem of phosphorus from the bottom surface being plated around to the top surface, causing a short circuit or failure of the battery.

[0074] At the same time, the heterojunction solar cell provided by the present invention is highly compatible with the traditional P-type PERC cell and has practical application prospects; the heterojunction solar cell sheet provided by the present invention has a relatively simple structure and is easy to produce and manufacture, and the manufacturing method provided by the present invention has a simple process route and is easy to implement.

[0075] The above description of various embodiments of the present invention is provided to one of ordinary skill in the relevant art for the purpose of description. It is not intended that the present invention be exclusive or limited to a single disclosed embodiment. As mentioned above, a person of ordinary skill in the field of the above teachings will understand the various substitutions and variations of the present invention. Therefore, although some alternative embodiments are specifically described, a person of ordinary skill in the art will understand or relatively easily develop other embodiments. The present invention is intended to include all substitutions, modifications and variations of the present invention described herein, as well as other embodiments that fall within the spirit and scope of the present invention described above.

[0076] Reference numerals:

[0077] Heterojunction solar cell1

[0078] Monocrystalline silicon wafer 2

[0079] Intrinsic amorphous silicon thin film layer 3

[0080] P-type amorphous silicon thin film layer 4

[0081] Anti-reflection film 5

[0082] Tunneling layer 6

[0083] N-type passivation layer 7

[0084] Top side secondary grid line 8

[0085] Bottom side secondary grid line 9

[0086] The light-transmitting conductive layer 10 .

Claims

1. A heterojunction solar cell, characterized in that: The heterojunction solar cell comprises a substrate sheet and grid lines arranged on the top surface and the bottom surface of the substrate sheet, wherein the substrate sheet comprises: Monocrystalline silicon wafer; A tunneling layer, wherein the tunneling layer is disposed on the bottom surface of the single crystal silicon wafer; An N-type passivation layer, the N-type passivation layer being disposed on the bottom surface of the tunneling layer; A P-type passivation layer, the P-type passivation layer being disposed on the top surface of the single crystal silicon wafer; a light-transmitting conductive layer, the light-transmitting conductive layer being disposed on a top surface of the P-type passivation layer; The steps of arranging the substrate sheet in the heterojunction solar cell include: Setting a single crystal silicon wafer; Disposing a tunneling layer on the bottom surface of the single crystal silicon wafer; Disposing an N-type passivation layer on the bottom surface of the tunneling layer; Etching the edge and top surface of the single crystal silicon wafer to remove phosphorus thereon; Disposing a P-type passivation layer on the top surface of the single crystal silicon wafer; A light-transmitting conductive layer is disposed on the P-type passivation layer.

2. The heterojunction solar cell according to claim 1, characterized in that: The P-type passivation layer includes an intrinsic thin film layer disposed on a top surface of the single crystal silicon wafer and a P-type thin film layer disposed on a top surface of the intrinsic thin film layer.

3. The heterojunction solar cell according to claim 2, characterized in that: The intrinsic film layer is one of an intrinsic amorphous silicon film layer, an intrinsic microcrystalline silicon film layer and an intrinsic nanosilicon film layer, and the P-type film layer is one of a P-type amorphous silicon film layer, a P-type microcrystalline silicon film layer and a P-type nanosilicon film layer.

4. The heterojunction solar cell according to claim 1, characterized in that: The N-type passivation layer includes at least one of doped polysilicon, doped silicon carbide, and doped silicon oxide.

5. The heterojunction solar cell according to claim 1, characterized in that: The thickness of the P-type passivation layer is 2nm-40nm.

6. The heterojunction solar cell according to claim 1, characterized in that: An anti-reflection film is also included on the bottom surface of the N-type passivation layer.

7. The heterojunction solar cell according to claim 6, characterized in that: The anti-reflection film is a silicon nitride anti-reflection film or a silicon oxynitride anti-reflection film, and the thickness of the anti-reflection film is 70nm-200nm.

8. The heterojunction solar cell according to claim 1, characterized in that: The tunneling layer is a silicon dioxide tunneling layer, and the thickness of the silicon dioxide tunneling layer is 0.8 nm-3 nm.

9. The heterojunction solar cell according to claim 1, characterized in that: The light-transmitting conductive layer includes at least one of an indium tin oxide layer, a tungsten-doped indium oxide layer, an indium zinc oxide layer, and a zinc aluminum oxide layer.

10. The heterojunction solar cell according to claim 1, characterized in that: The thickness of the N-type passivation layer is 20nm-300nm.

11. The heterojunction solar cell according to claim 3, characterized in that: The light-transmitting conductive layer is a multi-layer structure, each of which is stacked on the top surface of the P-type amorphous silicon thin film layer, and the light transmittance of each of the light-transmitting conductive layers increases gradually in the direction from the P-type amorphous silicon thin film layer to the top side gate line of the substrate.

12. A manufacturing method for manufacturing a heterojunction solar cell, the method comprising providing a substrate sheet and applying grid lines on the top surface and the bottom surface of the substrate sheet, characterized in that: The step of setting the substrate sheet comprises the following steps in sequence: Setting a single crystal silicon wafer; Disposing a tunneling layer on the bottom surface of the single crystal silicon wafer; Disposing an N-type passivation layer on the bottom surface of the tunneling layer; Etching the edge and top surface of the single crystal silicon wafer to remove phosphorus thereon; Disposing a P-type passivation layer on the top surface of the single crystal silicon wafer; A light-transmitting conductive layer is disposed on the P-type passivation layer.

13. The method according to claim 12, characterized in that The single crystal silicon wafer is a P-type silicon wafer or an N-type silicon wafer, and the step of setting the single crystal silicon wafer includes: cleaning and texturing the single crystal silicon wafer with a sodium hydroxide or potassium hydroxide solution to remove metal ions on its surface and cut the damaged layer and form a pyramid texture surface on its surface.

14. The method according to claim 12, characterized in that The step of providing a P-type passivation layer on the top surface of the single crystal silicon wafer comprises: Disposing an intrinsic thin film layer on the top surface of the single crystal silicon wafer, wherein the intrinsic thin film layer is one of an intrinsic amorphous silicon thin film layer, an intrinsic microcrystalline silicon thin film layer and an intrinsic nano silicon thin film layer; A P-type thin film layer is disposed on the top surface of the intrinsic thin film layer, and the P-type thin film layer is one of a P-type amorphous silicon thin film layer, a P-type microcrystalline silicon thin film layer, and a P-type nano-silicon thin film layer.

15. The method according to claim 14, characterized in that The step of setting the P-type passivation layer includes: preparing the P-type passivation layer by using at least one of LPCVD method, PECVD method, ion implantation method, thermal diffusion method, ALD method, thermal oxidation method and evaporation method, and making the thickness of the P-type passivation layer 2nm-40nm.

16. The method according to claim 12, characterized in that The step of etching the edge and top surface of the single crystal silicon wafer is achieved by chemical wet etching and / or dry etching method.

17. The method according to claim 12, characterized in that The method further comprises the step of: disposing an anti-reflection film on the bottom surface of the N-type passivation layer.

18. The method according to claim 17, characterized in that The anti-reflection film is a silicon nitride anti-reflection film or a silicon oxynitride anti-reflection film, and the step of providing the anti-reflection film is achieved by a PECVD method, and the thickness of the anti-reflection film is formed to be 70nm-200nm.

19. The method according to claim 12, characterized in that The tunneling layer is a silicon dioxide tunneling layer, and the step of providing the silicon dioxide tunneling layer includes: preparing the silicon dioxide tunneling layer by using at least one of thermal oxidation, ozone, wet oxidation and ALD methods, so that the thickness of the silicon dioxide tunneling layer is 0.8nm-3nm.

20. The method according to claim 12, characterized in that The step of providing a light-transmitting conductive layer is achieved by magnetron sputtering or ordinary physical plating, and the light-transmitting conductive layer includes at least one of an indium tin oxide layer, a tungsten-doped indium oxide layer, an indium zinc oxide layer, and a zinc aluminum oxide layer.

21. The method according to claim 12, characterized in that The step of setting the N-type passivation layer includes: preparing the N-type passivation layer by at least one of LPCVD method, PECVD method, ion implantation method, thermal diffusion method, ALD method, thermal oxidation method and evaporation method, so that the thickness of the N-type passivation layer is 20nm-300nm.

Images