Chip sealing ring structure and preparation method thereof, semiconductor chip and preparation method thereof

Abstract

The present invention provides a chip sealing ring structure and a preparation method thereof, a semiconductor chip and a preparation method thereof, wherein the preparation method of the chip sealing ring structure comprises: providing a chip, wherein a bottom protective layer is formed on the active surface of the chip; forming a sealing ring metal layer pattern on the bottom protective layer, wherein the sealing ring metal layer pattern is located around the active surface of the chip; forming an insulating dielectric layer on the bottom protective layer, wherein the insulating dielectric layer has an isolation opening for exposing the sealing ring metal layer pattern, wherein the isolation opening also exposes the bottom protective layer; forming a moisture-proof layer on the insulating dielectric layer and in the isolation opening, wherein the moisture-proof layer covers a first exposed portion of the sealing ring metal layer pattern and a second exposed portion of the bottom protective layer in the isolation opening. The present invention forms a moisture-proof layer on the surface of the sealing ring metal layer pattern, which can effectively prevent the metal layer from being directly exposed to the air during the manufacturing process and being oxidized or corroded by oxygen, water vapor or other gas and liquid, thereby greatly enhancing the gas-liquid barrier capability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip sealing ring structure and a preparation method thereof, a semiconductor chip and a preparation method thereof. Background Art

[0002] Since silicon materials are brittle, when the wafer is cut, the cutting method of the cutting knife will generate certain mechanical stress on the front and back of the wafer, which may cause chipping at the edge of the chip. The chipping problem will reduce the mechanical strength of the chip. The initial chip edge cracks will further spread in the subsequent packaging process or in the use of the chip product, which is likely to cause the chip to break, resulting in electrical failure of the chip. In order to protect the internal circuit of the chip, prevent dicing damage, and improve chip reliability, a chip seal ring (SR) structure is usually designed around the chip. Figure 1 As shown, the chip sealing ring structure includes a sealing ring metal layer pattern 12 between the scribe lane (SL) 20 of the wafer and the periphery region (PR) of the chip 10. When the wafer cutting process is performed along the scribe lane, the chip sealing ring structure can block the unwanted stress expansion and cracking from the scribe lane to the chip caused by the above-mentioned wafer cutting process. In addition, the chip sealing ring structure also has the ability to resist gas and liquid erosion, and can prevent the penetration and damage of water vapor or other chemical pollution sources. In today's semiconductor technology, the size of semiconductor components has been miniaturized, which puts higher requirements on the crack blocking ability and gas and liquid shielding ability of the chip sealing ring. In the existing process, the metal layer is directly exposed to the air during the process and will be oxidized or corroded by oxygen, water vapor or other gas and liquid. The existing chip sealing ring structure mainly blocks oxygen to prevent the metal layer from being oxidized, but has poor resistance to erosion by water vapor or other gas and liquid, so that the electrical properties and reliability of the chip will be affected. Therefore, how to enhance the gas-liquid barrier capability of the chip sealing ring structure without reducing the ability to block stress expansion is an urgent problem to be solved. Summary of the invention

[0003] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a chip sealing ring structure and a preparation method thereof, a semiconductor chip and a preparation method thereof, so as to solve the problem that the chip sealing ring structure in the prior art has poor resistance to gas and liquid corrosion, resulting in the electrical properties and reliability of the chip being affected.

[0004] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a chip sealing ring structure, wherein the method for preparing a chip sealing ring structure comprises at least the following steps:

[0005] Providing a chip, wherein a bottom protection layer is formed on an active surface of the chip;

[0006] forming a sealing ring metal layer pattern on the bottom protection layer, wherein the sealing ring metal layer pattern is located around the active surface of the chip;

[0007] forming an insulating dielectric layer on the bottom protective layer, wherein the insulating dielectric layer has an isolation opening, and the isolation opening exposes the sealing ring metal layer pattern and the bottom protective layer;

[0008] forming a moisture-proof layer on the insulating dielectric layer and in the isolation opening, wherein the moisture-proof layer covers a first exposed portion of the sealing ring metal layer pattern and a second exposed portion of the bottom protection layer in the isolation opening;

[0009] The chip sealing ring structure enhances the gas-liquid barrier capability by covering the moisture-proof layer on the sealing ring metal layer pattern, thereby preventing the sealing ring metal layer pattern from being oxidized or corroded by gas and liquid.

[0010] Preferably, the process of forming the insulating dielectric layer on the bottom protective layer includes:

[0011] forming a temporary insulating dielectric layer on the bottom protective layer to cover the sealing ring metal layer pattern and the bottom protective layer;

[0012] Disposing a first photomask on the insulating medium temporary layer, wherein a mask opening of the first photomask is aligned with the sealing ring metal layer pattern region; and

[0013] The insulating dielectric temporary layer is etched by using the mask opening of the first mask until the sealing ring metal layer pattern is exposed, thereby obtaining the insulating dielectric layer having the isolation opening, wherein the isolation opening corresponds to the mask opening.

[0014] Preferably, in the process of etching the temporary insulating dielectric layer, the etching stops at the bottom protective layer.

[0015] Preferably, the sealing ring metal layer pattern includes at least one continuous metal ring structure, the isolation opening exposes at least one continuous metal ring structure of the sealing ring metal layer pattern, the continuous metal ring structure is formed by an alternating stack of multiple barrier layers, metal layers and plug parts, and metal interconnection is achieved between the metal layers through the barrier layers and the plug parts.

[0016] Preferably, the width of the isolation opening is greater than or equal to the width of the sealing ring metal layer pattern, so that the isolation opening completely exposes the sealing ring metal layer pattern.

[0017] Preferably, the width of the isolation opening is smaller than the width of the sealing ring metal layer pattern, so that the isolation opening partially exposes the sealing ring metal layer pattern, and the sealing ring metal layer pattern is partially embedded in the insulating dielectric layer.

[0018] Preferably, the material of the moisture-proof layer includes nitride or oxynitride, the material of the bottom protection layer includes silicon carbon nitride, and the material of the insulating dielectric layer includes oxide.

[0019] Preferably, the method for preparing the chip sealing ring structure further comprises:

[0020] A top covering layer is formed on the moisture-proof layer.

[0021] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor chip, wherein the method for preparing a semiconductor chip at least comprises: preparing a chip sealing ring structure by adopting the method for preparing a chip sealing ring structure as described above.

[0022] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor chip, wherein the method for preparing a semiconductor chip at least comprises:

[0023] Providing a wafer, on which a plurality of chips and dicing lanes between adjacent chips are prepared;

[0024] The chip sealing ring structure is prepared by the method for preparing the chip sealing ring structure as described above, and the chip sealing ring structure is prepared between the peripheral area of ​​the chip and the cutting path; wherein, a pad metal layer pattern is formed simultaneously with the formation of the sealing ring metal layer pattern, the pad metal layer pattern is located in the peripheral area of ​​the chip, and the pad metal layer pattern is partially wrapped in the insulating dielectric layer;

[0025] A pad opening is formed above the pad metal layer pattern to expose the pad region of the chip.

[0026] Preferably, the process of forming a pad opening above the pad metal layer pattern includes:

[0027] forming a top covering layer on the moisture-proof layer;

[0028] Disposing a second photomask on the top covering layer;

[0029] The top cover layer is patterned using the second mask, and the moisture-proof layer and the insulating dielectric layer are etched until the pad metal layer pattern is exposed to form the pad opening, and the portion of the pad metal layer pattern exposed in the pad opening serves as a chip pad, thereby exposing the pad area of ​​the chip.

[0030] Preferably, the method for preparing the semiconductor chip further comprises:

[0031] The wafer is cut along the cutting paths to obtain a plurality of the semiconductor chips.

[0032] To achieve the above objectives and other related objectives, the present invention provides a chip sealing ring structure, wherein the chip sealing ring structure at least includes:

[0033] chip;

[0034] A bottom protection layer, located on the active surface of the chip;

[0035] A sealing ring metal layer pattern is located on the bottom protection layer, and the sealing ring metal layer pattern is located around the chip;

[0036] an insulating dielectric layer, located on the bottom protective layer, the insulating dielectric layer having an isolation opening, the isolation opening exposing the sealing ring metal layer pattern and the bottom protective layer; and,

[0037] A moisture-proof layer, located on the insulating dielectric layer and in the isolation opening, the moisture-proof layer covers a first exposed portion of the sealing ring metal layer pattern and a second exposed portion of the bottom protection layer in the isolation opening;

[0038] The chip sealing ring structure enhances the gas-liquid barrier capability by covering the moisture-proof layer on the sealing ring metal layer pattern, thereby preventing the sealing ring metal layer pattern from being oxidized or corroded by gas and liquid.

[0039] Preferably, the width of the isolation opening is greater than or equal to the width of the sealing ring metal layer pattern, so that the sealing ring metal layer pattern is completely exposed in the isolation opening, and the moisture-proof layer covers the surface of the sealing ring metal layer pattern.

[0040] Preferably, the width of the isolation opening is smaller than the width of the sealing ring metal layer pattern, so that the sealing ring metal layer pattern is partially exposed in the isolation opening and the sealing ring metal layer pattern is partially embedded in the insulating dielectric layer.

[0041] Preferably, the sealing ring metal layer pattern comprises at least one continuous metal ring structure, which is formed by staggered stacking of a plurality of barrier layers, metal layers and plug parts, and metal interconnection is achieved between the metal layers through the barrier layers and the plug parts.

[0042] Preferably, the isolation opening exposes at least one of the continuous metal ring structures of the seal ring metal layer pattern.

[0043] Preferably, the material of the moisture-proof layer includes nitride or oxynitride, the material of the bottom protection layer includes silicon carbon nitride, and the material of the insulating dielectric layer includes oxide.

[0044] To achieve the above object and other related objects, the present invention provides a semiconductor chip, wherein the semiconductor chip at least includes: the chip sealing ring structure as described above.

[0045] To achieve the above objectives and other related objectives, the present invention provides a semiconductor device structure, which at least includes:

[0046] A wafer, on which a plurality of chips and dicing lanes between adjacent chips are prepared;

[0047] The chip sealing ring structure as described above is located between the chip surrounding area and the dicing road; and

[0048] A pad metal layer pattern is located in the area surrounding the chip, and the pad metal layer pattern is partially wrapped in the insulating dielectric layer;

[0049] The pad area is located on the pad metal layer pattern and includes a chip pad and a pad opening, wherein the pad opening exposes a portion of the pad metal layer pattern as the chip pad.

[0050] As described above, the chip sealing ring structure and the manufacturing method thereof, the semiconductor chip and the manufacturing method thereof of the present invention have the following beneficial effects:

[0051] The chip sealing ring structure and preparation method thereof of the present invention utilize chip circuit area manufacturing process to form a moisture-proof layer on the surface of the sealing ring metal layer pattern without increasing the process steps. The moisture-proof layer is wrapped around the outside of the sealing ring metal layer pattern, which can effectively prevent the metal layer from being directly exposed to the air during the manufacturing process and being oxidized or corroded by oxygen, water vapor or other gases and liquids, greatly enhancing the gas-liquid blocking ability without reducing the stress expansion and cracking blocking ability. Compared with the prior art that mainly blocks oxygen, it also enhances the ability to resist corrosion by water vapor or other gases and liquids, thereby preventing the electrical properties and reliability of the chip from being affected.

[0052] The semiconductor chip and the preparation method thereof of the present invention adopt the chip sealing ring structure and the preparation method thereof of the present invention. On a wafer with a plurality of chips, a chip sealing ring structure is simultaneously prepared between the surrounding area of ​​each chip and the cutting path, and a chip circuit area manufacturing process is utilized to form a pad metal layer pattern while forming a sealing ring metal layer pattern, and a pad opening is formed above the pad metal layer pattern to open the pad area of ​​each chip, and finally the wafer is cut along the cutting path to obtain a plurality of semiconductor chips. When the wafer cutting process is performed along the cutting path, the chip sealing ring structure can effectively block stress expansion and rupture capabilities, and at the same time has a strong gas-liquid blocking capability, and can effectively resist the erosion of water vapor or other gas-liquids. Therefore, the semiconductor chip obtained by the above method has excellent electrical performance and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A top view of a chip sealing ring structure in the prior art of the present invention is shown.

[0054] Figure 2 Display as Figure 1 An exemplary structural cross-sectional view along the AA direction.

[0055] Figure 3 It is a schematic flow chart of a method for preparing a chip sealing ring structure in a first embodiment of the present invention.

[0056] Figure 4 to Figure 12 The schematic diagram shows the specific steps of the method for preparing the chip sealing ring structure according to the first embodiment of the present invention. Figure 7 (a) is a top view showing a first mask disposed on the temporary insulating dielectric layer, wherein the width of the mask opening is greater than the width of the sealing ring metal layer pattern.

[0057] Fig.12 Also shown is a schematic diagram of a chip sealing ring structure in a case where the sealing ring metal layer pattern includes a continuous metal ring structure in the method for preparing the chip sealing ring structure according to the first embodiment of the present invention.

[0058] Fig.13 (a) A top view showing a method for preparing a chip sealing ring structure according to the first embodiment of the present invention, in which the sealing ring metal layer pattern includes two continuous metal ring structures, a first mask is disposed on the insulating medium temporary layer, and the width of the mask opening is greater than or equal to the width of the sealing ring metal layer pattern.

[0059] Fig.13 (b) is a schematic diagram showing a chip sealing ring structure in the method for preparing a chip sealing ring structure according to the first embodiment of the present invention, in which the sealing ring metal layer pattern includes two continuous metal ring structures and the width of the isolation opening is greater than or equal to the width of the sealing ring metal layer pattern.

[0060] Fig.14 (a) A top view showing a method for preparing a chip sealing ring structure according to the first embodiment of the present invention, in which the sealing ring metal layer pattern includes three continuous metal ring structures, a first mask is disposed on the insulating medium temporary layer, and the width of the mask opening is greater than the width of the sealing ring metal layer pattern.

[0061] Fig.14 (b) is a schematic diagram showing a chip sealing ring structure in the method for preparing a chip sealing ring structure according to the first embodiment of the present invention, in which the sealing ring metal layer pattern includes three continuous metal ring structures and the width of the isolation opening is greater than or equal to the width of the sealing ring metal layer pattern.

[0062] Fig.15 (a) A top view showing a method for preparing a chip sealing ring structure according to the first embodiment of the present invention, in which the sealing ring metal layer pattern includes two continuous metal ring structures, a first mask is disposed on the insulating medium temporary layer, and the width of the mask opening is smaller than the width of the sealing ring metal layer pattern.

[0063] Fig.15 (b) is a schematic diagram showing a chip sealing ring structure in the method for preparing a chip sealing ring structure according to the first embodiment of the present invention, in which the sealing ring metal layer pattern includes two continuous metal ring structures and the width of the isolation opening is smaller than the width of the sealing ring metal layer pattern.

[0064] Fig.16 (a) is a top view showing a method for preparing a chip sealing ring structure according to the first embodiment of the present invention, in which the sealing ring metal layer pattern includes three continuous metal ring structures, and a first mask is set on the insulating medium temporary layer, and the width of the mask opening is smaller than the width of the sealing ring metal layer pattern.

[0065] Fig.16 (b) is a schematic diagram showing a chip sealing ring structure in the method for preparing a chip sealing ring structure according to the first embodiment of the present invention, in which the sealing ring metal layer pattern includes three continuous metal ring structures and the width of the isolation opening is smaller than the width of the sealing ring metal layer pattern.

[0066] Fig.17 (a) is a top view showing a first photomask having a spacer pattern disposed on a temporary insulating dielectric layer when the seal ring metal layer pattern includes three continuous metal ring structures in the method for preparing a chip seal ring structure according to the first embodiment of the present invention.

[0067] Fig.17 (b) Displayed as per Fig.17 (a) Schematic diagram of the final chip sealing ring structure.

[0068] Fig.18 and Fig.19 A top view showing a method for fabricating a chip seal ring structure according to a first embodiment of the present invention, in which a mask opening is aligned with a selected area of ​​a seal ring metal layer pattern.

[0069] Fig. 20 It is a schematic diagram of a wafer having a chip, a dicing street and a chip sealing ring structure prepared in a method for preparing a semiconductor chip according to a third embodiment of the present invention.

[0070] Figure 21~Figure 24 The schematic diagram shows the specific steps of preparing the pad in the method for preparing the semiconductor chip according to the third embodiment of the present invention. Fig. 22 Shown is a top view of a mask covering pad locations.

[0071] Component number description

[0072] 10 chips;

[0073] 11 bottom protective layer;

[0074] 11a second exposure site;

[0075] 12. Sealing ring metal layer pattern;

[0076] 12a First exposure site;

[0077] 121 metal layer;

[0078] 122 barrier layer;

[0079] 123 plug part;

[0080] 13 insulating dielectric layer;

[0081] 131 Temporary layer of insulating medium;

[0082] 132 Isolation opening;

[0083] 133 Photoresist;

[0084] 14 first light mask;

[0085] 141 mask opening;

[0086] 15 Moisture barrier;

[0087] 16 top cover layer;

[0088] 17 pad metal layer pattern;

[0089] 171 pad opening;

[0090] 18 second light mask;

[0091] 20 cutting lanes;

[0092] Steps S1~S4. DETAILED DESCRIPTION

[0093] See also Figure 1 and Figure 2 In the prior art, the chip sealing ring structure at least includes: a chip 10; a bottom protection layer 11, located on the chip 10; a sealing ring metal layer pattern 12, located on the bottom protection layer 11, and the sealing ring metal layer pattern 12 is located at the periphery of the chip 10; an insulating dielectric layer 13, located on the bottom protection layer 11, and the sealing ring metal layer pattern 12 is wrapped in the insulating dielectric layer 13; a moisture-proof layer 15, located on the insulating dielectric layer 13; and a top cover layer 16, located on the moisture-proof layer 15. The sealing ring metal layer pattern 12 includes at least one continuous metal ring structure, which is formed by staggered stacking of multiple barrier layers 122, metal layers 121, and plugs 123, and the metal layers 121 are interconnected by metals through the barrier layers 122 and the plugs 123.

[0094] After long-term practice, the inventor found that, since the moisture-proof layer 15 in the prior art only covers the insulating dielectric layer 13, and the sealing ring metal layer pattern 12 is wrapped in the insulating dielectric layer 13, the moisture-proof layer 15 has limited gas-liquid barrier capability for the sealing ring metal layer pattern 12 located in the insulating dielectric layer 13; and since the insulating dielectric layer 13 is usually made of oxide material, it mainly blocks oxygen to prevent the metal layer in the sealing ring metal layer pattern 12 from being oxidized, but has poor resistance to corrosion by water vapor or other gas and liquid. The metal layer is directly exposed to the air during the manufacturing process and is easily corroded by water vapor or other gas and liquid, thereby affecting the electrical properties and reliability of the chip 10. In order to solve the problems of the prior art, after long-term experiments and research, the inventor has achieved the purpose of enhancing the gas-liquid barrier capability of the chip sealing ring structure without reducing the ability to block stress expansion.

[0095] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0096] See also Figure 3~Figure 19The first embodiment of the present invention relates to a method for preparing a chip sealing ring structure. It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention, and the drawings only show components related to the present invention rather than the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0097] like Figure 3 As shown, the method for preparing the chip sealing ring structure of this embodiment at least includes the following steps:

[0098] Step S1 : providing a chip 10 , wherein a bottom protection layer 11 is formed on an active surface of the chip 10 .

[0099] In step S2 , a sealing ring metal layer pattern 12 is formed on the bottom protection layer 11 . The sealing ring metal layer pattern 12 is located around the active surface of the chip 10 .

[0100] In step S3 , an insulating dielectric layer 13 is formed on the bottom protection layer 11 . The insulating dielectric layer 13 has an isolation opening 132 . The isolation opening 132 exposes the sealing ring metal layer pattern 12 and the bottom protection layer 11 .

[0101] Step S4 , forming a moisture-proof layer 15 on the insulating dielectric layer 13 and in the isolation opening 132 , the moisture-proof layer 15 covers the first exposed portion 12 a of the sealing ring metal layer pattern 12 and the second exposed portion 11 a of the bottom protection layer 11 in the isolation opening.

[0102] The chip sealing ring structure enhances the gas-liquid barrier capability by means of the moisture-proof layer 15 covering the sealing ring metal layer pattern 12 , thereby preventing the sealing ring metal layer pattern 12 from being oxidized or corroded by gas and liquid.

[0103] like Figure 4~Figure 11 As shown, each step in the method for preparing the chip sealing ring structure of this embodiment is specifically described below.

[0104] First, step S1 is performed to provide a chip 10, and a bottom protection layer 11 is formed on the active surface of the chip 10. Figure 4 shown.

[0105] It should be noted that, in the present embodiment, the active surface of the chip 10 is the side provided with the device pattern, and a bottom protective layer 11 is formed on the active surface of the chip 10, and the material of the bottom protective layer 11 includes silicon carbon nitrogen SiCN. The method for forming the bottom protective layer 11 includes chemical vapor deposition (CVD) or a film growth method that can be thought of by a person skilled in the art. It is worth mentioning that the bottom protective layer 11 can be used as an etching stop layer in subsequent steps. In addition, the bottom protective layer 11 also has the function of protecting the bottom metal layer in the sealing ring metal layer pattern 12 above it and protecting the device layer below the interlayer dielectric (ILD) layer on the active surface of the chip 10 below it. Of course, in other embodiments, the bottom protective layer 11 may also include other materials with protective functions, and is not limited to the examples in the present embodiment.

[0106] Next, step S2 is performed to form a sealing ring metal layer pattern 12 on the bottom protection layer 11. The sealing ring metal layer pattern 12 is located around the active surface of the chip 10. Figure 5 shown.

[0107] In this embodiment, the sealing ring metal layer pattern 12 includes at least one continuous metal ring structure, which is formed by staggered stacking of multiple barrier layers 122, metal layers 121, and plug portions 123, and the metal layers 121 are interconnected by the barrier layers 122 and the plug portions 123 to ensure the reliability of the chip sealing ring structure as an electrostatic protection device for grounding and the ability to conduct static electricity during wafer cutting, such as Figure 5 As shown. In order to ensure good electrical connection, at least two layers of metal layer 121 are prepared from bottom to top. The formation methods of metal layer 121, barrier layer 122 and plug part 123 include physical vapor deposition (PVD) or other methods of metal film growth that can be thought of by those skilled in the art. In addition, the plug part 123 can be formed integrally by extending downward from the metal layer 121 located in the upper layer using a dual Damascene process, and metal interconnection is achieved with the metal layer 121 located in the lower layer through the barrier layer 122. At the same time, the bottom metal layer 121 can be extended downward to form the plug part 123 and the barrier layer 122 as a whole, so as to achieve metal interconnection with the chip 10. Of course, the plug part 123 can also be formed by filling with other metal filling plugs. As an example, the material of the metal layer 121 includes metal copper or aluminum, the material of the barrier layer 122 includes titanium nitride or titanium, and the material of the plug part 123 includes metal copper or tungsten.

[0108] In addition, the number of continuous metal ring structures can be designed according to actual needs, taking into account the balance between sealing effect and occupied space layout. Figure 5 As shown, as an example, the seal ring metal layer pattern 12 includes a continuous metal ring structure.

[0109] Next, step S3 is performed to form an insulating dielectric layer 13 on the bottom protection layer 11. The insulating dielectric layer 13 has an isolation opening 132. The isolation opening 132 exposes the sealing ring metal layer pattern 12 and the bottom protection layer 11. Figure 6~Figure 11 shown.

[0110] The process of step S3 includes:

[0111] A temporary insulating dielectric layer 131 is formed on the bottom protection layer 11 to cover the sealing ring metal layer pattern 12 and the bottom protection layer 11. Figure 6 shown.

[0112] In this embodiment, the method for forming the temporary insulating dielectric layer 131 includes chemical vapor deposition (CVD) or other film growth methods that can be conceived by those skilled in the art.

[0113] A first mask 14 is disposed on the insulating dielectric temporary layer 131, wherein a mask opening 141 of the first mask 14 is aligned with the sealing ring metal layer pattern 12 region. Figure 7 (a) and Figure 7 In the process of setting the first photomask 14 on the insulating dielectric temporary layer 131, a photoresist 133 is first formed on the insulating dielectric temporary layer 131, and then the first photomask 14 is placed above the photoresist 133, and the mask opening 141 is aligned with the sealing ring metal layer pattern 12 area, as shown in FIG. Figure 7 (a) and 7(b). The pattern of the mask opening 141 enables the subsequently formed isolation opening 132 to fully or partially expose the sealing ring metal layer pattern 12. As a preferred solution, the pattern of the mask opening 141 enables the subsequently formed isolation opening 132 to expose at least one continuous metal ring structure of the sealing ring metal layer pattern 12.

[0114] The insulating dielectric temporary layer 131 is etched by using the mask opening 141 of the first mask 14 until the sealing ring metal layer pattern 12 is exposed, thereby obtaining the insulating dielectric layer 13 having the isolation opening 132, and the isolation opening 132 corresponds to the mask opening 141. Figure 7 (b) Figure 8 , Fig. 9 and Fig.10 As shown, the insulating dielectric layer 13 is obtained. In the process of etching the insulating dielectric temporary layer 131, specifically, as Figure 7As shown in (b), the mask opening 141 of the first mask 14 and the seal ring metal layer pattern 12 area are first aligned and focused, and then the photoresist 133 is exposed to ultraviolet light to copy the pattern of the first mask 14 onto the photoresist 133 to obtain the patterned photoresist 133, as shown in FIG. Figure 8 As shown, the first photomask 14 is then removed, and the insulating dielectric temporary layer 131 is then dry-etched or wet-etched using the patterned photoresist 133 as a mask, or an etching method that can be thought of by a person skilled in the art, until an isolation opening 132 is formed, and the etching stops at the bottom protective layer 11, as shown in FIG. Fig. 9 As shown, the sealing ring metal layer pattern 12 is exposed, and finally the patterned photoresist 133 is removed. Fig.10 .

[0115] In this embodiment, the material of the insulating dielectric layer 13 includes oxide. As an example, the material of the insulating dielectric layer 13 includes silicon oxide. Of course, in other embodiments, the insulating dielectric layer 13 may also include other materials with insulating isolation functions, and is not limited to the examples in this embodiment.

[0116] In addition, in this embodiment, the width of the isolation opening 132 is greater than or equal to the width of the seal ring metal layer pattern 12, so that the isolation opening 132 completely exposes the seal ring metal layer pattern 12. Figure 7 As shown in (a), the width d1 of the mask opening 141 is greater than or equal to the width d2 of the sealing ring metal layer pattern 12, that is, d1≥d2, so that the width d3 of the isolation opening 132 formed subsequently is greater than or equal to the width d2 of the sealing ring metal layer pattern 12, that is, d3≥d2, so that the isolation opening 132 formed subsequently completely exposes the sealing ring metal layer pattern 12, as shown in FIG. Fig.10 It should be noted that when the width d1 of the mask opening 141 is greater than or equal to the width d2 of the sealing ring metal layer pattern 12, the isolation opening 132 can completely expose the sealing ring metal layer pattern 12, so that the moisture-proof layer 15 formed subsequently can cover and wrap the sealing ring metal layer pattern 12 with a larger area, thereby enhancing the sealing effect of the chip sealing ring structure of this embodiment.

[0117] In addition, it should be noted that, since the isolation opening 132 can expose the seal ring metal layer pattern 12 and the bottom protection layer 11, in this embodiment, the portion of the seal ring metal layer pattern 12 exposed by the isolation opening 132 is referred to as the first exposure portion 12a, and the portion of the bottom protection layer 11 exposed by the isolation opening 132 is referred to as the second exposure portion 11a. Due to the different patterns of the mask opening 141 and the different etching depths of the insulating dielectric temporary layer 131, the isolation opening 132 is also different accordingly, so the positions of the first exposure portion 12a and the second exposure portion 11a will also change accordingly. As a preferred solution, since the pattern of the mask opening 141 enables the subsequently formed isolation opening 132 to expose at least one continuous metal ring structure of the sealing ring metal layer pattern 12, the first exposed portion 12a of the sealing ring metal layer pattern 12 at least includes the sidewall and top of the exposed continuous metal ring structure; and since the etching stops at the bottom protection layer 11 when etching the insulating dielectric temporary layer 131, the second exposed portion 11a of the bottom protection layer 11 in the isolation opening 132 at least includes the upper surface of the bottom protection layer 11 located on both sides of the exposed continuous metal ring structure. As an example, Fig.10 As shown, since the sealing ring metal layer pattern 12 only includes one continuous metal ring structure, the isolation opening 132 completely exposes the continuous metal ring structure. Therefore, the first exposed portion 12a of the sealing ring metal layer pattern 12 is the side wall and the top of the exposed continuous metal ring structure, and the second exposed portion 11a of the bottom protective layer 11 in the isolation opening 132 is the upper surface of the bottom protective layer 11 located on both sides of the exposed continuous metal ring structure. Therefore, the moisture-proof layer 15 formed subsequently covers the first exposed portion 12a of the sealing ring metal layer pattern 12, that is, covers the side wall and the top of the exposed continuous metal ring structure, and the moisture-proof layer 15 formed subsequently covers the second exposed portion 11a of the bottom protective layer 11 in the isolation opening 132, that is, covers the upper surface of the bottom protective layer 11 located on both sides of the exposed continuous metal ring structure.

[0118] Next, step S4 is performed to form a moisture-proof layer 15 on the insulating dielectric layer 13 and in the isolation opening 132. The moisture-proof layer 15 covers the first exposed portion 12a of the sealing ring metal layer pattern 12 and the second exposed portion 11a of the bottom protection layer 11 in the isolation opening 132. Fig.10 and Fig.11 shown.

[0119] In this embodiment, the material of the moisture-proof layer 15 includes nitride or oxynitride. As an example, the material of the moisture-proof layer 15 includes silicon nitride. It should be explained that the silicon nitride layer located in the isolation opening 132 covers the first exposed portion 12a of the sealing ring metal layer pattern 12 to form a silicon nitride support protective film (spacer nitride), which can effectively prevent the metal layer in the sealing ring metal layer pattern 12 from being directly exposed to the air during the process and being oxidized or corroded by oxygen, water vapor or other gas and liquid. Compared with the existing process that mainly blocks oxygen, the ability to block gas and liquid to prevent corrosion will be better. Of course, in other embodiments, the moisture-proof layer 15 may also include other materials that have gas and liquid blocking capabilities and can effectively protect the metal layer. The method for forming the moisture-proof layer 15 includes chemical vapor deposition (CVD) or a film growth method that can be thought of by a person skilled in the art.

[0120] In addition, the method for preparing the chip sealing ring structure of this embodiment further includes:

[0121] Step S5, forming a top cover layer 16 on the moisture-proof layer 15, such as Fig.12 shown.

[0122] In this embodiment, the material of the top cover layer 16 includes photoresist. The top cover layer 16 can be used as a mask layer to facilitate subsequent photolithography and etching processes. In addition, the material of the top cover layer 16 can also include polyimide or benzocyclobutene (BCB), and the top cover layer 16 can be used as a passivation layer to protect the moisture-proof layer 15 below it, while providing a protective passivation effect for other subsequent processes. Of course, in other embodiments, the top cover layer 16 can also include other materials with a protective passivation effect, and is not limited to the examples in this embodiment.

[0123] The above steps finally produce Fig.12 The chip seal ring structure is shown.

[0124] It is worth mentioning that Fig.12 The chip sealing ring structure shown is only an example of a case where the sealing ring metal layer pattern 12 includes a continuous metal ring structure; in this case, a first mask 14 is set on the insulating dielectric temporary layer 131, and the width d1 of the mask opening 141 is greater than or equal to the width d2 of the sealing ring metal layer pattern 12. Figure 7 As shown in (a), d1≥d2, so that the width d3 of the isolation opening 132 formed subsequently is greater than or equal to the width d2 of the sealing ring metal layer pattern 12, d3≥d2, so that the isolation opening 132 completely exposes the sealing ring metal layer pattern 12, and finally obtains Fig.12 The chip seal ring structure is shown.

[0125] As another example, the sealing ring metal layer pattern 12 includes two continuous metal ring structures; in this case, a first mask 14 is disposed on the insulating dielectric temporary layer 131, and the width d1 of the mask opening 141 is greater than or equal to the width d2 of the sealing ring metal layer pattern 12. Fig.13 As shown in (a), d1≥d2, so that the width d3 of the isolation opening 132 formed subsequently is greater than or equal to the width d2 of the sealing ring metal layer pattern 12, d3≥d2, so that the isolation opening 132 completely exposes the sealing ring metal layer pattern 12, and finally obtains Fig.13 (b) The chip sealing ring structure shown.

[0126] As a third example, the sealing ring metal layer pattern 12 includes three continuous metal ring structures; in this case, a first mask 14 is disposed on the insulating dielectric temporary layer 131, and the width d1 of the mask opening 141 is greater than or equal to the width d2 of the sealing ring metal layer pattern 12. Fig.14 As shown in (a), d1≥d2, so that the width d3 of the isolation opening 132 formed subsequently is greater than or equal to the width d2 of the sealing ring metal layer pattern 12, d3≥d2, so that the isolation opening 132 completely exposes the sealing ring metal layer pattern 12, and finally obtains Fig.14 (b) The chip sealing ring structure shown.

[0127] Furthermore, in this embodiment, the width of the isolation opening 132 may also be smaller than the width of the sealing ring metal layer pattern 12 , so that the isolation opening 132 partially exposes the sealing ring metal layer pattern 12 , and the sealing ring metal layer pattern 12 is partially embedded in the insulating dielectric layer 13 .

[0128] As an example, the sealing ring metal layer pattern 12 includes two continuous metal ring structures; in this case, a first mask 14 is disposed on the insulating dielectric temporary layer 131, and the width d1 of the mask opening 141 is smaller than the width d2 of the sealing ring metal layer pattern 12. Fig.15 As shown in (a), d1 < d2, so that the width d3 of the isolation opening 132 formed subsequently is less than or equal to the width d2 of the sealing ring metal layer pattern 12, that is, d3 < d2, so that the isolation opening 132 partially exposes the sealing ring metal layer pattern 12, and the sealing ring metal layer pattern 12 is partially embedded in the insulating dielectric layer 13, and finally the following is obtained Fig.15 (b) The chip sealing ring structure shown.

[0129] As another example, the sealing ring metal layer pattern 12 includes three continuous metal ring structures; in this case, a first mask 14 is disposed on the insulating dielectric temporary layer 131, and the width d1 of the mask opening 141 is smaller than the width d2 of the sealing ring metal layer pattern 12. Fig.16 As shown in (a), d1 < d2, so that the width d3 of the isolation opening 132 formed subsequently is less than or equal to the width d2 of the sealing ring metal layer pattern 12, that is, d3 < d2, so that the isolation opening 132 partially exposes the sealing ring metal layer pattern 12, and the sealing ring metal layer pattern 12 is partially embedded in the insulating dielectric layer 13, and finally the following is obtained Fig.16 (b) The chip sealing ring structure shown.

[0130] In addition, in this embodiment, when the first mask 14 is set, the mask opening 141 pattern is designed as an interval pattern according to actual needs, so that the isolation openings 132 formed subsequently expose the continuous metal ring structure in the sealing ring metal layer pattern at intervals. As an example, the sealing ring metal layer pattern 12 includes three continuous metal ring structures. The mask opening 141 pattern of the first mask 14 set on the insulating dielectric temporary layer 131 is as follows: Fig.17 As shown in (a), the pattern of the mask opening 141 can enable the subsequently formed isolation opening 132 to expose the inner continuous metal ring structure and the outer continuous metal ring structure in the sealing ring metal layer pattern 12, while the insulating dielectric layer 13 is still retained on the middle continuous metal ring structure, and the width of the isolation opening 132 is greater than or equal to the width of any continuous metal ring structure in the sealing ring metal layer pattern 12, so that the final result is as shown in FIG. Fig.17 (b) shows the chip sealing ring structure. Of course, the pattern of the mask opening 141 can also be designed according to actual needs, taking into account the balance between the sealing effect and the occupied space layout.

[0131] In addition, in this embodiment, when setting the first mask 14, the mask opening 141 is designed according to actual needs, so that the mask opening 141 is aligned with the selected area of ​​the sealing ring metal layer pattern 12, so that the isolation opening 132 formed subsequently exposes the selected area of ​​the sealing ring metal layer pattern 12. It should be noted that the isolation opening 132 exposes the selected area of ​​the sealing ring metal layer pattern 12, so that the moisture-proof layer 15 formed in the subsequent process can wrap the surface of the sealing ring metal layer pattern 12 covering the selected area; by covering the moisture-proof layer 15 in the selected area, the circuit or device accessories that are more easily corroded by gas and liquid or need to be protected can be sealed and protected. As an example, Fig.18 and Fig.19 As shown, the right parts of the two continuous metal ring structures are used together as the selected area of ​​the sealing ring metal layer pattern 12, and the width of the mask opening 141 is designed to be larger and smaller than the width of the sealing ring metal layer pattern 12, respectively. Then, the mask opening 141 is aligned with the selected area of ​​the sealing ring metal layer pattern 12, and finally, a moisture-proof layer 15 is formed in the selected area to wrap and cover the surface of the sealing ring metal layer pattern 12, which can effectively enhance the sealing effect of the selected area.

[0132] The preparation method of the chip sealing ring structure of the present embodiment forms a moisture-proof layer 15 on the surface of the sealing ring metal layer pattern 12 by utilizing the chip 10 circuit area manufacturing process without increasing the process steps. The moisture-proof layer 15 wraps the metal layer 121 in the sealing ring metal layer pattern 12, which can effectively prevent the metal layer 121 from being directly exposed to the air during the process and being oxidized or corroded by oxygen, water vapor or other gases and liquids, greatly enhancing the gas-liquid blocking ability without reducing the stress expansion and cracking blocking ability. Compared with the prior art that mainly blocks oxygen, the moisture-proof layer 15 also enhances the ability to resist corrosion by water vapor or other gases and liquids, thereby preventing the electrical properties and reliability of the chip 10 from being affected.

[0133] The step division of the above methods is only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they contain the same logical relationship, they are all within the scope of protection of this patent; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this patent.

[0134] A second embodiment of the present invention relates to a method for preparing a semiconductor chip, which at least comprises: preparing a chip sealing ring structure by using the method for preparing a chip sealing ring structure as described in the first embodiment of the present invention.

[0135] It is not difficult to find that this embodiment requires the cooperation of the first embodiment, so the relevant technical details mentioned in the second embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.

[0136] The method for preparing a semiconductor chip of this embodiment adopts the method for preparing a chip sealing ring structure of the first embodiment of the present invention to prepare a chip sealing ring structure. The chip sealing ring structure prepared can effectively block stress expansion and cracking capabilities, and at the same time has strong gas-liquid blocking capabilities, and can effectively resist the erosion of water vapor or other gases and liquids. Therefore, the semiconductor chip 10 obtained by the above method has excellent electrical performance and reliability.

[0137] A third embodiment of the present invention relates to a method for preparing a semiconductor chip, such as Figure 20~Figure 24 As shown, it at least includes:

[0138] A wafer is provided, on which a plurality of chips 10 and a dicing path 20 between adjacent chips 10 are prepared. Fig. 20 shown.

[0139] By adopting the method for preparing a chip sealing ring structure according to the first embodiment of the present invention, a chip sealing ring structure is prepared between the peripheral area of ​​the chip 10 and the dicing street 20, such as Fig. 20 As shown, Fig.13 (a) Fig. 20 A partial enlarged view of a in the figure. The pad metal layer pattern 17 is formed while the sealing ring metal layer pattern 12 is formed. The pad metal layer pattern 17 is located in the area around the chip 10, and the pad metal layer pattern 17 is partially wrapped in the insulating dielectric layer 13, as shown in FIG. Fig.21 It is worth mentioning that, in this embodiment, the sealing ring metal layer pattern 12 and the pad metal layer pattern 17 are prepared simultaneously by using the chip 10 circuit area manufacturing process without increasing the process steps.

[0140] A pad opening 171 is formed above the pad metal layer pattern 17 to expose the pad region of the chip 10 .

[0141] In addition, in the present embodiment, during the process of forming the pad opening 171 above the pad metal layer pattern 17, as shown in FIG. Figure 21~Figure 24 As shown, including:

[0142] A top covering layer 16 is formed on the moisture-proof layer 15, such as Fig.21 shown.

[0143] A second mask 18 is disposed on the top cover layer 16, such as Fig. 22 and Fig.23 As shown, Fig. 22 It is a top view of the second mask 18 disposed on the top cover layer 16, that is, a mask image covering the pad position.

[0144] The top cover layer 16 is patterned using a second photomask 18, and the moisture-proof layer 15 and the insulating dielectric layer 13 are etched until the pad metal layer pattern 17 is exposed to form a pad opening 171. The portion of the pad metal layer pattern 17 exposed within the pad metal layer pattern 17 serves as a chip pad, thereby exposing the pad area of ​​the chip 10, such as Fig.23 and Fig.24 In this embodiment, the etching method used includes dry etching or other etching methods that can be thought of by those skilled in the art.

[0145] In addition, in this embodiment, the method for preparing the semiconductor chip further includes:

[0146] The wafer is cut along the dicing streets 20 to obtain a plurality of semiconductor chips 10 .

[0147] It is not difficult to find that this embodiment requires the cooperation of the first embodiment, so the relevant technical details mentioned in the second embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.

[0148] The preparation method of the semiconductor chip of the present embodiment adopts the preparation method of the chip sealing ring structure of the first embodiment of the present invention. On a wafer with a plurality of chips 10, a chip sealing ring structure is simultaneously prepared between the surrounding area of ​​each chip 10 and the cutting path 20, and the chip 10 circuit area manufacturing process is used to form a pad metal layer pattern 17 while forming the sealing ring metal layer pattern 12, and a pad opening 171 is formed above the pad metal layer pattern 17 to open the pad area of ​​each chip 10, and finally the wafer is cut along the cutting path 20 to obtain a plurality of semiconductor chips 10; when the wafer cutting process is performed along the cutting path 20, the chip sealing ring structure can effectively block stress expansion and rupture, and at the same time has a strong gas-liquid blocking ability, and can effectively resist the erosion of water vapor or other gas-liquids. Therefore, the semiconductor chip 10 obtained by the above method has excellent electrical performance and reliability.

[0149] A fourth embodiment of the present invention relates to a chip sealing ring structure, such as Fig.12 As shown, it at least includes:

[0150] The chip 10 has an active surface on which a bottom protection layer 11 is formed.

[0151] The sealing ring metal layer pattern 12 is located on the bottom protection layer 11 . The sealing ring metal layer pattern 12 is located around the chip 10 .

[0152] The insulating dielectric layer 13 is located on the bottom protection layer 11, and the insulating dielectric layer 13 has an isolation opening 132, and the isolation opening 132 exposes the sealing ring metal layer pattern 12 and the bottom protection layer 11. And,

[0153] The moisture-proof layer 15 is located on the insulating dielectric layer 13 and in the isolation opening 132 . The moisture-proof layer 15 covers the first exposed portion 12 a of the sealing ring metal layer pattern 12 and the second exposed portion 11 a of the bottom protection layer 11 in the isolation opening 132 .

[0154] The chip sealing ring structure enhances the gas-liquid barrier capability by means of the moisture-proof layer 15 covering the sealing ring metal layer pattern 12 , thereby preventing the sealing ring metal layer pattern 12 from being oxidized or corroded by gas and liquid.

[0155] In addition, in the present embodiment, the width of the isolation opening 132 is greater than or equal to the width of the sealing ring metal layer pattern 12, so that the sealing ring metal layer pattern 12 is completely exposed in the isolation opening 132, and the moisture-proof layer 15 covers the surface of the sealing ring metal layer pattern 12. The moisture-proof layer 15 can cover and wrap the sealing ring metal layer pattern 12 in a larger area, thereby enhancing the sealing effect of the chip sealing ring structure of the present embodiment.

[0156] In addition, in this embodiment, the seal ring metal layer pattern 12 includes at least one continuous metal ring structure, which is formed by staggered stacking of multiple barrier layers 122, metal layers 121, and plug portions 123, and the metal layers 121 are interconnected through the barrier layers 122 and the plug portions 123. Fig.11 To ensure good electrical connection, at least two layers of metal layer 121 are prepared from bottom to top. As an example, the material of metal layer 121 includes metal aluminum, the material of barrier layer 122 includes titanium nitride or titanium, and the material of plug portion 123 includes metal copper or tungsten.

[0157] Moreover, in the present embodiment, the isolation opening 132 at least exposes at least one continuous metal ring structure of the seal ring metal layer pattern 12 .

[0158] As an example, the seal ring metal layer pattern 12 includes a continuous metal ring structure, and the isolation opening 132 completely exposes the seal ring metal layer pattern 12, forming a Fig.12 The chip seal ring structure is shown.

[0159] As another example, the seal ring metal layer pattern 12 includes two continuous metal ring structures, and the isolation opening 132 completely exposes the seal ring metal layer pattern 12, forming a seal ring metal layer pattern 12 as shown in FIG. Fig.13 (b) The chip sealing ring structure shown.

[0160] As a third example, the seal ring metal layer pattern 12 includes three continuous metal ring structures, and the isolation opening 132 completely exposes the seal ring metal layer pattern 12, forming a seal ring metal layer pattern 12 as shown in FIG. Fig.14 (b) The chip sealing ring structure shown.

[0161] In addition, in the present embodiment, the width of the isolation opening 132 may also be smaller than the width of the sealing ring metal layer pattern 12, so that the sealing ring metal layer pattern 12 is partially exposed in the isolation opening 132, and the sealing ring metal layer pattern 12 is partially embedded in the insulating dielectric layer 13, and the subsequently formed moisture-proof layer 15 can cover and wrap the first exposed portion 12a of the sealing ring metal layer pattern 12 and the second exposed portion 11a of the bottom protective layer 11 in the isolation opening 132, thereby enhancing the sealing effect of the chip sealing ring structure of the present embodiment while occupying a smaller space layout.

[0162] As an example, the seal ring metal layer pattern 12 includes a continuous metal ring structure, and the isolation opening 132 partially exposes the seal ring metal layer pattern 12, forming a Fig.23 The chip seal ring structure is shown.

[0163] As another example, the seal ring metal layer pattern 12 includes two continuous metal ring structures, and the isolation opening 132 partially exposes the seal ring metal layer pattern 12, forming a Fig.15 (b) The chip sealing ring structure shown.

[0164] As a third example, the seal ring metal layer pattern 12 includes three continuous metal ring structures, and the isolation opening 132 partially exposes the seal ring metal layer pattern 12, forming a seal ring metal layer pattern 12 as shown in FIG. Fig.16 (b) The chip sealing ring structure shown.

[0165] As a fourth example, the sealing ring metal layer pattern 12 includes three continuous metal ring structures, the isolation opening 132 exposes the inner continuous metal ring structure and the outer continuous metal ring structure in the sealing ring metal layer pattern 12, and the insulating dielectric layer 13 is still retained on the middle continuous metal ring structure, forming Fig.17 (b) The chip sealing ring structure shown.

[0166] In addition, in this embodiment, the position of the isolation opening 132 is designed according to actual needs, so that the isolation opening 132 exposes the selected area of ​​the sealing ring metal layer pattern 12. It should be noted that the isolation opening 132 exposes the selected area of ​​the sealing ring metal layer pattern 12, so that the moisture-proof layer 15 formed in the subsequent process can wrap the surface of the sealing ring metal layer pattern 12 in the selected area; by covering the moisture-proof layer 15 in the selected area, the circuit or device accessories that are more easily corroded by gas and liquid or need to be protected can be sealed and protected, effectively enhancing the sealing effect of the selected area.

[0167] In addition, in this embodiment, the moisture-proof layer 15 located in the isolation opening 132 wraps the sidewall and the top of the sealing ring metal layer pattern 12 , and its bottom surface is connected to the bottom protection layer 11 .

[0168] In this embodiment, the material of the moisture-proof layer 15 includes nitride or nitride oxide.

[0169] In this embodiment, the material of the bottom protection layer 11 includes silicon carbon nitride.

[0170] In this embodiment, the material of the insulating dielectric layer 13 includes oxide.

[0171] In addition, the chip sealing ring structure of this embodiment further includes:

[0172] The top covering layer 16 is located on the moisture-proof layer 15 .

[0173] In this embodiment, the material of the top cover layer 16 includes polyimide or benzoylcyclobutene (BCB). The top cover layer 16 has a passivation effect, which can protect the moisture-proof layer 15 below it, and provide a protective passivation effect for other subsequent processes. Of course, in other embodiments, the top cover layer 16 can also include other materials with a protective passivation effect, and is not limited to the examples in this embodiment.

[0174] It is not difficult to find that this embodiment is a product implementation method corresponding to the first embodiment, and this embodiment can be implemented in conjunction with the first embodiment. The relevant technical details mentioned in the first embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.

[0175] The chip sealing ring structure of the present embodiment forms a moisture-proof layer 15 on the surface of the sealing ring metal layer pattern 12. The moisture-proof layer 15 is wrapped around the metal layer, which can effectively prevent the metal layer from being directly exposed to the air during the manufacturing process and being oxidized or corroded by oxygen, water vapor or other gases and liquids, thereby greatly enhancing the gas-liquid blocking ability without reducing the ability to block stress expansion and rupture. Compared with the prior art that mainly blocks oxygen, it also enhances the ability to resist corrosion from water vapor or other gases and liquids, thereby preventing the electrical properties and reliability of the chip 10 from being affected.

[0176] The fifth embodiment of the present invention relates to a semiconductor chip 10 , which at least includes: the chip seal ring structure as described in the fourth embodiment of the present invention.

[0177] It is not difficult to find that the semiconductor chip 10 involved in this embodiment adopts the chip sealing ring structure involved in the fourth embodiment, so the relevant technical details mentioned in the fourth embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the fourth embodiment.

[0178] The semiconductor chip 10 of this embodiment, due to the chip sealing ring structure involved in the fourth embodiment of the present invention, can effectively prevent the metal layer from being directly exposed to the air during the process and being oxidized or corroded by oxygen, water vapor or other gases and liquids, thereby greatly enhancing the gas-liquid barrier capability without reducing the ability to block stress expansion and cracking; compared with the prior art that mainly blocks oxygen, it also enhances the ability to resist corrosion by water vapor or other gases and liquids, thereby avoiding the electrical properties and reliability of the chip 10 being affected.

[0179] A sixth embodiment of the present invention relates to a semiconductor device structure, such as Fig. 20 and Fig.24 As shown, it at least includes:

[0180] A wafer is provided with a plurality of chips 10 and dicing lanes 20 between adjacent chips 10 .

[0181] The chip seal ring structure according to the fourth embodiment of the present invention is located between the peripheral area of ​​the chip 10 and the dicing street 20 .

[0182] The pad metal layer pattern 17 is located in the area surrounding the chip 10 , and the pad metal layer pattern 17 is partially wrapped in the insulating dielectric layer 13 .

[0183] The pad region is located on the pad metal layer pattern 17 and includes a chip pad and a pad opening 171 , wherein the pad opening 171 exposes a portion of the pad metal layer pattern 17 as a chip pad.

[0184] The semiconductor device structure of this embodiment adopts the chip sealing ring structure of the fourth embodiment of the present invention, and forms a chip sealing ring structure between the surrounding area of ​​each chip 10 and the cutting path 20 at the same time, and forms a pad metal layer pattern 17 while forming the sealing ring metal layer pattern 12, and forms a pad opening 171 above the pad metal layer pattern 17 to open the pad area of ​​each chip 10; when the wafer is cut along the cutting path 20, the chip sealing ring structure can effectively block the stress expansion and rupture ability, and at the same time has a strong gas-liquid blocking ability, and can effectively resist the erosion of water vapor or other gas-liquids. Therefore, the semiconductor chip 10 obtained by cutting the wafer has excellent electrical performance and reliability.

[0185] In summary, the chip sealing ring structure and the manufacturing method thereof, the semiconductor chip and the manufacturing method thereof of the present invention have the following beneficial effects:

[0186] The chip sealing ring structure and preparation method thereof of the present invention utilize chip circuit area manufacturing process to form a moisture-proof layer on the surface of the sealing ring metal layer pattern without increasing the process steps. The moisture-proof layer is wrapped around the outside of the metal layer, which can effectively prevent the metal layer from being directly exposed to the air during the manufacturing process and being oxidized or corroded by oxygen, water vapor or other gases and liquids, thereby greatly enhancing the gas-liquid blocking ability and not reducing the stress expansion and rupture blocking ability. Compared with the prior art that mainly blocks oxygen, it also enhances the ability to resist corrosion by water vapor or other gases and liquids, thereby preventing the electrical properties and reliability of the chip from being affected.

[0187] The semiconductor chip and the preparation method thereof of the present invention adopt the chip sealing ring structure and the preparation method thereof of the present invention. On a wafer with a plurality of chips, a chip sealing ring structure is simultaneously prepared between the surrounding area of ​​each chip and the cutting path without increasing the process steps. The chip circuit area manufacturing process is utilized to form a pad metal layer pattern while forming a sealing ring metal layer pattern, and a pad opening is formed above the pad metal layer pattern to open the pad area of ​​each chip. Finally, the wafer is cut along the cutting path to obtain a plurality of semiconductor chips. When the wafer cutting process is performed along the cutting path, the chip sealing ring structure can effectively block stress expansion and rupture capabilities, and at the same time has a strong gas-liquid blocking capability, and can effectively resist the erosion of water vapor or other gas-liquids. Therefore, the semiconductor chip obtained by the above method has excellent electrical performance and reliability.

[0188] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0189] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a chip sealing ring structure, characterized in that: The method for preparing the chip sealing ring structure comprises the following steps: Providing a chip (10), wherein a bottom protection layer (11) is formed on an active surface of the chip (10); forming a sealing ring metal layer pattern (12) on the bottom protection layer (11), wherein the sealing ring metal layer pattern (12) is located around the active surface of the chip (10); An insulating dielectric layer (13) is formed on the bottom protective layer (11), the insulating dielectric layer (13) having an isolation opening (132), the isolation opening (132) exposing the sealing ring metal layer pattern (12) and the bottom protective layer (11), the sealing ring metal layer pattern (12) comprising at least one continuous metal ring structure, the isolation opening (132) exposing at least one continuous metal ring structure of the sealing ring metal layer pattern (12), the continuous metal ring structure being formed by staggered stacking of a plurality of barrier layers (122) and metal layers (121) and plug portions (123), and metal interconnection between the metal layers (121) being achieved through the barrier layers (122) and the plug portions (123); A moisture-proof layer (15) is formed on the insulating dielectric layer (13) and in the isolation opening (132), wherein the moisture-proof layer (15) wraps around the outside of the sealing ring metal layer pattern (12), and the moisture-proof layer (15) covers a first exposed portion (12a) of the sealing ring metal layer pattern (12) and a second exposed portion (11a) of the bottom protective layer (11) in the isolation opening (132); The chip sealing ring structure enhances the gas-liquid barrier capability by means of the moisture-proof layer (15) covering the sealing ring metal layer pattern (12), thereby preventing the sealing ring metal layer pattern (12) from being oxidized or corroded by gas and liquid.

2. The method for preparing a chip sealing ring structure according to claim 1, characterized in that: The process of forming the insulating dielectric layer (13) on the bottom protective layer (11) comprises: forming a temporary insulating dielectric layer (131) on the bottom protective layer (11) to cover the sealing ring metal layer pattern (12) and the bottom protective layer (11); A first photomask (14) is disposed on the insulating medium temporary layer (131), wherein a mask opening (141) of the first photomask (14) is aligned with a region of the sealing ring metal layer pattern (12); and The insulating dielectric temporary layer (131) is etched using the mask opening (141) of the first mask (14) until the sealing ring metal layer pattern (12) is exposed, thereby obtaining the insulating dielectric layer (13) having the isolation opening (132), wherein the isolation opening (132) corresponds to the mask opening (141).

3. The method for preparing a chip sealing ring structure according to claim 2, characterized in that: During the process of etching the insulating dielectric temporary layer (131), the etching stops at the bottom protective layer (11).

4. The method for preparing a chip sealing ring structure according to claim 1, characterized in that: The width of the isolation opening (132) is greater than or equal to the width of the sealing ring metal layer pattern (12), so that the isolation opening (132) completely exposes the sealing ring metal layer pattern (12).

5. The method for preparing a chip sealing ring structure according to claim 1, characterized in that: The width of the isolation opening (132) is smaller than the width of the sealing ring metal layer pattern (12), so that the isolation opening (132) partially exposes the sealing ring metal layer pattern (12), and the sealing ring metal layer pattern (12) is partially embedded in the insulating dielectric layer (13).

6. The method for preparing a chip sealing ring structure according to claim 1, characterized in that: The material of the moisture-proof layer (15) comprises nitride or oxynitride, the material of the bottom protection layer (11) comprises silicon carbon nitride, and the material of the insulating dielectric layer (13) comprises oxide.

7. The method for preparing a chip sealing ring structure according to claim 1, characterized in that: The method for preparing the chip sealing ring structure further includes: A top covering layer (16) is formed on the moisture-proof layer (15).

8. A method for preparing a semiconductor chip, characterized in that: The method for preparing the semiconductor chip comprises: preparing a chip sealing ring structure by adopting the method for preparing a chip sealing ring structure according to any one of claims 1 to 7.

9. A method for preparing a semiconductor chip, characterized in that: The method for preparing the semiconductor chip at least comprises: Providing a wafer, on which a plurality of chips (10) and dicing lanes (20) located between adjacent chips (10) are prepared; A chip sealing ring structure is prepared between the peripheral area of ​​the chip (10) and the cutting path (20) by using the method for preparing a chip sealing ring structure according to any one of claims 1 to 7; wherein a pad metal layer pattern (17) is formed simultaneously with forming the sealing ring metal layer pattern (12); the pad metal layer pattern (17) is located in the peripheral area of ​​the chip (10), and the pad metal layer pattern (17) is wrapped in the insulating dielectric layer (13); A pad opening (171) is formed above the pad metal layer pattern (17) to expose the pad region of the chip (10).

10. The method for preparing a semiconductor chip according to claim 9, characterized in that: The process of forming a pad opening (171) above the pad metal layer pattern (17) comprises: forming a top covering layer (16) on the moisture-proof layer (15); A second light mask (18) is arranged on the top covering layer (16); The top cover layer (16) is patterned using the second photomask (18), and the moisture-proof layer (15) and the insulating dielectric layer (13) are etched until the pad metal layer pattern (17) is exposed to form the pad opening (171), and the portion of the pad metal layer pattern (17) exposed in the pad opening (171) serves as a chip pad, thereby exposing the pad region of the chip (10).

11. The method for preparing a semiconductor chip according to claim 9, characterized in that: The method for preparing the semiconductor chip further includes: The wafer is cut along the cutting path (20) to obtain a plurality of the semiconductor chips.

12. A chip sealing ring structure, characterized in that: The chip sealing ring structure at least includes: Chip (10); A bottom protective layer (11) located on the active surface of the chip (10); A sealing ring metal layer pattern (12) located on the bottom protection layer (11), and the sealing ring metal layer pattern (12) is located around the active surface of the chip (10), the sealing ring metal layer pattern (12) comprising at least one continuous metal ring structure, the continuous metal ring structure being formed by staggered stacking of a plurality of barrier layers (122) and metal layers (121) and plug portions (123), and metal interconnection between the metal layers (121) is achieved through the barrier layers (122) and the plug portions (123); an insulating dielectric layer (13) located on the bottom protective layer (11), the insulating dielectric layer (13) having an isolation opening (132), the isolation opening (132) exposing the sealing ring metal layer pattern (12) and the bottom protective layer (11); and, a moisture-proof layer (15) located on the insulating dielectric layer (13) and in the isolation opening (132), the moisture-proof layer (15) wrapping around the outside of the sealing ring metal layer pattern (12), the moisture-proof layer (15) covering a first exposed portion (12a) of the sealing ring metal layer pattern (12) and a second exposed portion (11a) of the bottom protective layer (11) in the isolation opening (132); The material of the moisture-proof layer (15) comprises nitride or oxynitride, the material of the bottom protection layer (11) comprises silicon carbon nitride, and the material of the insulating dielectric layer (13) comprises oxide. The chip sealing ring structure enhances the gas-liquid barrier capability by covering the moisture-proof layer (15) on the sealing ring metal layer pattern (12), thereby preventing the sealing ring metal layer pattern (12) from being oxidized or corroded by gas and liquid.

13. The chip sealing ring structure according to claim 12, characterized in that: The width of the isolation opening (132) is greater than or equal to the width of the sealing ring metal layer pattern (12), so that the sealing ring metal layer pattern (12) is completely exposed in the isolation opening (132), and the moisture-proof layer (15) covers the surface of the sealing ring metal layer pattern (12).

14. The chip sealing ring structure according to claim 12, characterized in that: The width of the isolation opening (132) is smaller than the width of the sealing ring metal layer pattern (12), so that the sealing ring metal layer pattern (12) is partially exposed in the isolation opening (132), and the sealing ring metal layer pattern (12) is partially embedded in the insulating dielectric layer (13).

15. The chip sealing ring structure according to claim 12, characterized in that: The isolation opening (132) exposes at least one of the continuous metal ring structures of the sealing ring metal layer pattern (12).

16. The chip sealing ring structure according to claim 12, characterized in that: The chip sealing ring structure further includes: A top covering layer (16) is located on the moisture-proof layer (15).

17. A semiconductor chip, characterized in that: The semiconductor chip at least comprises: the chip sealing ring structure according to any one of claims 12 to 16.

18. A semiconductor device structure, characterized in that: include: A wafer, the wafer comprising a plurality of chips (10) and a dicing path (20) between adjacent chips (10); The chip sealing ring structure according to any one of claims 12 to 16, located between the peripheral area of ​​the chip (10) and the dicing street (20); and A pad metal layer pattern (17) is located in a region surrounding the chip (10), and the pad metal layer pattern (17) is partially wrapped in the insulating dielectric layer (13); A pad area is located on the pad metal layer pattern (17), comprising a chip pad and a pad opening (171), wherein: The pad opening (171) exposes a portion of the pad metal layer pattern (17) as the chip pad.

Images