Chip sealing ring structure and preparation method thereof, semiconductor chip and preparation method thereof

Abstract

The present invention provides a chip sealing ring structure and a preparation method thereof, a semiconductor chip and a preparation method thereof, the method comprising: providing a chip, wherein a bottom protective layer is formed on the active surface of the chip; forming a metal stiffening ring structure and an insulating dielectric layer covering the metal stiffening ring structure on the bottom protective layer, wherein the metal stiffening ring structure is located around the active surface of the chip; forming an isolation opening in the insulating dielectric layer, wherein the isolation opening has a first pattern that is partially overlapped with the metal stiffening ring structure and is not aligned, so as to expose a first surface portion of the metal stiffening ring structure and a second surface portion of the bottom protective layer; and forming an isolation film on the insulating dielectric layer, wherein the isolation film has a second pattern that completely overlaps the isolation opening, so that the isolation film covers the first surface portion of the metal stiffening ring structure and the second surface portion of the bottom protective layer. The present invention enhances the gas-liquid blocking capability for the portion of the chip that is prone to gas-liquid erosion, thereby avoiding the electrical performance and reliability of the chip from being affected.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip sealing ring structure and a preparation method thereof, a semiconductor chip and a preparation method thereof. Background Art

[0002] Since silicon materials are brittle, when the wafer is cut, the cutting method of the cutting knife will generate certain mechanical stress on the front and back of the wafer, which may cause chipping at the edge of the chip. The chipping problem will reduce the mechanical strength of the chip. The initial chip edge cracks will further spread in the subsequent packaging process or in the use of the chip product, which is likely to cause the chip to break, resulting in electrical failure of the chip. In order to protect the internal circuit of the chip, prevent dicing damage, and improve chip reliability, a chip seal ring (SR) structure is usually designed around the chip. Figure 1 As shown, the chip sealing ring structure includes a sealing ring metal layer pattern 12' between the scribe lane (SL) 20 of the wafer and the periphery region (PR) of the chip 10. When the wafer cutting process is performed along the scribe lane, the chip sealing ring structure can block the unwanted stress expansion and cracking from the scribe lane to the chip caused by the above-mentioned wafer cutting process. In addition, the chip sealing ring structure also has the ability to resist gas and liquid erosion, and can block the penetration and damage of water vapor or other chemical pollution sources. In today's semiconductor technology, the size of semiconductor components has been miniaturized, which puts higher requirements on the crack prevention ability and gas and liquid shielding ability of the chip sealing ring. In the existing process, the metal layer is directly exposed to the air during the process and will be oxidized or corroded by oxygen, water vapor or other gas and liquid. The existing chip sealing ring structure mainly blocks oxygen to prevent the metal layer from being oxidized, but has poor resistance to water vapor or other gas and liquid corrosion, especially for the parts of the chip that are prone to gas and liquid corrosion (such as corners, etc.). The resistance is insufficient, which makes these parts very susceptible to gas and liquid corrosion, thereby affecting the electrical performance and reliability of the chip. Therefore, how to enhance the gas-liquid barrier capability of the chip that is prone to gas-liquid corrosion without reducing the ability to block stress expansion is an urgent problem to be solved. Summary of the invention

[0003] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a chip sealing ring structure and a preparation method thereof, a semiconductor chip and a preparation method thereof, so as to solve the problem in the prior art that the chip is prone to gas-liquid corrosion and has poor ability to resist gas-liquid corrosion, resulting in the electrical performance and reliability of the chip being affected.

[0004] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a chip sealing ring structure, which comprises the following steps:

[0005] Providing a chip, wherein a bottom protection layer is formed on an active surface of the chip;

[0006] Forming a metal stiffening ring structure and an insulating medium layer covering the metal stiffening ring structure on the bottom protection layer, wherein the metal stiffening ring structure is located around the active surface of the chip;

[0007] forming an isolation opening in the insulating dielectric layer, the isolation opening exposing a first surface portion of the metal stiffening ring structure, and the isolation opening having a first pattern partially overlapping and non-aligned with the metal stiffening ring structure, so that the isolation opening also exposes a second surface portion of the bottom protective layer; and

[0008] An isolation film is formed on the insulating dielectric layer, wherein the isolation film has a second pattern that completely overlaps the isolation opening, so that the isolation film covers the first surface portion of the metal stiffening ring structure and the second surface portion of the bottom protection layer.

[0009] Preferably, the size of the second pattern is larger than that of the first pattern, so that the isolation film also covers the sidewalls of the isolation opening and extends onto the insulating dielectric layer.

[0010] Preferably, the size of the second pattern is equal to the size of the first pattern, so that the isolation film also covers the sidewalls of the isolation opening.

[0011] Preferably, the step of forming an isolation opening in the insulating dielectric layer comprises:

[0012] Disposing a first photomask on the insulating dielectric layer, wherein the first photomask has a photomask opening aligned with a first surface portion of the metal stiffening ring structure and a second surface portion of the bottom protective layer; and

[0013] Based on the pattern of the mask opening of the first mask, the insulating dielectric layer is etched until the isolation opening having a pattern corresponding to the mask opening is formed, thereby exposing a first surface portion of the metal stiffening ring structure and a second surface portion of the bottom protective layer.

[0014] Preferably, during the process of etching the insulating dielectric layer, the etching stops at the bottom protective layer.

[0015] Preferably, the width of the isolation opening is greater than or equal to the width of the unit ring of the metal stiffening ring structure, and the width of the isolation membrane formed subsequently is greater than or equal to the width of the unit ring of the metal stiffening ring structure.

[0016] Preferably, the metal stiffening ring structure is a multi-ring type with a ring gap between the inner and outer rings, the width of the isolation opening is greater than or equal to the width of the ring gap of the metal stiffening ring structure, and the width of the isolation membrane formed subsequently is greater than or equal to the width of the ring gap of the metal stiffening ring structure.

[0017] Preferably, the first surface portion of the metal stiffening ring structure includes a partial area of ​​at least one continuous metal ring structure, and the continuous metal ring structure is formed by staggered stacking of multiple barrier layers, metal layers and plug parts, and metal interconnection is achieved between the metal layers through the barrier layers and the plug parts.

[0018] Preferably, the first surface portion of the metal stiffening ring structure is located at a side edge or a corner of the active surface of the chip, which includes at least one side edge or a corner portion of the continuous metal ring structure.

[0019] Preferably, the metal stiffening ring structure further comprises at least one corner stiffening structure located outside the corner portion of the continuous metal ring structure, and the corner stiffening structure has the same interlayer structure as that of the continuous metal ring structure.

[0020] Preferably, the first surface portion of the metal stiffening ring structure is located at the corner stiffening structure.

[0021] Preferably, the corner stiffening structure is composed of three metal segments which are sequentially connected to form a double obtuse angle.

[0022] Preferably, the material of the isolation film includes nitride or oxynitride, the material of the bottom protection layer includes silicon carbon nitride, and the material of the insulating dielectric layer includes oxide.

[0023] Preferably, the method for preparing the chip sealing ring structure further comprises:

[0024] A top covering layer covering the isolation film is formed on the insulating dielectric layer.

[0025] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor chip, wherein the method for preparing a semiconductor chip at least comprises: preparing a chip sealing ring structure by adopting the method for preparing a chip sealing ring structure as described above.

[0026] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor chip, wherein the method for preparing a semiconductor chip at least comprises:

[0027] Providing a wafer, on which a plurality of chips and dicing lanes between adjacent chips are prepared;

[0028] The chip sealing ring structure is prepared between the peripheral area of ​​the chip and the cutting path by using the method for preparing the chip sealing ring structure as described above; wherein a pad metal layer pattern is formed while forming the metal stiffening ring structure, the pad metal layer pattern is located in the peripheral area of ​​the chip, and the pad metal layer pattern is wrapped in the insulating dielectric layer;

[0029] A pad opening is formed above the pad metal layer pattern to expose the pad region of the chip.

[0030] Preferably, the step of forming a pad opening above the pad metal layer pattern comprises:

[0031] forming a top covering layer on the isolation film;

[0032] Disposing a second photomask on the top covering layer;

[0033] The top cover layer is patterned using the opening pattern of the second mask, and the isolation film and the insulating dielectric layer are etched until the pad opening is formed above the pad metal layer pattern, and the portion of the pad metal layer pattern exposed in the pad opening serves as a chip pad, thereby exposing the pad area of ​​the chip.

[0034] Preferably, the method for preparing the semiconductor chip further comprises:

[0035] The wafer is cut along the cutting paths to obtain a plurality of semiconductor chips.

[0036] To achieve the above objectives and other related objectives, the present invention provides a chip sealing ring structure, wherein the chip sealing ring structure at least includes:

[0037] A chip, wherein a bottom protection layer is formed on an active surface of the chip;

[0038] A metal stiffening ring structure and an insulating dielectric layer covering the metal stiffening ring structure are formed on the bottom protective layer, and the metal stiffening ring structure is located on the active surface of the chip; wherein an isolation opening is formed in the insulating dielectric layer, the isolation opening exposes a first surface portion of the metal stiffening ring structure, and the isolation opening has a first pattern that is partially overlapped with the metal stiffening ring structure and is non-aligned, so that the isolation opening also exposes a second surface portion of the bottom protective layer; and,

[0039] An isolation film is formed on the insulating dielectric layer, and the isolation film has a second pattern that completely overlaps the isolation opening, so that the isolation film covers the first surface portion of the metal stiffening ring structure and the second surface portion of the bottom protective layer.

[0040] Preferably, the size of the second pattern is larger than that of the first pattern, so that the isolation film also covers the sidewalls of the isolation opening and extends onto the insulating dielectric layer.

[0041] Preferably, the size of the second pattern is equal to the size of the first pattern, so that the isolation film also covers the sidewalls of the isolation opening.

[0042] Preferably, the width of the isolation opening is greater than or equal to the width of the unit ring of the metal stiffening ring structure, and the width of the isolation membrane is greater than or equal to the width of the unit ring of the metal stiffening ring structure.

[0043] Preferably, the metal stiffening ring structure is a multi-ring structure with a ring gap between the inner and outer rings, the width of the isolation opening is greater than or equal to the ring gap of the metal stiffening ring structure, and the width of the isolation membrane is greater than or equal to the ring gap of the metal stiffening ring structure.

[0044] Preferably, the metal stiffening ring structure comprises at least one continuous metal ring structure, the continuous metal ring structure is formed by staggered stacking of a plurality of barrier layers and metal layers, and the metal layers are interconnected by integrally forming a plug portion on the barrier layer.

[0045] Preferably, the isolation opening exposes a first surface portion of the metal stiffening ring structure, and the first surface portion of the metal stiffening ring structure includes a partial area of ​​at least one continuous metal ring structure.

[0046] Preferably, the first surface portion of the metal stiffening ring structure is located at a side edge or a corner of the active surface of the chip, which includes at least one side edge or a corner portion of the continuous metal ring structure.

[0047] Preferably, the metal stiffening ring structure further comprises at least one corner stiffening structure located outside the corner portion of the continuous metal ring structure, and the corner stiffening structure has the same interlayer structure as that of the continuous metal ring structure.

[0048] Preferably, the first surface portion of the metal stiffening ring structure is located at the corner stiffening structure.

[0049] Preferably, the corner stiffening structure is composed of three metal segments which are sequentially connected to form a double obtuse angle.

[0050] Preferably, the material of the isolation film includes nitride or oxynitride, the material of the bottom protection layer includes silicon carbon nitride, and the material of the insulating dielectric layer includes oxide.

[0051] Preferably, the chip sealing ring structure further includes:

[0052] A top covering layer is formed on the insulating medium layer, and the top covering layer covers the isolation film.

[0053] To achieve the above object and other related objects, the present invention provides a semiconductor chip, which at least includes: the chip sealing ring structure as described above.

[0054] To achieve the above objectives and other related objectives, the present invention provides a semiconductor device structure, which at least includes:

[0055] A wafer, on which a plurality of chips and dicing lanes between adjacent chips are prepared;

[0056] The chip sealing ring structure as described above is located between the chip surrounding area and the dicing road; and

[0057] A pad metal layer pattern is located in the area surrounding the chip, and the pad metal layer pattern is wrapped in the insulating dielectric layer;

[0058] The insulating dielectric layer has a pad opening formed above the pad metal layer pattern, and the pad opening also passes through the isolation film to reveal a portion of the pad metal layer pattern as a chip pad, thereby exposing the pad area of ​​the chip.

[0059] As described above, the chip sealing ring structure and the manufacturing method thereof, the semiconductor chip and the manufacturing method thereof of the present invention have the following beneficial effects:

[0060] The chip sealing ring structure and preparation method thereof of the present invention first form an isolation opening for the part of the chip that is prone to gas-liquid corrosion, and then use an isolation film to cover the isolation opening, so as to enhance the gas-liquid blocking ability for the part of the chip that is prone to gas-liquid corrosion, thereby preventing it from being oxidized or corroded by gas and liquid; that is, without increasing the process flow, the chip circuit area manufacturing process is used to form an isolation opening in the insulating dielectric layer, the isolation opening has a first pattern that is non-aligned and partially overlaps with the metal stiffening ring structure, and can reveal the first surface part of the metal stiffening ring structure and the second surface part of the bottom protective layer, and then an isolation film is formed on the insulating dielectric layer, and the isolation film has a pattern that completely overlaps the isolation opening. The second pattern enables the isolation film to cover the first surface portion of the metal stiffening ring structure and the second surface portion of the bottom protective layer, which can effectively prevent the metal layer in the first surface portion of the metal stiffening ring structure from being directly exposed to the air and oxidized or corroded by oxygen, water vapor or other gases and liquids during the manufacturing process, greatly enhancing the gas-liquid blocking ability for the first surface portion of the metal stiffening ring structure, that is, enhancing the gas-liquid blocking ability for the chip that is prone to gas-liquid corrosion problems, and does not reduce the ability to block stress expansion and rupture; compared with the prior art that mainly blocks oxygen, it also enhances the ability to resist corrosion from water vapor or other gases and liquids, thereby avoiding the impact on the electrical performance and reliability of the chip.

[0061] The semiconductor chip and the preparation method thereof of the present invention adopt the chip sealing ring structure and the preparation method thereof of the present invention. On a wafer with a plurality of chips, a chip sealing ring structure is simultaneously prepared between the surrounding area of ​​each chip and the cutting path, and a chip circuit area manufacturing process is utilized to form a pad metal layer pattern while forming a metal stiffening ring structure, and a pad opening is formed above the pad metal layer pattern to open the pad area of ​​each chip, and finally the wafer is cut along the cutting path to obtain a plurality of semiconductor chips. When the wafer cutting process is performed along the cutting path, the chip sealing ring structure can effectively block stress expansion and rupture capabilities, and at the same time has a strong gas-liquid blocking capability for the chip parts prone to gas-liquid erosion, and can effectively resist the erosion of water vapor or other gas-liquids. Therefore, the semiconductor chip obtained by the above method has excellent electrical performance and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 A top view of a chip sealing ring structure in the prior art of the present invention is shown.

[0063] Figure 2 Display as Figure 1 An exemplary structural cross-sectional view along the AA direction.

[0064] Figure 3 It is a schematic flow chart of a method for preparing a chip sealing ring structure in a first embodiment of the present invention.

[0065] Figures 4 to 12 The schematic diagram shows the specific steps of the method for preparing the chip sealing ring structure according to the first embodiment of the present invention. Figure 7 (a) is a top view showing a first photomask disposed on an insulating dielectric material, wherein a mask opening of the first photomask is aligned with a first surface portion of the metal stiffening ring structure and a second surface portion of the bottom protective layer, and a width of the mask opening is greater than a width of a unit ring of the metal stiffening ring structure; Figure 7 (b) Figure 7 (a) Cross-sectional view along the BB direction; Fig.11 (a) is a schematic diagram showing that when the size of the second pattern is larger than the size of the first pattern, the isolation film also covers the sidewalls of the isolation opening and extends onto the insulating dielectric layer; Fig.11 (b) is a schematic diagram showing that when the size of the second pattern is equal to the size of the first pattern, the isolation film also covers the sidewalls of the isolation opening; Fig.12 (a) is a schematic diagram showing that a top cover layer is formed on the insulating dielectric layer when the size of the second pattern is larger than the size of the first pattern; Fig.12 (b) is a schematic diagram showing a top cover layer formed on the insulating dielectric layer when the size of the second pattern is equal to the size of the first pattern.

[0066] Fig.12 (a) and Fig.12 (b) also shows a schematic diagram of the chip sealing ring structure in the case where the metal stiffening ring structure includes a continuous metal ring structure in the method for preparing the chip sealing ring structure according to the first embodiment of the present invention.

[0067] Fig.13 (a) shows a top view of a method for preparing a chip sealing ring structure according to the first embodiment of the present invention, in which the metal stiffening ring structure includes two continuous metal ring structures, a first mask is set on the insulating dielectric material, the mask opening of the first mask is aligned with the first surface portion of the metal stiffening ring structure and the second surface portion of the bottom protective layer, and the width of the mask opening is greater than or equal to the width of the two rings of the metal stiffening ring structure.

[0068] Fig.13 (b) is a schematic diagram of a chip sealing ring structure in which the metal stiffening ring structure includes two continuous metal ring structures and the width of the isolation opening is greater than or equal to the unit ring width of the metal stiffening ring structure in the preparation method of the chip sealing ring structure according to the first embodiment of the present invention.

[0069] Fig.14(a) shows a top view of a method for preparing a chip sealing ring structure according to the first embodiment of the present invention, in which the metal stiffening ring structure includes three continuous metal ring structures, a first mask is set on the insulating dielectric material, the mask opening of the first mask is aligned with the first surface portion of the metal stiffening ring structure and the second surface portion of the bottom protective layer, and the width of the mask opening is greater than the width of the three rings of the metal stiffening ring structure.

[0070] Fig.14 (b) is a schematic diagram of a chip sealing ring structure in which the metal stiffening ring structure includes three continuous metal ring structures and the width of the isolation opening is greater than or equal to the width of the three rings of the metal stiffening ring structure in the preparation method of the chip sealing ring structure according to the first embodiment of the present invention.

[0071] Fig.15 (a) shows a top view of a method for preparing a chip sealing ring structure according to the first embodiment of the present invention, in which the metal stiffening ring structure includes two continuous metal ring structures, a first mask is set on the insulating dielectric material, the mask opening of the first mask is aligned with the first surface portion of the metal stiffening ring structure and the second surface portion of the bottom protective layer, and the width of the mask opening is greater than or equal to the ring gap of the metal stiffening ring structure.

[0072] Fig.15 (b) is a schematic diagram of a chip sealing ring structure in which the metal stiffening ring structure includes two continuous metal ring structures and the width of the isolation opening is greater than or equal to the spacing of the ring gaps of the metal stiffening ring structures in the preparation method of the chip sealing ring structure according to the first embodiment of the present invention.

[0073] Fig.16 (a) shows a top view of a method for preparing a chip sealing ring structure according to the first embodiment of the present invention, in which the metal stiffening ring structure includes three continuous metal ring structures, a first mask is set on the insulating dielectric material, the mask opening of the first mask is aligned with the first surface portion of the metal stiffening ring structure and the second surface portion of the bottom protective layer, and the width of the mask opening is greater than or equal to the total spacing between the two ring gaps of the metal stiffening ring structure.

[0074] Fig.16 (b) is a schematic diagram of a chip sealing ring structure in which the metal stiffening ring structure includes three continuous metal ring structures and the width of the isolation opening is greater than or equal to the total spacing between the two ring gaps of the metal stiffening ring structure in the preparation method of the chip sealing ring structure according to the first embodiment of the present invention.

[0075] Fig.17(a) shows a top view of a method for preparing a chip sealing ring structure according to the first embodiment of the present invention, in which the metal stiffening ring structure includes three continuous metal ring structures, a first mask having a spacing pattern is disposed on an insulating dielectric material, and a mask opening of the first mask is aligned with a first surface portion of the metal stiffening ring structure and a second surface portion of the bottom protective layer.

[0076] Fig.17 (b) Displayed as per Fig.17 (a) Schematic diagram of the final chip sealing ring structure.

[0077] Fig.18 It is a top view showing the alignment of the mask opening with the corner stiffening structure in the method for preparing the chip seal ring structure according to the first embodiment of the present invention.

[0078] Fig.19 It is a schematic diagram of a wafer having a chip, a dicing street and a chip sealing ring structure prepared in a method for preparing a semiconductor chip according to a third embodiment of the present invention.

[0079] Figure 20 to Figure 23 The schematic diagram shows the specific steps of preparing the pad in the method for preparing the semiconductor chip according to the third embodiment of the present invention. Fig. 22 A mask image showing the locations of the pads covered.

[0080] Component number description

[0081] 10 chips;

[0082] 11 bottom protective layer;

[0083] 11a second surface portion;

[0084] 12' sealing ring metal layer pattern;

[0085] 12 metal stiffening ring structure;

[0086] 12a first surface portion;

[0087] 121 metal layer;

[0088] 122 barrier layer;

[0089] 123 plug part;

[0090] 124 ring gap;

[0091] 13 insulating dielectric layer;

[0092] 131 photoresist;

[0093] 132 isolation opening;

[0094] 14 first light mask;

[0095] 141 mask opening;

[0096] 15' moisture barrier;

[0097] 15 isolation film;

[0098] 16 top cover layer;

[0099] 17 pad metal layer pattern;

[0100] 171 pad opening;

[0101] 18 second light mask;

[0102] 20 cutting lanes;

[0103] Steps S1 to S4. DETAILED DESCRIPTION

[0104] See also Figure 1 and Figure 2 In the prior art, the chip sealing ring structure at least includes: a chip 10, on which a bottom protection layer 11 is formed; a sealing ring metal layer pattern 12' formed on the bottom protection layer 11, and the sealing ring metal layer pattern 12' is located at the periphery of the chip 10; an insulating dielectric layer 13 formed on the bottom protection layer 11, and the sealing ring metal layer pattern 12' is wrapped in the insulating dielectric layer 13; a moisture-proof layer 15' formed on the insulating dielectric layer 13; and a top cover layer 16 formed on the moisture-proof layer 15'. The sealing ring metal layer pattern 12' includes at least one continuous metal ring structure, which is formed by a plurality of barrier layers 122 and metal layers 121 being stacked alternately, and the metal layers 121 are interconnected by metals through the barrier layers 122 and the plug portions 123.

[0105] After long-term practice, the inventor found that, since the moisture-proof layer 15' in the prior art only covers the insulating dielectric layer 13, and the sealing ring metal layer pattern 12' is wrapped in the insulating dielectric layer 13, the moisture-proof layer 15' has limited gas-liquid blocking ability for the sealing ring metal layer pattern 12' located in the insulating dielectric layer 13; and since the insulating dielectric layer 13 is usually made of oxide material, it mainly blocks oxygen to prevent the metal layer in the sealing ring metal layer pattern 12' from being oxidized, but has poor resistance to water vapor or other gas and liquid corrosion. The metal layer is directly exposed to the air during the manufacturing process and is easily corroded by water vapor or other gas and liquid. In particular, the chip sealing ring structure has insufficient resistance to corrosion for the chip parts prone to gas and liquid corrosion (such as corners, etc.), which makes these specific areas very susceptible to gas and liquid corrosion, thereby affecting the electrical performance and reliability of the chip 10. In order to solve the problems of the prior art, after long-term experiments and research, the inventor has achieved the purpose of enhancing the gas-liquid blocking ability of the chip parts prone to gas and liquid corrosion without reducing the ability to block stress expansion.

[0106] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0107] See also Figure 3 to Figure 19 The first embodiment of the present invention relates to a method for preparing a chip sealing ring structure. It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention, and the drawings only show components related to the present invention rather than the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0108] like Figure 3 As shown, the method for preparing the chip sealing ring structure of this embodiment at least includes the following steps:

[0109] Step S1 : providing a chip 10 , wherein a bottom protection layer 11 is formed on an active surface of the chip 10 .

[0110] Step S2 , forming a metal stiffening ring structure 12 and an insulating dielectric layer 13 covering the metal stiffening ring structure 12 on the bottom protection layer 11 , wherein the metal stiffening ring structure 12 is located around the active surface of the chip 10 .

[0111] In step S3, an isolation opening 132 is formed in the insulating dielectric layer 13, wherein the isolation opening exposes the first surface portion 12a of the metal stiffening ring structure 12, and the isolation opening 132 has a first pattern that is non-aligned and partially overlaps the metal stiffening ring structure 12, so that the isolation opening 132 also exposes the second surface portion 11a of the bottom protective layer 11.

[0112] Step S4 , forming an isolation film 15 on the insulating dielectric layer 13 , wherein the isolation film 15 has a second pattern that completely overlaps the isolation opening 132 , so that the isolation film 15 covers the first surface portion 12 a of the metal stiffening ring structure 12 and the second surface portion 11 a of the bottom protection layer 11 .

[0113] The size of the second pattern is larger than that of the first pattern, so that the isolation film 15 also covers the sidewalls of the isolation opening 132 and extends onto the insulating dielectric layer 13. Alternatively, the size of the second pattern is equal to that of the first pattern, so that the isolation film 15 also covers the sidewalls of the isolation opening 132.

[0114] like Figures 4 to 11 As shown, each step in the method for preparing the chip sealing ring structure of this embodiment is specifically described below.

[0115] First, step S1 is performed to provide a chip 10, and a bottom protection layer 11 is formed on the active surface of the chip 10. Figure 4 shown.

[0116] It should be noted that, in the present embodiment, the active surface of the chip 10 is the surface provided with the device pattern, and a bottom protective layer 11 is formed on the active surface of the chip 10, and the material of the bottom protective layer 11 includes silicon carbon nitride SiCN. It is worth mentioning that the bottom protective layer 11 can be used as an etching stop layer in subsequent steps. In addition, the bottom protective layer 11 also has the function of protecting the bottom metal layer in the metal stiffening ring structure 12 above it and protecting the device layer below the ILD (Inter Layer Dielectric) layer of the active surface of the chip 10 below it. Of course, in other embodiments, the bottom protective layer 11 may also include other materials with protective functions, and is not limited to the examples in the present embodiment.

[0117] Then, step S2 is performed to form a metal stiffening ring structure 12 and an insulating dielectric layer 13 covering the metal stiffening ring structure 12 on the bottom protection layer 11. The metal stiffening ring structure 12 is located around the active surface of the chip 10, wherein the periphery includes the side edges and corners. Figure 5 and Figure 6 shown.

[0118] In this embodiment, the metal stiffening ring structure 12 includes at least one continuous metal ring structure, which is formed by staggered stacking of multiple barrier layers 122, metal layers 121, and plug portions 123, and the metal layers 121 are interconnected by barrier layers 122 and plug portions 123 to ensure the reliability of the chip sealing ring structure as an electrostatic protection device for grounding and the ability to conduct static electricity during wafer cutting, such as Figure 5 As shown. In order to ensure good electrical connection, at least two layers of metal layer 121 are prepared from bottom to top. The formation methods of metal layer 121, barrier layer 122 and plug part 123 include physical vapor deposition (PVD) or other methods of metal film growth that can be thought of by those skilled in the art. In addition, the plug part 123 can be formed integrally by extending downward from the metal layer 121 located in the upper layer using a dual Damascene process, and metal interconnection is achieved with the metal layer 121 located in the lower layer through the barrier layer 122. At the same time, the bottom metal layer 121 can be extended downward to form the plug part 123 and the barrier layer 122 as a whole, so as to achieve metal interconnection with the chip 10. Of course, the plug part 123 can also be formed by filling with other metal filling plugs. As an example, the material of the metal layer 121 includes metal copper or aluminum, the material of the barrier layer 122 includes titanium nitride or titanium, and the material of the plug part 123 includes metal copper or aluminum or tungsten.

[0119] In addition, the metal reinforcing ring structure 12 can be a multi-ring structure, and the number of continuous metal ring structures can be designed according to actual needs, taking into account the balance between the sealing effect and the occupied space layout. It is worth mentioning that the width of the isolation opening 132 only needs to be greater than the width of any ring to ensure that the second surface portion 11a of the bottom protective layer 11 is exposed. Figure 5 As shown, as an example, the metal stiffening ring structure 12 comprises a continuous metal ring structure.

[0120] Next, step S3 is performed to form an isolation opening 132 in the insulating dielectric layer 13, wherein the isolation opening exposes the first surface portion 12a of the metal stiffening ring structure 12, and the isolation opening 132 has a first pattern that is non-aligned and partially overlaps the metal stiffening ring structure 12, so that the isolation opening 132 also exposes the second surface portion 11a of the bottom protective layer 11, as shown in FIG. Figure 7 to Figure 11 shown.

[0121] It needs to be explained that the isolation opening has a first pattern that is non-aligned and partially overlaps with the metal stiffening ring structure, that is, the isolation opening and the metal stiffening ring structure are not completely aligned and overlapped, and the pattern of the isolation opening and the pattern of the metal stiffening ring structure only overlap partially. The isolation opening will not completely expose the metal stiffening ring structure, but can only reveal the first surface portion of the metal stiffening ring structure and the second surface portion of the bottom protective layer.

[0122] Wherein, in step S3, it includes:

[0123] A first mask 14 is disposed on the insulating dielectric layer 13, wherein the first mask 14 has a mask opening 141 aligned with the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11, as shown in FIG. Figure 7 (a) and Figure 7 In the process of setting the first photomask 14 on the insulating dielectric layer 13, a photoresist 131 is first formed on the insulating dielectric layer 13, and then the first photomask 14 is placed above the photoresist 131, and the photomask opening 141 is aligned with the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11, as shown in FIG. Figure 7 (a) and 7(b), Figure 7 (b) Yes Figure 7 (a) is a cross-sectional view taken along the BB direction. The pattern of the mask opening 141 enables the subsequently formed isolation opening 132 to expose the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11. The first surface portion 12a of the metal stiffening ring structure 12 includes a partial area of ​​at least one continuous metal ring structure. As a preferred embodiment, the first surface portion 12a of the metal stiffening ring structure 12 includes a side or corner portion of at least one continuous metal ring structure. In this embodiment, as Figure 7 (a) and Figure 7 As shown in (b), the first surface portion 12a of the metal stiffening ring structure 12 includes a corner portion of a continuous metal ring structure, and the mask opening 141 is aligned with the corner portion of the continuous metal ring structure and the bottom protective layer 11 on both sides of the corner portion.

[0124] Based on the pattern of the mask opening 141 of the first mask 14, the insulating dielectric layer 13 is etched until an isolation opening 132 having a pattern corresponding to the mask opening 141 is formed, thereby exposing the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protection layer 11 while protecting the chip 10 area, and the other portions of the metal stiffening ring structure 12 are wrapped in the insulating dielectric layer 13, such as Figure 7 (b) Figure 8 , Fig. 9 and Fig.10As shown, an isolation opening 132 is formed in the insulating dielectric layer 13. In the process of etching the insulating dielectric layer 13, specifically, as shown in FIG. Figure 7 As shown in (b), the mask opening 141 of the first mask 14 is first aligned with the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11 and focused, and then the photoresist 131 is exposed to make the pattern of the first mask 14 be copied to the photoresist 131 to obtain the patterned photoresist 131, as shown in FIG. Figure 8 As shown, the first photomask 14 is then removed, and the insulating dielectric layer 13 is dry-etched using the patterned photoresist 131 as a mask, or an etching method that can be thought of by a person skilled in the art, until an isolation opening 132 is formed, and the etching stops at the bottom protective layer 11, as shown in FIG. Fig. 9 As shown, the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protection layer 11 are exposed, and finally the patterned photoresist 131 is removed, as shown in FIG. Fig.10 shown.

[0125] In this embodiment, the material of the insulating dielectric layer 13 includes oxide. As an example, the material of the insulating dielectric layer 13 includes silicon oxide. Of course, in other embodiments, the insulating dielectric layer 13 may also include other materials with insulating isolation functions, and is not limited to the examples in this embodiment.

[0126] In addition, in this embodiment, the width of the isolation opening 132 is greater than or equal to the unit ring width of the metal stiffening ring structure 12, and the width of the isolation film 15 formed subsequently is greater than or equal to the unit ring width of the metal stiffening ring structure 12, so as to ensure that the second surface portion 11a of the bottom protection layer 11 is exposed. Figure 7 As shown in (a), the width d1 of the mask opening 141 is greater than or equal to the unit ring width d2 of the metal stiffening ring structure 12, that is, d1≥d2, so that the width d3 of the isolation opening 132 formed subsequently is greater than or equal to the unit ring width d2 of the metal stiffening ring structure 12, that is, d3≥d2. Fig.10 As shown, the width d4 of the isolation film 15 formed subsequently is greater than or equal to the unit ring width d2 of the metal stiffening ring structure 12, that is, d4 ≥ d2. Fig.11 It should be noted that when the width d1 of the mask opening 141 is greater than or equal to the unit ring width d2 of the metal stiffening ring structure 12, the width d3 of the isolation opening 132 is greater than or equal to the unit ring width d2 of the metal stiffening ring structure 12, so that the isolation film 15 formed later and located in the isolation opening 132 can cover and wrap the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11 with a larger area, thereby enhancing the sealing effect of the chip sealing ring structure of this embodiment.

[0127] In addition, it should be noted that, in the present embodiment, the isolation opening 132 has a first pattern that is partially overlapped with the metal stiffening ring structure 12 and is not aligned. The portion exposed by the first pattern of the isolation opening 132 is the portion of the chip that is prone to gas-liquid erosion. The portion of the metal stiffening ring structure 12 exposed by the isolation opening 132 is referred to as the first surface portion 12a, and the portion of the bottom protective layer 11 exposed by the isolation opening 132 is referred to as the second surface portion 11a. Since the isolation opening 132 can expose the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11, and since the patterns of the mask opening 141 are different and the etching depths of the insulating dielectric layer 13 are different, the isolation opening 132 is also different accordingly, and therefore the positions of the first surface portion 12a and the second surface portion 11a will also change accordingly. As a preferred solution, since the pattern of the mask opening 141 enables the subsequently formed isolation opening 132 to expose a partial area of ​​at least one continuous metal ring structure of the metal stiffening ring structure 12, the first surface portion 12a of the metal stiffening ring structure 12 at least includes the sidewall and top of the exposed partial area of ​​the continuous metal ring structure; and since the etching stops at the bottom protective layer 11 when etching the insulating dielectric layer 13, the second surface portion 11a of the bottom protective layer 11 at least includes the upper surface of the bottom protective layer 11 located on both sides of the exposed continuous metal ring structure. As an example, Fig.10 As shown, since the metal stiffening ring structure 12 includes only one continuous metal ring structure, the isolation opening 132 exposes a partial area of ​​the continuous metal ring structure, and therefore, the first surface portion 12a of the metal stiffening ring structure 12 is the side wall and top of the partial area of ​​the exposed continuous metal ring structure, and the second surface portion 11a of the bottom protective layer 11 is the upper surface of the bottom protective layer 11 located on both sides of the exposed continuous metal ring structure, and therefore the subsequently formed isolation film 15 covers the first surface portion 12a of the metal stiffening ring structure 12, that is, covers the side wall and top of the partial area of ​​the exposed continuous metal ring structure, and the subsequently formed isolation film 15 covers the second surface portion 11a of the bottom protective layer 11, that is, covers the upper surface of the bottom protective layer 11 located on both sides of the exposed continuous metal ring structure. As a more preferred embodiment, the first surface portion 12a of the metal stiffening ring structure 12 is located on the side or corner of the active surface of the chip 10, which includes at least one side or corner portion of the continuous metal ring structure.

[0128] Finally, step S4 is performed to form an isolation film 15 on the insulating dielectric layer 13. The isolation film 15 has a second pattern that completely overlaps the isolation opening 132, so that the isolation film 15 covers the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11. Fig.10 and Fig.11 shown.

[0129] In this embodiment, the size of the second pattern is larger than that of the first pattern, so that the isolation film 15 also covers the sidewalls of the isolation opening 132 and extends onto the insulating dielectric layer 13. Fig.10 and Fig.11 As shown in (a), the width d3 of the isolation opening 132 is the width of the first pattern, and the width d4 of the isolation film 15 is the width of the second pattern. Since the second pattern of the isolation film 15 completely overlaps the first pattern of the isolation opening 132, when the size of the second pattern is larger than the size of the first pattern, the width of the second pattern is larger than the width of the first pattern, that is, the width d4 of the isolation film 15 is larger than the width d3 of the isolation opening 132. Therefore, the isolation film 15 can cover the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protection layer 11 and the side wall of the isolation opening 132 and extend to the insulating dielectric layer 13. In other words, the second pattern of the isolation film 15 can cover the first pattern of the isolation opening 132 with a larger area, and at the same time wrap the first surface portion 12a of the metal stiffening ring structure 12, and can play a better sealing enhancement effect for the portion of the chip where gas-liquid erosion is prone to occur and its surroundings, thereby enhancing the sealing effect of the chip sealing ring structure of this embodiment.

[0130] In addition, in this embodiment, the size of the second pattern may also be equal to the size of the first pattern, so that the isolation film 15 also covers the sidewalls of the isolation opening 132. Fig.10 and Fig.11 As shown in (b), the width d3 of the isolation opening 132 is the width of the first pattern, and the width d4 of the isolation film 15 is the width of the second pattern. Since the second pattern of the isolation film 15 completely overlaps the first pattern of the isolation opening 132, when the size of the second pattern is equal to the size of the first pattern, the width of the second pattern is equal to the width of the first pattern, that is, the width d4 of the isolation film 15 is equal to the width d3 of the isolation opening 132. Therefore, the isolation film 15 can cover the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protection layer 11 and the side wall of the isolation opening 132. In other words, the second pattern of the isolation film 15 can cover the first pattern of the isolation opening 132 and wrap the first surface portion 12a of the metal stiffening ring structure 12 at the same time. Therefore, for the part of the chip that is prone to gas-liquid erosion, it can play a better sealing enhancement effect while occupying a smaller space layout, thereby enhancing the sealing effect of the chip sealing ring structure of this embodiment.

[0131] In this embodiment, the material of the isolation film 15 includes nitride or oxynitride. As an example, the material of the isolation film 15 includes silicon nitride. It should be explained that the silicon nitride layer located in the isolation opening 132 covers the first surface portion 12a of the metal stiffening ring structure 12 to form a silicon nitride support protective film, which can effectively prevent the metal layer in the first surface portion 12a of the metal stiffening ring structure 12 from being directly exposed to the air during the process and being oxidized or corroded by oxygen, water vapor or other gas and liquid. Compared with the existing process that mainly blocks oxygen, the ability to block gas and liquid to prevent corrosion will be better. Of course, in other embodiments, the isolation film 15 may also include other materials that have gas-liquid blocking capabilities and can effectively protect the metal layer.

[0132] In addition, the method for preparing the chip sealing ring structure of this embodiment further includes:

[0133] Step S5, forming a top cover layer 16 covering the isolation film 15 on the insulating dielectric layer 13, such as Fig.12 shown.

[0134] In this embodiment, the material of the top cover layer 16 includes photoresist. The top cover layer 16 can be used as a mask layer to facilitate subsequent photolithography processes.

[0135] The above steps finally produce Fig.12 (a) or Fig.12 (b) shows the chip sealing ring structure. When the size of the second pattern is larger than the size of the first pattern, the chip sealing ring structure is as shown in FIG. Fig.12 (a); when the size of the second pattern is equal to the size of the first pattern, the chip sealing ring structure is as shown in Fig.12 (b) as shown.

[0136] It is worth mentioning that Fig.12 (a) and Fig.12 The chip sealing ring structure shown in (b) is only an example in which the metal stiffening ring structure 12 includes a continuous metal ring structure; in this case, a first mask 14 is provided on the insulating dielectric layer 13, and the width d1 of the mask opening 141 is greater than or equal to the unit ring width d2 of the metal stiffening ring structure 12. Figure 7 As shown in (a), that is, d1≥d2, so that the width d3 of the isolation opening 132 is greater than or equal to the unit ring width d2 of the metal stiffening ring structure 12, that is, d3≥d2, so that the width d4 of the isolation film 15 covering the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11 is greater than or equal to the unit ring width d2 of the metal stiffening ring structure 12, that is, d4≥d2, and the size of the second pattern is greater than or equal to the size of the first pattern, and finally the following is obtained: Fig.12 (a) or Fig.12(b) shows the chip sealing ring structure.

[0137] As another example, the metal stiffening ring structure 12 includes two continuous metal ring structures; in this case, a first mask 14 is disposed on the insulating dielectric layer 13, and the width d1 of the mask opening 141 is greater than or equal to the width d2 of the metal stiffening ring structure 12. Fig.13 As shown in (a), that is, d1≥d2, so that the width d3 of the isolation opening 132 is greater than or equal to the two ring widths d2 of the metal stiffening ring structure 12, that is, d3≥d2, so that the width d4 of the isolation film 15 covering the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11 is greater than or equal to the two ring widths d2 of the metal stiffening ring structure 12, that is, d4≥d2, and the size of the second pattern is larger than the size of the first pattern, so that the isolation film 15 also covers the side wall of the isolation opening 132 and extends to the insulating dielectric layer 13, and finally obtains the following Fig.13 (b) shows the chip seal ring structure. Of course, in other examples, the size of the second pattern may be equal to the size of the first pattern, so that the isolation film 15 also covers the sidewalls of the isolation opening 132 .

[0138] As a third example, the metal stiffening ring structure 12 includes three continuous metal ring structures; in this case, a first mask 14 is disposed on the insulating dielectric layer 13, and the width d1 of the mask opening 141 is greater than or equal to the top view of the three ring widths d2 of the metal stiffening ring structure 12. Fig.14 As shown in (a), that is, d1≥d2, so that the width d3 of the isolation opening 132 is greater than or equal to the three ring widths d2 of the metal stiffening ring structure 12, that is, d3≥d2, so that the width d4 of the isolation film 15 covering the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11 is greater than or equal to the three ring widths d2 of the metal stiffening ring structure 12, that is, d4≥d2, and the size of the second pattern is larger than the size of the first pattern, so that the isolation film 15 also covers the side wall of the isolation opening 132 and extends to the insulating dielectric layer 13, and finally obtains the following Fig.14 (b) shows the chip seal ring structure. Of course, in other examples, the size of the second pattern may be equal to the size of the first pattern, so that the isolation film 15 also covers the sidewalls of the isolation opening 132 .

[0139] In addition, in this embodiment, the metal stiffening ring structure 12 is a multi-ring structure with a ring gap 124 between the inner and outer rings, the width of the isolation opening 132 can also be greater than or equal to the width of the ring gap 124 of the metal stiffening ring structure 12, and the width of the isolation film 15 formed subsequently is greater than or equal to the width of the ring gap 124 of the metal stiffening ring structure 12, so as to ensure that the second surface portion 11a of the bottom protection layer 11 is exposed. Therefore, the sealing effect of the chip sealing ring structure of this embodiment can be enhanced while occupying a smaller space layout.

[0140] As an example, the metal stiffening ring structure 12 includes two continuous metal ring structures; in this case, a first mask 14 is disposed on the insulating dielectric layer 13, and the width d1 of the mask opening 141 is greater than or equal to the spacing d5 of the ring gap 124 of the metal stiffening ring structure 12. Fig.15 As shown in (a), that is, d1≥d5, so that the width d3 of the isolation opening 132 is greater than or equal to the spacing d5 of the ring gap 124 of the metal stiffening ring structure 12, that is, d3≥d5, so that the width d4 of the isolation film 15 covering the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11 is greater than or equal to the spacing d5 of the ring gap 124 of the metal stiffening ring structure 12, that is, d4≥d5, and the size of the second pattern is larger than the size of the first pattern, so that the isolation film 15 also covers the side wall of the isolation opening 132 and extends to the insulating dielectric layer 13, and finally obtains the following Fig.15 (b) shows the chip seal ring structure. Of course, in other examples, the size of the second pattern may be equal to the size of the first pattern, so that the isolation film 15 also covers the sidewalls of the isolation opening 132 .

[0141] As another example, the metal stiffening ring structure 12 includes three continuous metal ring structures; in this case, a first mask 14 is disposed on the insulating dielectric layer 13, and the width d1 of the mask opening 141 is greater than or equal to the total spacing d5 of the two ring gaps 124 of the metal stiffening ring structure 12. Fig.16 As shown in (a), that is, d1≥d5, so that the width d3 of the isolation opening 132 is greater than or equal to the total spacing d5 of the two ring gaps 124 of the metal stiffening ring structure 12, that is, d3≥d5, so that the width d4 of the isolation film 15 covering the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11 is greater than or equal to the total spacing d5 of the two ring gaps 124 of the metal stiffening ring structure 12, that is, d4≥d5, and the size of the second pattern is larger than the size of the first pattern, so that the isolation film 15 also covers the side wall of the isolation opening 132 and extends to the insulating dielectric layer 13, and finally obtains the following Fig.16(b) shows the chip seal ring structure. Of course, in other examples, the size of the second pattern may be equal to the size of the first pattern, so that the isolation film 15 also covers the sidewalls of the isolation opening 132 .

[0142] In addition, in this embodiment, when the first mask 14 is set, the mask opening 141 pattern is designed as an interval pattern according to actual needs, so that the isolation openings 132 formed subsequently expose the partial area of ​​the continuous metal ring structure in the metal stiffening ring structure. As an example, the metal stiffening ring structure 12 includes three continuous metal ring structures, and the mask opening 141 pattern of the first mask 14 set on the insulating dielectric layer 13 is as follows: Fig.17 As shown in (a), the pattern of the mask opening 141 can make the subsequently formed isolation opening 132 reveal a part of the inner continuous metal ring structure and a part of the outer continuous metal ring structure in the metal stiffening ring structure 12, while the insulating dielectric layer 13 is still retained on the middle continuous metal ring structure, and the width of the isolation opening 132 is greater than or equal to the width of any continuous metal ring structure in the metal stiffening ring structure 12, and the size of the second pattern is greater than the size of the first pattern, so that the isolation film 15 also covers the side wall of the isolation opening 132 and extends to the insulating dielectric layer 13, so that the final result is as shown in FIG. Fig.17 (b) shows the chip sealing ring structure. Of course, in other examples, the size of the second pattern can also be equal to the size of the first pattern, so that the isolation film 15 also covers the side wall of the isolation opening 132. Of course, the pattern of the mask opening 141 can also be designed according to actual needs, taking into account the balance between the sealing effect and the occupied space layout.

[0143] In addition, in this embodiment, the metal stiffening ring structure 12 includes at least one corner stiffening structure located outside the corner portion of the continuous metal ring structure, and the corner stiffening structure has the same interlayer structure as the continuous metal ring structure, such as Fig.18 As shown. Preferably, the first surface portion 12a of the metal stiffening ring structure 12 is located at the corner stiffening structure. In addition, in order to further enhance the sealing effect, the shape of the corner stiffening structure where the first surface portion 12a of the metal stiffening ring structure 12 is located can be designed. As an example, the corner stiffening structure is composed of three metal segments connected in sequence to form a double obtuse angle. Of course, the corner stiffening structure can also be designed according to actual conditions, and is not limited to the design of this embodiment.

[0144] Furthermore, in this embodiment, if Fig.18 As shown, when the first light mask 14 is set, the light mask opening 141 is aligned with the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11, so that the subsequently formed isolation opening 132 at least exposes a corner stiffening structure in the first surface portion 12a of the metal stiffening ring structure 12. As an example, Fig.18 As shown, the metal stiffening ring structure 12 includes two continuous metal ring structures and a corner stiffening structure. It should be explained that Fig.18 The corners of the continuous metal ring structure are not right angles, but obtuse angles. Since the corners are more prominent than the sides, they are also the places most susceptible to gas and liquid erosion. In order to prevent the corners from being eroded by gas and liquid, in this embodiment, a corner stiffening structure is added outside the corners of the two continuous metal ring structures. The corner stiffening structure is exposed by the isolation opening 132, so that it can be wrapped and covered by the isolation membrane 15, effectively preventing water vapor from corroding the corners of the continuous metal ring structure to the internal circuits or devices.

[0145] In addition, in this embodiment, it is necessary to pre-determine the part of the chip that is prone to gas-liquid corrosion, and then design the alignment position of the mask opening 141 according to actual needs to obtain the position of the isolation opening 132, so that the isolation opening 132 can expose the first surface part 12a of the metal stiffening ring structure 12 and the second surface part 11a of the bottom protective layer 11. It should be noted that since the isolation opening 132 exposes the first surface part 12a of the metal stiffening ring structure 12, the isolation film 15 formed in the subsequent process can wrap the surface of the metal layer covered in the first surface part 12a of the metal stiffening ring structure 12; therefore, by covering the isolation film 15 on the first surface part 12a of the metal stiffening ring structure 12, it is possible to focus on sealing and protecting the part of the chip that is prone to gas-liquid corrosion or near the circuit or device that needs to be protected, effectively enhancing the sealing effect of the part of the chip that is prone to gas-liquid corrosion.

[0146] The preparation method of the chip sealing ring structure of the present embodiment first forms an isolation opening for the part of the chip that is prone to gas-liquid corrosion, and then uses an isolation film to cover the isolation opening, so as to enhance the gas-liquid blocking ability of the part of the chip that is prone to gas-liquid corrosion, thereby preventing it from being oxidized or corroded by gas and liquid; that is, without increasing the process flow, the chip circuit area manufacturing process is used to form an isolation opening in the insulating dielectric layer, the isolation opening has a first pattern that is non-aligned and partially overlaps with the metal stiffening ring structure, and can reveal the first surface part of the metal stiffening ring structure and the second surface part of the bottom protective layer, and then an isolation film is formed on the insulating dielectric layer, and the isolation film has a pattern that completely overlaps the isolation opening. The second pattern enables the isolation film to cover the first surface portion of the metal stiffening ring structure and the second surface portion of the bottom protective layer, which can effectively prevent the metal layer in the first surface portion of the metal stiffening ring structure from being directly exposed to the air and oxidized or corroded by oxygen, water vapor or other gases and liquids during the manufacturing process, greatly enhancing the gas-liquid blocking ability for the first surface portion of the metal stiffening ring structure, that is, enhancing the gas-liquid blocking ability for the chip that is prone to gas-liquid corrosion problems, and does not reduce the ability to block stress expansion and rupture; compared with the prior art that mainly blocks oxygen, it also enhances the ability to resist corrosion from water vapor or other gases and liquids, thereby avoiding the impact on the electrical performance and reliability of the chip.

[0147] The step division of the above methods is only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they contain the same logical relationship, they are all within the scope of protection of this patent; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this patent.

[0148] A second embodiment of the present invention relates to a method for preparing a semiconductor chip, which at least comprises: preparing a chip sealing ring structure by using the method for preparing a chip sealing ring structure as described in the first embodiment of the present invention.

[0149] It is not difficult to find that this embodiment needs to be implemented in conjunction with the first embodiment, so the relevant technical details mentioned in the second embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.

[0150] The method for preparing a semiconductor chip of this embodiment adopts the method for preparing a chip sealing ring structure of the first embodiment of the present invention to prepare a chip sealing ring structure. The chip sealing ring structure prepared by the method can effectively block stress expansion and cracking, and at the same time has a strong gas-liquid blocking ability for parts of the chip that are prone to gas-liquid corrosion problems, and can effectively resist corrosion from water vapor or other gases and liquids. Therefore, the semiconductor chip obtained by the above method has excellent electrical performance and reliability.

[0151] A third embodiment of the present invention relates to a method for preparing a semiconductor chip, such as Figure 19 to Figure 23 As shown, it at least includes:

[0152] A wafer is provided, on which a plurality of chips 10 and a dicing lane 20 between adjacent chips 10 are prepared. Fig.19 shown.

[0153] By adopting the method for preparing the chip sealing ring structure according to the first embodiment of the present invention, a chip sealing ring structure is prepared between the peripheral area of ​​the chip 10 and the dicing street 20, as shown in FIG. Fig.19 As shown, Fig.13 (a) Fig.19 A local enlarged view of a in the figure. When the metal stiffening ring structure 12 is formed, a pad metal layer pattern 17 is formed. The pad metal layer pattern 17 is located in the area around the chip 10, and the pad metal layer pattern 17 is wrapped in the insulating dielectric layer 13, as shown in FIG. Fig. 20 It is worth mentioning that, in this embodiment, the metal stiffening ring structure 12 and the pad metal layer pattern 17 are prepared simultaneously by using the chip 10 circuit area manufacturing process without increasing the process flow.

[0154] A pad opening 171 is formed above the pad metal layer pattern 17 to expose the pad region of the chip 10 .

[0155] In addition, in the present embodiment, during the process of forming the pad opening 171 above the pad metal layer pattern 17, as shown in FIG. Figure 20 to Figure 23 As shown, including:

[0156] A top cover layer 16 is formed on the isolation film 15, such as Fig. 20 shown.

[0157] A second mask 18 is disposed on the top cover layer 16, such as Fig.21 and Fig. 22 As shown, Fig.21 It is a top view of the second mask 18 disposed on the top cover layer 16, that is, a mask image covering the pad position.

[0158] The top cover layer 16 is patterned by using the second photomask 18, and the isolation film 15 and the insulating dielectric layer 13 are etched until a pad opening 171 is formed above the pad metal layer pattern 17. The portion of the pad metal layer pattern 17 exposed in the pad metal layer pattern 17 serves as a chip pad, thereby exposing the pad area of ​​the chip 10. Fig. 22 and Fig.23 shown.

[0159] In addition, in this embodiment, the method for preparing the semiconductor chip further includes:

[0160] The wafer is cut along the dicing streets 20 to obtain a plurality of semiconductor chips 10 .

[0161] It is not difficult to find that this embodiment needs to be implemented in conjunction with the first embodiment, so the relevant technical details mentioned in the second embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.

[0162] The preparation method of the semiconductor chip of the present embodiment adopts the preparation method of the chip sealing ring structure of the first embodiment of the present invention. On a wafer with a plurality of chips 10, a chip sealing ring structure is simultaneously prepared between the surrounding area of ​​each chip 10 and the cutting path 20, and the chip 10 circuit area manufacturing process is used to form a pad metal layer pattern 17 while forming the metal stiffening ring structure 12, and a pad opening 171 is formed above the pad metal layer pattern 17 to open the pad area of ​​each chip 10, and finally the wafer is cut along the cutting path 20 to obtain a plurality of semiconductor chips 10; when the wafer cutting process is performed along the cutting path 20, the chip sealing ring structure can effectively block the stress expansion and rupture ability, and at the same time has a strong gas-liquid blocking ability for the specific area of ​​the metal stiffening ring structure, and can effectively resist the erosion of water vapor or other gas and liquid, therefore, the semiconductor chip 10 obtained by the above method has excellent electrical performance and reliability.

[0163] A fourth embodiment of the present invention relates to a chip sealing ring structure, such as Fig.12 As shown, it at least includes:

[0164] The chip 10 has an active surface on which a bottom protection layer 11 is formed.

[0165] A metal stiffening ring structure 12 and an insulating dielectric layer 13 covering the metal stiffening ring structure 12 are formed on the bottom protective layer 11, and the metal stiffening ring structure 12 is located around the active surface of the chip 10; wherein an isolation opening 132 is formed in the insulating dielectric layer 13, the isolation opening exposing the first surface portion 12a of the metal stiffening ring structure 12, and the isolation opening 132 has a first pattern that is non-aligned and partially overlaps with the metal stiffening ring structure 12, so that the isolation opening 132 also exposes the second surface portion 11a of the bottom protective layer 11.

[0166] And, an isolation film 15 is formed on the insulating dielectric layer 13, and the isolation film 15 has a second pattern that is larger than the first pattern and completely overlaps the isolation opening 132, so that the isolation film 15 covers the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11 and extends to the insulating dielectric layer 13.

[0167] In this embodiment, the size of the second pattern is larger than that of the first pattern, so that the isolation film 15 can cover the first surface portion 12a of the metal stiffening ring structure 12, the second surface portion 11a of the bottom protection layer 11, and the sidewall of the isolation opening 132 and extend to the insulating dielectric layer 13. In other words, the second pattern of the isolation film 15 can cover the first pattern of the isolation opening 132 with a larger area, and at the same time wrap the first surface portion 12a of the metal stiffening ring structure 12, which can play a better sealing enhancement effect for the portion of the chip that is prone to gas-liquid erosion and its surroundings, thereby enhancing the sealing effect of the chip sealing ring structure of this embodiment.

[0168] In addition, in this embodiment, the size of the second pattern can also be equal to the size of the first pattern, so that the isolation film 15 can cover the first surface portion 12a of the metal stiffening ring structure 12, the second surface portion 11a of the bottom protection layer 11, and the side wall of the isolation opening 132. In other words, the second pattern of the isolation film 15 can cover the first pattern of the isolation opening 132 and wrap the first surface portion 12a of the metal stiffening ring structure 12. Therefore, for the portion of the chip that is prone to gas-liquid erosion, it can play a better sealing enhancement effect while occupying a smaller space layout, thereby enhancing the sealing effect of the chip sealing ring structure of this embodiment.

[0169] In addition, in the present embodiment, the width of the isolation opening 132 is greater than or equal to the unit ring width of the metal stiffening ring structure 12, and the width of the isolation membrane 15 is greater than or equal to the unit ring width of the metal stiffening ring structure 12, so as to ensure that the second surface portion 11a of the bottom protective layer 11 is exposed, so that the isolation membrane 15 can cover and wrap the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11 with a larger area, thereby enhancing the sealing effect of the chip sealing ring structure of the present embodiment.

[0170] In addition, in this embodiment, the metal stiffening ring structure 12 includes at least one continuous metal ring structure, which is formed by staggered stacking of multiple barrier layers 122, metal layers 121, and plugs 123, and the metal layers 121 are interconnected through the barrier layers 122 and plugs 123. Fig.11 As shown. To ensure good electrical connection, at least two layers of metal layer 121 are prepared from bottom to top. As an example, the material of metal layer 121 includes metal copper or aluminum, the material of barrier layer 122 includes titanium nitride or titanium, and the material of plug portion 123 includes metal copper or aluminum or tungsten.

[0171] Furthermore, in this embodiment, the isolation opening 132 exposes the first surface portion 12a of the metal stiffening ring structure 12, and the first surface portion 12a of the metal stiffening ring structure 12 includes a partial area of ​​at least one continuous metal ring structure. Preferably, the first surface portion 12a of the metal stiffening ring structure 12 is located on the side or corner of the active surface of the chip 10, which includes the side or corner portion of at least one continuous metal ring structure.

[0172] As an example, the metal stiffening ring structure 12 includes a continuous metal ring structure, and the isolation opening 132 reveals a partial area of ​​the continuous metal ring structure, forming a Fig.12 (a) or Fig.12 (b) shows the chip sealing ring structure. When the size of the second pattern is larger than the size of the first pattern, the chip sealing ring structure is as shown in FIG. Fig.12 (a); when the size of the second pattern is equal to the size of the first pattern, the chip sealing ring structure is as shown in Fig.12 (b) as shown.

[0173] As another example, the metal stiffening ring structure 12 includes two continuous metal ring structures, the isolation opening 132 exposes a portion of the two continuous metal ring structures, and the size of the second pattern is larger than the size of the first pattern, so that the isolation film 15 also covers the side wall of the isolation opening 132 and extends to the insulating dielectric layer 13, forming a Fig.13 (b) shows the chip seal ring structure. Of course, in other examples, the size of the second pattern may be equal to the size of the first pattern, so that the isolation film 15 also covers the sidewalls of the isolation opening 132 .

[0174] As a third example, the metal stiffening ring structure 12 includes three continuous metal ring structures, the isolation opening 132 exposes a portion of the three continuous metal ring structures, and the size of the second pattern is larger than the size of the first pattern, so that the isolation film 15 also covers the side wall of the isolation opening 132 and extends to the insulating dielectric layer 13, forming a Fig.14(b) shows the chip seal ring structure. Of course, in other examples, the size of the second pattern may be equal to the size of the first pattern, so that the isolation film 15 also covers the sidewalls of the isolation opening 132 .

[0175] In addition, in the present embodiment, the metal stiffening ring structure 12 is a multi-ring type so that there is a ring gap 124 between the inner and outer rings, and the width of the isolation opening 132 can also be greater than or equal to the ring gap 124 of the metal stiffening ring structure 12, and the width of the isolation membrane 15 is greater than or equal to the ring gap 124 of the metal stiffening ring structure 12, so as to ensure that the second surface portion 11a of the bottom protective layer 11 is exposed, so that the isolation membrane 15 can cover and wrap the metal layer in the first surface portion 12a of the metal stiffening ring structure 12 and the second surface portion 11a of the bottom protective layer 11, thereby enhancing the sealing effect of the chip sealing ring structure of the present embodiment while occupying a smaller space layout.

[0176] As an example, the metal stiffening ring structure 12 includes two continuous metal ring structures, the isolation opening 132 exposes a portion of the two continuous metal ring structures, and the size of the second pattern is larger than the size of the first pattern, so that the isolation film 15 also covers the side wall of the isolation opening 132 and extends to the insulating dielectric layer 13, forming a Fig.15 (b) shows the chip seal ring structure. Of course, in other examples, the size of the second pattern may be equal to the size of the first pattern, so that the isolation film 15 also covers the sidewalls of the isolation opening 132 .

[0177] As another example, the metal stiffening ring structure 12 includes three continuous metal ring structures, the isolation opening 132 exposes a portion of the three continuous metal ring structures, and the size of the second pattern is larger than the size of the first pattern, so that the isolation film 15 also covers the side wall of the isolation opening 132 and extends to the insulating dielectric layer 13, forming a Fig.16 (b) shows the chip seal ring structure. Of course, in other examples, the size of the second pattern may be equal to the size of the first pattern, so that the isolation film 15 also covers the sidewalls of the isolation opening 132 .

[0178] As a third example, the metal stiffening ring structure 12 includes three continuous metal ring structures, and the isolation opening 132 reveals a portion of the inner ring continuous metal ring structure and a portion of the outer ring continuous metal ring structure in the metal stiffening ring structure 12, while the insulating dielectric layer 13 is still retained on the middle continuous metal ring structure, and the size of the second pattern is larger than the size of the first pattern, so that the isolation film 15 also covers the side wall of the isolation opening 132 and extends to the insulating dielectric layer 13, forming a structure as shown in FIG. Fig.17 (b) shows the chip seal ring structure. Of course, in other examples, the size of the second pattern may be equal to the size of the first pattern, so that the isolation film 15 also covers the sidewalls of the isolation opening 132 .

[0179] In addition, in the present embodiment, the metal stiffening ring structure 12 includes at least one corner stiffening structure located outside the corner portion of the continuous metal ring structure, and the corner stiffening structure has the same interlayer structure as the continuous metal ring structure. Preferably, the first surface portion 12a of the metal stiffening ring structure 12 is located at the corner stiffening structure. In addition, in order to further enhance the sealing effect, the shape of the corner stiffening structure of the metal stiffening ring structure 12 can be designed. As an example, the corner stiffening structure is composed of three metal segments connected in sequence to form a double obtuse angle. Of course, the corner stiffening structure can also be designed according to actual conditions, and is not limited to the design of the present embodiment.

[0180] Furthermore, in this embodiment, the isolation opening 132 exposes at least one corner stiffening structure in the metal stiffening ring structure 12. As an example, Fig.18 As shown, the metal stiffening ring structure 12 includes two continuous metal ring structures and a corner stiffening structure. It should be explained that Fig.18 The corners of the continuous metal ring structure are not right angles but obtuse angles. However, since the corners are more prominent than the sides, the corners are most susceptible to gas and liquid erosion. In order to prevent the corners from being eroded by gas and liquid, in this embodiment, a corner stiffening structure is added outside the corners of the two continuous metal ring structures. The corner stiffening structure is exposed by the isolation opening 132, so that it can be wrapped and covered by the isolation membrane 15, effectively preventing water vapor from corroding the corners of the continuous metal ring structure to the internal circuits or devices.

[0181] In addition, in this embodiment, it is necessary to pre-determine the part of the chip that is prone to gas-liquid corrosion, so that the isolation opening 132 can expose the first surface part 12a of the metal stiffening ring structure 12 and the second surface part 11a of the bottom protective layer 11. It should be noted that since the isolation opening 132 exposes the first surface part 12a of the metal stiffening ring structure 12, the isolation film 15 can wrap the surface of the metal layer covered in the first surface part 12a of the metal stiffening ring structure 12; therefore, by covering the isolation film 15 on the first surface part 12a of the metal stiffening ring structure 12, it is possible to focus on sealing and protecting the part of the chip that is prone to gas-liquid corrosion or near the circuit or device that needs to be protected, effectively enhancing the sealing effect of the part of the chip that is prone to gas-liquid corrosion. In addition, in this embodiment, the isolation film 15 located in the isolation opening 132 wraps the side wall and top of the continuous metal ring structure in a specific area of ​​the metal stiffening ring structure 12, and its bottom surface is connected to the bottom protective layer 11.

[0182] In this embodiment, the material of the isolation film 15 includes nitride or oxynitride. As an example, the material of the isolation film 15 includes silicon nitride. It should be explained that the silicon nitride layer located in the isolation opening 132 covers the first surface portion 12a of the metal stiffening ring structure 12 to form a silicon nitride support protective film (spacer nitride), which can effectively prevent the metal layer in the first surface portion 12a of the metal stiffening ring structure 12 from being directly exposed to the air during the process and being oxidized or corroded by oxygen, water vapor or other gas and liquid. Compared with the existing process that mainly blocks oxygen, the ability to block gas and liquid to prevent corrosion will be better. Of course, in other embodiments, the isolation film 15 may also include other materials that have gas-liquid blocking capabilities and can effectively protect the metal layer.

[0183] In this embodiment, the material of the bottom protection layer 11 includes silicon carbon nitride.

[0184] In this embodiment, the material of the insulating dielectric layer 13 includes oxide.

[0185] In addition, in the chip sealing ring structure of this embodiment, the metal stiffening ring structure 12 further includes:

[0186] The top cover layer 16 is formed on the insulating dielectric layer 13 , and covers the isolation film 15 .

[0187] In this embodiment, the material of the top cover layer 16 includes polyimide or benzoylcyclobutene (BCB). The top cover layer 16 has a passivation effect, which can protect the isolation film 15 below it and provide a protective passivation effect for other subsequent processes. Of course, in other embodiments, the top cover layer 16 can also include other materials with a protective passivation effect, and is not limited to the examples in this embodiment.

[0188] It is not difficult to find that this embodiment is a product implementation method corresponding to the first embodiment, and this embodiment can be implemented in conjunction with the first embodiment. The relevant technical details mentioned in the first embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.

[0189] The chip sealing ring structure of this embodiment first forms an isolation opening for the chip portion prone to gas-liquid corrosion, and then uses an isolation film to cover the isolation opening, so as to enhance the gas-liquid barrier capability for the chip portion prone to gas-liquid corrosion, thereby preventing it from being oxidized or corroded by gas and liquid; that is, without increasing the process flow, the chip circuit area manufacturing process is used to form an isolation opening in the insulating dielectric layer, the isolation opening has a first pattern that is partially overlapped with the metal stiffening ring structure and is non-aligned, and can reveal a first surface portion of the metal stiffening ring structure and a second surface portion of the bottom protective layer, and then an isolation film is formed on the insulating dielectric layer, the isolation film has a second pattern that completely overlaps the isolation opening. The pattern enables the isolation film to cover the first surface portion of the metal stiffening ring structure and the second surface portion of the bottom protective layer, which can effectively prevent the metal layer in the first surface portion of the metal stiffening ring structure from being directly exposed to the air and oxidized or corroded by oxygen, water vapor or other gases and liquids during the manufacturing process, greatly enhancing the gas-liquid blocking ability for the first surface portion of the metal stiffening ring structure, that is, enhancing the gas-liquid blocking ability for the chip that is prone to gas-liquid corrosion problems, and does not reduce the ability to block stress expansion and rupture; compared with the prior art that mainly blocks oxygen, it also enhances the ability to resist corrosion to water vapor or other gases and liquids, thereby avoiding the electrical performance and reliability of the chip being affected.

[0190] A fifth embodiment of the present invention relates to a semiconductor chip, which at least includes: the chip sealing ring structure as described in the fourth embodiment of the present invention.

[0191] It is not difficult to find that the semiconductor chip involved in this embodiment adopts the chip sealing ring structure involved in the fourth embodiment, so the relevant technical details mentioned in the fourth embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the fourth embodiment.

[0192] The semiconductor chip of this embodiment adopts the chip sealing ring structure involved in the fourth embodiment of the present invention, which can effectively prevent the metal layer from being directly exposed to the air during the manufacturing process and being oxidized or corroded by oxygen, water vapor or other gases and liquids. It greatly enhances the gas-liquid barrier capability for the parts of the chip that are prone to gas-liquid corrosion, and does not reduce the ability to block stress expansion and rupture. Compared with the prior art that mainly blocks oxygen, it also enhances the ability to resist corrosion by water vapor or other gases and liquids, thereby avoiding the impact on the electrical performance and reliability of the chip.

[0193] A sixth embodiment of the present invention relates to a semiconductor device structure, such as Fig.19 and Fig.23 As shown, it at least includes:

[0194] A wafer is provided with a plurality of chips 10 and dicing lanes 20 between adjacent chips 10 .

[0195] The chip seal ring structure according to the fourth embodiment of the present invention is located between the peripheral area of ​​the chip 10 and the dicing street 20 .

[0196] The pad metal layer pattern 17 is located in the area surrounding the chip 10 , and the pad metal layer pattern 17 is wrapped in the insulating dielectric layer 13 .

[0197] The insulating dielectric layer 13 has a pad opening 171 formed above the pad metal layer pattern 17 . The pad opening 171 also passes through the isolation film 15 to expose a portion of the pad metal layer pattern 17 as a chip pad, thereby exposing the pad area of ​​the chip 10 .

[0198] The semiconductor device structure of this embodiment adopts the chip sealing ring structure of the fourth embodiment of the present invention. On a wafer with a plurality of chips, a chip sealing ring structure is simultaneously prepared between the surrounding area of ​​each chip and the cutting path, and a chip circuit area manufacturing process is utilized to form a pad metal layer pattern while forming a metal stiffening ring structure, and a pad opening is formed above the pad metal layer pattern to open the pad area of ​​each chip, and finally the wafer is cut along the cutting path to obtain a plurality of semiconductor chips. When the wafer cutting process is performed along the cutting path, the chip sealing ring structure can effectively block stress expansion and rupture capabilities, and at the same time has a strong gas-liquid blocking capability for the parts of the chip that are prone to gas-liquid erosion problems, and can effectively resist the erosion of water vapor or other gas-liquid, and therefore has excellent electrical performance and reliability.

[0199] In summary, the chip sealing ring structure and the manufacturing method thereof, the semiconductor chip and the manufacturing method thereof of the present invention have the following beneficial effects:

[0200] The chip sealing ring structure and preparation method thereof of the present invention first form an isolation opening for the part of the chip that is prone to gas-liquid corrosion, and then use an isolation film to cover the isolation opening, so as to enhance the gas-liquid blocking ability for the part of the chip that is prone to gas-liquid corrosion, thereby preventing it from being oxidized or corroded by gas and liquid; that is, without increasing the process flow, the chip circuit area manufacturing process is used to form an isolation opening in the insulating dielectric layer, the isolation opening has a first pattern that is non-aligned and partially overlaps with the metal stiffening ring structure, and can reveal the first surface part of the metal stiffening ring structure and the second surface part of the bottom protective layer, and then an isolation film is formed on the insulating dielectric layer, and the isolation film has a pattern that completely overlaps the isolation opening. The second pattern enables the isolation film to cover the first surface portion of the metal stiffening ring structure and the second surface portion of the bottom protective layer, which can effectively prevent the metal layer in the first surface portion of the metal stiffening ring structure from being directly exposed to the air and oxidized or corroded by oxygen, water vapor or other gases and liquids during the manufacturing process, greatly enhancing the gas-liquid blocking ability for the first surface portion of the metal stiffening ring structure, that is, enhancing the gas-liquid blocking ability for the chip that is prone to gas-liquid corrosion problems, and does not reduce the ability to block stress expansion and rupture; compared with the prior art that mainly blocks oxygen, it also enhances the ability to resist corrosion from water vapor or other gases and liquids, thereby avoiding the impact on the electrical performance and reliability of the chip.

[0201] The semiconductor chip and the preparation method thereof of the present invention adopt the chip sealing ring structure and the preparation method thereof of the present invention. On a wafer with a plurality of chips, a chip sealing ring structure is simultaneously prepared between the surrounding area of ​​each chip and the cutting path, and a chip circuit area manufacturing process is utilized to form a pad metal layer pattern while forming a metal stiffening ring structure, and a pad opening is formed above the pad metal layer pattern to open the pad area of ​​each chip, and finally the wafer is cut along the cutting path to obtain a plurality of semiconductor chips. When the wafer cutting process is performed along the cutting path, the chip sealing ring structure can effectively block stress expansion and rupture capabilities, and at the same time has a strong gas-liquid blocking capability for the parts of the chip that are prone to gas-liquid erosion problems, and can effectively resist the erosion of water vapor or other gas-liquids. Therefore, the semiconductor chip obtained by the above method has excellent electrical performance and reliability.

[0202] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0203] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a chip sealing ring structure, characterized in that: The steps include: Providing a chip (10), wherein a bottom protection layer (11) is formed on an active surface of the chip (10); A metal stiffening ring structure (12) and an insulating dielectric layer (13) covering the metal stiffening ring structure (12) are formed on the bottom protection layer (11), the metal stiffening ring structure (12) is located at the periphery of the chip (10), a first surface portion (12a) of the metal stiffening ring structure (12) comprises a partial area of ​​at least one continuous metal ring structure, the continuous metal ring structure is formed by staggered stacking of a plurality of barrier layers (122) and metal layers (121) and plug portions (123), and metal interconnection is achieved between the metal layers (121) via the barrier layers (122) and the plug portions (123); An isolation opening (132) is formed in the insulating dielectric layer (13), the isolation opening exposing a first surface portion (12a) of the metal stiffening ring structure (12), and the isolation opening (132) has a first pattern that is non-aligned and partially overlaps the metal stiffening ring structure (12), so that the isolation opening (132) also exposes a second surface portion (11a) of the bottom protective layer (11); and An isolation film (15) is formed on the insulating dielectric layer (13), wherein the isolation film (15) has a second pattern that completely overlaps the isolation opening (132), so that the isolation film (15) covers a first surface portion (12a) of the metal stiffening ring structure (12) and a second surface portion (11a) of the bottom protective layer (11).

2. The method for preparing a chip sealing ring structure according to claim 1, characterized in that: The size of the second pattern is greater than that of the first pattern, so that the isolation film (15) also covers the side wall of the isolation opening (132) and extends onto the insulating dielectric layer (13).

3. The method for preparing a chip sealing ring structure according to claim 1, characterized in that: The size of the second pattern is equal to the size of the first pattern, so that the isolation film (15) also covers the side wall of the isolation opening (132).

4. The method for preparing a chip sealing ring structure according to claim 1, characterized in that: The step of forming an isolation opening (132) in the insulating dielectric layer (13) comprises: A first light mask (14) is arranged on the insulating dielectric layer (13), wherein the first light mask (14) has a light mask opening (141) aligned with a first surface portion (12a) of the metal stiffening ring structure (12) and a second surface portion (11a) of the bottom protective layer (11); and Based on the pattern of the mask opening (141) of the first mask (14), the insulating dielectric layer (13) is etched until the isolation opening (132) having a pattern corresponding to the mask opening (141) is formed, thereby exposing a first surface portion (12a) of the metal stiffening ring structure (12) and a second surface portion (11a) of the bottom protective layer (11).

5. The method for preparing a chip sealing ring structure according to claim 4, characterized in that: In the process of etching the insulating dielectric layer (13), the etching stops at the bottom protection layer (11).

6. The method for preparing a chip sealing ring structure according to claim 1, characterized in that: The width of the isolation opening (132) is greater than or equal to the unit ring width of the metal stiffening ring structure (12), and the width of the isolation membrane (15) formed subsequently is greater than or equal to the unit ring width of the metal stiffening ring structure (12).

7. The method for preparing a chip sealing ring structure according to claim 1, characterized in that: The metal stiffening ring structure (12) is a multi-ring structure with a ring gap (124) between the inner and outer rings, the width of the isolation opening (132) is greater than or equal to the width of the ring gap (124) of the metal stiffening ring structure (12), and the width of the isolation membrane (15) formed subsequently is greater than or equal to the width of the ring gap (124) of the metal stiffening ring structure (12).

8. The method for preparing a chip sealing ring structure according to claim 1, characterized in that: The first surface portion (12a) of the metal stiffening ring structure (12) is located on the side or corner of the active surface of the chip (10), and includes at least one side or corner portion of the continuous metal ring structure.

9. The method for preparing a chip sealing ring structure according to claim 8, characterized in that: The metal stiffening ring structure (12) further comprises at least one corner stiffening structure located outside the corner portion of the continuous metal ring structure, and the corner stiffening structure has the same interlayer structure as the continuous metal ring structure.

10. The method for preparing a chip sealing ring structure according to claim 9, characterized in that: The first surface portion (12a) of the metal stiffening ring structure (12) is located at the corner stiffening structure.

11. The method for preparing a chip sealing ring structure according to claim 10, characterized in that: The corner reinforcement structure is composed of three metal segments which are connected in sequence to form a double obtuse angle.

12. The method for preparing a chip sealing ring structure according to claim 1, characterized in that: The material of the isolation film (15) comprises nitride or oxynitride, the material of the bottom protection layer (11) comprises silicon carbon nitride, and the material of the insulating dielectric layer (13) comprises oxide.

13. The method for preparing a chip sealing ring structure according to claim 1, characterized in that: The method for preparing the chip sealing ring structure further includes: A top cover layer (16) covering the isolation film (15) is formed on the insulating dielectric layer (13).

14. A method for preparing a semiconductor chip, characterized in that: The method for preparing the semiconductor chip at least comprises: preparing a chip sealing ring structure by using the method for preparing a chip sealing ring structure according to any one of claims 1 to 13.

15. A method for preparing a semiconductor chip, characterized in that: The method for preparing the semiconductor chip at least comprises: Providing a wafer, on which a plurality of chips (10) and a dicing road (20) located between adjacent chips (10) are prepared; A chip sealing ring structure is prepared by using the method for preparing a chip sealing ring structure as claimed in claim 1, wherein the chip sealing ring structure is prepared between the peripheral area of ​​the chip (10) and the cutting path (20); wherein a pad metal layer pattern (17) is formed while forming the metal stiffening ring structure (12), the pad metal layer pattern (17) is located in the peripheral area of ​​the chip (10), and the pad metal layer pattern (17) is wrapped in the insulating medium layer (13); A pad opening (171) is formed above the pad metal layer pattern (17) to expose the pad region of the chip (10).

16. The method for preparing a semiconductor chip according to claim 15, characterized in that: The step of forming a pad opening (171) above the pad metal layer pattern (17) comprises: forming a top covering layer (16) on the isolation film (15); A second light mask (18) is disposed on the top covering layer (16); The second photomask (18) is used to pattern the top cover layer (16), and to etch the isolation film (15) and the insulating dielectric layer (13) until the pad opening (171) is formed above the pad metal layer pattern (17), and the portion of the pad metal layer pattern (17) exposed in the pad opening (171) serves as a chip pad, thereby exposing the pad area of ​​the chip (10).

17. The method for preparing a semiconductor chip according to claim 15, characterized in that: The method for preparing the semiconductor chip further includes: The wafer is cut along the cutting path (20) to obtain a plurality of semiconductor chips.

18. A chip sealing ring structure, characterized in that: The chip sealing ring structure at least includes: A chip (10), wherein a bottom protection layer (11) is formed on the chip (10); A metal stiffening ring structure (12) and an insulating dielectric layer (13) covering the metal stiffening ring structure (12) are formed on the bottom protective layer (11); the metal stiffening ring structure (12) is located at the periphery of the chip (10); the metal stiffening ring structure (12) comprises at least one continuous metal ring structure; the continuous metal ring structure is formed by staggered stacking of a plurality of barrier layers (122) and metal layers (121) and plug portions (123); and the metal layers (121) are connected by the barrier layers. The metal layer (122) and the plug portion (123) are connected to realize metal interconnection; wherein an isolation opening (132) is formed in the insulating dielectric layer (13), the isolation opening exposing a first surface portion (12a) of the metal stiffening ring structure (12), and the isolation opening (132) has a first pattern that is non-aligned and partially overlaps with the metal stiffening ring structure (12), so that the isolation opening (132) also exposes a second surface portion (11a) of the bottom protective layer (11); and, An isolation film (15) is formed on the insulating dielectric layer (13), the isolation film (15) having a second pattern that completely overlaps the isolation opening (132), so that the isolation film (15) covers the first surface portion (12a) of the metal stiffening ring structure (12) and the second surface portion (11a) of the bottom protective layer (11), the material of the isolation film (15) comprises nitride or oxynitride, the material of the bottom protective layer (11) comprises silicon carbon nitride, and the material of the insulating dielectric layer (13) comprises oxide.

19. The chip sealing ring structure according to claim 18, characterized in that: The size of the second pattern is greater than that of the first pattern, so that the isolation film (15) also covers the side wall of the isolation opening (132) and extends onto the insulating dielectric layer (13).

20. The chip sealing ring structure according to claim 18, characterized in that: The size of the second pattern is equal to the size of the first pattern, so that the isolation film (15) also covers the side wall of the isolation opening (132).

21. The chip sealing ring structure according to claim 18, characterized in that: The width of the isolation opening (132) is greater than or equal to the unit ring width of the metal stiffening ring structure (12), and the width of the isolation membrane (15) is greater than or equal to the unit ring width of the metal stiffening ring structure (12).

22. The chip sealing ring structure according to claim 18, characterized in that: The metal stiffening ring structure (12) is a multi-ring structure with a ring gap (124) between the inner and outer rings, the width of the isolation opening (132) is greater than or equal to the ring gap (124) of the metal stiffening ring structure (12), and the width of the isolation membrane (15) is greater than or equal to the ring gap (124) of the metal stiffening ring structure (12).

23. The chip sealing ring structure according to claim 18, characterized in that: The isolation opening (132) exposes a first surface portion (12a) of the metal stiffening ring structure (12), and the first surface portion (12a) of the metal stiffening ring structure (12) includes a partial area of ​​at least one continuous metal ring structure.

24. The chip sealing ring structure according to claim 18, characterized in that: The first surface portion (12a) of the metal stiffening ring structure (12) is located on the side or corner of the active surface of the chip (10), and includes at least one side or corner portion of the continuous metal ring structure.

25. The chip sealing ring structure according to claim 24, characterized in that: The metal stiffening ring structure (12) further comprises at least one corner stiffening structure located outside the corner portion of the continuous metal ring structure, and the corner stiffening structure has the same interlayer structure as the continuous metal ring structure.

26. The chip sealing ring structure according to claim 25, characterized in that: The first surface portion (12a) of the metal stiffening ring structure (12) is located at the corner stiffening structure.

27. The chip sealing ring structure according to claim 25, characterized in that: The corner reinforcement structure is composed of three metal segments which are connected in sequence to form a double obtuse angle.

28. The chip sealing ring structure according to claim 18, characterized in that: Also includes: A top cover layer (16) is formed on the insulating dielectric layer (13), and the top cover layer (16) covers the isolation film (15).

29. A semiconductor chip, characterized in that: At least: The chip sealing ring structure according to any one of claims 18 to 28.

30. A semiconductor device structure, characterized in that: At least: A wafer, on which a plurality of chips (10) and a dicing path (20) located between adjacent chips (10) are prepared; The chip sealing ring structure according to any one of claims 18 to 28, located between the peripheral area of ​​the chip (10) and the dicing street (20); and A pad metal layer pattern (17) is located in a region surrounding the chip (10), and the pad metal layer pattern (17) is wrapped in the insulating dielectric layer (13); The insulating dielectric layer (13) has a pad opening (171) formed above the pad metal layer pattern (17); the pad opening (171) also penetrates the isolation film (15) to expose a portion of the pad metal layer pattern (17) as a chip pad, thereby exposing the pad area of ​​the chip (10).

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