A subthreshold digital circuit timing optimization method and system

Abstract

The present invention discloses a subthreshold digital circuit timing optimization method and system. The method first determines the logic unit circuit that can improve the performance by using the reverse short channel effect; then performs timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirements; then determines a number of main delay units in each signal path that does not meet the timing requirements that can improve the performance by using the reverse short channel effect; finally, the reverse short channel effect is used to increase the gate length of the device of the main delay unit according to the preset timing constraint condition to optimize the timing of the subthreshold digital circuit by adjusting the gate length size. The present invention increases the gate length of the device of the main delay unit by using the reverse short channel effect to achieve timing optimization, improve the circuit performance of the subthreshold digital circuit, and reduce the delay time of the unit; at the same time, the consistency of the unit delay is improved by increasing the area, thereby enhancing the robustness of the circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit timing optimization, and in particular to a sub-threshold digital circuit timing optimization method and system. Background Art

[0002] Subthreshold digital circuits refer to digital logic circuits whose operating voltage is lower than the threshold voltage of transistor devices. Since the circuit operates in the subthreshold region, the dynamic power consumption and static power consumption of the circuit can be greatly reduced. And precisely because the device operates in the subthreshold region, the current and voltage of the device are exponentially related. Changes in device size will lead to significant changes in current and parasitic capacitance, which will significantly change the electrical performance of the circuit. In addition, the circuit performance fluctuates greatly with PVT (Process-Voltage-Temperature) deviations. In order to make the designed subthreshold digital circuit have higher robustness, the statistical analysis and optimization of PVT deviations need to be considered in the design optimization process of subthreshold digital circuits. This will exponentially increase the complexity of device size optimization of subthreshold digital circuits, making the device optimization speed process extremely slow.

[0003] At present, with the increase in the scale of subthreshold digital circuits, the statistical analysis and optimization of PVT deviation combined with traditional random optimization algorithms and heuristic optimization algorithms can no longer be directly applied to the optimization of large-scale subthreshold digital circuits, especially large-scale subthreshold digital timing circuits. In addition, in order to improve the performance of subthreshold digital circuits, the traditional method is to increase the gate width / gate length ratio of the MOS device in the circuit. However, increasing the gate width will significantly increase the area, which will cause the height of the cells in the standard cell library used to be discretized, further causing area waste; and reducing the gate length of the cells working in the subthreshold region may reduce the performance of the cells due to the reverse short channel effect, and at the same time, the performance distribution of the cells will become flatter due to the reduction of the product of gate width-gate length, thereby reducing the robustness of the circuit design. Summary of the invention

[0004] The present invention proposes a subthreshold digital circuit timing optimization method and system, which utilizes the reverse short channel effect to increase the gate length of the device of the main delay unit to achieve timing optimization, improve the circuit performance of the subthreshold digital circuit, and reduce the delay time of the unit; at the same time, the consistency of the unit delay is improved by increasing the area, thereby enhancing the robustness of the circuit.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A subthreshold digital circuit timing optimization method, comprising:

[0007] Identify logic cell circuits that can exploit the reverse short channel effect to improve performance;

[0008] Performing timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirements, the signal paths including: a latch and its front-end combinational logic or a trigger and its front-end combinational logic;

[0009] Determine several main delay units in each of the signal paths that do not meet the timing requirements, which can utilize the reverse short channel effect to improve performance;

[0010] The reverse short channel effect is utilized to increase the gate length of the device of the main delay unit according to the preset timing constraint condition, so as to optimize the timing of the sub-threshold digital circuit by adjusting the gate length size.

[0011] Furthermore, the step of determining a logic unit circuit whose performance can be improved by utilizing the reverse short channel effect includes:

[0012] Obtaining a logic unit circuit in a used logic unit library or a logic unit circuit referenced in a design to be optimized;

[0013] For each of the logic unit circuits, the gate length of the MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained by simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit under the corresponding gate length, and the gate length-delay data is obtained;

[0014] Check the gate length-delay data to see if there is an area with a delay less than the delay under the original gate length in the area where the gate length is greater than the original gate length;

[0015] If so, the logic unit circuit is classified as a logic unit circuit that can utilize the reverse short channel effect to improve performance; otherwise, it is classified as a logic unit circuit that cannot utilize the reverse short channel effect to improve performance.

[0016] Furthermore, it also includes:

[0017] For the logic unit circuit that can utilize the reverse short channel effect to improve performance, the gate length of the MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained by simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit, and a delay-gate length relationship query table of the logic unit circuit is established.

[0018] Furthermore, it also includes:

[0019] For the logic unit circuit that can improve performance by utilizing the reverse short channel effect, the gate length of the MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained by simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit, and the power consumption of the logic unit circuit under the delay is obtained, and a delay-power consumption relationship query table of the logic unit circuit is established.

[0020] Furthermore, it also includes:

[0021] For the logic unit circuit that can utilize the reverse short channel effect to improve performance, the minimum delay of the logic unit circuit under a preset gate width and the maximum value of the delay reduction coefficient relative to the original gate length, that is, the performance optimization coefficient of the logic unit circuit, are obtained.

[0022] Furthermore, it also includes:

[0023] For the design that meets the timing constraints, its gate length is used as the initial value, and the gate length is fine-tuned through the optimization algorithm. On the premise of meeting the preset timing constraints, the power consumption of the logic unit circuit is estimated using the gate length-power consumption relationship query table to optimize the power consumption of the circuit.

[0024] Furthermore, the step of performing timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirements includes:

[0025] Perform timing analysis on a given integrated circuit using statistical timing analysis tools or based on circuit statistical simulation to obtain the delay distribution of all signal paths;

[0026] Determining whether the delay distribution of each of the signal paths satisfies the preset timing constraint condition;

[0027] The signal paths that do not meet the preset timing constraint conditions are listed as signal paths that do not meet the timing requirements.

[0028] Furthermore, the step of determining several main delay unit circuits in each signal path that does not meet the timing requirement, which can utilize the reverse short channel effect to improve performance, includes:

[0029] If the logic unit circuit in the signal path that does not meet the timing requirement is a calibrated logic unit circuit that can improve performance by using the reverse short channel effect, then the logic unit circuit is included in the main delay unit circuit that can improve performance by using the reverse short channel effect;

[0030] If the latch or trigger in the signal path that does not meet the timing requirement is a calibrated logic unit circuit that can utilize the reverse short channel effect to improve performance, it will be included in the main delay unit circuit that can utilize the reverse short channel effect to improve performance.

[0031] A subthreshold digital circuit timing optimization system, comprising:

[0032] A first determining unit, used to determine a logic unit circuit whose performance can be improved by utilizing a reverse short channel effect;

[0033] An analysis unit, used to perform timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirements, wherein the signal paths include: a relay and its front-end combinational logic;

[0034] A second determining unit, used to determine a number of main delay units in each of the signal paths that do not meet the timing requirements, the performance of which can be improved by using the reverse short channel effect;

[0035] The adjustment unit is used to increase the gate length of the device of the main delay unit according to the preset timing constraint condition by utilizing the reverse short channel effect, so as to optimize the timing of the sub-threshold digital circuit by adjusting the gate length size.

[0036] Furthermore, the first determining unit includes:

[0037] An acquisition unit, used to acquire a logic unit circuit in a used logic unit library or a logic unit circuit referenced in a design to be optimized;

[0038] A processing unit, configured to change the gate length of the MOS device in each of the logic unit circuits, obtain the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measure the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit under the corresponding gate length, and obtain gate length-delay data;

[0039] A checking unit, used for checking the gate length-delay data, to check whether there is an area with a delay less than the delay under the original gate length in an area where the gate length is greater than the original gate length;

[0040] If so, the logic unit circuit is classified as a logic unit circuit that can utilize the reverse short channel effect to improve performance; otherwise, it is classified as a logic unit circuit that cannot utilize the reverse short channel effect to improve performance.

[0041] Through the above technical solution, it can be known that compared with the prior art, the present invention discloses a subthreshold digital circuit timing optimization method and system, which first determines the logic unit circuit that can use the reverse short channel effect to improve performance; then performs timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirements; then determines a number of main delay units in each signal path that does not meet the timing requirements that can use the reverse short channel effect to improve performance; finally, the reverse short channel effect is used to increase the gate length of the device of the main delay unit according to the preset timing constraint conditions to optimize the timing of the subthreshold digital circuit by adjusting the gate length size. The present invention uses the reverse short channel effect to increase the gate length of the device of the main delay unit to achieve timing optimization, improve the circuit performance of the subthreshold digital circuit, and reduce the delay time of the unit; at the same time, the area increase is used to improve the consistency of the unit delay, thereby enhancing the robustness of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0043] Figure 1 A flow chart of a sub-threshold digital circuit timing optimization method provided by an embodiment of the present invention;

[0044] Figure 2 A flowchart of a specific implementation method of step S101 provided in an embodiment of the present invention;

[0045] Figure 3 A flowchart of a specific implementation method of step S102 provided in an embodiment of the present invention;

[0046] Figure 4 A structural diagram of a sub-threshold digital circuit timing optimization system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] like Figure 1As shown, an embodiment of the present invention provides a sub-threshold digital circuit timing optimization method, which may specifically include the following steps:

[0049] S101. Determine a logic unit circuit whose performance can be improved by utilizing a reverse short channel effect.

[0050] In the embodiment of the present invention, Figure 2 FIG. 1 is a specific implementation of the above step S101. Specifically, the above step of determining the logic unit circuit whose performance can be improved by utilizing the reverse short channel effect includes:

[0051] S201. Obtain a logic unit circuit in a used logic unit library or a logic unit circuit referenced in a design to be optimized.

[0052] S202. For each logic unit circuit, change the gate length of the MOS device in the above logic unit circuit, obtain the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measure the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit under the corresponding gate length, and obtain gate length-delay data.

[0053] S203, check the gate length-delay data to see whether there is an area with a delay less than the original gate length in the area where the gate length is greater than the original gate length. If so, execute step S204, if not, execute step S205.

[0054] S204. List the logic unit circuit as a logic unit circuit that can utilize the reverse short channel effect to improve performance.

[0055] S205 , listing the logic unit circuit as a logic unit circuit that cannot utilize the reverse short channel effect to improve performance.

[0056] Further, after determining the logic unit circuit that can utilize the reverse short channel effect to improve performance, it also includes:

[0057] For logic unit circuits that can utilize the reverse short channel effect to improve performance, the gate length of the MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained by simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit, and a delay-gate length relationship query table of the logic unit circuit is established.

[0058] Further, after determining the logic unit circuit that can utilize the reverse short channel effect to improve performance, it also includes:

[0059] For logic unit circuits that can utilize the reverse short channel effect to improve performance, the gate length of the MOS device in the logic unit circuit is changed, and the input-output waveform of the logic unit circuit under the corresponding gate length is obtained by simulating the logic unit circuit. The input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit, and the power consumption of the logic unit circuit under the delay is obtained at the same time, and a delay-power consumption relationship query table of the logic unit circuit is established.

[0060] Further, after determining the logic unit circuit that can utilize the reverse short channel effect to improve performance, it also includes:

[0061] For logic unit circuits that can utilize the reverse short channel effect to improve performance, the minimum delay of the logic unit circuit under a preset gate width and the maximum delay reduction factor relative to the original gate length, that is, the performance optimization coefficient of the logic unit circuit, are obtained.

[0062] Further, after determining the logic unit circuit that can utilize the reverse short channel effect to improve performance, it also includes:

[0063] Based on the statistical simulation of the logic unit circuit, a statistical delay-gate length relationship query table of the logic unit circuit is established.

[0064] Further, after determining the logic unit circuit that can utilize the reverse short channel effect to improve performance, it also includes:

[0065] For the design that meets the timing constraints, its gate length is used as the initial value, and the gate length is fine-tuned through the optimization algorithm. On the premise of meeting the preset timing constraints, the power consumption of the logic unit circuit is estimated using the gate length-power consumption relationship query table to optimize the power consumption of the circuit.

[0066] S102, performing timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirements, the signal paths including: a latch and its front-end combinational logic or a trigger and its front-end combinational logic.

[0067] In the embodiment of the present invention, Figure 3 FIG. 1 is a specific implementation of the above step S102. Specifically, the above step of performing timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirements includes:

[0068] S301. Perform timing analysis on a given integrated circuit using a statistical timing analysis tool or based on circuit statistical simulation to obtain delay distribution of all signal paths, where the signal paths include: a latch and its front-end combinational logic or a trigger and its front-end combinational logic.

[0069] S302, determine whether the delay distribution of each signal path meets the preset timing constraint condition, if not, execute step S303, if yes, execute step S304.

[0070] S303: List the signal paths that do not meet the preset timing constraint conditions into signal paths that do not meet the timing requirements.

[0071] S304: List the signal paths that meet the preset timing constraint conditions into the signal paths that meet the timing requirements.

[0072] In the embodiment of the present invention, each latch and its front-end combinational logic or trigger and its front-end combinational logic need to meet a preset timing constraint condition, and the preset timing constraint condition is specifically:

[0073] t Prev_FF-Pdelay,max +t CML-Pdelay,max +t FF-setup,max <α.T clock

[0074] t Prev_FF-Pdelay,min +t CML-Pdelay,min >β.t FF-hold,max

[0075] Among them, α is between (0, 1), β is between (1, ∞), t Prev_FF-Pdelay,max The maximum value of the output delay time of the previous latch or trigger; t CML-Pdelay,max T is the maximum time for the output signal of the front-end combinational logic circuit to reach the latch or trigger; clock It is the clock signal period of the sequential circuit, that is, the inverse value of the clock signal frequency; t CML-Pdelay,min The minimum time it takes for the output of the front-end combinational logic to reach the latch or trigger; t Prev_FF-Pdelay,min The minimum delay time of the previous latch or trigger data output; t FF-hold,max The maximum hold time of the data input of a latch or flip-flop; t FF-setup,max is the maximum setup time for the data input of a latch or flip-flop.

[0076] S103, determining a number of main delay units in each signal path that does not meet the timing requirement, the performance of which can be improved by utilizing the reverse short channel effect.

[0077] In the embodiment of the present invention, specifically, the step of determining several main delay unit circuits in each signal path that does not meet the timing requirement and can utilize the reverse short channel effect to improve performance includes:

[0078] If the logic unit circuit in the signal path that does not meet the timing requirements is a logic unit circuit that has been calibrated to improve performance by utilizing the reverse short channel effect, it will be included in the main delay unit circuit that can improve performance by utilizing the reverse short channel effect.

[0079] If the latch or trigger in the signal path that does not meet the timing requirements is a logic unit circuit that has been calibrated to improve performance by utilizing the reverse short channel effect, it will be included in the main delay unit circuit that can improve performance by utilizing the reverse short channel effect.

[0080] Specifically, for each front-end combinational logic circuit and latch or trigger that does not meet the timing requirements, the result of the unit whose performance can be improved by utilizing the reverse short channel effect is used to check out the main delay unit whose performance can be improved by utilizing the reverse short channel effect; if the logic unit in the front-end combinational logic circuit that does not meet the timing requirements is the aforementioned calibrated logic unit whose performance can be improved by utilizing the reverse short channel effect, it is included in the main delay unit whose performance can be improved by utilizing the reverse short channel effect, otherwise the logic unit is excluded from the unit to be optimized; the same process is performed on the latch or trigger circuit.

[0081] S104, utilizing the reverse short channel effect to increase the gate length of the device of the main delay unit according to the preset timing constraint condition, so as to optimize the timing of the sub-threshold digital circuit by adjusting the gate length size.

[0082] In the embodiment of the present invention, each latch or trigger and the front-end combinational logic circuit must comply with the above-mentioned preset timing constraints, and the preset timing constraints are:

[0083] t Prev_FF-Pdelay,max +t CML-Pdelay,max +t FF-setup,max <α.T clock

[0084] t Prev_FF-Pdelay,min +t CML-Pdelay,min >β.t FF-hold,max

[0085] Among them, T clock It is the clock signal period of the sequential circuit, that is, the inverse value of the clock signal frequency; t Prev_FF-Pdelay,max The maximum value of the output delay time of the previous latch or trigger; t CM-LPd,elay T is the maximum time for the output signal of the front-end x combinational logic circuit to reach the latch or trigger; clock It is the clock signal period of the sequential circuit, that is, the inverse value of the clock signal frequency; t CML-Pdelay,min The minimum time it takes for the output of the front-end combinational logic to reach the latch or trigger; t Prev_FF-Pdelay,min The minimum delay time of the previous latch or trigger data output; t FF-hold,max The maximum hold time of the data input of a latch or flip-flop; t FF-setup,max is the maximum setup time for the data input of a latch or flip-flop.

[0086] In addition, t CML-Pdelay,max and t CML-Pdelay,min They are determined by the maximum delay time and minimum delay time of each level of logic gates, specifically:

[0087] t CML-Pdelay,max =∑t Cell-Pdelay,max,i

[0088] t CML-Pdelay,min =∑t Cell-Pdelay,min,i

[0089] For latches or triggers and their front-end combinational logic that do not meet the above preset timing constraints, the delay space that needs to be improved is respectively positioned as follows:

[0090] t delay_improve_goal1 =(t Prev_FF-Pdelay,max +t CML-Pdelay,max +t FF-setup,max )-α.T clock

[0091] t delay_improve_goal2 =β.t FF-hold,max -(t Prev_FF-Pdelay,min +t CML-Pdelay,min )

[0092] In addition, considering that only the logic unit circuit that can utilize the reverse short channel effect is adjusted to optimize the delay performance of the front-end combinational logic circuit (the latch or trigger is not adjusted or cannot be adjusted):

[0093] -∑Δt RCSE_Cell-Pdelay,max,i ≥t delay_improve_goal1

[0094] ∑Δt RCSE_Cell-Pdelay,min,i ≥t delay_improve_goal2

[0095] In addition, considering adjusting the unit (including latch or flip-flop) that can utilize the reverse short channel effect to optimize the delay performance of the front-end combinational logic circuit:

[0096] -∑Δt RCSE_Cell-Pdelay，max，i -Δt Prev_FF-Pdelay，max -Δt FF-setup，max ≥t delay_improve_goal1

[0097] ∑Δt RCSE_Cell-Pdelay，min,i -Δt FF-hold，max +Δt Prev_FF-Pdelay，min ≥t delay_improve_goal2

[0098] in:

[0099] Δt RCSE_Cell-Pdelay，max，i =t RCSE_Cell-Pdelay，max，i，new -tRCSE_Cell-Pdelay，max，I，org

[0100] Δt RCSE_Cell-Pdelay，min，i =t RCSE_Cell-Pdelay，min，i，new -t RCSE_Cell-Pdelay，min，i，org

[0101] Δt Prev_FF-Pdelay，max =t Prev_FF-Pdelay，max，new -t Prev_FF-Pdelay，max，org

[0102] Δt Prev_FF-Pdelay，min =t Prev_FF-Pdelay,min,new -t Prev_FF-Pdelay,min,org

[0103] Δt FF-setup，max =t FF-setup，max，new -t FF-setup，max，org

[0104] Δt FF-hold，max =t FF-hold，max，new -t FF-hold，max，org

[0105] Specifically, RCSE_Cell-Pdelay,max,i,new The maximum delay time after adjusting the gate length of the logic unit i that can utilize the reverse short channel effect to improve the delay performance; t RCSE_Cell-Pdelay,max,I,org The maximum delay time before the gate length (i.e., the original gate length) of the logic unit i that can utilize the reverse short channel effect to improve the delay performance is adjusted; t RCSE_Cell-Pdelay,min,i,new The minimum delay time after adjusting the gate length of the logic unit i that can utilize the reverse short channel effect to improve the delay performance; t RCSE_Cell-Pdelay,min,i,org The minimum delay time before adjusting the gate length (i.e., the original gate length) of the logic unit i that can utilize the reverse short channel effect to improve the delay performance; t Prev_FF-Pdelay,max,new The maximum delay time after adjusting the gate length of the previous latch or trigger that can utilize the reverse short channel effect to improve the delay performance; t Prev_FF-Pdelay,max,org The maximum delay time before the gate length (i.e., the original gate length) of the preceding latch or trigger that can utilize the reverse short channel effect to improve the delay performance is adjusted; t Prev_FF-Pdelay,min,new The minimum delay time after adjusting the gate length of the previous latch or trigger that can utilize the reverse short channel effect to improve the delay performance; t Prev_FF-Pdelay,min,org The minimum delay time before the gate length (i.e., the original gate length) of the preceding latch or trigger that can utilize the reverse short channel effect to improve the delay performance is adjusted; t FF-setup,max,new The maximum setup time of input data after adjusting the gate length for latches or flip-flops that can utilize the reverse short channel effect to improve delay performance; t FF-setup,max,org The maximum setup time of input data before adjusting the gate length (i.e., the original gate length) for a latch or trigger that can utilize the reverse short channel effect to improve delay performance; t FF-hold,max,newThe maximum input data hold time after adjusting the gate length for a latch or flip-flop that can utilize the reverse short channel effect to improve delay performance; t FF-hold,max,org The maximum holding time of input data before adjusting the gate length (i.e., the original gate length) for a latch or trigger that can utilize the reverse short channel effect to improve the delay performance.

[0106] For the system of inequalities:

[0107] -∑Δt RCSE_Cell-Pdelay,max,i ≥t delay_improve_goal1

[0108] ∑Δt RCSE_Cell-Pdelay，min，i ≥t delay_improve_goal2

[0109] or

[0110] -∑Δt RCSE_Cell-Pdelay,max,i -Δt FF-setup,max ≥t delay_improve_goal1 +Δt Prev_FF-Pdelay,max

[0111] ∑Δt RCSE_Cell-Pdelay,min,i -Δt FF-hold,max ≥t delay_improve_goal2 -Δt Prev_FF-Pdelay,min

[0112] Solve and get: Δt of each adjustable logic unit circuit RCSE_Cell-Pdelay,max,i The minimum value of each adjustable logic unit Δt RCSE_Cell-Pdelay,min,i The maximum value of each adjustable latch or flip-flop Δt FF-setup,max The maximum value of each adjustable latch or flip-flop Δt FF-hold,max The maximum value of

[0113] Further according to the following four formulas:

[0114] t RCSE_Cell-Pdelay,max,i,new =t RCSE_Cell-Pdelay,max,I,org +Δt RCSE_Cell-Pdelay,max,i

[0115] t RCSE_Cell-Pdelay,min,i,new =t RCSE_Cell-Pdelay,min,i,org +Δt RCSE_Cell-Pdelay,min,i

[0116] t FF-setup,max,new =t FF-setup,max,org +Δt FF-setup,max

[0117] t FF-hold,max,new =t FF-hold,max,org +Δt FF-hold,max

[0118] The delay of the unit under the new gate length can be obtained: t RCSE_Cell-Pdelay,max,i,new ;tRCSE_Cell-Pdelay,min,i,new ;t FF-setup,max,new and t FF-hold,max,new .

[0119] According to the delay-gate length relationship query table of the unit established above, the gate length of the corresponding adjustable logic unit after adjustment is obtained, and the delay t of the unit under the new gate length is RCS_EC-ellP,dela,y,max、i t RCSE_Cell-Pdelay,min,i,new ,t FF-setup,max,new and t FF-hold,max,new The corresponding front-end combinational logic circuit and latch or trigger circuit can meet the timing requirements. Thus, the timing is optimized by adjusting the gate length.

[0120] Furthermore, taking the above-adjusted gate length as the initial value, the gate length is fine-tuned through an optimization algorithm, and on the premise of meeting the above-mentioned preset timing constraints, the unit power consumption is estimated using the above-established gate length-power consumption relationship query table, thereby optimizing the power consumption of the circuit.

[0121] Furthermore, based on the sequence of the signal path, the front-end combinational logic circuit and the latch or trigger circuit combination use the reverse short channel effect to increase the gate length of the device of the main delay unit, thereby improving its circuit performance, reducing the delay time of the unit, and improving the consistency of the unit delay, thereby achieving timing optimization and improving the delay consistency of the path.

[0122] A subthreshold digital circuit timing optimization method disclosed in an embodiment of the present invention first determines a logic unit circuit that can improve performance by using a reverse short channel effect; then performs a timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirements; then determines a number of main delay units in each signal path that does not meet the timing requirements that can improve performance by using a reverse short channel effect; finally, uses a reverse short channel effect to increase the gate length of the device of the main delay unit according to a preset timing constraint condition to optimize the timing of the subthreshold digital circuit by adjusting the gate length size. The present invention increases the gate length of the device of the main delay unit by using a reverse short channel effect to achieve timing optimization, improve the circuit performance of the subthreshold digital circuit, and reduce the delay time of the unit; at the same time, increases the area to improve the consistency of the unit delay, thereby enhancing the robustness of the circuit.

[0123] See also Figure 4 Based on the sub-threshold digital circuit timing optimization method disclosed in the above embodiment, this embodiment correspondingly discloses a sub-threshold digital circuit timing optimization system, which specifically includes: a first determination unit 401, an analysis unit 402, a second determination unit 403 and an adjustment unit 404, wherein:

[0124] A first determining unit 401 is used to determine a logic unit circuit whose performance can be improved by utilizing the reverse short channel effect;

[0125] The analysis unit 402 is used to perform timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirements, wherein the signal paths include: a relay and its front-end combinational logic;

[0126] A second determining unit 403 is used to determine a number of main delay units in each signal path that does not meet the timing requirement, the performance of which can be improved by using the reverse short channel effect;

[0127] The adjustment unit 404 is used to increase the gate length of the device of the main delay unit according to the preset timing constraint condition by utilizing the reverse short channel effect, so as to optimize the timing of the sub-threshold digital circuit by adjusting the gate length size.

[0128] Furthermore, the first determining unit 401 specifically includes: an acquiring unit 4011, a processing unit 4012 and a checking unit 4013, wherein:

[0129] An acquisition unit 4011 is used to acquire a logic unit circuit in a used logic unit library or a logic unit circuit referenced in a design to be optimized;

[0130] The processing unit 4012 is used to change the gate length of the MOS device in each logic unit circuit, obtain the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measure the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit under the corresponding gate length, and obtain gate length-delay data;

[0131] The checking unit 4013 is used to check the gate length-delay data to check whether there is an area with a delay less than the original gate length in the area where the gate length is greater than the original gate length;

[0132] If so, the logic unit circuit is classified as a logic unit circuit that can utilize the reverse short channel effect to improve performance; otherwise, it is classified as a logic unit circuit that cannot utilize the reverse short channel effect to improve performance.

[0133] The embodiment of the present invention discloses a subthreshold digital circuit timing optimization system, which determines a logic unit circuit that can improve performance by using the reverse short channel effect through a first determination unit; then performs timing analysis on a given integrated circuit through an analysis unit to obtain all signal paths that do not meet the timing requirements; then determines a number of main delay units in each signal path that does not meet the timing requirements that can improve performance by using the reverse short channel effect through a second determination unit; finally, the adjustment unit uses the reverse short channel effect to increase the gate length of the device of the main delay unit according to preset timing constraints to optimize the timing of the subthreshold digital circuit by adjusting the gate length size. The present invention increases the gate length of the device of the main delay unit by using the reverse short channel effect to achieve timing optimization, improve the circuit performance of the subthreshold digital circuit, and reduce the delay time of the unit; at the same time, the consistency of the delay of the unit is improved by increasing the area, thereby enhancing the robustness of the circuit.

[0134] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0135] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0136] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A subthreshold digital circuit timing optimization method, characterized in that: include: Identify logic cell circuits that can exploit the reverse short channel effect to improve performance; Performing timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirements, the signal paths including: a latch and its front-end combinational logic or a trigger and its front-end combinational logic; Determine several main delay units in each of the signal paths that do not meet the timing requirements, which can utilize the reverse short channel effect to improve performance; Using the reverse short channel effect, the gate length of the device of the main delay unit is increased and adjusted according to the preset timing constraint condition, so as to optimize the timing of the sub-threshold digital circuit by adjusting the gate length size; The step of determining a logic unit circuit that can utilize the reverse short channel effect to improve performance includes: Obtaining a logic unit circuit in a used logic unit library or a logic unit circuit referenced in a design to be optimized; For each of the logic unit circuits, the gate length of the MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained by simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit under the corresponding gate length, and the gate length-delay data is obtained; Check the gate length-delay data to see if there is an area with a delay less than the delay under the original gate length in the area where the gate length is greater than the original gate length; If so, the logic unit circuit is classified as a logic unit circuit that can utilize the reverse short channel effect to improve performance; otherwise, the logic unit circuit is classified as a logic unit circuit that cannot utilize the reverse short channel effect to improve performance; The step of determining a number of main delay units in each signal path that does not meet the timing requirement and can utilize the reverse short channel effect to improve performance includes: If the logic unit circuit in the signal path that does not meet the timing requirement is a calibrated logic unit circuit that can improve performance by using the reverse short channel effect, then the logic unit circuit is included in the main delay unit circuit that can improve performance by using the reverse short channel effect; If the latch or trigger in the signal path that does not meet the timing requirement is a calibrated logic unit circuit that can utilize the reverse short channel effect to improve performance, it will be included in the main delay unit circuit that can utilize the reverse short channel effect to improve performance.

2. The method according to claim 1, characterized in that Also includes: For the logic unit circuit that can utilize the reverse short channel effect to improve performance, the gate length of the MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained by simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit, and a delay-gate length relationship query table of the logic unit circuit is established.

3. The method according to claim 1, characterized in that: Also includes: For the logic unit circuit that can improve performance by utilizing the reverse short channel effect, the gate length of the MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained by simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit, and the power consumption of the logic unit circuit under the delay is obtained, and a delay-power consumption relationship query table of the logic unit circuit is established.

4. The method according to claim 1, characterized in that: Also includes: For the logic unit circuit that can utilize the reverse short channel effect to improve performance, the minimum delay of the logic unit circuit under a preset gate width and the maximum value of the delay reduction coefficient relative to the original gate length, that is, the performance optimization coefficient of the logic unit circuit, are obtained.

5. The method according to claim 1, characterized in that: Also includes: For the design that meets the timing constraints, its gate length is used as the initial value, and the gate length is fine-tuned through the optimization algorithm. On the premise of meeting the preset timing constraints, the power consumption of the logic unit circuit is estimated using the gate length-power consumption relationship query table to optimize the power consumption of the circuit.

6. The method according to claim 1, characterized in that The step of performing timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirements includes: Perform timing analysis on a given integrated circuit using statistical timing analysis tools or based on circuit statistical simulation to obtain the delay distribution of all signal paths; Determining whether the delay distribution of each of the signal paths satisfies the preset timing constraint condition; The signal paths that do not meet the preset timing constraint conditions are listed as signal paths that do not meet the timing requirements.

7. A subthreshold digital circuit timing optimization system, characterized in that: include: A first determining unit, used to determine a logic unit circuit whose performance can be improved by utilizing a reverse short channel effect; An analysis unit, used to perform timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirements, wherein the signal paths include: a relay and its front-end combinational logic; A second determining unit, used for determining a number of main delay units in each signal path that does not meet the timing requirement, the performance of which can be improved by using the reverse short channel effect; An adjustment unit, used to increase the gate length of the device of the main delay unit according to a preset timing constraint condition by utilizing a reverse short channel effect, so as to optimize the timing of the subthreshold digital circuit by adjusting the gate length size; The first determining unit includes: An acquisition unit, used to acquire a logic unit circuit in a used logic unit library or a logic unit circuit referenced in a design to be optimized; A processing unit, configured to change the gate length of the MOS device in each of the logic unit circuits, obtain the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measure the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit under the corresponding gate length, and obtain gate length-delay data; A checking unit, used for checking the gate length-delay data, to check whether there is an area with a delay less than the delay under the original gate length in an area where the gate length is greater than the original gate length; If so, the logic unit circuit is classified as a logic unit circuit that can utilize the reverse short channel effect to improve performance; otherwise, the logic unit circuit is classified as a logic unit circuit that cannot utilize the reverse short channel effect to improve performance; The second determining unit is specifically configured to: If the logic unit circuit in the signal path that does not meet the timing requirement is a calibrated logic unit circuit that can improve performance by using the reverse short channel effect, then the logic unit circuit is included in the main delay unit circuit that can improve performance by using the reverse short channel effect; If the latch or trigger in the signal path that does not meet the timing requirement is a calibrated logic unit circuit that can utilize the reverse short channel effect to improve performance, it will be included in the main delay unit circuit that can utilize the reverse short channel effect to improve performance.

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