Transmitting device, receiving device, relay device and transceiver system

Abstract

A transmitting device, a receiving device, a relay device and a transceiver system are provided. The number of communication links, power consumption and circuit layout area can be suppressed, and the increase can also be applied to long-distance transmission. The transmitting device includes a high-speed signal generating unit, a low-speed signal generating unit and a signal overlapping unit. The high-speed signal generating unit generates a high-speed signal with a limited frequency band. The low-speed signal generating unit generates a low-speed signal with a frequency lower than the frequency band of the high-speed signal. The signal overlapping unit outputs an overlapping signal obtained by overlapping the high-speed signal with the low-speed signal. The receiving device includes a signal separation unit and a restoration unit. The signal separation unit separates the high-speed signal and the low-speed signal from the received signal. The restoration unit performs frequency tracking based on the separated low-speed signal and performs phase tracking based on the separated high-speed signal.

Description

Technical Field

[0001] The invention relates to a sending device, a receiving device, a relay device and a sending and receiving system. Background Art

[0002] The clock data recovery (CDR) technology in the transceiver system is a technology in which the transmitting device outputs data embedded with a clock, and the receiving device that receives the signal including the clock recovers the clock and data. The receiving device generally has a Bang-Bang phase comparator (BBPD: Bang-Bang Phase Detector, switching phase detector) to recover the clock and data from the received signal. The receiving device uses the BBPD to detect the phase deviation between the received signal and the recovered clock, performs feedback control to reduce the phase deviation, and recovers the clock and data from the received signal.

[0003] BBPD can detect the phase deviation between the received signal and the recovered clock, but cannot detect the frequency deviation between the received signal and the recovered data. Therefore, sometimes a phenomenon of locking at an unexpected frequency occurs (hereinafter referred to as "frequency error synchronization"). In order to avoid the occurrence of this frequency error synchronization, the following technology is known: in addition to BBPD, a phase frequency comparator (PFD: Phase Frequency Detector) is also set in the receiving device to perform a frequency tracking loop (FTL: Frequency Tracking Loop) and a phase tracking loop (PTL: Phase Tracking Loop).

[0004] In the technology for avoiding the occurrence of this frequency error synchronization, when a reference clock is sent from a transmitting device to a receiving device in the first stage, the receiving device performs frequency tracking based on the reference clock by using a PFD to lock the frequency. When data embedded with a clock is sent from the transmitting device to the receiving device in the second stage after the frequency is locked, the receiving device performs phase tracking by using a BBPD to lock the phase and restore the clock and data from the received signal.

[0005] In this technology, a reference clock communication link for sending a reference clock from a transmitting device to a receiving device in FTL and a data communication link for sending data embedded with a clock from a transmitting device to a receiving device in PTL can also be separately set. In this case, when the receiving device detects that frequency locking is completed through FTL based on the reference clock in the first stage, phase locking is performed through PTL in the second stage to restore the clock and data from the data embedded with the clock. The reference clock communication link and the data communication link can be wired for transmitting electrical signals or wireless for transmitting optical signals, etc. In the case where the reference clock communication link and the data communication link transmit electrical signals, differential signal lines can be used as their signal lines to transmit high-speed (bit rate of, for example, several Gbps) electrical signals. In this technology, since the reference clock communication link and the data communication link are separately set, the number of components used for sending and receiving increases.

[0006] In addition, it is also possible to use a common communication link to send a reference clock from a transmitting device to a receiving device and to send data embedded with a clock. In this case, when the receiving device detects that the frequency lock is completed through the FTL based on the reference clock in the first stage, it sends a lock signal indicating the message to the transmitting device. The transmitting device that receives the lock signal replaces the previous reference clock and sends the data embedded with the clock to the receiving device. Then, the receiving device performs phase lock through PTL in the second stage, restores the clock and data from the received data and outputs them. In this technology, in addition to the common communication link for sending data from the transmitting device to the receiving device after the reference clock, a communication link for sending a lock signal from the receiving device to the transmitting device is also required, so the number of components used for sending and receiving is still increased.

[0007] A transceiver system having a transmitting device and a receiving device is used, for example, as a television video transmission interface. Not limited to this example, there is a case where a lot of data embedded with a clock is sent in parallel. In such a case, the increase in communication links leads to a large system. Therefore, it is preferred to reduce the number of communication links between the transmitting device and the receiving device. Inventions capable of reducing the number of communication links between the transmitting device and the receiving device are disclosed in Japanese Patent Publication No. 11-98130 (Patent Document 1) and Japanese Patent Publication No. 2005-142872 (Patent Document 2).

[0008] In the invention disclosed in Patent Document 1, a differential signal line is used as a communication link between a transmitting device and a receiving device. The transmitting device transmits a reference clock as a differential signal to the receiving device using the differential signal line in the first stage. When the receiving device detects that the frequency lock is completed by the FTL based on the reference clock in the first stage, it changes the common level of the differential signal line and sends a lock signal to the transmitting device. The transmitting device, which receives the lock signal by the change of the common level of the differential signal line, transmits data embedded with the clock as a differential signal to the receiving device using the differential signal line in the second stage. In the present invention, a communication link for sending data from the transmitting device to the receiving device after the reference clock and a communication link for sending a lock signal from the receiving device to the transmitting device are shared.

[0009] In the invention disclosed in Patent Document 2, a transmitting device multiplexes a word clock representing a delimiter of a word consisting of a continuous specified number of data included in the serial data to be transmitted with the word, and generates a logic signal to which amplitude adjustment corresponding to the word clock is implemented as output data. A receiving device extracts the serial data and the word clock from the received logic signal. In the present invention, after the phase of the word clock representing the word delimiter of the serial data is made consistent with the phase of the word of the serial data, the word clock is overlapped with the serial data as a logic signal, and the logic signal is sent from the transmitting device to the receiving device. The logic signal is a signal consisting of four logic levels. In the present invention, since a logic signal consisting of the overlap of the word clock and the serial data is sent from the transmitting device to the receiving device, it is not necessary to send a lock signal from the receiving device to the transmitting device, and a communication link for sending the lock signal is not necessary. Summary of the invention

[0010] The inventor has studied the above-mentioned prior art and found the following problems. That is, the invention disclosed in Patent Document 1 uses a common communication link to perform bidirectional signal transmission between a transmitting device and a receiving device, and therefore cannot be applied to the case where a communication link (e.g., a communication link based on light and wireless) capable of only unidirectional signal transmission is used. In addition, the invention disclosed in Patent Document 1 requires the following series of procedures, which takes time until the frequency and phase are locked again, and the series of procedures are to notify the transmitting device of the release of the frequency lock when the receiving device releases the frequency lock, to send a reference clock from the transmitting device to the receiving device, to notify the transmitting device of the frequency tracking performed by the FTL based on the reference clock in the receiving device, to send a message that the frequency lock in the receiving device has been completed, and to send data embedded with a clock from the transmitting device to the receiving device.

[0011] In the invention disclosed in Patent Document 2, a logic signal based on superposition of a word clock and serial data is transmitted from a transmitting device to a receiving device, thereby overcoming the above-mentioned problem of the invention disclosed in Patent Document 1. However, the invention disclosed in Patent Document 2 has the following problem.

[0012] In the invention disclosed in Patent Document 2, the phase of the word clock and the phase of the word of the serial data need to be made consistent with each other in the transmitting device. If there is a phase difference between the word clock and the word of the serial data, the word delimiter of the serial data represented by the word clock is wrong, so the receiving device cannot accurately convert the serial data into parallel data. The higher the transmission rate, the higher the phase consistency accuracy between the word clock and the word of the serial data is required. Therefore, in order to achieve high phase consistency accuracy, the power consumption of the circuit increases, and the layout area when the circuit is integrated on the semiconductor substrate increases.

[0013] In addition, in the invention disclosed in Patent Document 2, it is necessary to make the level transition times (Tr, Tf) of the word clock and the serial data consistent with each other in the transmitting device. If the level transition times of the word clock and the serial data are different from each other, the same problem as the case where there is a phase difference as described above occurs. In order to make the level transition time of the low-speed word clock consistent with the level transition time of the high-speed serial data, the circuit for generating the word clock needs to be high-speed. Therefore, the power consumption of the circuit is also increased, and the layout area when the circuit is integrated on a semiconductor substrate is increased.

[0014] Furthermore, in the invention disclosed in Patent Document 2, the logic signal sent from the transmitting device to the receiving device is a signal composed of four logic levels. Therefore, in order to restore the word clock and serial data from the received logic signal in the receiving device, three comparators are required. The first comparator of the three comparators compares the level of the logic signal with the first threshold. The second comparator compares the level of the logic signal with the second threshold. The third comparator compares the level of the logic signal with the third threshold. The first threshold, the second threshold, and the third threshold are set to different values. In the case where the logic signal is attenuated in the communication link between the transmitting device and the receiving device, it is necessary to change the first threshold, the second threshold, and the third threshold according to the degree of the attenuation. When the attenuation is large, it is difficult to set the first threshold, the second threshold, and the third threshold, and it is impossible to restore the word clock and serial data from the received logic signal. Therefore, the invention disclosed in Patent Document 2 is difficult to apply to long-haul transmission (long-haul transmission) in which the attenuation of the logic signal in the communication link is large.

[0015] The present invention is completed to solve the above-mentioned problems, and its purpose is to provide a sending device and a receiving device that can suppress the increase in the number of communication links, power consumption and circuit layout area and can also be used in long-distance transmission, a relay device arranged between the sending device and the receiving device, and a transceiver system having the sending device and the receiving device.

[0016] One mode of the transmitting device of the present invention comprises a high-speed signal generating unit, a low-speed signal generating unit and a signal superimposing unit. The high-speed signal generating unit generates a high-speed signal with a limited frequency band. The low-speed signal generating unit generates a low-speed signal with a frequency lower than the frequency band of the high-speed signal. The signal superimposing unit outputs a superimposed signal obtained by superimposing the high-speed signal and the low-speed signal.

[0017] One embodiment of the receiving device of the present invention comprises a signal separation unit and a restoration unit. The signal separation unit receives a superimposed signal obtained by superimposing a high-speed signal with a limited frequency band and a low-speed signal with a frequency lower than the frequency band of the high-speed signal. In addition, the signal separation unit separates the received superimposed signal into a high-speed signal and a low-speed signal. The restoration unit performs frequency tracking based on the low-speed signal output from the signal separation unit, performs phase tracking based on the high-speed signal output from the signal separation unit, and restores the clock and data.

[0018] One embodiment of the relay device of the present invention comprises a signal separation unit, a restoration unit and a signal superposition unit. The signal separation unit receives a superimposed signal obtained by superimposing a high-speed signal whose frequency band is limited and a low-speed signal whose frequency is lower than the frequency band of the high-speed signal. In addition, the signal separation unit separates the received signal into a high-speed signal and a low-speed signal. The restoration unit performs frequency tracking based on the low-speed signal output from the signal separation unit, performs phase tracking based on the high-speed signal output from the signal separation unit, and restores the clock and data. The signal superposition unit outputs a superimposed signal obtained by superimposing a high-speed signal obtained based on the data output from the restoration unit with a signal generated based on the clock output from the restoration unit (as a low-speed signal) or a low-speed signal output from the signal separation unit.

[0019] One mode of the transceiver system of the present invention comprises: a transmitting device having the above-mentioned structure; and a receiving device receiving a signal that arrives via a communication link after being output from the transmitting device, and having the above-mentioned structure. In addition, another mode of the transceiver system of the present invention comprises: a transmitting device having the above-mentioned structure; a relay device receiving a signal that arrives via a communication link after being output from the transmitting device, outputting the received signal to the communication link, and having the above-mentioned structure; and a receiving device receiving a signal that arrives via a communication link after being output from the relay device, and having the above-mentioned structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 2 is a diagram showing the configuration of the transmission and reception system 1 .

[0021] Figure 2A is a diagram for explaining the frequency bands of high-speed signals and low-speed signals, Figure 2B is used to explain the passband of the first filter 31, Figure 2C It is a diagram for explaining the passband of the second filter 32 .

[0022] Figure 3A 1 is a diagram for explaining that the high-speed signal generated by the high-speed signal generating unit 11 and the low-speed signal generated by the low-speed signal generating unit 12 are signals to be superimposed. Figure 3B is a diagram for explaining a signal (superimposed signal) output from the transmitting device 10 after superimposition by the signal superimposing unit 13, Figure 3C is a diagram for explaining a signal (received signal) input to the receiving device 20, Figure 3D This is a diagram for explaining the low-speed signal output from the second filter 32 and the high-speed signal output from the first filter 31 .

[0023] Figures 4A to 4C The diagram shows simulation results (eye patterns) when the amplitude ratio between the high-speed signal and the low-speed signal is set to 2:8.

[0024] Figures 5A to 5C This is a diagram showing simulation results (eye diagrams) when the amplitude ratio between the high-speed signal and the low-speed signal is set to 8:2.

[0025] Figure 6 It is a diagram showing a configuration example of the transmission device 10 .

[0026] Figure 7 It is a diagram showing another configuration example of the transmission device 10 .

[0027] Fig. 8A 1 is a diagram for explaining the frequency bands of the high-speed signal and the low-speed signal after SS is implemented. Figure 8B is a diagram for explaining the passband of the first filter 31. Figure 8C It is a diagram for explaining the passband of the second filter 32 .

[0028] Fig. 9 This is a table summarizing the interference amounts of the low-speed signal on the frequency band of the high-speed signal when the low-speed signal is a triangle wave with a fundamental frequency of 1 MHz and the cutoff frequency of the first filter 31 is 100 MHz.

[0029] Fig.10 It is a diagram showing another configuration example of the receiving device 20.

[0030] Fig.11Ais a diagram showing a circuit example of the signal detection unit 23, Fig. 11B This is a timing diagram of the signal waveform in each part.

[0031] Fig. 12A 2 is a diagram showing another circuit example of the signal detection unit 23. Figures 12B to 12D This is a timing diagram of the signal waveform in each part.

[0032] Fig.13 It is a diagram showing another configuration example of the receiving device 20.

[0033] Fig.14 This is a diagram for explaining the addition of noise to a signal.

[0034] Fig.15 This is a diagram for explaining the relationship between noise application and clock duty ratio.

[0035] Fig.16 It is a diagram showing another configuration example of the receiving device 20.

[0036] Fig.17 It is a diagram showing the structure of the transmission and reception system 2.

[0037] Fig.18 1 is a diagram showing a configuration example of the relay device 60 .

[0038] Fig.19 It is a diagram showing another configuration example of the relay device 60 .

[0039] Fig. 20 It is a diagram showing another configuration example of the relay device 60 .

[0040] Fig.21 It is a diagram showing another configuration example of the relay device 60 .

[0041] Fig. 22 It is a diagram showing the structure of the transmission and reception system 3.

[0042] Fig.23 1 is a diagram showing circuit configuration examples of the signal superimposing unit 13 and the signal separating unit 21 .

[0043] Fig.24 It is a diagram showing another circuit configuration example of the signal superimposing unit 13 .

[0044] Fig.25 It is a diagram showing another circuit configuration example of the signal superimposing unit 13 .

[0045] Fig.26 It is a diagram showing another circuit configuration example of the signal superimposing unit 13 .

[0046] Fig. 27 It is a diagram showing another circuit configuration example of the signal superimposing unit 13 .

[0047] Fig.28 It is a diagram showing another circuit configuration example of the signal superimposing unit 13 .

[0048] Fig.29 It is a diagram showing another circuit configuration example of the signal superimposing unit 13 .

[0049] Fig.30 2 is a diagram showing another circuit configuration example of the signal separation unit 21 .

[0050] Fig.31 2 is a diagram showing another circuit configuration example of the signal separation unit 21 .

[0051] Fig.32 2 is a diagram showing another circuit configuration example of the signal separation unit 21 .

[0052] Fig.33 2 is a diagram showing another circuit configuration example of the signal separation unit 21 . DETAILED DESCRIPTION

[0053] [Description of Embodiments of the Invention]

[0054] First, the contents of the embodiments of the present invention will be listed and described separately.

[0055] (1) The transmitting device of the present embodiment, as one mode thereof, has a high-speed signal generating unit, a low-speed signal generating unit, and a signal superimposing unit. The high-speed signal generating unit generates a high-speed signal with a limited frequency band. The high-speed signal generating unit has an output terminal provided for outputting the high-speed signal. The low-speed signal generating unit generates a low-speed signal with a frequency lower than the frequency band of the high-speed signal. The low-speed signal generating unit has an output terminal provided for outputting the low-speed signal. The signal superimposing unit generates a superimposed signal by superimposing the high-speed signal and the low-speed signal. In addition, the signal superimposing unit has a first input terminal, a second input terminal, and an output terminal. The first input terminal is electrically connected to the output terminal of the high-speed signal generating unit and is provided for taking in the high-speed signal. The second input terminal is electrically connected to the output terminal of the low-speed signal generating unit and is provided for taking in the low-speed signal. The output terminal is provided for outputting the superimposed signal.

[0056] (2) The transmitting device having the above-mentioned structure can use various methods. For example, as one method of this embodiment, preferably, the ratio of the data rate of the high-speed signal to the frequency of the low-speed signal is an integer ratio. In addition, as one method of this embodiment, preferably, the low-speed signal generating unit generates a low-speed signal having a time waveform of a sine wave or a triangle wave. As one method of this embodiment, preferably, the high-speed signal generating unit generates a high-speed signal with a limited frequency band by encoding. As one method of this embodiment, preferably, the high-speed signal generating unit generates a high-speed signal with a limited frequency band by mBnB encoding that ensures DC balance. As one method of this embodiment, preferably, the low-speed signal generating unit generates a low-speed signal that implements spread spectrum (SS). As one method of this embodiment, preferably, the high-speed signal generating unit generates a high-speed signal that implements spread spectrum (SS).

[0057] (3) Furthermore, as one mode of the present embodiment, preferably, the high-speed signal generating unit includes a serializer. The serializer converts parallel data into serial data, and outputs the serial data as a high-speed signal via the output end of the high-speed signal generating unit. In addition, preferably, the low-speed signal generating unit includes a phase-locked loop (PLL) circuit and a wiring structure. The phase-locked loop (PLL) circuit generates an indication clock and provides the indication clock to the serializer, and the indication clock indicates the timing (output timing) of each bit of the serial data output from the serializer. The wiring structure outputs the clock input to the PLL circuit or the clock output from the PLL circuit as a low-speed signal to the signal overlapping unit via the output end of the low-speed signal generating unit.

[0058] (4) As one mode of the present embodiment, preferably, the signal overlapping portion includes a first current mode logic (CML) circuit and a second current mode logic circuit, wherein the first current mode logic circuit and the second current mode logic circuit share a resistor configured between a power supply potential supply terminal and a ground potential supply terminal, and are configured between the resistor and the ground potential supply terminal. The first CML circuit has an input terminal provided for taking in a high-speed signal, and an output terminal electrically connected to the output terminal of the signal overlapping portion. The second CML circuit has an input terminal for taking in a low-speed signal, and an output terminal electrically connected to the output terminal of the signal overlapping portion. In addition, as one mode of the present embodiment, the signal overlapping portion may also include a power supply circuit and a buffer. The power supply circuit outputs a driving voltage that is amplitude modulated using a low-speed signal. The buffer is driven by the driving voltage applied from the power supply circuit to overlap the high-speed signal with the low-speed signal. In addition, the buffer has an input terminal provided for taking in a high-speed signal, and an output terminal electrically connected to the output terminal of the signal overlapping portion and provided for outputting an overlapping signal.

[0059] (5) As one aspect of the present embodiment, preferably, the phase relationship between the low-speed signal and the high-speed signal is independent.

[0060] (6) The receiving device of the present embodiment preferably has a signal separation unit and a restoration unit as one mode thereof. The signal separation unit separates a superimposed signal formed by superimposing a high-speed signal with a limited frequency band and a low-speed signal with a frequency lower than the frequency band of the high-speed signal into the high-speed signal and the low-speed signal. In addition, the signal separation unit has: an input terminal, which is provided for receiving the superimposed signal; a first output terminal, which is provided for outputting the high-speed signal separated from the superimposed signal; and a second output terminal, which is provided for outputting the low-speed signal separated from the superimposed signal. On the other hand, the restoration unit has a first input terminal and a second input terminal. The first input terminal is electrically connected to the first output terminal of the signal separation unit and is provided for taking in the high-speed signal. The second input terminal is electrically connected to the second output terminal of the signal separation unit and is provided for taking in the low-speed signal. The restoration unit performs frequency tracking based on the low-speed signal output from the second output terminal of the signal separation unit, performs phase tracking based on the high-speed signal output from the first output terminal of the signal separation unit, and restores the clock and data.

[0061] (7) As one method of the present embodiment, preferably, the data rate DR of the high-speed signal, the coefficient K corresponding to the data communication method of the high-speed signal, the frequency F of the low-speed signal, and the ratio (M / N) of the frequency of the clock at the end of frequency tracking in the recovery unit to the frequency of the low-speed signal satisfy the relationship expressed by the following formula (1).

[0062]

[0063] (8) As one mode of this embodiment, preferably, the signal separation unit includes: a first filter, which is arranged between the input end and the first output end of the signal separation unit; and a second filter, which is arranged between the input end and the second output end of the signal separation unit. The first filter selectively outputs the high-speed signal in the received overlapping signal. The second filter selectively outputs the low-speed signal in the received overlapping signal.

[0064] (9) As one method of the present embodiment, preferably, the frequency F of the low-speed signal, the data rate DR of the high-speed signal, the coefficient L corresponding to the data encoding method of the high-speed signal, the ratio Vr of the amplitude of the high-speed signal to the amplitude of the low-speed signal, and the interference tolerance Gd of the low-speed signal on the frequency band of the high-speed signal satisfy the relationship expressed by the following formula (2).

[0065]

[0066] (10) As one mode of the present embodiment, preferably, the restoration unit has a first phase comparator, a second phase comparator, a lock detector, a charge pump, a loop filter and a voltage controlled oscillator. The first phase comparator has a third input terminal, a fourth input terminal and an output terminal. The third input terminal is electrically connected to the first output terminal of the signal separation unit as the first input terminal of the restoration unit and is provided for taking in a high-speed signal. The fourth input terminal is provided for taking in an oscillation signal. The output terminal is provided for outputting a first phase difference signal indicating a phase difference between a high-speed signal and an oscillation signal. The second phase comparator has a fifth input terminal, a sixth input terminal and an output terminal. The fifth input terminal is electrically connected to the second output terminal of the signal separation unit as the second input terminal of the restoration unit and is provided for taking in a low-speed signal or a signal after frequency division of the low-speed signal. The sixth input terminal is provided for taking in an oscillation signal or a signal after frequency division of the oscillation signal. The output terminal is provided for outputting a second phase difference signal indicating a phase difference between a first input signal taken in via a fifth input terminal and a second input signal taken in via a sixth input terminal. The lock detector detects whether a frequency lock is performed between the first input signal and the second input signal. The charge pump has an input terminal and an output terminal. In the charge pump, the input terminal is provided for taking in the second phase difference signal during a period when the lock detector detects that the frequency lock is not performed, or for taking in the first phase difference signal during a period when the lock detector detects that the frequency lock is performed. The output terminal is provided for outputting a correction voltage value that reduces the phase difference indicated by the first phase difference signal or the second phase difference signal. The loop filter has an input terminal and an output terminal. In the loop filter, the input terminal is electrically connected to the output terminal of the charge pump and is provided for taking in a correction voltage value. The output terminal is provided for outputting a control voltage value that increases or decreases in accordance with a change in the correction voltage value taken in. The voltage controlled oscillator has an input terminal and an output terminal. In the voltage controlled oscillator, the input terminal is electrically connected to the output terminal of the loop filter and is provided for taking in a control voltage value. The output terminal is provided for outputting an oscillation signal having a frequency corresponding to the taken-in control voltage value. The restoration unit having the above-mentioned structure outputs restored data from the first phase comparator and outputs the restored clock from the voltage controlled oscillator as an oscillation signal during a period in which the frequency locking is detected by the lock detector.

[0067] (11) As one aspect of this embodiment, the receiving device may further include a signal detection unit that detects the presence or absence of the low-speed signal. The signal detection unit has an input terminal that is electrically connected to the second output terminal of the signal separation unit and is provided to receive the low-speed signal.

[0068] (12) As one mode of this embodiment, the receiving device may further include an error detection unit that detects whether the low-speed signal is normal. The error detection unit has an input terminal that is electrically connected to the second output terminal of the signal separation unit and is provided to take in the low-speed signal. In this case, the recovery unit stops the recovery action when the error detection unit detects that the low-speed signal is abnormal, and restarts the recovery action when the error detection unit detects that the low-speed signal is normal after the recovery action stops.

[0069] (13) As one mode of the present embodiment, the receiving device may further include: a first error detection unit that detects whether the high-speed signal is normal; and a second error detection unit that detects whether the low-speed signal is normal. The first error detection unit has an input terminal that is electrically connected to the first output terminal of the signal separation unit (or the output terminal of the first phase comparator) and is provided for taking in the high-speed signal. The second error detection unit has an input terminal that is electrically connected to the second output terminal of the signal separation unit and is provided for taking in the low-speed signal. The recovery unit stops the recovery action when the first error detection unit detects that the high-speed signal is abnormal, and restarts the recovery action when the second error detection unit detects that the low-speed signal is normal after the recovery action stops.

[0070] (14) As one aspect of the present embodiment, preferably, the phase relationship between the low-speed signal and the high-speed signal is independent.

[0071] (15) The relay device of this embodiment, as one mode thereof, has a signal separation unit, a restoration unit, and a signal superposition unit. The signal separation unit separates the superimposed signal obtained by superimposing a high-speed signal whose frequency band is limited and a low-speed signal whose frequency is lower than the frequency band of the high-speed signal into a high-speed signal and a low-speed signal. In addition, the signal separation unit has an input end, a first output end, and a second output end. The input end is provided for receiving the superimposed signal. The first output end is provided for outputting the high-speed signal separated from the superimposed signal. The second output end is provided for outputting the low-speed signal separated from the superimposed signal. The restoration unit has a first input end and a second input end. The first input end is electrically connected to the first output end of the signal separation unit and is provided for taking in the high-speed signal. The second input end is electrically connected to the second output end of the signal separation unit and is provided for taking in the low-speed signal. The restoration unit performs frequency tracking based on the low-speed signal output from the second output end of the signal separation unit, performs phase tracking based on the high-speed signal output from the first output end of the signal separation unit, and restores the clock and data. The signal superposition unit outputs a superimposed signal obtained by superimposing a high-speed signal obtained from the restored data with a low-speed signal generated according to the restored clock or a low-speed signal output from the second output terminal of the signal separation unit. In addition, the signal superposition unit has a first input terminal, a second input terminal and an output terminal. The first input terminal is provided for taking in a high-speed signal. The second input terminal is provided for taking in a signal generated according to the restored clock or a low-speed signal. The output terminal is provided for outputting the superimposed signal.

[0072] (16) As one aspect, the transceiver system of the present embodiment preferably comprises: a transmitting device (the transmitting device of the present embodiment) having the structure as described above; and a receiving device having the structure as described above. In addition, as one aspect of the present embodiment, the transceiver system may comprise: a transmitting device (the transmitting device of the present embodiment) having the structure as described above; one or more relay devices (the relay devices of the present embodiment) each having the structure as described above; and a receiving device (the receiving device of the present embodiment) having the structure as described above. In addition, the relay device is arranged on the communication link, receives the superimposed signal arriving from the transmitting device via the communication link, and outputs the superimposed signal to the receiving device via the communication link.

[0073] (17) As one mode of the present embodiment, the transceiver system may include a plurality of communication units, each of which has the same structure as a communication unit consisting of a transmitting device (transmitting device of the present embodiment) and a receiving device (receiving device of the present embodiment) connected via a communication link. In particular, any transmitting device among the transmitting devices included in the plurality of communication units outputs an overlapping signal obtained by overlapping a high-speed signal with a low-speed signal, and on the other hand, the remaining transmitting devices output non-overlapping high-speed signals. In addition, among the receiving devices included in the plurality of communication units, the receiving device that receives the overlapping signal separates the received overlapping signal into a high-speed signal and a low-speed signal and provides the separated low-speed signal to the remaining receiving devices.

[0074] (18) As one aspect of the present embodiment, preferably, each of the receiving devices included in the plurality of communication units detects whether or not the superimposed signal is received using a signal detection unit that detects the presence or absence of a low-speed signal.

[0075] Each aspect listed in the column of [Description of Embodiments of the Present Invention] described above can be applied to all of the remaining aspects, or all combinations of the remaining aspects.

[0076] [Details of the embodiments of the present invention]

[0077] Hereinafter, the specific structure of the present embodiment will be described in detail with reference to the accompanying drawings. In addition, the present invention is not limited to these examples, but is represented by the claims, which means that all changes within the meaning and scope equivalent to the claims are included. In addition, in the description of the accompanying drawings, the same reference numerals are used to mark the same elements, and repeated descriptions are omitted.

[0078] Figure 1 2 is a diagram showing the configuration of the transmission and reception system 1 . Figure 1 The transceiver system 1 shown has a transmitting device 10 and a receiving device 20 connected to each other via a communication link. The transmitting device 10 outputs a signal to the communication link. The receiving device 20 receives the signal output from the transmitting device 10 to the communication link. The communication link can be a wired link or a wireless link. The communication link can also be a link that can communicate only in a unidirectional direction from the transmitting device 10 to the receiving device 20. The communication link can also be a differential communication link or a single link.

[0079] The transmitting device 10 has a high-speed signal generating unit 11, a low-speed signal generating unit 12, and a signal superimposing unit 13. The high-speed signal generating unit 11 generates a high-speed signal with a limited frequency band, and outputs the high-speed signal from an output terminal. The low-speed signal generating unit 12 generates a low-speed signal with a frequency lower than the frequency band of the high-speed signal, and outputs the low-speed signal from an output terminal. The signal superimposing unit 13 inputs the high-speed signal generated by the high-speed signal generating unit 11 from a first input terminal, and inputs the low-speed signal generated by the low-speed signal generating unit 12 from a second input terminal. In addition, the signal superimposing unit 13 outputs a superimposed signal obtained by superimposing the high-speed signal and the low-speed signal to the communication link via the output terminal.

[0080] The receiving device 20 has a signal separation unit 21 and a restoration unit 22. The signal separation unit 21 receives the overlapping signal output from the transmitting device 10 to the communication link from the input end, separates the high-speed signal and the low-speed signal from the received overlapping signal, outputs the high-speed signal from the first output end, and outputs the low-speed signal from the second output end. The restoration unit 22 performs frequency tracking based on the low-speed signal output from the second output end of the signal separation unit 21, performs phase tracking based on the high-speed signal output from the first output end of the signal separation unit 21, and restores the clock and data.

[0081] The signal separation unit 21 includes: a first filter (HPF) 31, which selectively outputs a high-speed signal in the received superimposed signal; and a second filter (LPF) 32, which selectively outputs a low-speed signal in the received superimposed signal. The first filter 31 is composed of a high-pass filter or a band-pass filter. The second filter 32 is composed of a low-pass filter or a band-pass filter.

[0082] The restoration unit 22 includes a first input terminal for taking in a high-speed signal, a second input terminal for taking in a low-speed signal, a first phase comparator (PD) 41, a second phase comparator (PFD) 42, a lock detector (LD) 43, a charge pump (CP) 44, a loop filter (LF) 45, a voltage-controlled oscillator (VCO) 46, a divider (denoted as "1 / N" in the figure) 47, a feedback divider (denoted as "1 / M" in the figure) 48, a switch 51, a switch 52 and an inverter circuit 53.

[0083] The first phase comparator 41 receives a high-speed signal output from the first filter 31 of the signal separation unit 21 from one input terminal (the third input terminal corresponding to the first input terminal of the restoration unit 22), receives an oscillation signal output from the voltage-controlled oscillator 46 from another input terminal (the fourth input terminal), and outputs a first phase difference signal indicating the phase difference between the two signals from an output terminal. The first phase comparator 41 is a Bang-Bang type phase comparator (BBPD).

[0084] The second phase comparator 42 receives from one input terminal (the fifth input terminal corresponding to the second input terminal of the restoration unit 22) a signal obtained by dividing the low-speed signal output from the second filter 32 of the signal separation unit 21 by the frequency divider 47 (or the low-speed signal before the frequency division), and receives from another input terminal (the sixth input terminal) a signal obtained by dividing the oscillation signal output from the output terminal of the voltage-controlled oscillator 46 by the feedback frequency divider 48 (or the oscillation signal before the frequency division), and outputs from the output terminal a second phase difference signal indicating the phase difference between the two signals. The second phase comparator 42 is a phase frequency comparator (PFD).

[0085] The lock detector 43 detects whether the frequency is locked between the two signals input to the second phase comparator 42. The switch 51 and the switch 52 are set to the open / closed state according to the output signal of the lock detector 43. An inverter circuit 53 is provided between the output end of the lock detector 43 and the switch 52. By means of the inverter circuit 53, when one of the switch 51 and the switch 52 is in the open state, the other is in the open state. During the period when the lock detector 43 determines that the frequency is not locked, the switch 51 is in the open state and the switch 52 is in the conducting state. On the contrary, during the period when the lock detector 43 determines that the frequency is locked, the switch 51 is in the conducting state and the switch 52 is in the open state.

[0086] The charge pump 44 receives the second phase difference signal output from the second phase comparator 42 from its input terminal during a period in which the lock detector 43 detects that the frequency is not locked. The charge pump 44 receives the first phase difference signal output from the first phase comparator 41 from its input terminal during a period in which the lock detector 43 detects that the frequency is locked. The charge pump 44 outputs a charging current corresponding to the phase difference represented by the input first phase difference signal or the second phase difference signal from its output terminal to the loop filter 45 (or a discharge current corresponding to the phase difference flows from the loop filter 45 to the charge pump 44 side via the output terminal). That is, the input terminal of the charge pump 44 is provided to take in the second phase difference signal during a period in which the lock detector 43 detects that the frequency is not locked, or to take in the first phase difference signal during a period in which the lock detector 43 detects that the frequency is locked. The output terminal of the charge pump 44 is provided to output a correction voltage value for reducing the phase difference represented by the first phase difference signal or the second phase difference signal.

[0087] The loop filter 45 inputs the charging current output from the charge pump 44 to the capacitor 45a, and outputs the voltage value corresponding to the accumulated charge amount of the capacitor 45a to the voltage controlled oscillator 46. Alternatively, the loop filter 45 allows the discharge current to flow from the capacitor 45a to the charge pump 44, and outputs the voltage value corresponding to the accumulated charge amount of the capacitor 45a to the voltage controlled oscillator 46. That is, the input end of the loop filter 45 is electrically connected to the output end of the charge pump 44, and is provided for taking in the correction voltage value. The output end of the loop filter 45 is provided for outputting the control voltage value that increases or decreases corresponding to the change of the correction voltage value taken in. The voltage controlled oscillator 46 inputs the voltage value output from the loop filter 45 from the input end, and outputs an oscillation signal having a frequency corresponding to the control voltage value to the first phase comparator 41 and the frequency divider 48 from the output end.

[0088] The restoration unit 22 performs frequency tracking based on the low-speed signal output from the output end of the second filter 32 of the signal separation unit 21 during the period in which the lock detector 43 detects that the frequency lock is not performed. The restoration unit 22 performs phase tracking based on the high-speed signal output from the output end of the first filter 31 of the signal separation unit 21 during the period in which the lock detector 43 detects that the frequency lock is performed, outputs the restoration data from the output end of the first phase comparator 41, and outputs the oscillation signal output from the output end of the voltage-controlled oscillator 46 as the restoration clock. In addition, when the lock detector 43 detects that the frequency lock is released during the phase tracking, the frequency tracking can be performed immediately based on the low-speed signal output from the second filter 32 of the signal separation unit 21.

[0089] In this way, by sending a signal obtained by superimposing a low-speed signal and a high-speed signal from the transmitting device 10 to the receiving device 20, the receiving device 20 can always input the low-speed signal used in frequency tracking. The receiving device 20 may not request the transmission of a low-speed signal from the transmitting device 10 when the frequency lock is released. Therefore, a communication link for requesting the transmission of a low-speed signal is not required.

[0090] In addition, in the receiving device 20, the signal separation unit 21 separates the received overlapping signal into a high-speed signal and a low-speed signal. Therefore, the phase relationship between the high-speed signal and the low-speed signal can be arbitrary, and the phase relationship between the low-speed signal and the high-speed signal can also be independent. The phases of the high-speed signal and the low-speed signal may not be consistent with each other. In addition, it is not necessary to make the level transition times (Tr, Tf) of the high-speed signal and the low-speed signal consistent with each other.

[0091] Therefore, it is possible to suppress an increase in the number of communication links, suppress an increase in power consumption of the circuit, and suppress an increase in the layout area of ​​the circuit.

[0092] Figure 2A This is a diagram for explaining the frequency distribution of high-speed signals and low-speed signals. Figure 2B is a diagram for explaining the passband of the first filter 31. Figure 2C 3 is a diagram for explaining the passband of each second filter 32. Specifically, Figure 2A The frequency distribution of the signal output from the transmitting device 10 is shown. Figure 2B The frequency distribution of the signal output from the first filter 31 and the passband of the first filter 31 in the receiving device 20 are shown. Figure 2C 2 shows the frequency distribution of the signal output from the second filter 32 and the passband of the second filter 32 in the receiving device 20. As shown in the figure, the frequency distribution of the high-speed signal is limited, and the low-speed signal has a lower frequency than the frequency distribution of the high-speed signal ( Figure 2A The first filter 31 can selectively output the high-speed signal ( Figure 2B The second filter 32 can selectively output the low-speed signal in the received signal ( Figure 2C ).

[0093] Figure 3A This is a diagram for explaining that a pair of a high-speed signal generated by the high-speed signal generating unit 11 and a low-speed signal generated by the low-speed signal generating unit 12 is a signal to be superimposed. Figure 3B 1 is a diagram for explaining a signal (superimposed signal) output from the output terminal of the transmission device 10 after superimposition by the signal superimposing unit 13 . Figure 3C It is a diagram for explaining a signal (received signal) input from an input terminal of the receiving device 20 . Figure 3D 3 is a diagram for explaining a combination of a low-speed signal output from the second filter 32 and a high-speed signal output from the first filter 31. Figures 3A to 3D In FIG. 1 , each signal is represented as a differential signal.

[0094] Figures 4A to 4C : is a diagram showing the simulation result (eye diagram) when the amplitude ratio between the high-speed signal and the low-speed signal is set to 2:8. Figures 4A to 4C In the figure, the horizontal axis represents time and the vertical axis represents voltage. Figures 5A to 5C : is a diagram showing the simulation result (eye diagram) when the amplitude ratio between the high-speed signal and the low-speed signal is set to 8:2. Figures 5A to 5C In the figure, the horizontal axis represents time and the vertical axis represents voltage. Figure 4A and 5A Each of the eye patterns of the signal superimposed by the signal superimposing unit 13 and output from the transmitting device 10 is shown. Figure 4B and 5B Each of them shows an eye pattern of the low-speed signal output from the second filter 32 . Figure 4C and 5CThey respectively represent eye diagrams of high-speed signals output from the first filter 31. Figures 4A to 4C and Figures 5A to 5C As shown, in the receiving device 20 , the received superimposed signal can be separated into a high-speed signal and a low-speed signal by the first filter 31 and the second filter 32 of the signal separation unit 21 .

[0095] In order to facilitate separation of the high-speed signal and the low-speed signal, the amount of interference of the low-speed signal on the frequency band of the high-speed signal is preferably as small as possible. Therefore, the low-speed signal preferably does not include information other than frequency.

[0096] Here, when the structure of this embodiment is compared with the structure of the invention disclosed in the above-mentioned Patent Document 2, it is as follows.

[0097] In the invention disclosed in Patent Document 2, a logic signal formed by overlapping a word clock and serial data is transmitted from a transmitting device to a receiving device. Therefore, the transmitting device obtains an exclusive OR of the word clock and serial data, overlaps the exclusive OR signal with the serial data, and generates a 4-value differential signal corresponding to the respective levels of the word clock and serial data. Therefore, if the word clock and serial data are not overlapped, the current output changes to +I, -I, but in the invention disclosed in Patent Document 2, the current output changes to +3I, +I, -I, -3I. The maximum value of the consumed current is 3I.

[0098] In contrast, in this embodiment, instead of a 4-value differential signal, a signal obtained by superimposing a high-speed signal and a low-speed signal is transmitted from the transmitting device 10 to the receiving device 20. The low-speed signal is set to a frequency lower than the frequency band of the high-speed signal so that it can be separated from the high-speed signal in the receiving device 20. Therefore, the low-speed signal generating unit 12 of the transmitting device 10 only needs to operate at a low speed, thereby suppressing an increase in power consumption. In addition, as Figures 5A to 5C As shown in FIG. 1 , since the amplitude of the low-speed signal can be made smaller than the amplitude of the high-speed signal, the low-speed signal generating unit 12 can also suppress the increase in power consumption based on this point. For example, when the amplitude of the low-speed signal is 1 / 2 of the amplitude of the high-speed signal and the current required for generating the high-speed signal is I, the maximum value of the consumed current is 1.5I. This value is 1 / 2 of the maximum value of the consumed current disclosed in Patent Document 2.

[0099] In addition, in the invention disclosed in Patent Document 2, the receiving device needs three comparators with different thresholds to separate the received 4-value differential signal into word clock and serial data. The three comparators need to operate at high speed to compare the high-speed 4-value differential signal with the threshold, so the power consumption is large. In addition, the receiving device needs a selector to extract the word clock, and the selector selects and outputs any one of the output signals of the two comparators according to the value of the serial data. In addition, the receiving device needs a low-pass filter to reduce the word clock failure that may occur due to the timing of selecting the serial data.

[0100] In contrast, in the present embodiment, after the signal separation unit 21 separates the received signal into a high-speed signal and a low-speed signal, the receiving device 20 uses the comparator included in the first phase comparator 41 to compare the high-speed signal with the threshold. Therefore, only one comparator is required. Even in the case where a comparator that compares the low-speed signal with the threshold is provided, the comparator can perform a low-speed operation, and thus, the power consumption can be about 1 / 10 of the power consumption of the comparator for the high-speed signal. The invention disclosed in Patent Document 2 requires three high-speed comparators, but in the present embodiment, only one high-speed comparator and one low-speed comparator are used, and thus, power consumption can be reduced.

[0101] Figure 6 1 is a diagram showing a configuration example of the transmission device 10. Figure 6 In the example configuration shown, the transmitter 10 has 8b10b encoded parallel data (in Figure 6 The serializer that converts the 8b 10b data (8b 10b Data)) into serial data is used as the high-speed signal generator 11. The transmitter 10 has a PLL (Phase Locked Loop) circuit as the low-speed signal generator 12. The serializer that is used as the high-speed signal generator 11 receives the bit clock (in the bit clock) from the other input terminal and the PLL circuit that is used as the low-speed signal generator 12 receives the bit clock (in the bit clock) from the other input terminal. Figure 6 In the example, a clock is generated by a bit clock (referred to as "bit clock"), and each bit of the serial data is output from the output terminal at the timing indicated by the clock. In addition, the PLL circuit as the low-speed signal generating unit 12 generates a low-speed signal based on the bit clock taken from the input terminal, and outputs the generated low-speed signal from the output terminal.

[0102] Figure 71 is a diagram showing another configuration example of the transmitting device 10. In the configuration example shown in the figure, the transmitting device 10 has a serializer that converts 8b10b encoded parallel data into serial data as a high-speed signal generating unit 11. The serializer as the high-speed signal generating unit 11 inputs a clock generated by the PLL circuit 14 based on the bit clock, and outputs each bit of the serial data at the timing indicated by the clock. The transmitting device 10 may also have a multiplier circuit as a low-speed signal generating unit 12. The multiplier circuit (denoted as "1 / J or xJ" in the figure) as the low-speed signal generating unit 12 generates a low-speed signal based on the bit clock taken in from the input end, and outputs the generated low-speed signal from the output end.

[0103] Let the data rate of the high-speed signal be DR. Let the coefficient corresponding to the data communication method of the high-speed signal be K. Let the frequency of the low-speed signal be F. Let the division ratio of the frequency divider 47 be N. Let the division ratio of the frequency divider 48 be M. The ratio of the frequency of the restored clock at the end of the frequency tracking in the restoration unit 22 to the frequency of the low-speed signal is M / N. When the data communication method of the high-speed signal is RZ (Return to Zero), K=0.5. When the data communication method of the high-speed signal is NRZ (Non Return to Zero), K=1. When the data communication method of the high-speed signal is PAM (Pulse Amplitude Modulation) 4, K=2. When the data communication method of the high-speed signal is PAM16, K=4. It is preferred that there is a relationship between these parameters represented by the following formula (3).

[0104]

[0105] If the ratio (DR / F) of the data rate DR of the high-speed signal included in the superimposed signal output from the transmitting device 10 to the frequency F of the low-speed signal is an integer ratio, the relationship of the above formula (3) can be satisfied by appropriately setting the frequency division ratio N of the frequency divider 47 of the receiving device 20 and the frequency division ratio M of the feedback frequency divider 48. For example, when the data rate DR of the high-speed signal is 1 Gbps, the coefficient K is 2, the frequency division ratio N of the frequency divider 47 is 1, and the frequency division ratio M of the frequency divider 48 is 50, the frequency F of the low-speed signal is 10 MHz. The transmitting device 10 generates a low-speed signal by multiplying the bit clock to match the frequency F of the low-speed signal required in the receiving device 20.

[0106] Preferably, the high-speed signal generating unit 11 of the transmitting device 10 generates a high-speed signal with a limited frequency band by coding so that the received signal can be separated into the high-speed signal and the low-speed signal by the signal separating unit 21 of the receiving device 20. As the coding, mBnB coding that ensures DC balance is preferred, and Manchester coding is also preferred.

[0107] In addition, when the received signal is separated into a high-speed signal and a low-speed signal by the signal separation unit 21 of the receiving device 20, it is preferred that the interference amount of the low-speed signal on the frequency band of the high-speed signal be less than about 1 / 100. If the noise amount can be set to a few mV and the interference amount of the low-speed signal on the frequency distribution of the high-speed signal can be reduced to the level of noise, the influence of the interference can be regarded as equal to the noise and eliminated. When the amplitude of the low-speed signal is several hundred mV, as long as the interference amount of the low-speed signal on the frequency band of the high-speed signal is about 1 / 100, the interference amount becomes a few mV equivalent to the noise, thereby eliminating the influence of the interference.

[0108] For example, when the data rate of a high-speed signal encoded with 8B10B is 1 Gbps, the frequency distribution of the high-speed signal is approximately above 100 MHz. Assume that a high-pass filter with a first order filter and a cutoff frequency of 100 MHz is used as the first filter 31. The filter attenuates to 0.01 at a frequency of 1 MHz and to 0.1 at a frequency of 10 MHz. At this time, when the amplitude ratio of the high-speed signal to the low-speed signal is 1:1 and the frequency of the low-speed signal is 1 MHz, the amount of interference of the low-speed signal on the high-speed signal is 1 / 100. When the amplitude ratio of the high-speed signal to the low-speed signal is 10:1 and the frequency of the low-speed signal is 10 MHz, the amount of interference of the low-speed signal on the high-speed signal is 1 / 100. In addition, if the order of the filter is increased, the attenuation at 1 MHz and 10 MHz can be increased. However, increasing the order of the filter is not preferred because it is feared that the area of ​​the IC will increase due to the increase in the number of components in the IC and the area of ​​the circuit substrate will increase due to the addition of components outside the IC.

[0109] The low-speed signal generating unit 12 of the transmitting device 10 preferably generates a low-speed signal having a time waveform of a sine wave or a triangular wave to reduce the interference of the low-speed signal with the frequency band of the high-speed signal. In particular, by making the low-speed signal a sine wave, the interference of the low-speed signal with the frequency band of the high-speed signal can be minimized. Thus, even if the high-speed signal and the low-speed signal are overlapped, the communication quality will not be impaired.

[0110] Let the frequency of the low-speed signal be F. Let the data rate of the high-speed signal be DR. Let the coefficient corresponding to the data encoding method of the high-speed signal be L. Let the cutoff frequency of the first filter 31 be Fc. Let the ratio of the amplitude of the high-speed signal to the amplitude of the low-speed signal be Vr. Let the interference tolerance of the low-speed signal on the frequency band of the high-speed signal be Gd. At this time, it is preferable that there is a relationship between these parameters expressed by the following equation (4). When Fc=DR / L is used, equation (4) is expressed by the following equation (5). The coefficient L is a value corresponding to the data encoding method of the high-speed signal. When the data encoding method of the high-speed signal is 8B10B encoding, L=10. When the data encoding method of the high-speed signal is Manchester encoding, L=2.

[0111]

[0112]

[0113] For example, when the data rate DR of the high-speed signal encoded with 8B10B is 1 Gbps, L = 10. Also, the amplitude ratio Vr is 10 and the interference tolerance Gd is 0.01. In this case, the frequency F of the low-speed signal is 10 MHz or less.

[0114] The low-speed signal generating unit 12 of the transmitting device 10 preferably generates a low-speed signal after spectrum spreading. By spreading the low-speed signal, the EMI (Electro Magnetic Interference) radiation from the communication link can be reduced. In addition, in addition to the low-speed signal generating unit 12 generating the low-speed signal after spectrum spreading, the high-speed signal generating unit 11 also preferably generates the high-speed signal after spectrum spreading. At this time, it is preferred that the modulation period of the spread spectrum (S: Spread Spectrum) between the low-speed signal and the high-speed signal is the same, and the modulation intensity of SS is preferably the same. This is because, when there is a large difference in frequency between the two signals input by the lock detector 43 of the receiving device 20, the lock detector 43 determines that the frequency lock is released and performs frequency tracking. Since the second phase comparator 42 is used during frequency tracking, the data cannot be restored based on the high-speed signal.

[0115] In addition, the modulation period and modulation intensity limits for SS can be adjusted by reducing the sensitivity of the lock detector 43. However, when the sensitivity is too low, the accuracy of frequency tracking deteriorates, frequency missynchronization occurs, and data cannot be accurately restored.

[0116] Fig. 8A This is a diagram for explaining the frequency distribution of the high-speed signal and the low-speed signal after SS is implemented. Figure 8B is used to explain the passband of the first filter 31, Figure 8C3 is a diagram for explaining the passband of the second filter 32. Specifically, Fig. 8A The frequency distribution of the signal output from the transmitting device 10 is shown. Figure 8B The frequency distribution of the signal output from the first filter 31 and the passband of the first filter 31 in the receiving device 20 are shown. Figure 8C 2 shows the frequency distribution of the signal output from the second filter 32 and the passband of the second filter 32 in the receiving device 20. Figures 2A to 2C ) is compared with the low-speed signal ( Figures 8A to 8C ) increases in frequency band and decreases in amplitude.

[0117] When SS is performed on a low-speed signal, it is sufficient to set the center data rate of the high-speed signal to DR and the center frequency of the low-speed signal to F so that the above equations (3) to (5) are satisfied.

[0118] The low-speed signal generating unit 12 of the transmitting device 10 may also generate a low-speed signal having a triangular wave time waveform to reduce the interference of the low-speed signal on the frequency band of the high-speed signal. A sine wave has a single frequency component, whereas a triangular wave has higher harmonic components in addition to the basic frequency component. However, unlike a rectangular wave, in a triangular wave, the amplitude of the odd-numbered (nth) higher harmonic component is n. 2 , which decays continuously. For example, the amplitude of the 11th harmonic component of the triangle wave is 1 / 121 of the amplitude of the fundamental frequency component. The following equation (6) is a formula for expressing the triangle wave function using the Fourier series. The following equation (7) is a formula for expressing the rectangular wave function using the Fourier series. Fig. 9 The table shows the interference amount of the low-speed signal on the frequency band of the high-speed signal when the low-speed signal is a triangle wave with a fundamental frequency of 1 MHz and the cutoff frequency of the first filter 31 is 100 MHz.

[0119]

[0120]

[0121] When compared with a sine wave, the amount of interference at 1MHz of a triangular wave is equal to that of a sine wave, but the amount of interference at 3MHz is more than one order of magnitude smaller than that of a sine wave, so the influence of interference becomes very small. In the case of a low-speed signal of a triangular wave with a basic frequency of 1MHz and an amplitude of 100mV, the amplitude of the third harmonic component is 0.3mV. This amplitude is smaller than the noise level (a few mV). In this way, the influence of the harmonic components of the low-speed signal of a triangular wave on interference is also very small.

[0122] The low-speed signal generating unit 12 of the transmitting device 10 may include low-speed data in addition to the frequency information in the low-speed signal. As an example, there are the following first to third methods.

[0123] In the first method, it is assumed that the amplitude of the low-speed signal corresponds to the level of the low-speed data. For example, the amplitude of the low-speed signal is 100 mV when the low-speed data is at a low level, and the amplitude of the low-speed signal is 200 mV when the low-speed data is at a high level.

[0124] In the second method, it is assumed that the frequency of the low-speed signal corresponds to the level of the low-speed data. In this case, the center frequency of the low-speed signal is preferably constant. Let the center frequency of the low-speed signal be F, and satisfy equations (3) to (5). If mBnB encoding or Manchester encoding is used, the center frequency of the low-speed signal can be made constant.

[0125] In the third method, it is assumed that the duty cycle of the low-speed signal corresponds to the level of the low-speed data. In this case, it is preferred that the moving average of the duty cycle of several cycles of the low-speed signal is about 50%. If mBnB encoding or Manchester encoding is used, the moving average of the duty cycle of several cycles of the low-speed signal can be made about 50%.

[0126] Fig.10 2 is a diagram showing another configuration example of the receiving device 20. Fig.10 In the structural example shown, the receiving device 20 has Figure 1 In addition to the structure of the receiving device shown, the signal detecting unit 23 for detecting the presence of the low-speed signal is further provided. The signal detecting unit 23 detects the presence of the low-speed signal based on the output of the second filter 32 of the signal separating unit 21.

[0127] When it is assumed that a signal detection unit is not provided, the receiving device operates as if an arbitrary signal is input even during a period when the transmitting device does not output a signal. The receiving device processes noise as a signal during a period when no signal is actually input, and outputs unexpected data to the subsequent circuit. In the case where the subsequent circuit is an image system, a state is achieved in which no image is displayed. In the case where the subsequent circuit is a communication system, a state is achieved in which communication is not normally established. Therefore, in a state in which no signal is input, it is preferred that the receiving device does not send erroneous data to the subsequent circuit. In addition, in a state in which no signal is input, it is preferred that the receiving device does not operate from the perspective of power consumption. Therefore, it is preferred that the receiving device detects whether a signal is input using a signal detection unit, and does not send erroneous data to the subsequent circuit during a period in which no signal is input, and stops part of the operation.

[0128] In a system where information indicating whether a transmitting device has output a signal is transmitted to a receiving device using another line, the receiving device does not need to have a signal detection unit. In this case, in addition to the communication link for transmitting the signal, there is no need to set up a separate communication link for transmitting information indicating whether a transmitting device has output a signal, and this method is not preferred in this respect.

[0129] Even in a system that can transmit information by changing the common level of a differential signal line as in the invention disclosed in Patent Document 1, the receiving device does not need to have a signal detection unit, and no additional communication link is required. However, in such a system, the signal transmitted using the differential signal line is high-speed, so the signal reaching the receiving device is attenuated. The receiving device needs to extract information indicating whether the transmitting device has output a signal from the attenuated signal. Therefore, the receiving device does not need a high-speed amplifier, etc., and power consumption and design man-hours increase.

[0130] In contrast, Fig.10 The receiving device 20 shown also has a signal detection unit (SDT) 23 for detecting the presence of a low-speed signal. The signal detection unit 23 can be configured by a simple circuit, which can suppress the increase in power consumption and design man-hours. The signal detection unit 23 detects the presence of a low-speed signal based on the output of the signal separation unit 21 that separates the received signal into a high-speed signal and a low-speed signal, so a high-speed amplifier or the like is not required. For example, the frequency band of the amplifier used in the invention disclosed in Patent Document 1 needs to reach several GHz, while the frequency band of the amplifier used in the receiving device 20 of this embodiment only needs to reach tens of MHz.

[0131] In the present embodiment, the signal detection unit 23 of the receiving device 20 detects the presence or absence of a low-speed signal and also detects the presence or absence of a high-speed signal. Therefore, the transmitting device 10 adopts the situation of outputting both the high-speed signal and the low-speed signal or not outputting either of the two. When it is assumed that the transmitting device 10 outputs a high-speed signal but does not output a low-speed signal, the receiving device 20 detects the situation of no signal using the signal detection unit 23 and does not send data to the subsequent circuit. In addition, when it is assumed that the transmitting device 10 does not output a high-speed signal but outputs a low-speed signal, the receiving device 20 detects the situation of having a signal using the signal detection unit 23, but in fact, no high-speed signal is input, so wrong data is sent to the subsequent circuit.

[0132] Fig.11A is a diagram showing a circuit example of the signal detection unit 23, Fig. 11B This is a timing diagram of the signal waveform in each part. Fig.11A In the circuit example shown, the signal detection unit 23 includes an NMOS transistor M1, an NMOS transistor M2, a PMOS transistor M3, a capacitor C1, a constant current source I1, and a constant current source I2. Fig. 11BAs shown, the signal detection unit 23 receives the low-speed signal as differential signals Vinp and Vinn, and outputs a signal Vout indicating whether a certain period of time has passed during which both Vinp and Vinn are at low level (a period during which no input signal is present).

[0133] The drain of the NMOS transistor M1 is connected to the power supply potential supply terminal. The source of the NMOS transistor M1 is connected to the ground potential supply terminal via the capacitor C1. Vinp is input to the gate of the NMOS transistor M1.

[0134] The drain of the NMOS transistor M2 is connected to the power supply potential supply terminal. The source of the NMOS transistor M2 is connected to the ground potential supply terminal via the constant current source I1. Vinn is input to the gate of the NMOS transistor M2.

[0135] The source of the PMOS transistor M3 is connected to the power supply potential supply terminal via the constant current source I2. The drain of the PMOS transistor M3 is connected to the ground potential supply terminal. The gate of the PMOS transistor M3 is connected to the source of the NMOS transistor M1 and the source of the NMOS transistor M2. The potential of the source of the PMOS transistor M3 becomes the output signal Vout.

[0136] During the period when no signal is input, both Vinp and Vinn become low level, so the state in which both NMOS transistor M1 and NMOS transistor M2 are in the off state continues. During this period, charge is not accumulated in capacitor C1 through NMOS transistor M1 or NMOS transistor M2, and charge can be discharged from capacitor C1 only through constant current source I1. As a result, PMOS transistor M3 becomes a conductor state, and output signal Vout becomes zero level.

[0137] During the period when the signal is input, Vinp and Vinn are alternately high level, so the time when both NMOS transistor M1 and NMOS transistor M2 are in the off state is short. During this period, the amount of charge accumulated in capacitor C1 through NMOS transistor M1 or NMOS transistor M2 and the amount of charge flowing out of capacitor C1 through constant current source I1 become equal to each other. As a result, PMOS transistor M3 remains in the off state, and output signal Vout is high level.

[0138] The signal detection unit 23 can detect whether a signal is input based on the level of the output signal Vout.

[0139] Fig. 12A 2 is a diagram showing another circuit example of the signal detection unit 23. Figures 12B to 12D This is a timing diagram of the signal waveform in each part. Fig. 12AIn the circuit example shown, the signal detection unit 23 includes an amplifier 231 and a Schmitt trigger buffer 232. The amplifier 231 receives a low-speed signal as a differential signal INp, INn, amplifies the input signal with a gain A, and outputs the amplified signal to the Schmitt trigger buffer 232. The amplifier 231 can be an amplifier that operates at a low speed (for example, tens of MHz). In addition, Figures 12B to 12D , the value of the low-speed signal (INp-INn), the value of the signal input to the Schmitt trigger buffer 232 (A(INp-INn)) (having a center value between the upper threshold Vtp and the lower threshold Vtn), and the output signal out of the Schmitt trigger buffer 232 are shown from top to bottom.

[0140] During the period when no signal is input, the value of the signal (A(INp-INn)) output from the amplifier 231 and input to the Schmitt trigger buffer 232 continues to be within the range m between the threshold value Vtp and the threshold value Vtn of the Schmitt trigger buffer 232. Therefore, the value of the output signal out from the Schmitt trigger buffer 232 does not change ( Fig. 12B and 12C ).

[0141] During the period when the signal is input, the value of the signal (A(INp-INn)) output from the amplifier 231 and input to the Schmitt trigger buffer 232 may deviate from the range between the threshold value Vtp and the threshold value Vtn of the Schmitt trigger buffer 232. Therefore, the value of the output signal out from the Schmitt trigger buffer 232 changes ( Fig.12D ).

[0142] The signal detection unit 23 can detect whether a signal is input based on the change state of the value of the output signal out from the Schmitt trigger buffer 232 .

[0143] Fig.13 2 is a diagram showing another configuration example of the receiving device 20. Fig.13 In the structural example shown, the receiving device 20 has Figure 1 In addition to the structure of the receiving device shown in the figure, an error detection unit (Err Det) 25 for detecting whether the low-speed signal is normal is also provided. The error detection unit 25 detects whether the low-speed signal is normal based on the output of the second filter 32 of the signal separation unit 21. The restoration unit 22 stops the restoration operation when the error detection unit 25 detects that the low-speed signal is abnormal, and then restarts the restoration operation when the error detection unit 25 detects that the low-speed signal is normal.

[0144] If the error detection unit is not provided, the following situation occurs: if noise is applied to the signal received by the receiving device and the waveform of the signal is disturbed, the first phase comparator 41 makes an error judgment, the frequency lock is released, and the restoration operation of the restoration unit (restoration of data and clock based on high-speed signals) cannot be accurately performed. After the noise is not applied, the receiving device needs to perform frequency tracking and phase tracking, and it takes time until the restoration operation of the restoration unit is restarted.

[0145] On the other hand, there is a method of detecting the application of noise using error detection of a high-speed signal and stopping the restoration operation of the restoration unit. The restoration operation of the restoration unit can be stopped by stopping the phase comparator or the charge pump.

[0146] However, this method cannot detect the situation where the noise application is no longer present. This is because the frequency and phase of the signal become abnormal after the noise is applied, so the receiving device cannot accurately receive the high-speed signal and cannot determine that there is no noise application by waiting for the high-speed signal to recover normally. Therefore, the receiving device stops the recovery action after a certain time has passed after the noise application is detected, and restarts the recovery action after a certain time has passed. Therefore, even if there is no noise application, the receiving device cannot restart the recovery action after a certain time has passed (see Fig.14 ).

[0147] In contrast, Fig.13 The receiving device 20 shown in the figure further includes an error detection unit 25, which detects whether the low-speed signal is normal. The error detection unit 25 can detect the presence of noise from the low-speed signal at an early stage, and can also detect the absence of noise at an early stage.

[0148] The error detection unit 25 can detect whether there is an influence of noise by monitoring the clock duty ratio of the low-speed signal (see Fig.15 ). If the duty cycle of the low-speed signal is within the normal range, the error detection unit 25 determines that the signal is not affected by noise and is normal. If the duty cycle of the low-speed signal deviates from the normal range, the error detection unit 25 determines that the signal is affected by noise and is abnormal.

[0149] When the error detection unit 25 determines that the signal is normal, the restoration unit 22 restarts the restoration operation. When the error detection unit 25 determines that the signal is normal after determining that the signal is abnormal for a long time, the restoration unit 22 preferably restarts the restoration operation after performing frequency tracking.

[0150] Fig.16 2 is a diagram showing another configuration example of the receiving device 20. Fig.16 In the structural example shown, the receiving device 20 has Figure 1 In addition to the structure of the receiving device shown, the first error detection unit 24 for detecting whether the high-speed signal is normal and the second error detection unit 25 for detecting whether the low-speed signal is normal are provided.

[0151] The first error detection unit 24 detects whether the high-speed signal is normal based on the output of the first filter 31 of the signal separation unit 21 or the output of the first phase comparator 41 of the restoration unit 22. The second error detection unit 25 detects whether the low-speed signal is normal based on the output of the second filter 32 of the signal separation unit 21. The restoration unit 22 stops the restoration operation when the first error detection unit 24 detects that the high-speed signal is abnormal, and then restarts the restoration operation when the second error detection unit 25 detects that the low-speed signal is normal.

[0152] In the above Fig.13 In the structure, there is no error detection unit for detecting whether the high-speed signal is normal. Fig.13 In the structure of the invention, the error detection unit 25 that detects whether the low-speed signal is normal monitors the low-speed signal with a low data rate or frequency, so error detection takes time. As a result, the frequency lock is sometimes released in the recovery unit 22 during the period from when the influence of noise is applied to the signal to when the error detection unit 25 detects an error. When the frequency lock is released, after the noise is no longer applied, frequency tracking and phase tracking are performed, and it takes time for the recovery operation in the recovery unit 22 to restart.

[0153] In contrast, Fig.16 In the structure, in addition to the second error detection unit 25 that detects whether the low-speed signal is normal, there is also a first error detection unit 24 that detects whether the high-speed signal is normal. The first error detection unit 24 can monitor the high-speed signal whose data rate is several tens to several hundreds of times higher than that of the low-speed signal. The period from when the influence of noise is applied to the signal to when the first error detection unit 24 detects an error is short. Therefore, it is possible to avoid the situation in which the frequency lock is released in the recovery unit 22 during this period, and the time required until the recovery action in the recovery unit 22 is restarted after the noise is no longer applied can be shortened.

[0154] Fig.17 is a diagram showing the structure of the transceiver system 2. Figure 1 When compared with the structure of the transceiver system 1 shown in FIG. Fig.17 The difference of the transceiver system 2 shown is that a relay device 60A and a relay device 60B are provided on the communication link between the transmitter 10 and the receiver 20. The relay devices 60A and 60B are devices that receive a signal arriving from the previous stage through the communication link and relay the received signal and output it to the next stage. The relay device can also be one or more stages.

[0155] A relay device specialized in waveform shaping of a signal can suppress power. On the contrary, when the waveform of a received signal is significantly degraded, even if multiple stages are used, it is sometimes impossible to completely waveform shape the signal.

[0156] In contrast, when the waveform of the received signal is significantly degraded, the retimer that temporarily converts the signal into digital data during relaying can output a completely shaped signal to the next stage. Therefore, the latter retimer is useful when the communication link is long.

[0157] One or more relay devices are provided between the transmitting device 10 and the receiving device 20. Fig.17 In the structure shown, two relay devices 60A and 60B are provided. The transmitting device 10 and the relay device 60A are mounted on the first substrate, and the relay device 60B and the receiving device 20 are mounted on the second substrate. In addition, it is assumed that the data rate of the high-speed signal is 8 GHz. At this time, typically, the attenuation of the signal in the communication link on the first substrate between the transmitting device 10 and the relay device 60A is several dB, and the attenuation of the signal in the communication link on the second substrate between the relay device 60B and the receiving device 20 is several dB. On the other hand, the attenuation of the signal in the communication link between the relay device 60A and the relay device 60B is sometimes 20 dB. In the case where the attenuation of the signal in the communication link is large as described above, the relay devices 60A and 60B are provided.

[0158] In the case where the relay device is a retimer, the signal after the high-speed signal and the low-speed signal are overlapped is output from the transmitting device 10 to the receiving device 20. Therefore, the relay devices 60A and 60B arranged between them receive the signal after the high-speed signal and the low-speed signal are overlapped, separate the received signal into the high-speed signal and the low-speed signal, temporarily convert the high-speed signal into digital data, and then overlap the high-speed signal and the low-speed signal and output it to the next stage. Figures 18 to 21 , the structure of the relay device 60 which is preferred as the relay devices 60A and 60B is described.

[0159] Fig.18 1 is a diagram showing a configuration example of the relay device 60 . Fig.18The relay device 60 shown has a signal superimposing unit 13, a signal separating unit 21, a restoring unit 22, and a serializer 61. The signal superimposing unit 13 of the relay device 60 has the same structure as the signal superimposing unit 13 of the transmitting device 10, and operates in the same manner. The signal separating unit 21 of the relay device 60 has the same structure as the signal separating unit 21 of the receiving device 20, and operates in the same manner. The restoring unit 22 of the relay device 60 has the same structure as the restoring unit 22 of the receiving device 20, and operates in the same manner. The first phase comparator 41 of the restoring unit 22 outputs restored data (digital data) based on the high-speed signal.

[0160] The serializer 61 serializes the restored data output from the first phase comparator 41 to form serial data, and outputs the serial data to the signal superimposing unit 13. The serializer 61 outputs data of each bit of the serial data at the timing indicated by the restored clock output from the voltage controlled oscillator 46. The signal superimposing unit 13 superimposes the high-speed signal (serial data) output from the serializer 61 and the low-speed signal output from the frequency divider 47, and outputs the superimposed signal.

[0161] Fig.19 It is a diagram showing another configuration example of the relay device 60 . Fig.19 The relay device 60 shown has a signal superimposing unit 13, a signal separating unit 21, a restoring unit 22, a serializer 61, and a PLL circuit 62. The serializer 61 serializes the restored data output from the first phase comparator 41 to form serial data, and outputs the serial data to the signal superimposing unit 13. The serializer 61 outputs data of each bit of the serial data at the timing indicated by the clock output from the PLL circuit 62. The PLL circuit 62 generates a clock based on the oscillation signal output from the frequency divider 48, and supplies it to the serializer 61. The signal superimposing unit 13 superimposes the high-speed signal (serial data) output from the serializer 61 and the low-speed signal output from the frequency divider 47, and outputs the superimposed signal.

[0162] Fig. 20 It is a diagram showing another configuration example of the relay device 60 . Fig. 20The relay device 60 shown has a signal superimposing unit 13, a signal separating unit 21, a restoring unit 22, a serializer 61, and a PLL circuit 62. The serializer 61 serializes the restored data output from the first phase comparator 41 to form serial data, and outputs the serial data to the signal superimposing unit 13. The serializer 61 outputs data of each bit of the serial data at the timing indicated by the clock output from the PLL circuit 62. The PLL circuit 62 generates a clock based on the oscillation signal output from the frequency divider 47, and supplies it to the serializer 61, and also generates a low-speed signal. The signal superimposing unit 13 outputs a superimposed signal obtained by superimposing the high-speed signal (serial data) output from the serializer 61 and the low-speed signal output from the PLL circuit 62.

[0163] Fig.21 It is a diagram showing another configuration example of the relay device 60 . Fig.21 The relay device 60 shown has a signal superimposing unit 13, a signal separating unit 21, a restoring unit 22, a serializer 61, and a PLL circuit 62. The serializer 61 serializes the restored data output from the first phase comparator 41 to form serial data, and outputs the serial data to the signal superimposing unit 13. The serializer 61 outputs data of each bit of the serial data at the timing indicated by the clock output from the PLL circuit 62. The PLL circuit 62 generates a clock based on the oscillation signal output from the frequency divider 48, and supplies it to the serializer 61, and also generates a low-speed signal. The signal superimposing unit 13 outputs a superimposed signal obtained by superimposing the high-speed signal (serial data) output from the serializer 61 and the low-speed signal output from the PLL circuit 62.

[0164] exist Figures 18 to 21 In any of the structures shown, when the restored data is deserialized in the first phase comparator 41 or when the restored data output from the first phase comparator 41 is deserialized at a later stage even if it is serial data, a serializer 61 is provided. By performing deserialization, any processing that is not easy to perform high-speed processing (for example, error detection, equalizer calibration, etc.) can be easily performed using a logic circuit. However, when the restored data output from the first phase comparator 41 is serial data and the serial data can be input to the signal superposition unit 13, the serializer 61 does not need to be provided.

[0165] In the serializer 61, the frequency Fin of the low-speed signal input to the relay device and the frequency Fout of the low-speed signal output from the relay device may be the same as or different from each other. The frequency division ratio N of the frequency divider 47 of the subsequent relay device or the receiving device and the frequency division ratio M of the feedback frequency divider 48 may be appropriately set according to the input-output frequency ratio (Fout / Fin) of the relay device. When the frequencies of the low-speed signals are made different in the relay device, EMI can be reduced, which is preferable.

[0166] When Figures 18 to 21 The structures of are compared as shown below. Fig.18 In the structure of , the clock output from the voltage controlled oscillator 46 is directly input to the serializer 61, so the jitter caused by the first phase comparator 41 is output from the serializer 61. Due to the influence of this jitter, the waveform of the signal output from the relay device fluctuates, and sometimes the signal cannot be normally received by the subsequent relay device or receiving device. Fig.19 In the structure of , the clock output from the PLL circuit 62 is input to the serializer 61, so the influence of jitter caused by the first phase comparator 41 can be suppressed.

[0167] exist Fig.19 In the structure of , the low-speed signal transmitted from the transmitting device 10 to the receiving device 20 is transmitted via a plurality of buffers connected in series. Therefore, noise is amplified by each buffer, and jitter of the low-speed signal increases. Fig. 20 In the structure, the PLL circuit 62 is provided on the path of the low-speed signal, so that the jitter of the low-speed signal can be removed. In addition, the clock output from the PLL circuit 62 is input to the serializer 61, so the influence of the jitter caused by the first phase comparator 41 can also be suppressed.

[0168] exist Fig. 20 In the structure of , when the phase of the low-speed signal output from the frequency divider 47 and the phase of the restored clock output from the voltage-controlled oscillator 46 are inconsistent with each other, in order to eliminate the phase inconsistency between the two, the serializer 61 needs to have a FIFO (First-In First-Out) memory, which may increase the circuit scale, circuit layout area, and power consumption. Fig.21 In the structure of FIG. 4 , a low-speed signal is generated by the PLL circuit 62 based on an oscillation signal outputted after the restored clock outputted from the voltage-controlled oscillator 46 is divided by the feedback divider 48. The relationship between the phase of the low-speed signal outputted from the divider 47 and the phase of the restored clock outputted from the voltage-controlled oscillator 46 can be easily known. Therefore, the FIFO can be eliminated or the circuit scale of the FIFO can be reduced.

[0169] Fig. 22 It is a diagram showing the structure of the transmission and reception system 3. Fig. 22 The transceiver system 3 shown in FIG. Figure 1 In addition to the configuration of the transmission and reception system 1 shown (one set of the transmission device 10 and the reception device 20), one or more sets of the transmission device 10A and the reception device 20A are provided. That is, the transmission and reception system 3 is composed of a plurality of lanes.

[0170] In the transceiver system 3 , a signal obtained by superimposing a high-speed signal and a low-speed signal by the signal superimposing unit 13 is transmitted from the transmitter 10 to the receiver 20 , and the signal is separated into a high-speed signal and a low-speed signal by the signal separating unit 21 of the receiver 20 .

[0171] The low-speed signal output from the signal separation unit 21 of the receiving device 20 is input to the frequency divider 47 of the restoration unit 22 of the receiving device 20 and is also input to the frequency divider 47 of the restoration unit 22 of another receiving device 20A.

[0172] The receiving device 20A receives a high-speed signal output from the transmitting device 10A connected via a communication link. The received high-speed signal passes through the first filter 31 and is input to the first phase comparator 41 .

[0173] The transmission device 10A does not need to generate a low-speed signal using the low-speed signal generation unit 12, and does not need to superimpose a high-speed signal and a low-speed signal using the signal superposition unit 13. The reception device 20A does not need to perform signal separation using the signal separation unit 21.

[0174] By forming such a structure, it is possible to make the channel for transmitting the signal after the high-speed signal and the low-speed signal are superimposed to one, so that EMI can be reduced. In addition, each receiving device has a signal detection unit 23 for detecting the presence or absence of a low-speed signal, thereby detecting whether each receiving device has received a low-speed signal, and the receiving device that has received a low-speed signal can send the low-speed signal to other receiving devices. In addition, by sequentially switching the channel for transmitting the low-speed signal, the radiation position of EMI can be dispersed, which can reduce EMI.

[0175] Next, circuit configuration examples of the signal superimposing unit 13 of the transmitting device 10 and the signal separating unit 21 of the receiving device 20 will be described.

[0176] Fig.23 1 is a diagram showing an example of a circuit configuration of each of the signal superimposing unit 13 and the signal separating unit 21. The signal superimposing unit 13 and the signal separating unit 21 are connected via a differential signal line. A coupling capacitor C is provided on one signal line of the differential signal line. 71 , C 73 , a coupling capacitor C is provided on another signal line72 , C 74 . Coupling capacitor C 71 , C 72 The coupling capacitor C is arranged near the output end of the signal superposition unit 13. 73 , C 74 It is provided near the input end of the signal separation unit 21 .

[0177] The signal superposition unit 13 includes a resistor R 11 , R 12 , NMOS transistor M 11 ~M 14 , constant current source I 11 ,I 12 and a waveform shaping circuit 15.

[0178] NMOS transistor M 11 The drain is connected via resistor R 11 The NMOS transistor M is connected to the power supply potential supply terminal 13a. 12 The drain is connected via resistor R 12 The NMOS transistor M is connected to the power supply potential supply terminal 13b (which may be shared with the power supply potential supply terminal 13a). 11 、M 12 Each source is connected to a constant current source I 11 Connect to the ground potential supply terminal. Resistor R 11 , R 12 , NMOS transistor M 11 、M 12 and constant current source I 11 The first CML (Current Mode Logic) circuit is formed. In the first CML circuit, the NMOS transistor M 11 、M 12 Each gate inputs a high-speed signal.

[0179] NMOS transistor M 13 The drain is connected via resistor R 11 The NMOS transistor M is connected to the power supply potential supply terminal 13a. 14 The drain is connected via resistor R 12 The NMOS transistor M is connected to the power supply potential supply terminal 13b. 13 、M 14 Each source is connected to a constant current source I 12 Connect to the ground potential supply terminal. Resistor R 11 , R 12 , NMOS transistor M 13 、M 14 and constant current source I 12In the second CML circuit, the NMOS transistor M 13 、M 14 Each gate inputs a low-speed signal waveform-shaped by the waveform shaping circuit 15. The waveform shaping circuit 15 generates a low-speed signal having a time waveform of a sine wave or a triangle wave, for example, to reduce interference of the low-speed signal with the frequency band of the high-speed signal.

[0180] The first CML circuit and the second CML circuit share the resistor R 11 , R 12 The signal superimposing unit 13 inputs a high-speed signal to the first CML circuit and a low-speed signal to the second CML circuit, superimposes the high-speed signal and the low-speed signal, and outputs the superimposed signal as a differential signal. The amplitude of the superimposed signal output from the signal superimposing unit 13 is the same as that of the constant current source I 11 ,I 12 Generally, in CML circuits, there is an upper limit to the output amplitude. Therefore, the constant current source I 11 ,I 12 The sum of the currents flowing through the resistors and the resistance value of the terminal resistors ensures that the output amplitude does not exceed the upper limit.

[0181] The first filter 31 of the signal separation unit 21 is composed of a coupling capacitor C 73 , C 74 and resistor R 21 , R 22 The resistor R 21 One end of the resistor R is connected to the first input terminal of the amplifier 33, and a constant voltage is applied to the other end. 22 One end of the high-pass filter is connected to the second input terminal of the amplifier 33, and a constant voltage is applied to the other end. The cut-off frequency of the high-pass filter is determined by the coupling capacitor C 73 , C 74 The capacitance value and resistor R 21 , R 22 The amplifier 33 amplifies the high-speed signal output from the first filter 31 and outputs it to the first phase comparator 41.

[0182] The second filter 32 of the signal separation unit 21 is composed of an inductor L 21 , L 22 and capacitor C 21 , C 22 The inductor L 21 One end is connected to a signal line, and the other end is connected to a capacitor C 21 Connect to the ground potential supply terminal. Inductor L 22 One end is connected to another signal line, and the other end is connected to another signal line through a capacitor C22 The cut-off frequency of the low-pass filter is determined by the inductor L. 21 , L 22 The inductor and capacitor C 21 , C 22 The Schmitt trigger buffer 34 outputs the low-speed signal output from the second filter 32 to the frequency divider 47 as a rectangular wave.

[0183] Figures 24 to 29 1 is a diagram showing another circuit configuration example of the signal superposition unit 13. The effects of each configuration are summarized below. Fig.24 and 25 In the structural example shown, it is possible to reduce Fig.23 The NMOS transistor M 13 、M 14 , ESD (Electro-StaticDischarge, electrostatic discharge) protection diode parasitic capacitance, can improve the waveform quality. Fig.26 In the configuration example shown, since low-speed signals can be overlapped without using a waveform shaping circuit, the circuit area can be reduced. Fig. 27 In the structural example shown, the capacitor C 11 , C 12 Reduce the degradation of the waveform quality of the low-speed signal caused by wrapping the high-speed signal around the low-speed signal. Fig.28 and 29 In the structural example shown, no Fig.23 The NMOS transistor M 13 、M 14 , which can reduce the influence of parasitic capacitance.

[0184] Fig.24 It is a diagram showing another circuit configuration example of the signal superimposing unit 13 . Fig.24 The signal overlap portion 13 shown in FIG. Fig.23 In addition to the structure of the signal superposition part 13, it also has a T coil T 11 、T 12 . T coil T 11 Set the NMOS transistor M 11 between the drain of the coil T and an output terminal of the signal overlapping portion 13. 12 Set the NMOS transistor M 12 By setting the T coil T 11 、T 12 , which can reduce the influence of the load of the buffer (second CML circuit) for low-speed signals.

[0185] Fig.25It is a diagram showing another circuit configuration example of the signal superimposing unit 13 . Fig.25 The signal overlap portion 13 shown in FIG. Fig.24 In addition to the structure of the signal overlapping portion 13, an ESD protection diode D 11 ~D 14 . ESD protection diode D 11 Set the NMOS transistor M 14 The ESD protection diode D 12 Set the NMOS transistor M 14 The ESD protection diode D 13 Set the NMOS transistor M 13 The ESD protection diode D 14 Set the NMOS transistor M 13 By forming such a structure, the load of the ESD protection diode viewed from the buffer (first CML circuit) for high-speed signals can be reduced.

[0186] Fig.26 It is a diagram showing another circuit configuration example of the signal superimposing unit 13 . Fig.26 The signal superposition section 13 shown includes a resistor R 11 ~R 14 , NMOS transistor M 11 ~M 14 , constant current source I 11 ,I 12 And waveform shaping circuit 16. Resistor R 11 , R 12 , NMOS transistor M 11 、M 12 (The respective drains are connected via resistors R 11 , R 12 and connected to the power supply potential supply terminals 13a, 13b) and the constant current source I 11 The first CML circuit is constituted. In the first CML circuit, the NMOS transistor M 11 、M 12 Each gate inputs a high-speed signal. Resistor R 13 , R 14 , NMOS transistor M 13 、M 14 (The respective drains are connected via resistors R 13 , R 14 connected to the power supply potential supply terminals 13c, 13d) and a constant current source I 12 In the second CML circuit, the NMOS transistor M13 、M 14 The first CML circuit and the second CML circuit are configured not to share a resistor, thereby reducing power consumption.

[0187] The waveform shaping circuit 16 is composed of a coupling capacitor C 71 , C 72 and inductor L 11 , L 12 Inductor L 11 Set the NMOS transistor M 13 Between the drain and a signal line. Inductor L 12 Set the NMOS transistor M 14 The waveform shaping circuit 16 can overlap the high-speed signal from the first CML circuit and the low-speed signal from the second CML circuit, and shape the waveform of the low-speed signal.

[0188] Fig. 27 It is a diagram showing another circuit configuration example of the signal superimposing unit 13 . Fig. 27 The signal overlap portion 13 shown in FIG. Fig.26 In addition to the structure of the signal superposition unit 13, the filter circuit 17 is further provided. The filter circuit 17 includes a capacitor C 11 , C 12 . Capacitor C 11 Set the NMOS transistor M 13 The capacitor C 12 Set the NMOS transistor M 14 between the drain and the ground potential supply terminal. If the filter circuit 17 is not provided, the output voltage range of the low-speed signal output side will add the signal wraparound from the high-speed signal output side to the low-speed signal output, and the output voltage of the low-speed signal will decrease. By providing the filter circuit 17, it is possible to prevent the signal from the high-speed signal output side to the low-speed signal output side from wraparound, and the output range of the low-speed signal output side can be improved.

[0189] Fig.28 It is a diagram showing another circuit configuration example of the signal superimposing unit 13 . Fig.28 The signal overlap section 13 shown has a resistor R 11 , R 12 , NMOS transistor M 11 、M 12 , constant current source I 11 The power supply circuits 18 and 19 are configured to receive a low-speed signal shaped into a sine wave or a triangular wave as a reference voltage, and apply a drive voltage modulated by the reference voltage to the resistor R.11 , R 12 One end of the resistor R 11 , R 12 , NMOS transistor M 11 、M 12 and constant current source I 11 The first CML circuit is composed of an NMOS transistor M 11 、M 12 Each gate of the NMOS transistor M 11 、M 12 The differential signal output from each drain is the NMOS transistor M 11 、M 12 The high-speed signal of each gate input and applied to the resistor R 11 , R 12 The power supply circuits 18 and 19 are preferably LDO (Low Drop Out) power supplies with characteristics such as low noise. In this structure, the second CML circuit for the low-speed signal is not required, and the load of the first CML circuit can be reduced. The LDO power supply is not suitable for high-speed operation, but is preferably used to output a driving voltage that changes corresponding to the time change of the low-speed signal.

[0190] Fig.29 It is a diagram showing another circuit configuration example of the signal superimposing unit 13 . Fig.29 The signal overlap section 13 shown has a buffer B 11 , B 12 , resistor R 15 , R 16 The power supply circuits 18 and 19 are configured to receive a low-speed signal shaped into a sine wave or a triangular wave as a reference voltage, and provide a driving voltage modulated by the reference voltage to the buffer B. 11 , B 12 Buffer B 11 The output terminal is connected via resistor R 15 Connect to a signal line. Buffer B 12 The output terminal is connected via resistor R 16 Connect to another signal line. Buffer B 11 , B 12 It is driven by a driving voltage (low-speed signal) applied from power supply circuits 18 and 19, inputs a high-speed signal, and outputs a signal in which the high-speed signal and the low-speed signal are superimposed. Buffer B 11 , B 12For example, a buffer (Source-Series-Terminated (SST) Buffer) having an inverter circuit structure including a PMOS transistor and an NMOS transistor applies a driving voltage from a power supply circuit to the source of the PMOS transistor. In this structure, a second CML circuit for low-speed signals is not required, and the load of the first CML circuit can be reduced. The LDO power supply is not suitable for high-speed operation, but is preferably used to output a driving voltage that changes in accordance with the time change of the low-speed signal.

[0191] Figures 30-33 2 is a diagram showing another circuit configuration example of the signal separation unit 21. The effects of each configuration are summarized below. Fig.30 and 31 In the configuration example shown, the use of a band limiting comparator can omit Fig.23 The second filter 32 in the circuit can reduce the circuit area. Fig.32 and 33 In the illustrated configuration example, the influence of the parasitic capacitance of the band limiting comparator 26 and the Schmitt trigger buffer 34 can be reduced.

[0192] Fig.30 2 is a diagram showing another circuit configuration example of the signal separation unit 21 . Fig.30 The first filter 31 of the signal separation unit 21 shown in FIG. 1 is composed of a capacitor C 23 , C 24 and resistor R 21 , R 22 The capacitor C 23 Set the coupling capacitor C 73 and the first input terminal of the amplifier 33. Capacitor C 24 Set the coupling capacitor C 74 and the second input terminal of the amplifier 33. Resistor R 21 One end of the resistor R is connected to the first input terminal of the amplifier 33, and a constant voltage is applied to the other end. 22 One end of the high-pass filter is connected to the second input terminal of the amplifier 33, and a constant voltage is applied to the other end. The cut-off frequency of the high-pass filter is determined by the capacitor C 23 , C 24 The capacitance value and resistor R 21 , R 22 The amplifier 33 amplifies the high-speed signal output from the first filter 31 and outputs it to the first phase comparator 41.

[0193] The second filter 32 is composed of a bias circuit 35 and a band-limiting comparator 36. A first input terminal of the band-limiting comparator 36 is connected to a signal line that connects the capacitor C23 With coupling capacitor C 73 The second input terminal of the band limiting comparator 36 is connected to a signal line which connects the capacitor C 24 With coupling capacitor C 74 The band limiting comparator 36 can selectively output a low-speed signal and has a low-pass filter function. The bias circuit 35 is provided to set a common voltage of the signal input to the first input terminal and the second input terminal of the band limiting comparator 36. The bias circuit 35 includes a resistor R 23 , R 24 . Resistor R 23 One end of the resistor R is connected to the first input terminal of the band limiting comparator 36, and a constant voltage is applied to the other end of the resistor R 24 One end of is connected to the second input terminal of the band limiting comparator 36, and a constant voltage is applied to the other end.

[0194] By forming such a structure, it is possible to avoid Fig.23 The structure shown in FIG. 1 is shown in FIG. 1 and FIG. 1 is a schematic diagram of a structure shown in FIG. 1 . In addition, the bias circuit 35 and the coupling capacitor C 73 , C 74 Together they form a high-pass filter. Therefore, it is necessary to increase the resistor R 23 , R 24 The resistance value is increased and the cutoff frequency of the high-pass filter is reduced, thereby also allowing low-speed signals to pass.

[0195] Fig.31 2 is a diagram showing another circuit configuration example of the signal separation unit 21 . Fig.31 The signal separation unit 21 shown in FIG. Fig.30 In addition to the structure of the signal separation unit 21, it also has an ESD protection diode D 21 ~D 24 . ESD protection diode D 21 It is provided between the first input terminal of the band limiting comparator 36 and the power supply potential supply terminal. 22 The ESD protection diode D is provided between the first input terminal of the band limiting comparator 36 and the ground potential supply terminal. 23 It is provided between the second input terminal of the band limiting comparator 36 and the power supply potential supply terminal. 24 It is provided between the second input terminal of the band limiting comparator 36 and the ground potential supply terminal.

[0196] Fig.32 2 is a diagram showing another circuit configuration example of the signal separation unit 21 . Fig.32 The signal separation unit 21 shown in FIG. Fig.30 In addition to the structure of the signal separation unit 21, it also has a T coil T21 、T 22 . Fig.33 2 is a diagram showing another circuit configuration example of the signal separation unit 21 . Fig.33 The signal separation unit 21 shown in FIG. Fig.31 In addition to the structure of the signal separation unit 21, it also has a T coil T 21 、T 22 .exist Fig.32 and 33 In the middle, T coil T 21 Set the capacitor C 23 With coupling capacitor C 73 Between. T coil T 22 Set the capacitor C 24 With coupling capacitor C 74 By forming such a structure, the load of the band limiting comparator 36 can be reduced.

[0197] In addition, the band limit comparator 36 may be configured to include: Figures 12A to 12D The low-speed amplifier and Schmitt trigger buffer shown in the figure can have the functions of both a low-pass filter and a comparator according to the structure. By setting the amplifier to a high gain and the threshold of the Schmitt trigger buffer to several hundred mV, the signal and the noise can be separated. In addition, the band-limited comparator 36 can also be used as the signal detection unit 23 for detecting the presence or absence of the low-speed signal, thereby reducing power consumption and circuit layout area.

[0198] As described above, the structure of this embodiment overlaps the high-speed signal and the low-speed signal and sends it from the transmitting device to the receiving device. Therefore, when the receiving device releases the phase lock, it is not necessary to notify the transmitting device of the message from the receiving device. Therefore, it can also be applied to a system that can only send signals in one direction from the transmitting device to the receiving device. In addition, the receiving device can immediately perform frequency tracking. Since there is no need to perform a high-level phase adjustment between the high-speed signal and the low-speed signal sent from the transmitting device to the receiving device in an overlapping state, the circuit design man-hours and power consumption can be reduced. In addition, since the overlapping signal is separated into a high-speed signal and a low-speed signal by a signal separation unit in the receiving device, the phase relationship between the high-speed signal and the low-speed signal can be arbitrary, and the phases of the high-speed signal and the low-speed signal can also be inconsistent with each other. Therefore, it is also unnecessary to make the level transition time (Tr, Tf) of the high-speed signal and the low-speed signal consistent with each other. Therefore, it is possible to suppress the increase in the number of communication links, the increase in the power consumption of the circuit, and the increase in the circuit layout area. In addition, it is also possible to apply it in long-distance transmission.

[0199] As described above, according to the present invention, it is possible to suppress increases in the number of communication links, power consumption, and circuit layout area, and the present invention is applicable also to long-distance transmission.

[0200] From the above description of the present invention, it is apparent that various modifications can be made to the present invention. Such modifications are not considered to be modifications that do not depart from the spirit and scope of the present invention, and modifications that are obvious to all those skilled in the art are encompassed by the following claims.

Claims

1. A sending device, comprising: a high-speed signal generating unit which generates a high-speed signal with a limited frequency band and has an output terminal provided for outputting the high-speed signal; a low-speed signal generating unit that generates a low-speed signal having a frequency lower than a frequency band of the high-speed signal and has an output terminal provided for outputting the low-speed signal; and a signal superimposing unit which generates a superimposed signal by superimposing the high-speed signal and the low-speed signal, and has a first input terminal which is electrically connected to the output terminal of the high-speed signal generating unit and is provided for taking in the high-speed signal, a second input terminal which is electrically connected to the output terminal of the low-speed signal generating unit and is provided for taking in the low-speed signal, and an output terminal which is provided for outputting the superimposed signal, The signal overlapping portion comprises: a power supply circuit, the output of which is a driving voltage that is amplitude-modulated using the low-speed signal; A buffer is driven by a driving voltage applied from the power supply circuit to overlap the high-speed signal with the low-speed signal, the buffer having an input terminal provided for taking in the high-speed signal, and an output terminal electrically connected to the output terminal of the signal overlapping portion and provided for outputting the overlapping signal.

2. The transmitting device according to claim 1, wherein: A ratio of a data rate of the high-speed signal to a frequency of the low-speed signal is an integer ratio.

3. The transmitting device according to claim 1, wherein: The low-speed signal generating unit generates a low-speed signal having a time waveform of a sine wave or a triangular wave.

4. The transmitting device according to claim 1, wherein: The high-speed signal generating unit generates a high-speed signal with a limited frequency band by encoding.

5. The transmitting device according to claim 4, wherein: The high-speed signal generation unit generates a high-speed signal with a limited frequency band by mBnB coding that ensures DC balance.

6. The transmitting device according to claim 1, wherein: The low-speed signal generating unit generates a low-speed signal to which spectrum spreading is performed.

7. The transmitting device according to claim 6, wherein: The high-speed signal generation unit generates a high-speed signal to which spectrum spreading is performed.

8. The transmitting device according to any one of claims 1 to 7, wherein: The high-speed signal generating section includes a serializer that converts parallel data into serial data and outputs the serial data as the high-speed signal via the output terminal of the high-speed signal generating section. The low-speed signal generating unit includes: a phase-locked loop circuit that generates an indication clock and provides the indication clock to the serializer, wherein the indication clock indicates the timing of each bit of the serial data output from the serializer; and a wiring structure that outputs the clock input to the phase-locked loop circuit or the clock output from the phase-locked loop circuit as the low-speed signal to the signal overlapping unit via the output end of the low-speed signal generating unit.

9. The transmitting device according to any one of claims 1 to 7, wherein: The phase relationship between the low-speed signal and the high-speed signal is independent.

10. A receiving device, comprising: a signal separation unit that separates a superimposed signal formed by superimposing a high-speed signal having a limited frequency band and a low-speed signal having a frequency lower than the frequency band of the high-speed signal into the high-speed signal and the low-speed signal, the signal separation unit having an input terminal provided for receiving the superimposed signal, a first output terminal provided for outputting the high-speed signal separated from the superimposed signal, and a second output terminal provided for outputting the low-speed signal separated from the superimposed signal; and A restoration unit having a first input terminal electrically connected to the first output terminal of the signal separation unit and provided for taking in the high-speed signal, and a second input terminal electrically connected to the second output terminal of the signal separation unit and provided for taking in the low-speed signal, the restoration unit performs frequency tracking based on the low-speed signal output from the second output terminal of the signal separation unit, performs phase tracking based on the high-speed signal output from the first output terminal of the signal separation unit, and restores clock and data, The data rate DR of the high-speed signal, the coefficient K corresponding to the data communication method of the high-speed signal, the frequency F of the low-speed signal, and the ratio of the frequency of the clock to the frequency of the low-speed signal at the end of the frequency tracking in the restoration unit, that is, M / N, satisfy the relationship represented by the following formula (1).

11. A receiving device, comprising: a signal separation unit that separates a superimposed signal formed by superimposing a high-speed signal having a limited frequency band and a low-speed signal having a frequency lower than the frequency band of the high-speed signal into the high-speed signal and the low-speed signal, the signal separation unit having an input terminal provided for receiving the superimposed signal, a first output terminal provided for outputting the high-speed signal separated from the superimposed signal, and a second output terminal provided for outputting the low-speed signal separated from the superimposed signal; and A restoration unit having a first input terminal electrically connected to the first output terminal of the signal separation unit and provided for taking in the high-speed signal, and a second input terminal electrically connected to the second output terminal of the signal separation unit and provided for taking in the low-speed signal, the restoration unit performs frequency tracking based on the low-speed signal output from the second output terminal of the signal separation unit, performs phase tracking based on the high-speed signal output from the first output terminal of the signal separation unit, and restores clock and data, The signal separation unit comprises: a first filter, which is arranged between the input terminal and the first output terminal of the signal separation unit and selectively outputs the high-speed signal in the received superimposed signal; and a second filter, which is arranged between the input terminal and the second output terminal of the signal separation unit and selectively outputs the low-speed signal in the received superimposed signal, The frequency F of the low-speed signal, the data rate DR of the high-speed signal, the coefficient L corresponding to the data encoding method of the high-speed signal, the ratio Vr of the amplitude of the high-speed signal to the amplitude of the low-speed signal, and the interference tolerance Gd of the low-speed signal on the frequency band of the high-speed signal satisfy the relationship represented by the following formula (2):

12. A receiving device, comprising: a signal separation unit that separates a superimposed signal formed by superimposing a high-speed signal having a limited frequency band and a low-speed signal having a frequency lower than the frequency band of the high-speed signal into the high-speed signal and the low-speed signal, the signal separation unit having an input terminal provided for receiving the superimposed signal, a first output terminal provided for outputting the high-speed signal separated from the superimposed signal, and a second output terminal provided for outputting the low-speed signal separated from the superimposed signal; a restoration unit having a first input terminal electrically connected to the first output terminal of the signal separation unit and provided for taking in the high-speed signal, and a second input terminal electrically connected to the second output terminal of the signal separation unit and provided for taking in the low-speed signal, the restoration unit performing frequency tracking based on the low-speed signal output from the second output terminal of the signal separation unit and performing phase tracking based on the high-speed signal output from the first output terminal of the signal separation unit to restore clock and data; and an error detection unit, which detects whether the low-speed signal is normal and has an input terminal electrically connected to the second output terminal of the signal separation unit and provided for taking in the low-speed signal, The restoration unit stops a restoration operation when the error detection unit detects that the low-speed signal is abnormal, and restarts the restoration operation when the error detection unit detects that the low-speed signal is normal after the restoration operation is stopped.

13. The receiving device according to claim 12, wherein: The receiving device further includes a second error detection unit that detects whether the high-speed signal is normal and has an input terminal that is electrically connected to the first output terminal of the signal separation unit and is provided to take in the high-speed signal. The restoration unit stops a restoration operation when the second error detection unit detects that the high-speed signal is abnormal, and restarts the restoration operation when the error detection unit detects that the low-speed signal is normal after the restoration operation is stopped.

14. The receiving device according to any one of claims 10 to 13, wherein: The recovery unit comprises: a first phase comparator having a third input terminal, a fourth input terminal provided for taking in an oscillation signal, and an output terminal provided for outputting a first phase difference signal indicating a phase difference between the high-speed signal and the oscillation signal, wherein the third input terminal serves as the first input terminal of the restoration unit, is electrically connected to the first output terminal of the signal separation unit, and is provided for taking in the high-speed signal; a second phase comparator having a fifth input terminal, a sixth input terminal provided for taking in the oscillation signal or a signal obtained by frequency-dividing the oscillation signal, and an output terminal, wherein the fifth input terminal is electrically connected to the second output terminal of the signal separation unit as the second input terminal of the restoration unit and provided for taking in the low-speed signal or a signal obtained by frequency-dividing the low-speed signal, and the output terminal is provided for outputting a second phase difference signal indicating a phase difference between the first input signal taken in via the fifth input terminal and the second input signal taken in via the sixth input terminal; a lock detector for detecting whether a frequency lock is performed between the first input signal and the second input signal; a charge pump having an input terminal and an output terminal, the input terminal being provided for taking in the second phase difference signal during a period in which the lock detector detects that the frequency is not locked, or taking in the first phase difference signal during a period in which the lock detector detects that the frequency is locked, and an output terminal being provided for outputting a correction voltage value for reducing the phase difference indicated by the first phase difference signal or the second phase difference signal; a loop filter having an input terminal electrically connected to the output terminal of the charge pump and provided for taking in the correction voltage value, and an output terminal provided for outputting a control voltage value which increases or decreases in accordance with a change in the correction voltage value taken in; and a voltage controlled oscillator having an input terminal electrically connected to the output terminal of the loop filter and provided for taking in the control voltage value, and an output terminal provided for outputting the oscillation signal having a frequency corresponding to the taken-in control voltage value, While the lock detector detects that the frequency is locked, the restored data is output from the first phase comparator, and the restored clock is output from the voltage-controlled oscillator as the oscillation signal.

15. The receiving device according to any one of claims 10 to 13, wherein: The receiving device further includes a signal detection unit that detects the presence or absence of the low-speed signal and includes an input terminal that is electrically connected to the second output terminal of the signal separation unit and is provided to take in the low-speed signal.

16. The receiving device according to any one of claims 10 to 13, wherein: The phase relationship between the low-speed signal and the high-speed signal is independent.

17. A transceiver system, comprising: The transmitting device according to any one of claims 1 to 9; and The receiving device according to any one of claims 10 to 16, which receives the superimposed signal that arrives via a communication link after being output from the transmitting device.

18. The transceiver system according to claim 17, wherein: The transceiver system includes a plurality of communication units, each of which has the same structure as a communication unit composed of the transmission device and the reception device connected via a communication link. any of the transmitting devices included in the plurality of communication units outputs a superimposed signal obtained by superimposing the high-speed signal and the low-speed signal, and the remaining transmitting devices output the high-speed signal without superimposing it, The receiving device that receives the superimposed signal among the receiving devices included in the plurality of communication units separates the received superimposed signal into the high-speed signal and the low-speed signal, and provides the separated low-speed signal to the remaining receiving devices.

19. The transceiver system according to claim 18, wherein: The receiving devices included in the plurality of communication units each detect whether the superimposed signal is received using a signal detection unit that detects the presence or absence of the low-speed signal.

20. A transceiver system, comprising: The transmitting device according to any one of claims 1 to 9; and One or more relay devices that receive the superimposed signal that arrives via a communication link after being output from the transmitting device, and output the received superimposed signal; and The receiving device according to any one of claims 10 to 16, which receives the superimposed signal arriving via a communication link configured with the one or more relay devices, The relay devices respectively include: A signal separation unit that separates a superimposed signal obtained by superimposing a high-speed signal having a limited frequency band and a low-speed signal having a frequency lower than the frequency band of the high-speed signal into the high-speed signal and the low-speed signal, the signal separation unit having an input terminal provided for receiving the superimposed signal, a first output terminal provided for outputting the high-speed signal separated from the superimposed signal, and a second output terminal provided for outputting the low-speed signal separated from the superimposed signal; a restoration unit having a first input terminal electrically connected to the first output terminal of the signal separation unit and provided for taking in the high-speed signal, and a second input terminal electrically connected to the second output terminal of the signal separation unit and provided for taking in the low-speed signal, the restoration unit performing frequency tracking based on the low-speed signal output from the second output terminal of the signal separation unit and performing phase tracking based on the high-speed signal output from the first output terminal of the signal separation unit to restore clock and data; and a signal superimposing unit that outputs a superimposed signal obtained by superimposing the high-speed signal obtained from the restored data with a signal generated based on the restored clock or the low-speed signal output from the second output terminal of the signal separation unit, the signal superimposing unit having a first input terminal provided for taking in the high-speed signal, a second input terminal provided for taking in the signal generated based on the restored clock or the low-speed signal, and an output terminal provided for outputting the superimposed signal, The low-speed signal has a time waveform of a triangular wave.

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