A simple POS charging surge test system

Abstract

The present invention discloses a simple POS machine charging surge resistance test system, which belongs to the technical field of POS machine performance testing. The system includes: a main control module, which sends a control signal, judges the test situation of the device under test during the test and gives feedback; a surge generation module, which receives the control signal, generates a surge and applies the surge to the device under test; a control detection module, which monitors the charging state of the device under test in real time and feeds back the charging state to the main control module in real time; the surge generation module and the control detection module are both communicatively connected with the main control module. In the present invention, the whole system is simple, and a surge generation module is used to generate a surge and apply the surge to the device under test to simulate the situation that the device under test is subjected to a surge. There is no need to use a surge generator, which reduces the cost and equipment maintenance cost, and the simple POS machine charging surge resistance performance can also be judged.

Description

Technical Field

[0001] The invention belongs to the technical field of POS machine performance testing, and in particular relates to a system capable of performing performance testing on a simple POS machine. Background Art

[0002] POS, also known as point of sale information management system, generally refers to the place in a shopping mall where payment is made for purchases. Generally speaking, POS refers to the computerized transaction system used by automated supermarkets, which uses scanners to read labels and barcodes, electronic cash registers, and other special equipment to record the revenue of the sales point. POS refers to the terminal used in this process. POS is widely used in major business districts. POS on the market can be roughly divided into smart POS and simple POS: Smart POS is widely used in B2C settlement, supporting face payment, QR code payment, magnetic stripe card, IC card, and contactless card payment; simple POS is widely used in C2C settlement, and only supports magnetic stripe card, IC card and contactless card payment required by the bank card testing center.

[0003] Surge is also called sudden wave. As the name implies, it is an instantaneous overvoltage that exceeds the normal working voltage. In the existing simple POS machines, the electrical performance design of the chip pins is compromised because the manufacturers reduce costs. In addition, simple POS machines that are not equipped with adapters when leaving the factory are not subject to the surge test standards in the 3C quality (China Compulsory Certification). Simple POS machines with poor surge resistance are easily damaged in the surge spikes of different charging adapters. Therefore, it is necessary to perform surge resistance tests on simple POS machines during charging to understand the surge resistance performance of simple POS machines. In the prior art, in the process of performing surge resistance tests on simple POS machines, a surge generator is usually used to apply surges to the simple POS machine under test. However, due to the high price of surge generator equipment and the high cost of equipment operation and maintenance, the cost of surge resistance testing for simple POS machines is relatively high and is not suitable for widespread application. Summary of the invention

[0004] To solve the above problems, the present invention provides a simple POS charging surge resistance test system. The whole system is simple, and uses a surge generation module to generate a surge and apply the surge to the device under test to simulate the situation where the device under test is subjected to a surge. There is no need to use a surge generator, which reduces costs and equipment maintenance costs, and can also judge the simple POS charging surge resistance performance.

[0005] Another object of the present invention is to provide a simple POS machine charging surge resistance test system, which is more convenient for judging whether the device under test has an abnormality during the test process. The judgment method is simple, and when an abnormality occurs, the main control chip controls the charging power supply to stop charging the device under test, thereby improving the reliability of the system; it can also realize accurate calculation of the sampling current, and distinguish the test conditions by the color status of the indicator light to judge whether the device under test can pass the surge resistance performance test, and control the display screen to display the current key input value and test status, so that when using the system to test the charging surge resistance performance of the simple POS machine, the operation is more convenient and it is easier to know the surge resistance performance of the simple POS machine.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] A simple POS charging surge protection test system, the system comprising:

[0008] A main control module, which sends out control signals, determines the test status of the device under test during the test process and gives feedback;

[0009] A surge generating module receives a control signal, generates a surge and applies the surge to the device under test;

[0010] A control detection module, which monitors the charging status of the device under test in real time and feeds back the charging status to the main control module in real time;

[0011] The surge generation module and the control detection module are both in communication connection with the main control module.

[0012] In the present invention, the system includes a main control module, a surge generating module and a control detection module. The surge generating module and the control detection module are both communicatively connected to the main control module. The entire system is simple. The main control module sends a control signal to the surge generating module, so that the surge generating module generates a surge and applies the surge to the device to be tested (simple POS machine) to simulate the situation where the device to be tested is subjected to a surge. The control detection module detects the charging status of the device to be tested in real time. The main control module reads the charging status to determine whether the device to be tested has an abnormality during the test. If it is abnormal, it indicates that the device to be tested is damaged by the surge and the surge resistance performance of the device to be tested does not meet the standard. In this process, there is no need to use a surge generator, which reduces costs and equipment maintenance costs. The charging surge resistance performance of the simple POS machine can also be determined.

[0013] Specifically, the main control module includes a main control chip, which sends out a control signal, determines whether the device under test is abnormal during the test and gives feedback; the surge generation module and the control detection module are both communicatively connected to the main control chip.

[0014] In the present invention, the model of the main control chip may be MH1902S, which has five 10-bit ADC potential detection IO ports, which detect the digital test signal returned by the control detection module in real time and protect the normal charging operation of the device under test. When an abnormality is found in the device under test during the test, a termination test instruction will be issued.

[0015] Specifically, the surge generating module includes a first surge generating circuit and a second surge generating circuit, and the two are electrically connected; the main control chip is electrically connected to the first surge generating circuit, and the first surge generating circuit and the second surge generating circuit cooperate with the control signal sent by the main control chip to generate a surge. The surge generating module includes the first surge generating circuit and the second surge generating circuit, and has a simple structure.

[0016] Specifically, the first surge generating circuit includes a first MOS tube and a first resistor, the gate of the first MOS tube is electrically connected to the control end of the main control chip, the source of the first MOS tube is grounded, and the drain of the first MOS tube is electrically connected to the second surge generating circuit; one end of the first resistor is connected to the gate of the first MOS tube, and the other end is connected to the source of the first MOS tube.

[0017] Specifically, the second surge generating circuit includes a second MOS tube, a second resistor, a first voltage-dividing resistor and a first diode; one end of the first voltage-dividing resistor is electrically connected to the drain of the first MOS tube, and the other end of the first voltage-dividing resistor is electrically connected to the gate of the second MOS tube; the source of the second MOS tube is connected to the VDD voltage; one end of the second resistor is connected to the gate of the second MOS tube, and the other end is connected to the source of the second MOS tube; the drain of the second MOS tube is electrically connected to one end of the first diode, and the other end of the first diode outputs a surge signal.

[0018] In the present invention, the first MOS tube is an N-channel MOS tube, the second MOS tube is a P-channel MOS tube, and the VDD voltage can be provided by a programmable power supply of model PWS4721. Before the main control chip gives a control signal (such as a pulse signal), the potentials at both ends of the first resistor are equal, and the first MOS tube is in a non-working state. Then, the potentials at both ends of the second resistor and the first voltage-dividing resistor are equal to the programmable power supply voltage VDD, so the second MOS tube is also in a non-working state. At this time, no surge signal (such as a high-voltage level signal) is output to the device under test.

[0019] When the main control chip outputs a control signal, a potential difference is formed across the first resistor, and the first MOS tube is in a working state (conducted), thereby lowering the potential difference across the first voltage-dividing resistor. As a result, a negative voltage difference is generated across the second resistor, and the second MOS tube is also turned on, outputting a surge signal to the device under test.

[0020] When the main control chip finishes outputting the control signal, the potentials at both ends of the first resistor are equal, the first MOS tube is quickly turned off, and then the potentials at both ends of the second resistor and the first voltage-dividing resistor are equal to the programmable power supply voltage VDD, so the second MOS tube is turned off, and at this time the surge generation module does not output a surge signal to the outside.

[0021] Specifically, the control detection module includes a charging status control circuit and a charging status detection circuit for real-time detection of the charging status of the device under test. One end of the charging status control circuit is connected to the main control chip, and the other end is electrically connected to the device under test. One end of the charging status detection circuit is connected to the charging status control circuit, and the other end is also connected to the main control chip.

[0022] In the present invention, the charging state control circuit is controlled by the main control chip, and the charging state control circuit charges the device under test. The charging state detection circuit is connected to the charging state control circuit to monitor the charging state of the device under test in real time, so that the main control chip can judge whether the device under test has any abnormality, and then shut down the charging output in time when an abnormality occurs and judge the surge resistance performance of the device under test.

[0023] Specifically, the charging state control circuit includes a third MOS tube, a fourth MOS tube, a second voltage-dividing resistor, a third resistor, a fourth resistor, a fifth resistor and a sampling unit; the gate of the third MOS tube is electrically connected to the main control chip, the source of the third MOS tube is grounded, the drain of the third MOS tube is electrically connected to one end of the second voltage-dividing resistor, and the other end of the second voltage-dividing resistor is electrically connected to the gate of the fourth MOS tube; the source of the fourth MOS tube is connected to the VCC voltage, the drain of the fourth MOS tube is connected to the sampling unit, and one end of the charging state detection circuit is connected to the sampling unit; the two ends of the third resistor are respectively connected to the source of the fourth MOS tube and the gate of the fourth MOS tube, one end of the fourth resistor is also connected to the VCC voltage, the other end of the fourth resistor is connected to the gate of the third MOS tube, one end of the fifth resistor is electrically connected to the gate of the third MOS tube, and the other end of the fifth resistor is grounded; the system also includes a buzzer for early warning when power is off, and the buzzer is electrically connected to the main control chip.

[0024] In the present invention, the voltage divider circuit formed by the fourth resistor and the fifth resistor makes the third MOS tube always in a saturated state, the fourth MOS tube is normally open, and the current flows through the fourth MOS tube to charge the device under test. The drain of the fourth MOS tube is connected to the sampling unit, so that the charging state detection circuit can sample the current charging state in real time, and the main control chip reads the charging state in real time to determine whether the device under test is abnormal during the test process. In the abnormal state, the main control chip gives a termination test shutdown instruction, and controls the third MOS tube to shut down the fourth MOS tube to stop charging the device under test. In addition, when the program-controlled power supply is powered off, a buzzer warning can be triggered, and the main control chip will shut down the charging in the charging state control detection circuit and stop the operation of the surge generation module.

[0025] Specifically, the sampling unit includes a sampling resistor and a second diode; one end of the sampling resistor is connected to the drain of the fourth MOS tube, and the other end is connected to one end of the second diode, and the other end of the second diode is connected to the device under test;

[0026] The charging state detection circuit includes an operational amplifier, a sixth resistor, a seventh resistor, an eighth resistor and a ninth resistor; the output end of the operational amplifier is electrically connected to the main control chip, one end of the sixth resistor is electrically connected to the in-phase input end of the operational amplifier, and the other end is electrically connected to one end of the sampling resistor; one end of the seventh resistor is electrically connected to the inverting input end of the operational amplifier, and the other end is electrically connected to the other end of the sampling resistor; one end of the eighth resistor is also connected to the in-phase input end of the operational amplifier, and the other end is grounded; one end of the ninth resistor is connected to the output end of the operational amplifier, and the other end is connected to the inverting input end of the operational amplifier.

[0027] In the present invention, the operational amplifier detects the charging current at both ends of the sampling resistor, and the operational amplifier can select a 40dB high-gain subtraction operational amplifier to achieve accurate calculation of the sampling current.

[0028] Specifically, the system also includes a display module for displaying the surge test status of the device under test, and the display module is communicatively connected to the main control chip; the system also includes a data interaction module for data interaction with the Internet of Things, and the data interaction module is also communicatively connected to the main control chip.

[0029] Specifically, the display module includes a key panel, a display screen, and a status indicator light, and the key panel, the display screen, and the status indicator light are all connected to the main control chip for communication; the data interaction module includes a Bluetooth module that establishes communication with the main control chip.

[0030] In the present invention, the key panel may include a 4x4 matrix keyboard, with a total of 16 keys, including 10 digital keys: numbers 0-9, and 6 function keys: up, down, start, reset, stop, and confirm; the status indicator light may include 3 operating states, which may be distinguished by color, such as yellow, blue, and red. When the indicator light displays a yellow state, it indicates that the device under test is in the process of surge testing; when the indicator light displays a blue state, it indicates that the device under test has passed the surge resistance performance test; when the indicator light displays a red state, it indicates that the device under test is damaged in the surge test and the surge resistance test has failed.

[0031] Specifically, the Bluetooth module includes a Bluetooth chip and an antenna, and the two are communicatively connected. The Bluetooth chip model may be WS8200, and the antenna is used to communicate with the Internet of Things, transmit the test status to the external production line system in real time, and record the test status of the device under test.

[0032] The advantages of the present invention are:

[0033] Compared with the prior art, the simple POS charging surge resistance test system of the present invention is simple in the entire system, and uses a surge generation module to generate a surge and apply the surge to the device under test to simulate the situation where the device under test is subjected to a surge. There is no need to use a surge generator, thus reducing costs and equipment maintenance costs, and the simple POS charging surge resistance performance can also be judged.

[0034] The system is more convenient for judging whether the device under test has an abnormality during the test process. The judgment method is simple, and when an abnormality occurs, the main control chip controls the charging power supply to stop charging the device under test, thereby improving the reliability of the system. The system can also realize accurate calculation of the sampling current, and distinguish the test conditions by the color state of the indicator light to judge whether the device under test can pass the surge resistance performance test, and control the display screen to display the current key input value and test status, so that when the system is used to test the charging surge resistance performance of the simple POS machine, the operation is more convenient and it is easier to know the surge resistance performance of the simple POS machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The present invention is a system block diagram of a simple POS charging surge protection test system.

[0036] Figure 2 It is a specific system block diagram of the simple POS charging surge protection test system implemented by the present invention.

[0037] Figure 3 It is a schematic diagram of the interface structure for human-computer interaction in the system implemented by the present invention.

[0038] Figure 4 It is a circuit schematic diagram of a surge generation module in the system implemented by the present invention.

[0039] Figure 5 It is a circuit schematic diagram of the control detection module in the system implemented by the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0041] The technical solution of the present invention is as follows:

[0042] like Figure 1-5 The simple POS charging surge protection test system implemented by the present invention comprises:

[0043] Main control module: the main control module sends out control signals, judges the test status of the device under test (simple POS machine) during the test process and gives feedback;

[0044] A surge generating module receives a control signal, generates a surge and applies the surge to the device under test;

[0045] A control detection module, which monitors the charging status of the device under test in real time and feeds back the charging status to the main control module in real time;

[0046] The surge generation module and the control detection module are both connected to the main control module for communication.

[0047] In the present invention, the system includes a main control module, a surge generating module and a control detection module. The surge generating module and the control detection module are both communicatively connected to the main control module. The whole system is simple. The main control module sends a control signal to the surge generating module, so that the surge generating module generates a surge and applies the surge to the device under test to simulate the situation where the device under test is subjected to a surge. The control detection module detects the charging status of the device under test in real time. The main control module reads the charging status to determine whether the device under test has an abnormality during the test. If it is abnormal, it indicates that the device under test is damaged by the surge and the surge resistance performance of the device under test does not meet the standard. In this process, there is no need to use a surge generator, which reduces costs and equipment maintenance costs. The charging surge resistance performance of a simple POS machine can also be determined.

[0048] In this embodiment, the main control module includes a main control chip, which sends a control signal, determines whether the device under test is abnormal during the test and gives feedback; the surge generation module and the control detection module are both communicatively connected to the main control chip.

[0049] In the present invention, the model of the main control chip may be MH1902S, which has five 10-bit ADC potential detection IO ports, which detect the digital test signal returned by the control detection module in real time and protect the normal charging operation of the device under test. When an abnormality is found in the device under test during the test, a termination test instruction will be issued.

[0050] In this embodiment, the surge generating module includes a first surge generating circuit and a second surge generating circuit, and the two are electrically connected; the main control chip is electrically connected to the first surge generating circuit, and the first surge generating circuit and the second surge generating circuit cooperate with the control signal sent by the main control chip to generate a surge. The surge generating module includes the first surge generating circuit and the second surge generating circuit, and has a simple structure; the main control chip gives the surge generating module a pulse trigger signal, so that the surge generating module applies a surge to the device under test.

[0051] In this embodiment, the first surge generating circuit includes a first MOS tube Q1 and a first resistor R1, the gate of the first MOS tube Q1 is electrically connected to the control end of the main control chip 1, the source of the first MOS tube Q1 is grounded, and the drain of the first MOS tube Q1 is electrically connected to the second surge generating circuit; one end of the first resistor R1 is connected to the gate of the first MOS tube Q1, and the other end is connected to the source of the first MOS tube Q1.

[0052] In this embodiment, the second surge generating circuit includes a second MOS tube Q2, a second resistor R3, a first voltage-dividing resistor R2 and a first diode D1; one end of the first voltage-dividing resistor R2 is electrically connected to the drain of the first MOS tube Q1, and the other end of the first voltage-dividing resistor R2 is electrically connected to the gate of the second MOS tube Q2; the source of the second MOS tube Q2 is connected to the VDD voltage; one end of the second resistor R3 is connected to the gate of the second MOS tube Q2, and the other end is connected to the source of the second MOS tube Q2; the drain of the second MOS tube Q2 is electrically connected to one end of the first diode D1, and the other end of the first diode D1 outputs a surge signal.

[0053] In the present invention, the first MOS tube Q1 is an N-channel MOS tube, the second MOS tube Q2 is a P-channel MOS tube, and the VDD voltage can be provided by a programmable power supply of model PWS4721. Before the main control chip gives a pulse trigger signal, the potentials at both ends of the first resistor R1 are equal, and the first MOS tube Q1 is in a non-working state. Then, the potentials at both ends of the second resistor R3 and the first voltage-dividing resistor R2 are equal to the programmable power supply voltage VDD, so the second MOS tube Q2 is also in a non-working state. At this time, no surge signal (such as a high-voltage level signal) is output to the device under test.

[0054] Among them, VDD can also come from the power adapter, and a backup power supply can be added to ensure the normal operation of the main control chip in case of sudden power failure; in addition, the first diode D1 is unidirectionally conducted to prevent the surge voltage from flowing back to the control system during the test and burning the 5V power adapter. In addition, in order to increase the reliability of this embodiment, in the surge generation module, the first MOS tube Q1 selects a low-latency NMOS tube (NCE2003) with a switch response of less than 20ns, and the second MOS tube Q2 selects a low-latency PMOS tube (NCE01P03S) with a switch response of less than 20ns.

[0055] In the present invention, when the main control chip outputs a control signal, a potential difference is formed across the first resistor R1, and the first MOS tube Q1 is in a working state (conducting), thereby lowering the potential difference across the first voltage-dividing resistor R2, thereby generating a negative voltage difference across the second resistor R3, and the second MOS tube Q2 is also turned on, applying a 72V surge pulse to the device 2 under test.

[0056] When the main control chip finishes outputting the control signal, the potentials at both ends of the first resistor R1 are equal, the first MOS tube Q1 is quickly turned off, and then the potentials at both ends of the second resistor R3 and the first voltage-dividing resistor R2 are equal to the programmable power supply voltage VDD, so the second MOS tube Q2 is turned off, and at this time the surge generation module does not output a surge signal to the outside.

[0057] In this embodiment, the control detection module includes a charging status control circuit and a charging status detection circuit for real-time detection of the charging status of the device under test. One end of the charging status control circuit is connected to the main control chip, and the other end is electrically connected to the device under test. One end of the charging status detection circuit is connected to the charging status control circuit, and the other end is also connected to the main control chip.

[0058] In the present invention, the charging state control circuit is controlled by the main control chip, and the charging state control circuit charges the device under test. The charging state detection circuit is connected to the charging state control circuit to monitor the charging state of the device under test in real time, so that the main control chip can judge whether the device under test has any abnormality, and then shut down the charging output in time when an abnormality occurs and judge the surge resistance performance of the device under test.

[0059] In this embodiment, the charging state control circuit includes a third MOS tube Q3, a fourth MOS tube Q4, a second voltage-dividing resistor R5, a third resistor R4, a fourth resistor R6, a fifth resistor R7 and a sampling unit; the gate of the third MOS tube Q3 is electrically connected to the main control chip, the source of the third MOS tube Q3 is grounded, the drain of the third MOS tube Q3 is electrically connected to one end of the second voltage-dividing resistor R5, and the other end of the second voltage-dividing resistor R5 is electrically connected to the gate of the fourth MOS tube Q4; the source of the fourth MOS tube Q4 is connected to the VCC voltage, and the fourth MOS tube Q4 is connected to the VCC voltage. The drain of Q4 is connected to the sampling unit, and one end of the charging state detection circuit is connected to the sampling unit; two ends of the third resistor R4 are respectively connected to the source of the fourth MOS tube Q4 and the gate of the fourth MOS tube Q4, one end of the fourth resistor R6 is also connected to the VCC voltage, and the other end of the fourth resistor R6 is connected to the gate of the third MOS tube Q3, one end of the fifth resistor R7 is electrically connected to the gate of the third MOS tube Q3, and the other end of the fifth resistor R7 is grounded; the system also includes a buzzer for early warning when power is off, and the buzzer is electrically connected to the main control chip.

[0060] In the present invention, the third MOS tube Q3 and the fourth MOS tube Q4 can be an N-channel MOS tube and a P-channel MOS tube respectively; the voltage divider circuit formed by the fourth resistor R6 and the fifth resistor R7 makes the third MOS tube Q3 always in a saturated state, the fourth MOS tube Q4 is normally open, and the current flows through the fourth MOS tube Q4 to charge the device under test. The drain of the fourth MOS tube Q4 is connected to the sampling unit, so that the charging state detection circuit can sample the current charging current in real time, and the main control chip reads the current state in real time to judge whether the device under test is abnormal during the test process (with the charging current exceeding the current threshold as the judgment standard). In the abnormal state, the main control chip gives a termination test shutdown instruction, and controls the third MOS tube Q3 to turn off the fourth MOS tube Q4 to stop charging the device under test. In addition, when the program-controlled power supply is powered off, a buzzer warning can be triggered, and the main control chip will turn off the charging in the charging state control detection circuit and stop the operation of the surge generation module.

[0061] In this embodiment, the sampling unit includes a sampling resistor R12 and a second diode D2; one end of the sampling resistor R12 is connected to the drain of the fourth MOS transistor Q4, and the other end is connected to one end of the second diode D2, and the other end of the second diode D2 is connected to the device under test;

[0062] The charging state detection circuit includes an operational amplifier U1, a sixth resistor R8, a seventh resistor R9, an eighth resistor R10 and a ninth resistor R11; the output end of the operational amplifier U1 is electrically connected to the main control chip, one end of the sixth resistor R8 is electrically connected to the in-phase input end of the operational amplifier U1, and the other end is electrically connected to one end of the sampling resistor R12; one end of the seventh resistor R9 is electrically connected to the inverting input end of the operational amplifier U1, and the other end is electrically connected to the other end of the sampling resistor R12; one end of the eighth resistor R10 is also connected to the in-phase input end of the operational amplifier U1, and the other end is grounded; one end of the ninth resistor R11 is connected to the output end of the operational amplifier U1, and the other end is connected to the inverting input end of the operational amplifier U1.

[0063] In the present invention, the operational amplifier U1 detects the charging current across the sampling resistor R12. The operational amplifier U1 can select a 40dB high-gain subtraction operational amplifier to achieve accurate calculation of the sampling current, specifically:

[0064]

[0065] U0 is the output voltage of the subtraction operational amplifier U1.

[0066] In this embodiment, the power supply provides power to the main control chip and also provides the 5V voltage required for charging to the device under test. The output voltage pin of the power supply is connected in series with the fourth MOS tube Q4 as a charging protection switch. The fourth MOS tube Q4 is connected in series with the sampling resistor R12 to sample the current charging current in real time.

[0067] In this embodiment, the system also includes a display module for displaying the surge test status of the device under test, and the display module is communicatively connected to the main control chip; the system also includes a data interaction module for data interaction with the Internet of Things, and the data interaction module is also communicatively connected to the main control chip.

[0068] In this embodiment, the display module includes a button panel, a display screen, and a status indicator light, and the button panel, the display screen, and the status indicator light are all connected to the main control chip for communication; the data interaction module includes a Bluetooth module that establishes communication with the main control chip.

[0069] In the present invention, the key panel may include a 4x4 matrix keyboard, with a total of 16 keys, including 10 digital keys: numbers 0-9, and 6 function keys: up, down, start, reset, stop, and confirm; the status indicator light may include 3 operating states, which can be distinguished by color, such as yellow, blue, and red. When the indicator light displays a yellow state, it means that the device under test is in the process of surge testing; when the indicator light displays a blue state, it means that the surge resistance performance test of the device under test has passed; when the indicator light displays a red state, it means that the device under test is damaged in the surge test and the surge resistance test has failed. The display screen may be an LCD display screen, which is controlled by the main control chip to display the current key input value and test status.

[0070] In this embodiment, the Bluetooth module includes a Bluetooth chip and an antenna, and the two are connected in communication. The Bluetooth chip model may be WS8200, and the antenna is used to communicate with the Internet of Things, transmit the test status to the external production line system in real time, and record the test status of the device under test.

[0071] In this embodiment, the system can be used to perform the following tests on a simple POS machine:

[0072] First, when the 5V charging adapter is connected, the main control chip enters the test mode, turns on the power, and provides the system with the required 72V test voltage; set the single surge test interval time to X seconds and the number of tests to Y times through the key panel. After pressing the start button, the status indicator lights up yellow, and the fourth MOS tube Q4 is turned on under the control of the main control chip to start charging the device under test.

[0073] At the same time, the countdown of Z seconds starts. When the countdown is completed, the main control chip is triggered to generate a 600 nanosecond high pulse signal to the surge generation module. The surge generation module generates a 500ns-72V surge voltage to test the surge resistance of the device under test. At the same time, the number of tests starts to accumulate from 0, and the control detection module starts to send back the charging status to the main control chip in real time.

[0074] First, during the process of accumulating the number of tests from 0 to Y, if the main control chip reads that the charging current sent back by the control detection module exceeds the threshold for 2 consecutive seconds, it will determine that the device under test is damaged by the surge and the device's surge resistance performance does not meet the standard. The main control chip will turn off the 5V charging in the charging status control detection module, stop the surge output of the surge generating module, the status indicator light will turn on red, the 1.8-inch LCD display will show that the test failed, and the Bluetooth module will automatically send the test record of the device under test back to the production line system.

[0075] Second, after the number of tests accumulates to Y, if the main control chip reads the charging current sent back by the control detection module for 2 consecutive seconds and it does not exceed the threshold, it will determine that the surge resistance performance of the device under test meets the standard. The main control chip will turn off the 5V charging in the control detection module and stop the surge output of the surge generating module. The status indicator light will turn on blue and the 1.8-inch LCD display will show that the test is passed. The Bluetooth module will automatically send the test record of the device under test back to the production line system.

[0076] The advantages of the present invention are:

[0077] Compared with the prior art, the simple POS charging surge resistance test system implemented by the present invention is simple in the entire system, and uses a surge generation module to generate a surge and apply the surge to the device under test to simulate the situation where the device under test is subjected to a surge. There is no need to use a surge generator, thus reducing costs and equipment maintenance costs, and the simple POS charging surge resistance performance can also be judged.

[0078] The system uses the charging current exceeding the current threshold as the judgment standard to enable the main control chip to more conveniently judge whether the device under test has an abnormality during the test process. The judgment method is simple, and in the event of an abnormality, a buzzer warning is triggered, and the main control chip controls the charging power supply to stop charging the device under test, thereby improving the reliability of the system; it can also realize accurate calculation of the sampling current, distinguish the test situation by the color state of the indicator light, so as to judge whether the device under test can pass the surge resistance performance test, and control the display screen to display the current key input value and test status, so that when using the system to test the charging surge resistance performance of the simple POS machine, the operation is more convenient, and it is also easier to know the surge resistance performance of the simple POS machine.

[0079] The above lists the preferred embodiments of the present invention, which are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A simple POS charging surge test system, characterized in that: The system includes: A main control module, which sends out control signals, determines the test status of the device under test during the test process and gives feedback; A surge generating module receives a control signal, generates a surge and applies the surge to the device under test; A control detection module, which monitors the charging status of the device under test in real time and feeds back the charging status to the main control module in real time; The surge generation module and the control detection module are both communicatively connected to the main control module; The main control module includes a main control chip, which sends a control signal, determines whether the device under test is abnormal during the test process and gives feedback; the surge generation module and the control detection module are both connected to the main control chip in communication; The surge generating module includes a first surge generating circuit and a second surge generating circuit, and the two are electrically connected; the main control chip is electrically connected to the first surge generating circuit, and the first surge generating circuit and the second surge generating circuit cooperate with the control signal sent by the main control chip to generate a surge; The control detection module includes a charging status control circuit and a charging status detection circuit for real-time detection of the charging status of the device under test. One end of the charging status control circuit is connected to the main control chip, and the other end is electrically connected to the device under test. One end of the charging status detection circuit is connected to the charging status control circuit, and the other end is also connected to the main control chip.

2. The simple POS charging surge protection test system as claimed in claim 1, characterized in that: The first surge generating circuit includes a first MOS tube and a first resistor, the gate of the first MOS tube is electrically connected to the control end of the main control chip, the source of the first MOS tube is grounded, and the drain of the first MOS tube is electrically connected to the second surge generating circuit; one end of the first resistor is connected to the gate of the first MOS tube, and the other end is connected to the source of the first MOS tube.

3. The simple POS charging surge protection test system as claimed in claim 2, characterized in that: The second surge generating circuit includes a second MOS tube, a second resistor, a first voltage-dividing resistor and a first diode; one end of the first voltage-dividing resistor is electrically connected to the drain of the first MOS tube, and the other end of the first voltage-dividing resistor is electrically connected to the gate of the second MOS tube; The source of the second MOS tube is connected to the VDD voltage; one end of the second resistor is connected to the gate of the second MOS tube, and the other end is connected to the source of the second MOS tube; the drain of the second MOS tube is electrically connected to one end of the first diode, and the other end of the first diode outputs a surge signal.

4. The simple POS charging surge protection test system as claimed in claim 1, characterized in that: The charging state control circuit comprises a third MOS tube, a fourth MOS tube, a second voltage-dividing resistor, a third resistor, a fourth resistor, a fifth resistor and a sampling unit; the gate of the third MOS tube is electrically connected to the main control chip, the source of the third MOS tube is grounded, the drain of the third MOS tube is electrically connected to one end of the second voltage-dividing resistor, and the other end of the second voltage-dividing resistor is electrically connected to the gate of the fourth MOS tube; the source of the fourth MOS tube is connected to the VCC voltage, the drain of the fourth MOS tube is connected to the sampling unit, and one end of the charging state detection circuit is connected to the sampling unit; Two ends of the third resistor are respectively connected to the source of the fourth MOS tube and the gate of the fourth MOS tube, one end of the fourth resistor is also connected to the VCC voltage, the other end of the fourth resistor is connected to the gate of the third MOS tube, one end of the fifth resistor is electrically connected to the gate of the third MOS tube, and the other end of the fifth resistor is grounded; the system also includes a buzzer for early warning when power is off, and the buzzer is electrically connected to the main control chip.

5. The simple POS charging surge protection test system as claimed in claim 4, characterized in that: The sampling unit includes a sampling resistor and a second diode; one end of the sampling resistor is connected to the drain of the fourth MOS tube, and the other end is connected to one end of the second diode, and the other end of the second diode is connected to the device under test; The charging state detection circuit includes an operational amplifier, a sixth resistor, a seventh resistor, an eighth resistor and a ninth resistor; the output end of the operational amplifier is electrically connected to the main control chip, one end of the sixth resistor is electrically connected to the in-phase input end of the operational amplifier, and the other end is electrically connected to one end of the sampling resistor; one end of the seventh resistor is electrically connected to the inverting input end of the operational amplifier, and the other end is electrically connected to the other end of the sampling resistor; one end of the eighth resistor is also connected to the in-phase input end of the operational amplifier, and the other end is grounded; one end of the ninth resistor is connected to the output end of the operational amplifier, and the other end is connected to the inverting input end of the operational amplifier.

6. The simple POS charging surge protection test system as claimed in claim 1, characterized in that: The system also includes a display module for displaying the surge protection test status of the device under test, and the display module is communicatively connected to the main control chip; the system also includes a data interaction module for data interaction with the Internet of Things, and the data interaction module is also communicatively connected to the main control chip.

7. The simple POS charging surge protection test system as claimed in claim 6, characterized in that: The display module includes a button panel, a display screen, and a status indicator light, and the button panel, display screen, and status indicator light are all communicatively connected to the main control chip; the data interaction module includes a Bluetooth module that establishes communication with the main control chip; the Bluetooth module includes a Bluetooth chip and an antenna, and the two are communicatively connected.

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