Method for in-memory processing using a memory device and memory device

Abstract

A method for processing in memory using a memory device and a memory device are disclosed. In the processing in memory (PIM) method using the memory device, m×n multiplicand arrangement bits are stored in m×n memory cells by copying and arranging m multiplicand bits of a multiplicand value, and m×n multiplier arrangement bits are stored in m×n read-write unit circuits corresponding to the m×n memory cells by copying and arranging n multiplier bits of a multiplier value. Based on the m×n multiplier arrangement bits stored in the m×n read-write unit circuits, the m×n multiplicand arrangement bits stored in the m×n memory cells are selectively read, and the m×n multiplication bits are stored in the m×n read-write unit circuits based on the selectively read m×n multiplicand arrangement bits. The multiplication value of the multiplicand value and the multiplier value is determined based on the m×n multiplication bits stored in the m×n read-write unit circuits.

Description

[0001] The entire contents of Korean Patent Application No. 10-2018-0173364, filed on December 31, 2018 in the Korean Intellectual Property Office (KIPO), are incorporated herein by reference for the claim of priority. Technical Field

[0002] The present disclosure relates generally to semiconductor integrated circuits, and more particularly, to a method of using a process-in-memory (PIM) of a memory device, and a memory device that performs the process-in-memory. Background Art

[0003] Memory bandwidth and latency are performance bottlenecks in many processing systems. Memory capacity can be increased by using a stacked memory device, in which multiple semiconductor devices are stacked in a package of a memory chip. The stacked semiconductor die can be electrically connected by using through silicon vias or through substrate vias (TSVs). In addition, a vertical NAND flash memory device includes memory cells arranged or stacked in a vertical direction to increase memory capacity. Such stacking technology can increase memory capacity and can also suppress bandwidth and latency penalties. However, each access of an external device to a stacked memory device involves data communication between stacked semiconductor dies. In this case, two device-to-device bandwidth and device-to-device latency penalties may occur for each access. Therefore, when the task of an external device requires multiple accesses to a stacked memory device, the device-to-device bandwidth and device-to-device latency will have a significant impact on the processing efficiency and power consumption of the system. Summary of the invention

[0004] Embodiments of the inventive concept provide a memory device capable of efficiently performing process-in-memory (PIM) or computation-in-memory (CIM) and / or a process-in-memory method using the same.

[0005] Embodiments of the inventive concept provide a process-in-memory (PIM) method using a memory device. The method includes: by copying and arranging m multiplicand bits of a multiplicand value, storing m×n multiplicand arrangement bits in m×n memory cells of a memory device, wherein m and n are natural numbers greater than 0; by copying and arranging n multiplier bits of a multiplier value, storing m×n multiplier arrangement bits in m×n read-write unit circuits corresponding to the m×n memory cells of the memory device; selectively reading the m×n multiplicand arrangement bits stored in the m×n memory cells based on the m×n multiplier arrangement bits stored in the m×n read-write unit circuits, and storing m×n multiplication bits in the m×n read-write unit circuits based on the selectively read m×n multiplicand arrangement bits, the m×n multiplication bits corresponding to the bit-by-bit multiplication value of the m×n multiplicand arrangement bits and the m×n multiplier arrangement bits; and determining the multiplication value of the multiplicand value and the multiplier value based on the m×n multiplication bits stored in the m×n read-write unit circuits.

[0006] Embodiments of the inventive concept also provide a processing-in-memory (PIM) method using a memory device. The method includes: determining each of p×r×q (i, k, j) multiplication values ​​by multiplying (i, k) multiplicand values ​​included in a p-row and r-column multiplicand matrix with (k, j) multiplier values ​​included in an r-row and q-column multiplier matrix for all i, k, and j, where i is a natural number from 1 to p, k is a natural number from 1 to r, and j is a natural number from 1 to q; and determining each of p×q (i, j) component values ​​included in a p-row and q-column multiplication matrix corresponding to the multiplication of the multiplicand matrix and the multiplier matrix by summing the r (i, k, j) multiplication values ​​for all k. The step of determining a p×r×q (i, k, j) multiplication value among the p×r×q (i, k, j) multiplication values ​​comprises: by copying and arranging m multiplicand bits of the (i, k) multiplicand value, storing the m×n multiplicand arrangement bits in m×n memory cells of the memory device, wherein m and n are natural numbers greater than 0; by copying and arranging n multiplier bits of the (k, j) multiplier value, storing the m×n multiplier arrangement bits in m×n read-write unit circuits corresponding to the m×n memory cells of the memory device; based on the data stored in the m×n read-write unit circuits, The invention relates to a method for determining a p×r×q(i, k, j) multiplication value of a (i, k) multiplicand value and a (k, j) multiplier value based on the m×n multiplicand arrangement bits in the m×n memory cells, and storing m×n multiplication bits in m×n read-write unit circuits based on the selectively read m×n multiplicand arrangement bits, the m×n multiplication bits corresponding to the bit-by-bit multiplication value of the m×n multiplicand arrangement bits and the m×n multiplier arrangement bits; and determining a p×r×q(i, k, j) multiplication value of a (i, k) multiplicand value and a (k, j) multiplier value based on the m×n multiplication bits stored in the m×n read-write unit circuits.

[0007] An embodiment of the inventive concept also provides a memory device, which includes: a data copy and arrangement circuit, configured to generate multiplicand arrangement bits by copying and arranging multiplicand bits of multiplicand values ​​included in a multiplicand matrix, and to generate multiplier arrangement bits by copying and arranging multiplier bits of multiplier values ​​included in a multiplier matrix; a memory cell array, including memory cells connected to bit lines and configured to store multiplicand arrangement bits; a read-write unit circuit, connected to the bit lines and configured to: store multiplier arrangement bits, receive multiplicand arrangement bits selectively read from the memory cells based on the multiplier arrangement bits stored in the read-write unit circuit, and store multiplication bits based on the multiplicand arrangement bits selectively read from the memory cells, the multiplication bits corresponding to the bit-by-bit multiplication values ​​of the multiplicand arrangement bits and the multiplier arrangement bits; and an operation circuit, configured to determine the component values ​​of the multiplication matrix corresponding to the multiplication of the multiplicand matrix and the multiplier matrix based on the multiplication bits stored in the read-write unit circuit.

[0008] An embodiment of the inventive concept also provides a memory system, the memory system comprising: a memory controller; and a non-volatile memory device, comprising a memory cell array and a read-write unit circuit, the read-write unit circuit accessing the memory cell of the memory cell array in response to the memory controller. The non-volatile memory device stores the multiplicand arrangement bits in the memory cell by copying and arranging the multiplicand bits of the multiplicand value; stores the multiplier arrangement bits in the read-write unit circuit corresponding to the memory cell by copying and arranging the multiplier bits of the multiplier value; selectively reads the multiplicand arrangement bits stored in the memory cell based on the multiplier arrangement bits stored in the read-write unit circuit, stores the multiplication bits in the read-write unit circuit based on the selectively read multiplicand arrangement bits, the multiplication bits corresponding to the bit-by-bit multiplication value of the multiplicand arrangement bits and the multiplier arrangement bits; and determines the multiplication value of the multiplicand value and the multiplier value based on the multiplication bits stored in the read-write unit circuit.

[0009] A memory device and a process-in-memory (PIM) method according to an embodiment of the inventive concept can reduce processing time and power consumption by performing data-intensive processing using a read / write circuit and an operation circuit included in the memory device to reduce the amount of data transmitted between the memory device and an external device.

[0010] A memory device and a processing-in-memory (PIM) method according to an embodiment of the inventive concept can reduce processing time and power consumption by using read and write circuits to perform data-intensive processing (such as MLP (Multi-layer Perceptron), RNN (Recurrent Neural Network), CNN (Convolutional Neural Network), etc.) through efficient rearrangement of data and parallel bit-by-bit multiplication. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 A flowchart of a process-in-memory (PIM) method according to an embodiment of the inventive concept is shown.

[0013] Figure 2 Data rearrangement of multiplicand bits and multiplier bits according to an embodiment of the inventive concept is shown.

[0014] Figure 3 The embodiment according to the inventive concept is shown Figure 2 Bit-by-bit multiplication of the rearranged data.

[0015] Figure 4 Data rearrangement of multiplicand bits and multiplier bits according to other embodiments of the inventive concept is shown.

[0016] Figure 5 The embodiment according to the inventive concept is shown Figure 4 Bit-by-bit multiplication of the rearranged data.

[0017] Figure 6 Circuit diagram showing read bias conditions for a three-dimensional flash memory.

[0018] Figure 7 A diagram illustrating a selective read operation applicable to a Process-In-Memory (PIM) method according to an embodiment of the inventive concept.

[0019] Figure 8 A diagram illustrating another selective read operation applicable to a process-in-memory (PIM) method according to an embodiment of the inventive concept.

[0020] Fig. 9 A weighted adder included in a memory device according to an embodiment of the inventive concept is shown.

[0021] Fig.10 Another weighted adder included in a memory device according to an embodiment of the inventive concept is shown.

[0022] Fig.11 A diagram illustrating data rearrangement according to an embodiment of the inventive concept.

[0023] Fig.12 Show according to Fig.11 FIG. 1 is a diagram of a multiplication bit of a selective read operation of rearranged data.

[0024] Fig.13 Shown based on Fig.12 Schematic diagram of the weighted addition operation of the multiplication bits.

[0025] Fig.14 A diagram illustrating multiplication bits according to a selective read operation of rearranged data according to an embodiment of the inventive concept.

[0026] Fig.15 Shown based on Fig.14 Schematic diagram of the weighted addition operation of the multiplication bits.

[0027] Fig.16 A diagram illustrating data rearrangement according to an embodiment of the inventive concept.

[0028] Fig.17 Show according to Fig.16 FIG. 1 is a diagram of a multiplication bit of a selective read operation of rearranged data.

[0029] Fig.18 Shown based on Fig.17 Schematic diagram of the weighted addition operation of the multiplication bits.

[0030] Fig.19A , Fig.19B , Fig.19C , Fig.19D and Fig.19E A diagram illustrating a data rearrangement method according to an embodiment of the inventive concept.

[0031] Fig. 20 A block diagram of a memory system according to an embodiment of the inventive concept is shown.

[0032] Fig.21 A block diagram of a nonvolatile memory device according to an embodiment of the inventive concept is shown.

[0033] Fig.22A Shown included in Fig.21 A block diagram of a memory cell array in a nonvolatile memory device.

[0034] Fig. 22B Show reference Fig.22A A circuit diagram depicting the equivalent circuit of the memory block.

[0035] Fig.23 A diagram describing an example of a deep learning neural network structure driven by an artificial neural network (ANN) system using a memory device according to one or more embodiments of the inventive concept is shown.

[0036] Fig.24 Diagram showing an example of matrix multiplication.

[0037] Fig.25 A flowchart illustrating a matrix multiplication method using a memory device according to an embodiment of the inventive concept is shown.

[0038] Fig.26 A command set of a matrix multiplication method using a memory device according to an embodiment of the inventive concept is shown.

[0039] Fig. 27 A command set of a matrix multiplication method using a memory device according to an embodiment of the inventive concept is shown.

[0040] Fig.28 A diagram illustrating an operation circuit included in a memory device according to an embodiment of the inventive concept.

[0041] Fig.29 A diagram illustrating an operation circuit included in a memory device according to an embodiment of the inventive concept.

[0042] Fig.30 A diagram illustrating a page buffer included in a memory device according to an embodiment of the inventive concept.

[0043] Fig.31A block diagram illustrating a mobile system including a memory device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0044] Various exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. In the accompanying drawings, like reference numerals refer to like elements throughout, and repeated description of the like elements may be omitted.

[0045] As a tradition in the field of inventive conception, embodiments can be described and illustrated according to the block of one or more functions of the execution description.These blocks, which may be referred to as units or modules, are physically implemented by analog and / or digital circuits (such as, logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc.), and may be optionally driven by firmware and / or software.For example, the circuit may be implemented in one or more semiconductor chips, or on a substrate support such as a printed circuit board.The circuit of the composition block may be implemented by dedicated hardware, or by a processor (for example, one or more programmed microprocessors and associated circuits), or by a combination of dedicated hardware for performing some functions of the block and a processor for performing other functions of the block.Without departing from the scope of the inventive conception, each block of the embodiment may be physically divided into two or more interactive and discrete blocks.Similarly, without departing from the scope of the inventive conception, the block of the embodiment may be physically combined into more complex blocks.

[0046] Figure 1 A flowchart of a process-in-memory (PIM) method according to an embodiment of the inventive concept is shown.

[0047] Figure 1 A process-in-memory (PIM) method using a memory device that performs a read operation and a write operation on a memory cell connected to the bit line using a read-write unit circuit connected to the bit line is shown. Figure 1 The PIM method may include a multiplication and accumulation (MAC) operation method. Figure 1 The PIM method corresponds to the multiplication of two values ​​of multiple bits, where the multiplication may be referred to as scalar multiplication. Scalar multiplication may be used to perform matrix multiplication as will be described below.

[0048] Reference Figure 1 , by copying and arranging the m multiplicand bits of the multiplicand value, the m×n multiplicand arrangement bits are stored in the m×n memory cells, where m and n are natural numbers greater than 0 (S100). In addition, by copying and arranging the n multiplier bits of the multiplier value, the m×n multiplier arrangement bits are stored in the m×n read-write unit circuits corresponding to the m×n memory cells (S200). Figure 1The multiplicand value and the multiplier value described do not indicate a specific value or data or data type, but indicate two arbitrary values ​​to be multiplied. In some example embodiments, the multiplicand value may correspond to a weight value of an artificial neural network (ANN), and the multiplier value may correspond to an input value or an excitation value of the ANN. In some example embodiments, the multiplicand value may correspond to an input value, and the multiplier value may correspond to a weight value.

[0049] The multiplicand and multiplier values ​​can be replicated and arranged by different schemes for bit-by-bit multiplication. Figures 2 to 5 Example embodiments of replication and permutation schemes are described.

[0050] Based on the m×n multiplier arrangement bits stored in the m×n read-write unit circuits, the m×n multiplicand arrangement bits stored in the m×n memory cells are selectively read, and the m×n multiplication bits are stored in the m×n read-write unit circuits based on the selectively read m×n multiplicand arrangement bits (S300). The m×n multiplication bits correspond to the bit-by-bit multiplication value of the m×n multiplicand arrangement bits and the m×n multiplier arrangement bits. The multiplication value of the multiplicand value and the multiplier value is determined based on the m×n multiplication bits stored in the m×n read-write unit circuits (S400).

[0051] In the first example embodiment, the result of the selective read operation may be stored in a latch of the read / write unit circuit storing the multiplier permutation bit. In other words, the multiplier permutation bit stored in the read / write unit circuit may be updated or replaced by the multiplication bit.

[0052] In a second example embodiment, the read / write unit circuit may include a first latch for storing a multiplier arrangement bit and a second latch different from the first latch, so that the result of the selective read operation can be stored in the second latch and the multiplier arrangement bit can be maintained without being replaced.

[0053] Although the PIM method according to the exemplary embodiment is described based on the first exemplary embodiment in the present disclosure, it should be understood that the same PIM method may be performed by the second exemplary embodiment.

[0054] The PIM method using the memory device according to the example embodiment uses the read / write unit circuit necessarily included in the memory device to perform bit-by-bit multiplication for the overall operation of the memory device. The bit-by-bit multiplication can be achieved by storing appropriately rearranged data bits and selectively reading the stored data bits. Fig. 9 and Fig.10 Example embodiments of selective read operations are described.

[0055] As such, a memory device and a PIM method according to example embodiments may reduce processing time and power consumption by performing bit-by-bit multiplication in parallel using efficient data rearrangement and read / write unit circuits and performing addition operations in a memory device as described below.

[0056] Figures 2 to 5 Diagram illustrating data rearrangement and bit-by-bit multiplication of the rearranged data according to an embodiment of the inventive concept.

[0057] exist Figures 2 to 5 In the expression 1, the multiplicand value VA includes m multiplicand bits A0 to Am-1, and the multiplier value VB includes n multiplier bits B0 to Bn-1. The multiplication value VA×VB of the multiplicand value VA and the multiplier value VB can be expressed by Expression 1.

[0058] Expression 1

[0059] VA×VB=(A0×2 0 +A1×2 1 +A2×2 2 +…+Am-1×2 m-1 )×(B0×2 0 +B1×2 1 +B2×2 2 +…+Bn-1×2 n-1 )=A0×B0×2 0 +(A1×B0+A0×B1)×2 1 +…+(Am-1×Bn-1)×2 m+n-2

[0060] In Expression 1, AiBj indicates (i, j) multiplication bits, where i is an integer from 0 to m-1, and j is an integer from 0 to n- 1. The total number of multiplication bits is m×n.

[0061] The multiplicand value VA stored in and selectively read from the memory cell and the multiplier value VB stored in the read / write unit circuit may be copied and arranged by various schemes.

[0062] Reference Figure 2, m×n multiplicand arrangement bits ARRA can be generated by a first copying and arrangement scheme SCH1, so that each of the m multiplicand bits A0 to Am-1 is repeatedly copied and arranged n times to be adjacent to each other, and m×n multiplier arrangement bits ARRB can be generated by a second copying and arrangement scheme SCH2, so that n multiplier bits B0 to Bn-1 are repeatedly copied and arranged m times. For example, according to the arrangement scheme SCH1, the multiplicand bit A0 is copied n times adjacent to each other, and then the multiplicand bit A1 is copied n times adjacent to each other, and so on. For another example, according to the arrangement scheme SCH2, the multiplier value VB (including bits B0 to Bn-1) is repeatedly copied m times.

[0063] Figure 3 Shown with Figure 2 The data is rearranged to correspond to the arrangement of the multiplication bits MBa. The multiplication bits MBa can be grouped into m bit groups GR0, GR1, ..., and GRm-1 (i.e., GR0 to GRm-1) corresponding to the m multiplicand bits A0 to Am-1. The m intermediate multiplication values ​​(AB)0 to (AB)m-1 or A0×B to Am-1×B corresponding to the m bit groups GR0 to GRm-1 can be represented by Expression 2.

[0064] Expression 2

[0065] (AB)i=Ai×B=Ai×(B0×2 0 +B1×2 1 +B2×2 2 +…+Bn-1×2 n-1 )

[0066] Where i is an integer from 0 to m-1

[0067] Using the intermediate multiplication value of Expression 2, the multiplication value VA×VB can be expressed by Expression 3.

[0068] Expression 3

[0069] VA×VB=A0×B×2 0 +A1×B×2 1 +A2×B×2 2 +…+Am-1×B×2 m-1

[0070] =(AB)0×2 0 +(AB)1×2 1 +(AB)2×2 2 +…+(AB)m-1×2 m-1

[0071] =SUMi{Ai×B×2 i}

[0072] As a result, the m weighted intermediate multiplication values ​​A0×B×2 0 To Am-1×B×2 m-1 The sum is performed to determine the multiplication value VA×VB, so that the m weighted intermediate multiplication values ​​A0×B×2 0 To Am-1×B×2 m-1 Each of the m intermediate multiplication values ​​A0×B to Am-1×B and the m bit weights 2 corresponding to the m multiplicand bits A0 to Am-1 0 to 2 m-1 The multiplication value of each in .

[0073] Reference Figure 4 , m×n multiplier arrangement bits ARRB can be generated by a first copying and arrangement scheme SCH1, so that each of the n multiplier bits B0 to Bn-1 is repeatedly copied and arranged m times to be adjacent to each other, and m×n multiplicand arrangement bits ARRA can be generated by a second copying and arrangement scheme SCH2, so that the m multiplicand bits A0 to Am-1 are repeatedly copied and arranged n times. For example, according to the arrangement scheme SCH1, the multiplier bit B0 is copied m times adjacent to each other, and then the multiplier bit B1 is copied m times adjacent to each other, and so on. For another example, according to the arrangement scheme SCH2, the multiplicand value VA (including bits A0 to Am-1) is repeatedly copied n times.

[0074] Figure 5 Shown with Figure 4 The data is rearranged to correspond to the arrangement of the multiplication bits MBb. The multiplication bits MBb can be grouped into n bit groups GR0 to GRn-1 corresponding to the n multiplier bits B0 to Bn-1. The n intermediate multiplication values ​​(AB)0 to (AB)n-1 or A×B0 to A×Bn-1 corresponding to the n bit groups GR0 to GRn-1 can be represented by Expression 4.

[0075] Expression 4

[0076] (AB)j=A×Bj=(A0×2 0 +A1×2 1 +A2×2 2 +…+Am-1×2 m-1 )×Bj

[0077] Where j is an integer from 0 to n-1

[0078] Using the intermediate multiplication value of Expression 4, the multiplication value VA×VB can be expressed by Expression 5.

[0079] Expression 5

[0080] VA×VB=A×B0×2 0 +A×B1×2 1 +A×B2×2 2 +…+A×Bn-1×2 n-1

[0081] =(AB)0×2 0 +(AB)1×2 1 +(AB)2×2 2 +…+(AB)n-1×2 n-1

[0082] =SUMj{A×Bj×2 j}

[0083] As a result, the n weighted intermediate multiplication values ​​A×B0×2 0 To A×Bn-1×2 n-1 The sum is performed to determine the multiplication value VA×VB, so that the n weighted intermediate multiplication values ​​A×B0×2 0 To A×Bn-1×2 n-1 Each of the n intermediate multiplication values ​​A×B0 to A×Bn-1 and the n bit weights 2 corresponding to the n multiplier bits B0 to Bn-1 0 to 2 n-1 The multiplication value of each in .

[0084] Figure 6 Circuit diagram showing read bias conditions for a three-dimensional flash memory.

[0085] For ease of illustration and description, Figure 6 , a block BLK of a three-dimensional flash memory is shown to include NAND strings NS11 and NS21 connected to a first bit line BL1 and NAND strings NS12 and NS22 connected to a second bit line BL2. In other embodiments, the block BLK may include a different number of NAND strings and bit lines.

[0086] During a read operation, the first bit line BL1 and the second bit line BL2 may be precharged from an initialization voltage corresponding to a value of "0" (e.g., 0V) to a precharge voltage corresponding to a value of "1" (e.g., 0.5V). For example, if NAND strings NS21 and NS22 are selected, a voltage of 0V may be applied to the first string selection line SSL1, and a power supply voltage Vcc may be applied to the second string selection line SSL2. In addition, a voltage of 0V may be applied to the first ground selection line GSL1, and a power supply voltage Vcc may be applied to the second ground selection line GSL2. A selected read voltage VR may be applied to a selected word line (e.g., WL5), and an unselected read voltage VPS may be applied to unselected word lines (e.g., WL4 and WL6). In addition, a voltage of 0V may be applied to the common source line CSL.

[0087] Under this example read bias condition, the drain voltage of the selected memory cells A and B is 0.5 V, and the source voltage of the selected memory cells A and B is 0 V. In addition, the selection read voltage VR is applied to the gates of the selected memory cells A and B. In addition, a read operation for verifying the data stored at the memory cells can be performed while changing the voltage level of the selection read voltage VR. The channels of the unselected NAND strings NS11 and NS12 including the memory cells C and D are floated.

[0088] Figure 7 and Figure 8 Diagrams illustrating respective selective read operations applicable to a PIM method according to an embodiment of the inventive concept.

[0089] For ease of illustration and description, Figure 7 and Figure 8 A configuration of four bit lines is shown, but the selective read operation described below can be implemented regardless of the number of bit lines.

[0090] Reference Figure 7 , the first to fourth pre-charging circuits PCCa, PCCb, PCCc and PCCd (i.e., PCCa to PCCd) included in the memory device can pre-charge the first to fourth bit lines BLa, BLb, BLc and BLd (i.e., BLa to BLd) with a pre-charging voltage VPC before sensing the values ​​stored in the first to fourth memory cells MCa, MCb, MCc and MCd (i.e., MCa to MCd).

[0091] In some example embodiments, Figure 7As shown in , a selective read operation SRO can be performed based on the multiplier arrangement bits respectively stored in the first to fourth read-write unit circuits RWUa, RWUb, RWUc, and RWUd (ie, RWUa to RWUd) to selectively precharge the first to fourth bit lines BLa to BLd. Figure 7 In the example of , the first bit line BLa and the fourth bit line BLd corresponding to the multiplier arrangement bit having a value of "1" are precharged from the initialization voltage Vo corresponding to the value "0" to the precharge voltage VPC corresponding to the value "1" by the first precharge circuit PCCa and the fourth precharge circuit PCCd enabled in response to the multiplier arrangement bit having a value of "1". In contrast, because the second precharge circuit and the third precharge circuit are disabled in response to the multiplier arrangement bit having a value of "0", the second bit line BLb and the third bit line BLc corresponding to the multiplier arrangement bit having a value of "0" maintain the initialization voltage Vo.

[0092] While (or after) the first bit line BLa to the fourth bit line BLd are selectively precharged in this way, a sensing operation is performed on the first memory cell MCa to the fourth memory cell MCd. The first memory cell MCa with a value of "1" is turned off, and the first bit line BLa maintains the precharge voltage VPC, so the first read-write unit circuit RWUa maintains the stored value "1". The fourth memory cell MCd with a value of "0" is turned on, and the fourth bit line BLd changes from the precharge voltage VPC to the initialization voltage Vo, so the value of the fourth read-write unit circuit RWUd is updated from "1" to "0". Regardless of the multiplicand arrangement bits stored in the second memory cell MCb and the third memory cell MCc, the second read-write unit circuit RWUb and the third read-write unit circuit RWUc maintain the stored value "0".

[0093] As a result, after the selective read operation SRO is completed, the multiplier arrangement bits stored in the read-write unit circuits RWUa to RWUd are updated to multiplication bits, which correspond to the bit-by-bit multiplication of the multiplicand arrangement bits stored in the memory cells MCa to MCd and the multiplier arrangement bits stored in the read-write unit circuits RWUa to RWUd.

[0094] Reference Figure 8 , the first to fourth switch circuits SWa, SWb, SWc and SWd (i.e., SWa to SWd) included in the memory device can control the electrical connection between the first bit line BLa to the fourth bit line BLd and the first read-write unit circuit RWUa to the fourth read-write unit circuit RWUd.

[0095] In some example embodiments, Figure 8As shown in , a selective read operation SRO can be performed based on the multiplier arrangement bits respectively stored in the first to fourth read-write unit circuits RWUa to RWUd to selectively electrically connect the first to fourth bit lines BLa to BLd to the first to fourth read-write unit circuits RWUa to RWUd. Figure 8 In the example of , the first bit line BLa and the fourth bit line BLd corresponding to the multiplier arrangement bit having a value of "1" are electrically connected to the first read-write unit circuit RWUa and the fourth read-write unit circuit RWUd by the first switch circuit SWa and the fourth switch circuit SWd that are turned on in response to the multiplier arrangement bit having a value of "1". In contrast, the second bit line BLb and the third bit line BLc corresponding to the multiplier arrangement bit having a value of "0" are electrically disconnected from the second read-write unit circuit RWUb and the third read-write unit circuit RWUc by the second switch circuit SWb and the third switch circuit SWc that are turned off in response to the multiplier arrangement bit having a value of "0".

[0096] While the first to fourth bit lines BLa to BLd are thus selectively electrically connected to the first to fourth read and write unit circuits RWUa to RWUd, a sensing operation is performed on the first to fourth memory cells MCa to MCd.

[0097] The first read-write unit circuit RWUa electrically connected to the first memory cell MCa having a value of "1" maintains the value of "1", and the value of the fourth read-write unit circuit RWUd electrically connected to the fourth memory cell MCd having a value of "0" is updated from "1" to "0". Regardless of the multiplicand arrangement bits stored in the second memory cell MCb and the third memory cell MCc, the second read-write unit circuit RWUb and the third read-write unit circuit RWUc maintain the stored value "0".

[0098] As a result, after the selective read operation SRO is completed, the multiplier arrangement bits stored in the read-write unit circuits RWUa to RWUd are updated to multiplication bits, which correspond to the bit-by-bit multiplication of the multiplicand arrangement bits stored in the memory cells MCa to MCd and the multiplier arrangement bits stored in the read-write unit circuits RWUa to RWUd.

[0099] Fig. 9 and Fig.10 A diagram illustrating a weighted adder included in a memory device according to an embodiment of the inventive concept.

[0100] Reference Fig. 9 The weighted adder WAD can sequentially receive the above intermediate multiplication values ​​(AB)i (i is an integer equal to or greater than 0) to perform weighted multiplication of the weighted intermediate multiplication values ​​(AB)i×2 iThe sum is performed to determine the multiplication value VA×VB so that the weighted intermediate multiplication value (AB)i×2 i Each of the intermediate multiplication values ​​(AB)i and the bit weight 2 i The multiplication value of each in .

[0101] Reference Fig.10 , the weighted adder 540 may include an adder 541 and a buffer 542. The adder 541 may perform a weighted addition operation on the sequentially received intermediate multiplication values ​​(AB)i. Bit weight 2 i The multiplication of can be implemented as a shift operation in response to the shift signal SFT. The weighted adder 540 can be initialized in response to the reset signal RST, and can output the multiplication value VA×VB as a result of the weighted addition operation in response to the output enable signal OUTEN. Using such a weighted adder 540, determining the multiplication value based on the multiplication bit as described below can be efficiently performed.

[0102] For the sake of illustration and description, reference will be made to Figures 11 to 18 An example embodiment is described in which a multiplicand value includes four multiplicand bits A0 to A3 and a multiplier value includes eight multiplier bits B0 to B7, but the example embodiment is not limited to a specific number of bits. Figures 11 to 18 In the example, the multiplicand value corresponds to 1001 (binary) = 9 (decimal), and the multiplier value corresponds to 10010011 (binary) = 147 (decimal).

[0103] Fig.11 A diagram illustrating data rearrangement according to an embodiment of the inventive concept. Fig.12 Show according to Fig.11 FIG. 1 is a diagram of a multiplication bit of a selective read operation of rearranged data. Fig.13 Shown based on Fig.12 Schematic diagram of the weighted addition operation of the multiplication bits.

[0104] Fig.11 , Fig.12 and Fig.13 Corresponds to Figure 2 and Figure 3 The data is rearranged and multiplied bit by bit. Fig.11 As shown in FIG. 1 , thirty-two (4×8=32) multiplicand arrangement bits according to the first replication and arrangement scheme SCH1 are stored in 32 memory cells MC0 to MC31 corresponding to 32 bit lines BL0 to BL31. Thereafter, 32 multiplier arrangement bits according to the second replication and arrangement scheme SCH2 are stored in 32 read / write unit circuits RWU0 to RWU31 corresponding to the 32 bit lines BL0 to BL31.

[0105] Reference Fig.12, using the above-mentioned selective read operation SRO, the 32 multiplier arrangement bits stored in the 32 read / write unit circuits RWU0 to RWU31 are updated or replaced by the 32 multiplication bits A0×B0 to A3×B7. The 32 multiplication bits A0×B0 to A3×B7 are grouped into four bit groups GR0 to GR3 corresponding to the four multiplicand bits A0 to A3. The four intermediate multiplication values ​​(AB)0 to (AB)3 or A0×B to A3×B corresponding to the four bit groups GR0 to GR3 can be expressed by Expression 2 as described above.

[0106] Reference Fig.13 The weighted adder WAD sequentially receives four intermediate multiplication values ​​A0×B to A3×B to sequentially perform weighted addition operations at time points T0 to T3. Fig.13 As shown in FIG. 1 , the bit weight 2 is realized by shifting the value stored in the weighted adder WAD by one bit. i In other words, Fig.13 As shown in , before adding the next intermediate multiplication value to the stored value, 2 of the stored value is added. 0 Shift the bit left by one position.

[0107] In this way, at the time point T4 when the weighted addition of the four intermediate multiplication values ​​A0×B to A3×B is completed, the value in the weighted adder WAD is 9×147 (decimal) = 1323 (decimal) = 10100101011 (binary) corresponding to the multiplication value VA×VB of the multiplicand value VA and the multiplier value VB.

[0108] Fig.14 A diagram illustrating multiplication bits according to a selective read operation of rearranged data according to an embodiment of the inventive concept. Fig.15 Shown based on Fig.14 Schematic diagram of the weighted addition operation of the multiplication bits.

[0109] Fig.12 32 multiplication bits A0×B0 to A3×B7 are stored in the read / write unit circuits RWU0 to RWU31 in ascending order, and Fig.14 The case where the multiplication bits A0×B0 to A3×B7 are stored in descending order in the read / write unit circuits RWU0 to RWU31 is shown. The arrangement of the multiplication bits A0×B0 to A3×B7 corresponds to data rearrangement in which each of the multiplicand arrangement bits and the multiplier arrangement bits is arranged in descending order.

[0110] Reference Fig.15 , the weighted adder WAD sequentially receives four intermediate multiplication values ​​A0×B to A3×B to sequentially perform weighted addition operations at time points T0 to T3. Fig.13In the exemplary embodiment of , four intermediate multiplication values ​​A0×B to A3×B are sequentially received in ascending order starting from A0×B, and

[0111] Fig.15 In the exemplary embodiment of FIG. 1 , four intermediate multiplication values ​​A0×B to A3×B are sequentially received in descending order starting from A3×B. Fig.15 As shown in FIG. 1 , the bit weight 2 is realized by shifting the value stored in the weighted adder WAD by one bit. i In other words, Fig.15 As shown in , the stored value itself is shifted left by one bit before the next intermediate multiplication value is summed to the stored value. Fig.14 In the example, bit 2 0 Not displaced but fixed.

[0112] In this way, at the time point T4 when the weighted addition of the four intermediate multiplication values ​​A0×B to A3×B is completed, the value in the weighted adder WAD is 9×147 (decimal) = 1323 (decimal) = 10100101011 (binary) corresponding to the multiplication value VA×VB of the multiplicand value VA and the multiplier value VB.

[0113] Fig.16 A diagram illustrating data rearrangement according to an embodiment of the inventive concept. Fig.17 Show according to Fig.16 FIG. 1 is a diagram of a multiplication bit of a selective read operation of rearranged data. Fig.18 Shown based on Fig.17 Schematic diagram of an embodiment of a weighted addition operation of multiplication bits.

[0114] Fig.16 , Fig.17 and Fig.18 Corresponds to Figure 4 and Figure 5 The data is rearranged and multiplied bit by bit. Fig.16 As shown in FIG. 1 , thirty-two (4×8=32) multiplicand arrangement bits according to the second replication and arrangement scheme SCH2 are stored in 32 memory cells MC0 to MC31 corresponding to 32 bit lines BL0 to BL31. Thereafter, 32 multiplier arrangement bits according to the first replication and arrangement scheme SCH1 are stored in 32 read / write unit circuits RWU0 to RWU31 corresponding to the 32 bit lines BL0 to BL31.

[0115] Reference Fig.17, using the above-mentioned selective read operation SRO, the 32 multiplier arrangement bits stored in the 32 read / write unit circuits RWU0 to RWU31 are updated or replaced by the 32 multiplication bits A0×B0 to A3×B7. The 32 multiplication bits A0×B0 to A3×B7 can be grouped into eight bit groups GR0 to GR7 corresponding to the eight multiplier bits B0 to B7. The eight intermediate multiplication values ​​(AB)0 to (AB)7 or A×B0 to A×B7 corresponding to the eight bit groups GR0 to GR7 can be expressed by Expression 4 as described above.

[0116] Reference Fig.18 The weighted adder WAD sequentially receives eight intermediate multiplication values ​​A×B0 to A×B7 to sequentially perform weighted addition operations at time points T0 to T7. Fig.18 As shown in FIG. 1 , the bit weight 2 is realized by shifting the value stored in the weighted adder WAD by one bit. i In other words, Fig.18 As shown in , before adding the next intermediate multiplication value to the stored value, 2 of the stored value is added. 0 Shift the bit left by one position.

[0117] In this way, at the time point T7 when the weighted addition of the eight intermediate multiplication values ​​A×B0 to A×B7 is completed, the value in the weighted adder WAD is 9×147 (decimal) = 1323 (decimal) = 10100101011 (binary) corresponding to the multiplication value VA×VB of the multiplicand value VA and the multiplier value VB.

[0118] FIG. 19A to FIG. 19E A diagram illustrating a data rearrangement method according to an embodiment of the inventive concept.

[0119] Although referenced Fig.11 , Fig.12 , Fig.14 and Fig.16 The data rearrangement method of the PIM method according to the embodiment of the inventive concept is described, but the inventive concept is not limited to the above embodiment. For example, it can be based on the following FIG. 19A to FIG. 19E The data rearrangement method shown in FIG. 1 is used to perform the PIM method.

[0120] Fig.19A An embodiment is shown in which the multiplicand permutation bits ARRA are generated in descending order by a first copying and permutation scheme SCH1 and the multiplier permutation bits ARRB are generated in ascending order by a second copying and permutation scheme SCH2.

[0121] Fig.19BAn embodiment is shown in which the multiplicand permutation bits ARRA are generated in ascending order by a first copying and permutation scheme SCH1 and the multiplier permutation bits ARRB are generated in descending order by a second copying and permutation scheme SCH2.

[0122] Fig.19C An embodiment is shown in which the multiplicand permutation bits ARRA are generated in descending order by the second copying and permutation scheme SCH2 and the multiplier permutation bits ARRB are generated in ascending order by the first copying and permutation scheme SCH1.

[0123] Fig.19D An embodiment is shown in which the multiplicand permutation bits ARRA are generated in ascending order by the second copying and permutation scheme SCH2 and the multiplier permutation bits ARRB are generated in descending order by the first copying and permutation scheme SCH1.

[0124] Fig.19E An embodiment is shown in which the multiplicand permutation bits ARRA are generated in descending order by the second copying and permutation scheme SCH2 and the multiplier permutation bits ARRB are generated in descending order by the first copying and permutation scheme SCH1.

[0125] Fig. 20 A block diagram of a memory system according to an embodiment of the inventive concept is shown.

[0126] Reference Fig. 20 , the memory system 10 includes a memory controller 20 and at least one memory device 30 .

[0127] The memory device 30 may be a nonvolatile memory device, and the memory system 10 may include a data storage medium based on a flash memory such as a memory card, a universal serial bus (USB) memory, a solid state drive (SSD), etc.

[0128] The memory device 30 may perform a read operation, an erase operation, a program operation, and / or a write operation under the control of the memory controller 20. The memory device 30 receives a command CMD, an address ADDR, and data DATA from the memory controller 20 through an input / output line to perform such operations. In addition, the memory device 30 receives a control signal CTRL from the memory controller 20 through a control line. In addition, the memory device 30 receives power PWR from the memory controller 20 through a power line.

[0129] The memory device 30 includes a read / write circuit RWC40, a data copy and arrangement circuit DCAC50, and an operation circuit OPER60, which are configured together to perform the scalar multiplication method as described above and the matrix multiplication method as will be described below. For example, the OPER circuit 60 may include a scalar multiplication method as described above. Fig.10 The structure and function of the weighted adder are described to perform scalar multiplication.

[0130] Fig.21 A block diagram of a nonvolatile memory device according to example embodiments is shown.

[0131] Reference Fig.21 , the nonvolatile memory device 30 includes a memory cell array 100 , a page buffer circuit 410 , a data input / output (I / O) circuit 420 , an address decoder 430 , a control circuit 450 , and a voltage generator 460 .

[0132] The memory cell array 100 may be connected to the address decoder 430 through a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. In addition, the memory cell array 100 may be connected to the page buffer circuit 410 through a plurality of bit lines BL.

[0133] The memory cell array 100 may include a plurality of memory cells connected to a plurality of word lines WL and a plurality of bit lines BL. In some example embodiments, the memory cell array 100 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (or a vertical structure). In this case, the memory cell array 100 may include a plurality of NAND strings in a vertical direction such that at least one memory cell is located above another memory cell.

[0134] The control circuit 450 can be obtained from the memory controller 20 (see Fig. 20 ) receives a command (signal) CMD and an address (signal) ADDR. The control circuit 450 may control the erase operation, programming operation, and read operation of the memory device 30 based on the command signal CMD and the address signal ADDR. The erase operation may include performing a series of erase cycles, and the programming operation may include performing a series of programming cycles. Each programming cycle may include a programming operation and a programming verification operation. Each erase cycle may include an erase operation and an erase verification operation. The read operation may include a normal read operation and a data recovery read operation.

[0135] For example, the control circuit 450 may generate a control signal CTL for controlling the voltage generator 460 based on the command signal CMD, and may generate a page buffer control signal PBC for controlling the page buffer circuit 410. The control circuit 450 may also generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 450 may provide the row address R_ADDR to the address decoder 430, and provide the column address C_ADDR to the data input / output circuit 420.

[0136] The address decoder 430 may be connected to the memory cell array 100 through a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. During a program operation or a read operation, the address decoder 430 may determine one of the plurality of word lines WL as a selected word line based on a row address R_ADDR, and determine the remaining word lines of the plurality of word lines WL except the selected word line as unselected word lines.

[0137] Furthermore, during a programming operation or a reading operation, the address decoder 430 may determine one of the plurality of string selection lines SSL as a selected string selection line based on the row address R_ADDR, and determine the remaining string selection lines of the plurality of string selection lines SSL except the selected string selection line as unselected string selection lines.

[0138] The voltage generator 460 may generate a word line voltage VWL that may be required for operation of the memory cell array 100 of the memory device 30 based on the control signal CTL. The voltage generator 460 may receive power PWR from the memory controller 20. The word line voltage VWL may be applied to a plurality of word lines WL through the address decoder 430.

[0139] The page buffer circuit 410 may be connected to the memory cell array 100 through a plurality of bit lines BL. The page buffer circuit 410 may include a plurality of buffers. In some example embodiments, each buffer may be connected to one bit line. In other example embodiments, each buffer may be connected to two or more bit lines.

[0140] The page buffer circuit 410 may temporarily store data to be programmed in a selected page or data read out from a selected page of the memory cell array 100 .

[0141] The data input / output circuit 420 may be connected to the page buffer circuit 410 through the data line DL. During a program operation, the data input / output circuit 420 may receive program data DATA received from the memory controller 20 and provide the program data DATA to the page buffer circuit 410 based on the column address C_ADDR received from the control circuit 450. During a read operation, the data input / output circuit 420 may provide read data DATA read from the memory cell array 100 and stored in the page buffer circuit 410 to the memory controller 20 based on the column address C_ADDR received from the control circuit 450.

[0142] The memory device 30 may include a data copy and arrangement circuit DCAC 50 and an operation circuit OPER60 that perform a PIM method using a page buffer circuit 410 according to an example embodiment. The above-mentioned read and write circuit may correspond to the page buffer circuit 410, and a read and write unit circuit included in the read and write circuit may correspond to a page buffer included in the page buffer circuit 410. The data copy and arrangement circuit 50 and the operation circuit 60 may be included in the data input / output circuit 420, or may be implemented as an additional component different from the data input / output circuit 420.

[0143] The data duplication and arrangement circuit 50 can generate multiplicand arrangement bits by duplicating and arranging the multiplicand bits of the multiplicand values ​​included in the multiplicand matrix. In addition, the data duplication and arrangement circuit 50 can generate multiplier arrangement bits by duplicating and arranging the multiplier bits of the multiplier values ​​included in the multiplier matrix.

[0144] The page buffer included in the page buffer circuit 410 is connected to the bit line. The page buffer can store the multiplier arrangement bits, receive the multiplicand arrangement bits selectively read from the memory cell based on the multiplier arrangement bits stored in the read / write unit circuit, and store the multiplication bits corresponding to the bit-by-bit multiplication value of the multiplicand arrangement bits and the multiplier arrangement bits.

[0145] The operation circuit 60 may determine component values ​​of a multiplication matrix corresponding to the multiplication of the multiplicand matrix and the multiplier matrix based on the multiplication bits stored in the page buffer.

[0146] Fig.22A Shown included in Fig.21 A block diagram of a memory cell array in a memory device of FIG. Fig. 22B Show reference Fig.22A A circuit diagram depicting the equivalent circuit of the memory block.

[0147] Reference Fig.22A , the memory cell array 100 may include a plurality of memory blocks BLK1, BLK2, . . . , and BLKz (ie, BLK1 to BLKz), where z is an integer greater than 2. In some example embodiments, the memory blocks BLK1 to BLKz are connected by Fig.21 For example, the address decoder 430 may select a specific memory block BLK corresponding to the block address among the memory blocks BLK1 to BLKz.

[0148] Fig. 22B The memory block BLKi may be formed on the substrate in a three-dimensional structure (or a vertical structure). For example, a plurality of NAND strings or cells included in the memory block BLKi may be formed in a first direction D1 perpendicular to an upper surface of the substrate.

[0149] Reference Fig. 22B , the memory block BLKi may include NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 (i.e., NS11 to NS33) connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1, MC2, MC3, ..., and MC8 (i.e., MC1 to MC8), and a ground selection transistor GST. Fig. 22B , each of the NAND strings NS11 to NS33 is illustrated as including eight memory cells MC1 to MC8. However, example embodiments are not limited thereto. In some example embodiments, each of the NAND strings NS11 to NS33 may include any number of memory cells.

[0150] Each string selection transistor SST may be connected to a corresponding string selection line (one of SSL1, SSL2, and SSL3). A plurality of memory cells MC1 to MC8 may be connected to corresponding gate lines GTL1, GTL2, GTL3, ..., and GTL8 (i.e., GTL1 to GTL8), respectively. The gate lines GTL1 to GTL8 may be word lines, and some of the gate lines GTL1 to GTL8 may be dummy word lines. Each ground selection transistor GST may be connected to a corresponding ground selection line (one of GSL1, GSL2, and GSL3). Each string selection transistor SST may be connected to a corresponding bit line (e.g., one of BL1, BL2, and BL3), and each ground selection transistor GST may be connected to a common source line CSL.

[0151] Word lines (eg, WL1) having the same height may be connected in common, and ground selection lines GSL1 to GSL3 and string selection lines SSL1 to SSL3 may be separated. Although not shown, as will be described below, gate lines corresponding to intermediate switching lines may be separated. Fig. 22B , the memory block BLKi is shown as being connected to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, example embodiments are not limited thereto. Each memory block in the memory cell array 100 may be connected to any number of word lines and any number of bit lines.

[0152] Fig.23 A diagram describing an example of a deep learning neural network structure driven by an artificial neural network (ANN) system using a memory device according to one or more embodiments of the inventive concept is shown.

[0153] Reference Fig.23A general neural network may include an input layer IL, multiple hidden layers HL1, HL2, ..., HLn and an output layer OL.

[0154] The input layer IL may include i input nodes x1, x2, ..., xi, where i is a natural number greater than 0. Input data (e.g., vector input data) IDAT having a length of i may be input to the input nodes x1, x2, ..., xi, so that each element of the input data IDAT is input to a corresponding node among the input nodes x1, x2, ..., xi.

[0155] The plurality of hidden layers HL1, HL2, ..., HLn may include n hidden layers, where n is a natural number greater than 0, and the plurality of hidden layers HL1, HL2, ..., HLn may include a plurality of hidden nodes h 1 1.h 1 2.h 1 3. ..., h 1 m、h 2 1.h 2 2.h 2 3. ..., h 2 m, …, h n 1.h n 2.h n 3. ..., h n For example, the hidden layer HL1 may include m hidden nodes h 1 1.h 1 2.h 1 3. ..., h 1 m, the hidden layer HL2 may include m hidden nodes h 2 1.h 2 2.h 2 3. ..., h 2 m, the hidden layer HLn may include m hidden nodes h n 1.h n 2.h n 3. ..., h n m, where m is a natural number greater than 0.

[0156] The output layer OL may include j output nodes y1, y2, ..., yj, where j is a natural number greater than 0. Each of the output nodes y1, y2, ..., yj may correspond to a corresponding class in the class to be classified. The output layer OL may output an output value ODAT (e.g., a class score or a simple score) associated with the input data IDAT for each class. The output layer OL may be called a fully connected layer and may indicate, for example, the probability that the input data IDAT corresponds to a car.

[0157] Fig.23The structure of the neural network shown in FIG. 1 may be represented by information about branches (or connections) between nodes shown as lines and weight values ​​assigned to each branch. Nodes within one layer may not be connected to each other, but nodes in different layers may be fully or partially connected to each other.

[0158] Each node (for example, node h 1 1) may receive the output of a previous node (e.g., node x1), may perform a computation operation or calculation on the received output, and may output the result of the computation operation or calculation as the next node (e.g., node h 2 1). Each node can calculate a value to be output by applying the input to a specific function (e.g., a nonlinear function).

[0159] Generally, the structure of a neural network can be set in advance, and the weight values ​​of the connections between nodes are appropriately set using data with known answers to which class the data belongs. The data with known answers is called "training data", and the process of determining the weight values ​​is called "training". The neural network "learns" during the training process. The set of independently trainable structures and weight values ​​is called a "model", and the process of predicting which class the input data belongs to by the model with determined weight values ​​and then outputting the predicted value is called a "testing" process.

[0160] Because each node (for example, node h 1 1) Connected to all nodes of the previous layer (e.g., nodes x1, x2, ..., xi included in layer IL), then as the size of the input image data increases, the number of weighted values ​​increases dramatically, so Fig.23 The general neural network shown in may not be suitable for processing input image data (or input sound data). Therefore, a convolutional neural network (CNN) implemented by combining filtering technology with a general neural network has been studied so that a two-dimensional image (e.g., input image data) can be efficiently trained by a convolutional neural network.

[0161] Thus, a deep learning neural network structure may include multiple layers, and matrix multiplication and / or matrix-vector multiplication may be required for each layer.

[0162] Fig.24 Diagram showing an example of matrix multiplication.

[0163] like Fig.24As shown in , each of the p×r×q (i, k, j) multiplication values ​​Wik×Xkj can be determined by multiplying the (i, k) multiplicand value Wik included in the multiplicand matrix MW with p rows and r columns with the (k, j) multiplier value Xkj included in the multiplier matrix with r rows and q columns for all i, k and j, where i is a natural number from 1 to p, k is a natural number from 1 to r, j is a natural number from 1 to q, and p, q and r are natural numbers greater than 1.

[0164] Each of the p×q (i, j) component values ​​Yij included in the multiplication matrix MY of p rows and q columns corresponding to the multiplication of the multiplicand matrix MW and the multiplier matrix MX can be determined by summing the r (i, k, j) multiplication values ​​Wik×Xkj for all k pairs.

[0165] The determination of the p×r×q (i, k, j) multiplication values ​​Wik×Xkj corresponds to scalar multiplication and can therefore be performed by referring to Figures 1 to 18 The method described is used to perform the determination of each multiplication value.

[0166] Fig.25 A flowchart illustrating a matrix multiplication method using a memory device according to an embodiment of the inventive concept is shown. Fig.26 and Fig. 27 A diagram illustrating a command set of a matrix multiplication method using a memory device according to an embodiment of the inventive concept.

[0167] The memory device may be used to perform Fig.24 The memory device uses a read-write unit circuit connected to a bit line to perform a read operation and a write operation on a memory cell connected to the bit line.

[0168] Reference Fig.24 and Fig.25 , the multiplicand values ​​W11 to Wpr of the multiplier matrix MW are stored in the memory cells of the memory device (S10). The memory cells may correspond to, for example, Fig.21 30. Thereafter, the multiplier values ​​X11 to Xrq of the multiplier matrix MX are stored in the read / write unit circuit of the memory device (S20). The read / write unit circuit may correspond to, for example, a circuit including a memory cell array 100 of the memory device 30 as shown in FIG. Fig.21 As previously described, the multiplicand arrangement bits can be stored in the memory unit by duplicating and arranging the multiplicand bits of each multiplicand value, and the multiplier arrangement bits can be stored in the read / write unit circuit by duplicating and arranging the multiplier bits of each multiplier value.

[0169] The multiplicand values ​​W11 to Wpr included in the multiplicand matrix MW may correspond to those given by reference to Fig.23 The weight values ​​of the multiplication and accumulation (MAC) operation performed by the artificial neural network (ANN), the multiplier values ​​X11 to Xrq included in the multiplier matrix MX may correspond to the input values ​​of the MAC operation.

[0170] Fig.26 and Fig. 27 Shown from a memory controller (e.g., Fig. 20 ) to a memory device (e.g., Fig. 20 The memory device 30 shown in FIG. 1 is used to transmit a command set for transmitting multiplicand data DW and multiplier data DX for matrix multiplication. R / B indicates a ready / busy signal provided from the memory device to the memory controller, and DQ indicates an input-output signal transmitted through an input-output pad between the memory controller and the memory device. The command set can be implemented as a combination of commands CMD1 to CMD4, an address ADD, and transmitted data DW and DX. tDCA indicates the time required for the above-mentioned data rearrangement, tPROG indicates the time for storing data in the memory cell, tR indicates the data read time, tOPER indicates the weighted addition operation of the weighted adder, and as will be referred to below Fig.28 and Fig.29 Describes the time required to accumulate data in the accumulator.

[0171] According to an example embodiment, Fig.26 The command set stores the multiplicand data in the memory cell corresponding to the write address. Fig. 27 The command set stores the multiplier data in a page buffer corresponding to the target address. Then, bit-by-bit multiplication of the multiplicand value and the multiplier value is performed (S30). The bit-by-bit multiplication can be performed by the above-mentioned selective read operation SRO, and the resulting multiplication bits can be stored in a read / write unit circuit (such as a page buffer).

[0172] Then, a multiplication value of the multiplicand value and the multiplier value is determined by performing a weighted addition operation (S40). The determination of the multiplication value can be performed using the above-mentioned weighted adder by reading out the multiplication bits in units of groups.

[0173] The component values ​​of the multiplication matrix are provided by summing the multiplication values ​​(S50). Fig.28 and Fig.29 The accumulator is used to sum or accumulate the multiplied values ​​as described in .

[0174] Fig.28 and Fig.29 A diagram illustrating an embodiment of an operation circuit 60 included in a memory device according to an embodiment of the inventive concept.

[0175] exist Fig.28 and Fig.29 In the embodiment, r subpage buffer circuits PBC1, PBC2, ..., and PBCr (ie, PBC1 to PBCr) are repeatedly arranged. The r subpage buffer circuits PBC1 to PBCr correspond to the subpage buffer circuits PBC1 to PBCr. Fig.24 The result of the matrix multiplication is the component value Yij of the multiplication matrix MY. For ease of explanation, Fig.28 and 29 A configuration corresponding to two component values ​​Y11 and Y21 is shown.

[0176] Reference Fig.28 The operation circuit 61 includes a plurality of weighted adders WAD11 and WAD21 and a plurality of accumulators ACC11 and ACC21.

[0177] A weighted adder included in the memory device is used to sequentially determine r (i, k, j) multiplication values ​​Wi1×X1j to Wir×Xrj for each i and each j. In other words, r multiplication values ​​W11×X11 to W1r×Xr1 are sequentially determined using the weighted adder WAD11, and r multiplication values ​​W21×X11 to W2r×Xr1 are sequentially determined using the weighted adder WAD21.

[0178] p×q accumulators included in the memory device are used to determine p×q (i, j) component values ​​Y11 to Ypq in parallel. Fig.28 As shown in , two accumulators ACC11 and ACC21 are used to determine two component values ​​Y11 and Y21 in parallel.

[0179] Reference Fig.29 The operation circuit 62 includes a plurality of weighted adders WAD111, WAD121, ..., and WAD1r1 (ie, WAD111 to WAD1r1) and WAD211, WAD221, ..., and WAD2r1 (ie, WAD211 to WAD2r1) and a plurality of accumulators ACC11 and ACC21.

[0180] r (i, k, j) multiplication values ​​Wi1×X1j to Wir×Xrj for each i and each j are determined in parallel using r weighted adders included in the memory device. In other words, r multiplication values ​​W11×X11 to W1r×Xr1 are determined in parallel using r weighted adders WAD111 to WAD1r1, and r multiplication values ​​W21×X11 to W2r×Xr1 are determined in parallel using r weighted adders WAD211 to WAD2r1.

[0181] p×q accumulators included in the memory device are used to determine p×q (i, j) component values ​​Y11 to Ypq in parallel. Fig.29 As shown in , two accumulators ACC11 and ACC21 are used to determine two component values ​​Y11 and Y21 in parallel.

[0182] Fig.30 Diagram illustrating an arrangement of a page buffer included in a memory device according to an embodiment of the inventive concept.

[0183] Reference Fig.30 , a plurality of read / write unit circuits (e.g., a plurality of page buffers) may be arranged in a matrix form of rows and columns. As shown, 64 page buffers PBij are included, where each of i and j is an integer from 0 to 7. For an example case where the multiplicand value W includes 8 multiplicand bits W0 to W7 and the multiplier value X also includes 8 bits, the 64 page buffers PBij correspond to one multiplication value W×X, respectively.

[0184] like Fig.30 As shown in , the page buffers arranged in the same column are commonly connected to the same input terminal of the weighted adder WAD included in the operation circuit. In other words, the page buffers PB00 to PB70 arranged in the first column are connected to the first input terminal N0 of the weighted adder WAD, the page buffers PB01 to PB71 arranged in the second column are connected to the second input terminal N1 of the weighted adder WAD, and so on, so that in this way, the page buffers PB07 to PB77 arranged in the eighth column are connected to the eighth input terminal N7 of the weighted adder WAD.

[0185] The page buffers in the same row are simultaneously enabled by the common selection signal to simultaneously provide the stored values ​​to the input terminals of the weighted adder WAD. In other words, the eight page buffers PB00 to PB07 arranged in the first row are simultaneously enabled in response to the first selection signal SEL0, the eight page buffers PB10 to PB17 arranged in the second row are simultaneously enabled in response to the second selection signal SEL1, and so on, so that in this way, the eight page buffers PB70 to PB77 arranged in the eighth row are simultaneously enabled in response to the eighth selection signal SEL7.

[0186] So, using Fig.30 The above weighted addition operation can be efficiently performed for a line or structure.

[0187] Fig.31 A block diagram illustrating a mobile system including a memory device according to an embodiment of the inventive concept.

[0188] Reference Fig.31 , the mobile system 3000 includes an application processor (AP) 3100, a connection unit 3200, a volatile memory device (VM) 3300, a nonvolatile memory device (NVM) 3400, a user interface 3500, and a power supply 3600 connected via a bus.

[0189] The application processor 3100 may run applications such as a web browser, a game application, a video player, etc. The connection unit 3200 may perform wired communication or wireless communication with an external device. The volatile memory device 3300 may store data processed by the application processor 3100, or may operate as a working memory. For example, the volatile memory device 3300 may include a DRAM (such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power DDR (LPDDR) SDRAM, a graphic DDR (GDDR) SDRAM, a Rambus DRAM, etc.) The nonvolatile memory device 3400 may store a boot image and other data for booting the mobile system 3000. The user interface 3500 may include at least one input device (such as a keyboard, a touch screen, etc.) and at least one output device (such as a speaker, a display device, etc.). The power supply 3600 may supply a power supply voltage to the mobile system 3000. In an embodiment of the inventive concept, the mobile system 3000 may further include a camera image processor (CIS) and / or a storage device (such as a memory card, a solid state drive (SSD), a hard disk drive (HDD), a compact disk read-only memory (CD-ROM), etc.).

[0190] The non-volatile memory device 3400 and / or the volatile memory device 3300 may include a memory device for performing the operations described in reference to Figures 1 to 30 The configuration of the scalar multiplication or matrix multiplication.

[0191] As described above, a memory device and a process-in-memory (PIM) method according to an embodiment of the inventive concept can reduce processing time and power consumption by efficiently performing parallel bit-by-bit multiplication through efficient rearrangement of data using a read and write circuit included in the memory device.

[0192] The inventive concept can be applied to a memory device and a system including the memory device. For example, embodiments of the inventive concept can be applied to systems such as a memory card, a solid-state drive (SSD), an embedded multimedia card (eMMC), a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, a personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, etc.

[0193] The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications to the example embodiments are possible without substantially departing from the inventive concept.

Claims

1. A method for processing in memory using a memory device, the method comprising: storing m×n permuted multiplicand bits in m×n memory cells of a memory device by replicating and permuting m multiplicand bits of a multiplicand value, wherein m and n are natural numbers greater than zero; By duplicating and arranging n multiplier bits of the multiplier value, the m×n multiplier arrangement bits are stored in m×n read / write unit circuits corresponding to the m×n memory cells of the memory device; Based on the m×n multiplier arrangement bits stored in the m×n read / write unit circuits, the m×n multiplicand arrangement bits stored in the m×n memory cells are selectively read, and m×n multiplication bits are stored in the m×n read / write unit circuits based on the selectively read m×n multiplicand arrangement bits, the m×n multiplication bits corresponding to the bit-by-bit multiplication value of the m×n multiplicand arrangement bits and the m×n multiplier arrangement bits; and The multiplication value of the multiplicand value and the multiplier value is determined based on the m×n multiplication bits stored in the m×n read / write unit circuits, The step of selectively reading the m×n multiplicand arrangement bits and storing the m×n multiplication bits in the m×n read / write unit circuits comprises: reading from the m×n memory units a multiplicand arrangement bit among the m×n multiplicand arrangement bits corresponding to a multiplier arrangement bit having a value of “1” among the m×n multiplier arrangement bits, and replacing the multiplier arrangement bit having a value of “1” stored in the m×n read / write unit circuits with the read multiplicand arrangement bit, and Regardless of the value of the multiplicand arrangement bit corresponding to the multiplier arrangement bit with the value "0" among the m×n multiplicand arrangement bits, the multiplier arrangement bit with the value "0" among the m×n multiplier arrangement bits stored in the m×n read-write unit circuits is maintained.

2. The in-memory processing method according to claim 1, wherein: The steps of storing m×n multiplication bits in m×n read / write unit circuits include: selectively precharging m×n bit lines connected to the m×n read / write unit circuits based on the m×n multiplier permutation bits stored in the m×n read / write unit circuits; and After selectively precharging the m×n bit lines, a sensing operation is performed on the m×n memory cells. Therein, m×n bit lines are connected to m×n memory cells.

3. The in-memory processing method according to claim 2, wherein: The step of selectively precharging m×n bit lines comprises: precharging a bit line among the m×n bit lines corresponding to a multiplier arrangement bit having a value of “1” among the m×n multiplier arrangement bits from an initialization voltage corresponding to a value of “0” to a precharge voltage corresponding to a value of “1”; and A bit line among the m×n bit lines corresponding to a multiplier arrangement bit having a value of “0” among the m×n multiplier arrangement bits is maintained at an initialization voltage.

4. The in-memory processing method according to claim 1, wherein: The steps of storing m×n multiplication bits include: selectively electrically connecting m×n bit lines to the m×n read / write unit circuits based on the m×n multiplier arrangement bits stored in the m×n read / write unit circuits; and When m×n bit lines are selectively electrically connected to m×n read / write unit circuits, a sensing operation is performed on the m×n memory cells.

5. The in-memory processing method according to claim 4, wherein: The step of selectively electrically connecting m×n bit lines to m×n read / write unit circuits comprises: electrically connecting a bit line among the m×n bit lines corresponding to a multiplier arrangement bit having a value of “1” among the m×n multiplier arrangement bits to a corresponding read / write unit circuit among the m×n read / write unit circuits; and Bit lines among the m×n bit lines corresponding to multiplier arrangement bits having a value of “0” among the m×n multiplier arrangement bits are electrically disconnected from corresponding read / write unit circuits among the m×n read / write unit circuits.

6. The in-memory processing method according to claim 1, wherein: generating m×n multiplicand permutation bits by a first duplication and permutation scheme such that each of the m multiplicand bits is repeatedly duplicated and permuted n times to be adjacent to each other, and Among them, m×n multiplier permutation bits are generated through the second replication and permutation scheme, so that n multiplier bits are repeatedly replicated and permuted m times.

7. The in-memory processing method according to claim 6, wherein: The steps of determining the multiplication value of the multiplicand value and the multiplier value include: Grouping the m×n multiplication bits stored in the m×n read / write unit circuits into m bit groups corresponding to the m multiplicand bits; sequentially reading m intermediate multiplication values ​​corresponding to the m bit groups; and The multiplication value is determined by summing m weighted intermediate multiplication values, wherein each of the m weighted intermediate multiplication values ​​is a multiplication value of each of the m intermediate multiplication values ​​and each of the m bit weights corresponding to the m multiplicand bits.

8. The in-memory processing method according to claim 1, wherein: generating m×n multiplier permutation bits by a first duplication and permutation scheme such that each of the n multiplier bits is repeatedly duplicated and permuted m times to be adjacent to each other, and Therein, m×n multiplicand arrangement bits are generated by a second replication and arrangement scheme, so that the m multiplicand bits are repeatedly replicated and arranged n times.

9. The in-memory processing method according to claim 8, wherein: The steps of determining the multiplication value of the multiplicand value and the multiplier value include: Grouping the m×n multiplication bits stored in the m×n read / write unit circuits into n bit groups corresponding to the n multiplier bits; sequentially reading n intermediate multiplication values ​​corresponding to the n bit groups; and The multiplication value is determined by summing n weighted intermediate multiplication values, wherein each of the n weighted intermediate multiplication values ​​is a multiplication value of each of the n intermediate multiplication values ​​and each of the n bit weights corresponding to the n multiplier bits.

10. A method for processing in memory using a memory device, the method comprising: determining each of p×r×q (i, k, j) multiplication values ​​by multiplying the (i, k) multiplicand values ​​included in the p-row and r-column multiplicand matrix with the (k, j) multiplier values ​​included in the r-row and q-column multiplier matrix for all i, k, and j, wherein i is a natural number from 1 to p, k is a natural number from 1 to r, j is a natural number from 1 to q, and p, q, and r are natural numbers greater than 1; and Each of the p×q (i, j) component values ​​included in the p-row and q-column multiplication matrix corresponding to the multiplication of the multiplicand matrix and the multiplier matrix is ​​determined by summing the r (i, k, j) multiplication values ​​for all k, The step of determining the (i, k, j) multiplication value among the p×r×q (i, k, j) multiplication values ​​comprises: storing m×n permuted multiplicand bits in m×n memory cells of a memory device by copying and permuting m multiplicand bits of a (i, k) multiplicand value, wherein m and n are natural numbers greater than 0; By duplicating and arranging n multiplier bits of the (k, j) multiplier value, the m×n multiplier arrangement bits are stored in m×n read / write unit circuits corresponding to the m×n memory cells of the memory device; Based on the m×n multiplier arrangement bits stored in the m×n read / write unit circuits, the m×n multiplicand arrangement bits stored in the m×n memory cells are selectively read, and m×n multiplication bits are stored in the m×n read / write unit circuits based on the selectively read m×n multiplicand arrangement bits, the m×n multiplication bits corresponding to the bit-by-bit multiplication value of the m×n multiplicand arrangement bits and the m×n multiplier arrangement bits; and Based on the m×n multiplication bits stored in the m×n read / write unit circuits, (i, k) multiplication value of the multiplicand value and the (k, j) multiplier value, The step of selectively reading the m×n multiplicand arrangement bits and storing the m×n multiplication bits in the m×n read / write unit circuits comprises: reading from the m×n memory units a multiplicand arrangement bit among the m×n multiplicand arrangement bits corresponding to a multiplier arrangement bit having a value of “1” among the m×n multiplier arrangement bits, and replacing the multiplier arrangement bit having a value of “1” stored in the m×n read / write unit circuits with the read multiplicand arrangement bit, and Regardless of the value of the multiplicand arrangement bit corresponding to the multiplier arrangement bit with the value "0" among the m×n multiplicand arrangement bits, the multiplier arrangement bit with the value "0" among the m×n multiplier arrangement bits stored in the m×n read-write unit circuits is maintained.

11. The in-memory processing method according to claim 10, wherein: r (i, k, j) multiplication values ​​with respect to each i and each j are sequentially determined using a weighted adder included in the memory device.

12. The in-memory processing method according to claim 10, wherein: r (i, k, j) multiplication values ​​with respect to each i and each j are determined in parallel using r weighted adders included in the memory device.

13. The in-memory processing method according to claim 10, wherein: The p×q (i, j) component values ​​are determined in parallel using p×q accumulators included in the memory device.

14. A memory device comprising: a data copy and permutation circuit configured to generate multiplicand permutation bits by copying and permuting multiplicand bits of multiplicand values ​​included in a multiplicand matrix, and to generate multiplier permutation bits by copying and permuting multiplier bits of multiplier values ​​included in a multiplier matrix; a memory cell array including memory cells connected to the bit lines and configured to store the multiplicand permutation bits; The read and write unit circuits are connected to the bit lines and are configured as: The storage multiplier is arranged into bits, receiving multiplicand permutation bits selectively read from a memory cell based on multiplier permutation bits stored in a read / write unit circuit, and storing multiplication bits based on the multiplicand permutation bits selectively read from the memory cell, the multiplication bits corresponding to a bit-by-bit multiplication value of the multiplicand permutation bits and the multiplier permutation bits; an operation circuit configured to determine component values ​​of a multiplication matrix corresponding to a multiplication of a multiplicand matrix and a multiplier matrix based on the multiplication bits stored in the read / write unit circuit; as well as A control circuit is configured to selectively read the multiplicand arrangement bits by: Reading from the memory unit a multiplicand arrangement bit among the multiplicand arrangement bits corresponding to a multiplier arrangement bit having a value of "1" among the multiplier arrangement bits, and replacing the multiplier arrangement bit having a value of "1" stored in the read-write unit circuit with the read multiplicand arrangement bit, and Regardless of the value of the multiplicand arrangement bit corresponding to the multiplier arrangement bit having the value of "0" among the multiplicand arrangement bits, the multiplier arrangement bit having the value of "0" among the multiplier arrangement bits stored in the read / write unit circuit is maintained.

15. The memory device of claim 14, wherein: The control circuit is also configured to selectively read the multiplicand permutation bits by selectively precharging bit lines connected to the read / write unit circuits based on the multiplier permutation bits stored in the read / write unit circuits.

16. The memory device of claim 14, wherein: The multiplicand values ​​included in the multiplicand matrix are weight values ​​of the multiplication and accumulation operation performed by the artificial neural network, and the multiplier values ​​included in the multiplier matrix are input values ​​of the multiplication and accumulation operation.

17. The memory device of claim 14, wherein: The read / write unit circuits are arranged in a matrix form of rows and columns, and the read / write unit circuits arranged in the same column among the read / write unit circuits are commonly connected to the same input terminal of the weighted adder included in the operation circuit.

18. The memory device of claim 14, wherein: The memory device is a NAND flash memory device, and the read / write unit circuit is a page buffer configured to perform a read operation and a write operation of the NAND flash memory device.

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