Ferroelectric memory and operation method thereof

Abstract

The present invention relates to a ferroelectric memory, comprising: a plurality of ferroelectric memory cells, which include a ferroelectric capacitor, the ferroelectric capacitor includes an upper plate and a lower plate and a ferroelectric material located between the upper plate and the lower plate; a write circuit, which is configured to apply a first voltage and a second voltage to the two plates of the ferroelectric capacitor of the ferroelectric memory cell in a forward direction and a reverse direction respectively, so that the ferroelectric material has corresponding first, second, third and fourth residual polarization intensity values ​​respectively, so as to write different storage data; and a read circuit, which includes a reference voltage generating circuit and a voltage comparison circuit, the voltage comparison circuit can compare the voltage at one end of the ferroelectric capacitor of the ferroelectric memory cell collected with the reference voltage generated by the reference voltage generating circuit to output different comparison results to read different storage data. Through the present invention, the storage of 2 bits of data per storage cell can be realized, thereby greatly improving the storage density and the storage capacity.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductors, and more particularly to a ferroelectric memory. In addition, the present invention also relates to a method for operating such a ferroelectric memory. Background Art

[0002] In recent years, ferroelectric memory, as a new type of memory with high writing speed and high read and write times, has been increasingly popular. Ferroelectric memory is a non-volatile memory with a special process. When an electric field is applied to the ferroelectric transistor, the central atom stops at the first low energy state along the electric field, and when the electric field is reversed and applied to the same ferroelectric transistor, the central atom moves in the crystal along the direction of the electric field and stops at the second low energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, and the ferroelectric domains form polarized charges under the action of the electric field. The polarized charge formed by the reversal of the ferroelectric domain under the electric field is higher, and the polarized charge formed by the non-reversal of the ferroelectric domain under the electric field is lower. This binary stable state of ferroelectric materials allows ferroelectrics to be used as memory.

[0003] When the electric field is removed, the central atom remains in a low energy state and the state of the memory is preserved and will not disappear. Therefore, the ferroelectric domain can be used to reverse under the electric field to form a high polarization charge, or to form a low polarization charge without reversal to determine whether the storage unit is in the "1" or "0" state. The reversal of the ferroelectric domain does not require a high electric field, and only a normal operating voltage can change the state of the storage unit to "1" or "0". There is no need for a charge pump to generate a high voltage for data erasure, so there is no erase delay. This feature enables the ferroelectric memory to continue to save data after power failure, with a fast write speed and unlimited write life, and it is not easy to be damaged. In addition, compared with existing non-volatile memory technology, ferroelectric memory has a higher write speed and a longer read and write life.

[0004] In current ferroelectric memories, each memory cell stores 1 bit of data, that is, 0 or 1. If more bits per memory cell can be achieved, the storage density or storage capacity of the ferroelectric memory can be greatly improved. Summary of the invention

[0005] The object of the present invention is to provide a ferroelectric memory and an operating method thereof, through which 2-bit data can be stored in each ferroelectric memory cell, thereby greatly improving the storage density and the storage capacity.

[0006] In a first aspect of the invention, the object is achieved by a ferroelectric memory comprising:

[0007] A plurality of ferroelectric memory cells, each ferroelectric memory cell comprising a ferroelectric capacitor, wherein the ferroelectric capacitor comprises an upper plate, a lower plate and a ferroelectric material located between the upper plate and the lower plate;

[0008] A write circuit configured to apply a first voltage and a second voltage to two plates of a ferroelectric capacitor of a ferroelectric memory cell in a forward direction and a reverse direction, respectively, so that the ferroelectric material has corresponding first, second, third and fourth remanent polarization intensity values, respectively, to write different storage data, wherein different remanent polarization intensity values ​​correspond to different storage data; and

[0009] The reading circuit includes a reference voltage generating circuit and a voltage comparison circuit. The voltage comparison circuit can compare the collected voltage at one end of the ferroelectric capacitor of the ferroelectric storage unit with the reference voltage generated by the reference voltage generating circuit to output different comparison results to read different storage data.

[0010] In a preferred embodiment of the present invention, it is stipulated that the values ​​of the third remanent polarization intensity and the fourth remanent polarization intensity corresponding to the second voltage applied by the write circuit to the ferroelectric capacitor are 1 / 3 of the values ​​of the first remanent polarization intensity and the second remanent polarization intensity corresponding to the first voltage applied by the write circuit to the ferroelectric capacitor.

[0011] In a preferred embodiment of the present invention, it is provided that the write circuit comprises first, second, third and fourth AND gates, wherein the two input terminals of the first AND gate respectively input the inverted values ​​of the most significant bit and the least significant bit of the signal to be written, and the output terminal thereof is connected to one of the input terminals of the first NAND gate, the input terminals of the second AND gate respectively input the most significant bit and the least significant bit of the signal to be written, and the output terminal thereof is connected to one of the input terminals of the second NAND gate, the input terminals of the third AND gate respectively input the inverted value of the most significant bit and the least significant bit of the signal to be written, and the output terminal thereof is connected to one of the input terminals of the third NAND gate, and the input terminals of the fourth AND gate respectively input the inverted value of the most significant bit and the inverted value of the least significant bit of the signal to be written, and the output terminal thereof is connected to one of the input terminals of the fourth NAND gate;

[0012] first, second, third and fourth NAND gates, wherein the other of the input terminals of the first, second, third and fourth NAND gates respectively inputs a write enable signal; and

[0013] A first, second, third and fourth transistor, wherein the gate of the first transistor is connected to the output terminal of the first NAND gate, one of its drain and source is connected to the first voltage, and the other of its drain and source is connected to the bit line of the ferroelectric memory cell to be written, the gate of the second transistor is connected to the output terminal of the second NAND gate, one of its drain and source is connected to the second voltage, and the other of its drain and source is connected to the bit line of the ferroelectric memory cell to be written, the gate of the third transistor is connected to the output terminal of the third NAND gate, one of its drain and source is connected to the third voltage, and the other of its drain and source is connected to the bit line of the ferroelectric memory cell to be written, and the gate of the fourth transistor is connected to the output terminal of the fourth NAND gate, one of its drain and source is connected to the fourth voltage, and the other of its drain and source is connected to the bit line of the ferroelectric memory cell to be written.

[0014] In a preferred embodiment of the present invention, it is provided that the reading circuit comprises:

[0015] four reference cells configured to generate first, second, third and fourth bit line voltages corresponding to 00, 01, 10 and 11 respectively on their bit lines when one of 00, 01, 10 and 11 is written, wherein the first, second, third and fourth bit line voltages increase in sequence;

[0016] A first reference voltage generating circuit generates a first reference voltage according to the first and second bit line voltages, wherein the magnitude of the first reference voltage is between the magnitudes of the first and second bit line voltages;

[0017] A second reference voltage generating circuit generates a second reference voltage according to the second and third bit line voltages, wherein the second reference voltage is between the second and third bit line voltages; and

[0018] The third reference voltage generating circuit generates a third reference voltage according to the third and fourth bit line voltages, wherein a magnitude of the third reference voltage is between magnitudes of the third and fourth bit line voltages.

[0019] In a preferred embodiment of the present invention, it is stipulated that the first reference voltage is the average value of the sum of the first bit line voltage and the second bit line voltage, the second reference voltage is the average value of the sum of the second bit line voltage and the third bit line voltage, and the third reference voltage is the average value of the sum of the third bit line voltage and the fourth bit line voltage.

[0020] In a preferred embodiment of the present invention, it is stipulated that the voltage comparison circuit includes three voltage comparators, wherein one input terminal of the first voltage comparator is connected to the first reference voltage, and the other input terminal is connected to the bit line of the ferroelectric memory cell; one input terminal of the second voltage comparator is connected to the second reference voltage, and the other input terminal is connected to the bit line of the ferroelectric memory cell; one input terminal of the third voltage comparator is connected to the third reference voltage, and the other input terminal is connected to the bit line of the ferroelectric memory cell.

[0021] In a preferred embodiment of the present invention, the voltage comparison circuit includes a voltage selection circuit and a voltage comparator, wherein three input terminals of the voltage selection circuit respectively input one of three reference voltages output by the reference voltage generation circuit, and an output terminal of the voltage selection circuit is connected to an input terminal of the voltage comparator.

[0022] Another of the input terminals of the voltage comparator is connected to the bit line of the ferroelectric memory cell, and its output terminal outputs the comparison result;

[0023] The voltage comparison circuit also includes a voltage comparator clock signal control circuit, which includes a delay circuit and a NOT gate, wherein the input end of the delay circuit is connected to the output end of the voltage comparator, and the output end of the NOT gate is connected to the clock signal input end of the voltage comparator.

[0024] In a preferred embodiment of the present invention, it is stipulated that the output end of the voltage comparator includes a first output end and a second output end, and the first output end and the second output end are compared with a ready signal through a NAND gate output; the reading circuit also includes a control signal generating circuit, and the control signal generating circuit includes a shift register composed of two interconnected D flip-flops, wherein the output end of the first D flip-flop is connected to the control signal input end of the voltage selection circuit, and the output end of the second D flip-flop is connected to the input end of the clock signal control circuit of the voltage comparator.

[0025] In a preferred embodiment of the present invention, it is provided that the reading circuit also includes a read signal latch circuit, which includes a third D flip-flop for latching the most significant bit of the read signal, and a fourth D flip-flop for latching the least significant bit of the read signal; wherein the output end of the voltage comparator is connected to the input end of the third D flip-flop and the fourth D flip-flop, the reverse signal for starting reading is connected to the reset end of the third D flip-flop and the fourth D flip-flop, the output end of the first D flip-flop is connected to the clock signal end of the third D flip-flop, and the output end of the second D flip-flop is connected to the clock signal end of the fourth D flip-flop.

[0026] In a second aspect of the present invention, the aforementioned task is accomplished by a method for performing a write operation on a ferroelectric memory according to the present invention, the method comprising:

[0027] The write circuit is used to apply a first voltage and a second voltage to the two plates of the ferroelectric capacitor of the ferroelectric storage unit in the forward and reverse directions respectively, so that the ferroelectric material has corresponding first, second, third and fourth residual polarization intensity values ​​respectively, so as to write different storage data corresponding to different residual polarization intensity values ​​respectively.

[0028] In a preferred embodiment of the present invention, it is provided that the method further comprises:

[0029] The read circuit is used to generate three reference voltages.

[0030] The bit line voltage of the ferroelectric memory cell collected by the reading circuit is compared with three reference voltages respectively, and the data stored in the ferroelectric memory cell is read out according to the comparison result.

[0031] In a preferred embodiment of the present invention, it is provided that the method further comprises:

[0032] The read circuit is used to generate three reference voltages, wherein the third reference voltage is greater than the second reference voltage, and the second reference voltage is greater than the first reference voltage;

[0033] Comparing the bit line voltage of the ferroelectric memory cell to be read with the second reference voltage to obtain a first comparison result, and using the first comparison result as the most significant bit of the read result; and

[0034] If the first comparison result is that the bit line voltage of the ferroelectric memory cell is greater than the second reference voltage, the bit line voltage is compared with the third reference voltage to obtain a second comparison result, and the second comparison result is used as the least significant bit of the read result; and if the first comparison result is that the bit line voltage of the ferroelectric memory cell is less than the second reference voltage, the bit line voltage is compared with the first reference voltage to obtain a third comparison result, and the third comparison result is used as the least significant bit of the read result.

[0035] The present invention has at least the following beneficial effects: the ferroelectric memory of the present invention, by applying different voltages to the ferroelectric memory cells, uses the different polarization strengths of the ferroelectric material to characterize different storage data, realizes that each storage cell stores multi-bit data, can improve the storage density of the ferroelectric memory, and improves the storage capacity per unit area of ​​the ferroelectric memory. At the same time, the present invention designs a new write circuit and read circuit of the ferroelectric memory, through which the data of the ferroelectric memory cell can be read and written. The write circuit and read circuit have simple structures and occupy a small chip structure size, which can reduce the size of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention will be further described below in conjunction with specific embodiments with reference to the accompanying drawings.

[0037] Figure 1It is a schematic structural diagram of a ferroelectric memory unit of the ferroelectric memory of the present invention.

[0038] Figure 2 It is a schematic diagram of the representation principle of the storage data of the ferroelectric memory of the present invention.

[0039] Figure 3 It is a schematic diagram of a hysteresis loop in which each storage unit of the ferroelectric memory of the present invention stores two bits of data.

[0040] Figure 4A A schematic diagram showing a reference voltage generating circuit of a ferroelectric memory when reading data according to the present invention

[0041] Figure 4B A schematic diagram showing the bit line voltage when the ferroelectric memory according to the present invention stores different data and the values ​​of different reference voltages when reading data;

[0042] Figure 5 1 is a schematic diagram of the structure of a data reading voltage comparison circuit according to an embodiment of the present invention, wherein three comparators are used to perform comparison simultaneously.

[0043] Figure 6 is a schematic structural diagram of a data reading voltage comparison circuit according to another embodiment of the present invention, wherein one comparator is used to perform two comparisons.

[0044] Fig. 7A Is adopted Figure 6 A structural diagram of a data reading comparison circuit according to the method shown.

[0045] Figure 7B yes Fig. 7A Schematic diagram of the structure of the circuit for generating control signals CK1 and CK2.

[0046] Figure 7C is based on Fig. 7A A structural schematic diagram of a read signal output circuit in an embodiment of the present invention.

[0047] Fig.7D is based on Fig. 7A A read control timing diagram of an embodiment in FIG.

[0048] Fig. 8A is a schematic structural diagram of a data writing circuit according to an embodiment of the present invention.

[0049] Figure 8B yes Fig. 8A Schematic diagram of the structure of the voltage signal generating circuit of the writing circuit.

[0050] Figure 8C yes Fig. 8A Schematic diagram of the structure of the control signal generating circuit of the write circuit.

[0051] Fig.8D yes Fig. 8A The write control timing diagram of the write circuit in FIG. DETAILED DESCRIPTION

[0052] It should be noted that the components in the figures may be shown exaggeratedly for the sake of illustration and are not necessarily true to scale. In the figures, identical or functionally identical components are provided with the same reference numerals.

[0053] In the present invention, unless otherwise specified, "arranged on...", "arranged above..." and "arranged above..." do not exclude the existence of an intermediate between the two. In addition, "arranged on or above..." merely indicates the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted into "arranged below or below...", and vice versa.

[0054] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0055] In the present invention, unless otherwise specified, the quantifiers "a", "an" and "an" do not exclude the presence of a plurality of elements.

[0056] It should also be pointed out that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but a person of ordinary skill in the art will understand that under the teachings of the present invention, required parts or components may be added as needed in specific scenarios.

[0057] It should also be noted that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the values ​​of the two are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", "substantially equal to". By analogy, in the present invention, the terms "perpendicular to", "parallel to" and the like indicating directions also cover the meanings of "substantially perpendicular to" and "substantially parallel to".

[0058] In addition, the numbering of the steps of the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps can be executed in different orders.

[0059] The present invention will be further described below in conjunction with specific embodiments with reference to the accompanying drawings.

[0060] like Figure 1As shown, a ferroelectric memory cell 100 of a ferroelectric memory according to the present invention has a ferroelectric capacitor 101 and a transistor 102. The ferroelectric capacitor 101 has two plates and a ferroelectric material sandwiched between the plates. One end of the capacitor 101 is connected to a plate line PL, and the other end is connected to one of the drain and source of the transistor 102. The gate of the transistor 102 is connected to a word line WL, and the other of its drain and source is connected to a bit line BL.

[0061] Due to the characteristics of ferroelectric materials, when an electric field is applied to a ferroelectric capacitor containing ferroelectric materials, the ferroelectric domains of the ferroelectric materials will be polarized. When the applied electric field is removed, the ferroelectric domains of the ferroelectric materials will maintain a certain degree of polarization, i.e., residual polarization intensity. The different residual polarization intensities of the ferroelectric materials will cause different electric fields between the two plates of the ferroelectric capacitor, so that the voltage of the bit line BL connected to the capacitor plate will be different.

[0062] See also Figure 2 As shown, in the read / write circuit 200, the potential of the bit line BL is measured by a collection capacitor 201 connected to the bit line BL, and the potential of the BL is converted into a digital signal 1 or 0 by an analog-to-digital converter 202. Then, the data stored in the ferroelectric memory cell is characterized by comparing the signal of the BL potential with the reference signal.

[0063] See also Figure 3 As shown, in the ferroelectric memory of the present invention, two different voltages VCC1 and VCC2 are applied to the capacitor 101 of the ferroelectric memory cell in the forward and reverse directions respectively. Due to the different applied voltages, the residual polarization strength of the ferroelectric material of the ferroelectric memory cell is different, so the hysteresis loop 300 of the ferroelectric memory cell corresponding to the two voltages will form Figure 3 There are two hysteresis loops in the circuit, namely the first hysteresis loop 301 and the second hysteresis loop 302. The intersection of the hysteresis loop and the vertical axis is the residual polarization intensity Pr of the ferroelectric material. Different logic storage signals are characterized by the different residual polarization intensity Pr of the ferroelectric material.

[0064] In this embodiment, the first hysteresis loop 301 has first and second intersections D and A with the Pr axis, which have first and second polarization intensity values, respectively. In this embodiment, they represent "00" and "01" in 2-bit data values, respectively; the second hysteresis loop 202 has third and fourth intersections H and G with the Pr axis, which have third and fourth polarization intensity values, respectively. In this embodiment, they represent "10" and "11" in 2-bit data values, respectively. For this reason, the ferroelectric memory cell preferably has a sufficiently large Pr window, that is, a hysteresis loop with a larger area. The Pr window of the material can be increased by optimizing the material, and at the same time, the minimum sensible pr window interval can be reduced by improving the accuracy of the reading circuit. By applying different voltages, the polarization degree of the ferroelectric material is different, and different data can be read out in the same reading mode through the polarization difference. A 2-bit read and write operation is realized. The ferroelectric material or ferroelectric itself can have multiple hysteresis loops (such as the first and second hysteresis loops described here), that is, the ferroelectric material or ferroelectric has different hysteresis loops according to the different voltages applied. However, it should be pointed out that the present invention can still be implemented in the case of a ferroelectric memory cell with a smaller Pr window. However, since the four intersection points (polarization intensity values) are relatively close to each other, a more precise reading determination method and writing method are required to achieve the distinction between smaller polarization intensities.

[0065] In this embodiment of the present invention, the values ​​of the voltages VCC1 and VCC2 applied to the ferroelectric capacitor are such that the absolute value of the third polarization intensity value ("10") is 1 / 3 of the absolute value of the first polarization intensity value ("00"), i.e., 1 / 3 Pr, and the absolute value of the fourth polarization intensity value ("11") is 1 / 3 of the absolute value of the second polarization intensity value ("01"), i.e., 1 / 3 Pr. With such a setting, a larger margin can be achieved when reading / writing data, thereby better avoiding miswriting or misreading.

[0066] Different voltages are applied to the ferroelectric capacitors, and then the applied voltages are canceled, and different logic storage signals are characterized by the residual polarization intensity of the ferroelectric material of the ferroelectric capacitor, thereby realizing the writing of the four values ​​of "00", "01", "10", and "11" of the ferroelectric memory. Here, the horizontal axis shows the different voltages applied to the ferroelectric capacitor, namely the first voltage Vcc2, the second voltage Vcc1, the third voltage -Vcc1, and the fourth voltage -Vcc2. The absolute value of the first voltage is greater than the absolute value of the second voltage, and the absolute value of the fourth voltage is greater than the absolute value of the third voltage. The negative voltage indicates that the voltage applied to the two plates of the ferroelectric capacitor is the opposite voltage to the positive voltage.

[0067] The ferroelectric memory uses the residual polarization intensity of the ferroelectric material in the ferroelectric capacitor to affect the potential of the bit line connected to one end of the ferroelectric capacitor. By measuring the potential of the bit line and comparing it with a reference voltage, the storage data of the ferroelectric memory cell is defined. Therefore, in order to read the data stored in the memory cell, a reference voltage needs to be set. Each memory cell of the ferroelectric memory of the present invention can store 2 bits of data, which can have four states: 00, 01, 10, and 11. The corresponding bit line voltages of the memory cells are VBL, ... 00 、VBL 01 、VBL 10 、VBL 11 In order to determine the specific data to be stored, three reference voltages need to be set to compare with the bit line voltage of the memory cell to determine the specific data to be stored.

[0068] See also Figure 4A As shown, a circuit for setting three reference voltages, i.e., a reference voltage generating circuit 400, is shown. When setting the three reference voltages, data 00, 01, 10, 11 are written into four reference cells (not shown) respectively, so that first, second, third, and fourth bit line voltages VBL corresponding to 00, 01, 10, 11 are generated on the bit lines of the reference cells, respectively. 00 、VBL 01 、VBL 10 、VBL 11 , where the first, second, third and fourth bit line voltages VBL 00 、VBL 01 、VBL 10 、VBL 11 Raise successively;

[0069] The reference voltage generating circuit 400 generates a voltage according to the first and second bit line voltages VBL. 00 、VBL 01 Generate a first reference voltage VREF1, wherein the first reference voltage VREF1 is between the first and second bit line voltages. Here, the first reference voltage is 1 / 2 of the sum of the first and second bit line voltages, that is, VREF1=(VBL 00 +VBL 01 ) / 2.

[0070] The reference voltage generating circuit 400 generates a voltage according to the second and third bit line voltages VBL. 01 、VBL 10 Generate a second reference voltage VREF2, wherein the second reference voltage VREF2 is between the second and third bit line voltages. Here, the second reference voltage is 1 / 2 of the sum of the second and third bit line voltages, that is, VREF2=(VBL 01 +VBL 10) / 2.

[0071] The reference voltage generating circuit 400 generates a voltage according to the third and fourth bit line voltages VBL. 10 、VBL 11 Generate a third reference voltage VREF3, wherein the third reference voltage VREF3 is between the third and fourth bit line voltages. Here, the third reference voltage is 1 / 2 of the sum of the third and fourth bit line voltages, that is, VREF3=(VBL 10 +VBL 11 ) / 2.

[0072] The reference voltage generating circuit 400 may be composed of, for example, an adder and a divider, and other configurations are also conceivable.

[0073] like Figure 4B As shown, the first, second and third reference voltages VREF1, VREF2, VREF3 are related to the bit line voltage VBL 00 、VBL 01 、VBL 10 、VBL 11 The size relationship between them. So when the bit line voltage VBL of the storage cell is 00 、VBL 01 、VBL 10 、VBL 11 When compared with the reference voltage, the bit line voltage value of the memory cell can be determined, thereby determining the data stored in the memory cell.

[0074] Because it is necessary to compare the bit line voltage of the memory cell with three reference voltages to determine the data stored in the memory cell, according to one embodiment of the present invention, Figure 5 As shown, three comparators 501, 502, and 503 can be set to compare the potential of the storage unit with three reference voltages at the same time to obtain the data stored in the storage unit. This can achieve a faster reading speed, but setting three comparators 501, 502, and 503 will occupy a larger chip area.

[0075] See also Figure 6 As shown, it shows that according to another embodiment of the present invention, a voltage selection circuit and a voltage comparator 600 are set, and a comparison method is adopted in a successive approximation method. The data stored in the ferroelectric memory cell of the present invention is 2-bit data, represented by D1D0. When reading, first, the comparison circuit, i.e., the voltage comparator 600, compares the bit line voltage VBL of the ferroelectric memory cell to be read with the second reference voltage VREF2 at an intermediate value to obtain a first comparison result, and the first comparison result is used as the most significant bit D1 of the 2-bit read result.

[0076] Then, if the bit line voltage VBL of the ferroelectric memory cell is higher than the second reference voltage, the first comparison result is 1, and the comparison circuit, i.e., the voltage comparator 600, compares the bit line voltage VBL with the third reference voltage VREF3 higher than the second reference voltage VREF2 to obtain a second comparison result, and the second comparison result is used as the least significant bit D0 of the 2-bit read result. If the bit line voltage VBL of the ferroelectric memory cell is lower than the second reference voltage, the first comparison result is 0, and the comparison circuit, i.e., the voltage comparator 600, compares the bit line voltage VBL with the first reference voltage VREF1 lower than the second reference voltage VREF2 to obtain a third comparison result, and the third comparison result is used as the least significant bit LSB of the 2-bit read result.

[0077] The following will combine the specific circuit and timing diagram to Figure 6 The illustrated embodiment is further described.

[0078] See also Fig. 7A As shown, it is displayed according to Figure 6 The schematic diagram of the readout circuit 700 of the embodiment shown in the figure. The readout circuit 700 according to an embodiment of the present invention comprises a comparator clock signal control circuit 701 composed of a delay circuit DELAY and a NOT gate, a voltage selection circuit MUX702, a comparator SA 703 and a NAND gate circuit NAND 704. The input end of the delay circuit DELAY is connected to the read comparison ready signal READY, the output end of the delay circuit and READ_N, READY_D and CK2 form the input end of the NOT gate, and the output end of the NOT gate NOR is used as the clock signal input end of the comparator SA.

[0079] The three input terminals of the MUX voltage selection circuit 702 are respectively connected to three reference voltages VREF1, VREF2, and VREF3, the control terminal of the voltage selection circuit is connected to CK1 and D1, the output terminal VREF_SEL of the voltage selection circuit 702 is connected to an input terminal of the voltage comparator SA 703, and the other input terminal of the voltage comparator 703 is connected to the bit line BL of the ferroelectric memory cell.

[0080] See also Figure 7BAs shown, it shows a schematic diagram of a control signal generating circuit 705 of a readout circuit of the present invention. As shown in the figure, the readout circuit control signal generating circuit 705 includes two D flip-flops DFF, wherein the input terminal of the first D flip-flop DFF1 is connected to VDD, the clock signal terminal is connected to the read comparison ready signal READY, the reset terminal RST is connected to the reverse signal READ_N for starting to read, the output terminal CK1 of the D flip-flop is used as the input terminal of the second D flip-flop DFF2, the clock signal terminal of the second D flip-flop DFF2 is connected to the comparison ready signal READY, the reset terminal RST of the second D flip-flop DFF2 is connected to the reverse signal READ_N for starting to read, and the output terminal of the second D flip-flop is CK2.

[0081] See also Figure 7C As shown, it shows the read signal latch circuit 706 of the present invention, which includes a third D flip-flop DFF3 for latching the D1 bit of the read signal, and a fourth D flip-flop DFF4 for latching the D0 bit of the read signal. The output terminal OUT of the comparator is used as the input terminal of the latch, the reverse signal READ_N for starting to read is connected to the reset terminals of the two flip-flops, the output terminal CK1 of the first flip-flop is connected to the clock signal terminal of DFF3, and the output terminal CK2 of the second flip-flop is connected to the clock signal terminal of DFF4.

[0082] Combine the following Fig.7D The timing diagram and Figures 7A-7C The circuit schematic diagram shown in the figure takes the stored data D1D0=10 as an example to illustrate the reading operation of the present invention.

[0083] See also Fig.7D Timing diagram, when the READ_N signal becomes low, the read operation starts. At this time, CK1 and D1 are reset to 0 by the previous operation, VREF_SEL is selected as VREF2 by the voltage selection circuit, and VREF2 is used as an input signal of the voltage comparator SA703;

[0084] Then, the voltages of WL and PL connected to the ferroelectric memory cell are increased. According to the different information stored in the ferroelectric memory cell, the voltage of BL is different. At this time, the voltage of BL is increased to VBL according to the stored information; VBL serves as another input signal of the voltage comparator 703;

[0085] Because the READ_N signal is low level 0, the CK_SA voltage increases and SA starts working. Because VBL is greater than VREF2, the output OUT of the comparator SA703 is 1 and OUT_N is 0. The NAND (NAND gate) detects that OUT_N is low, indicating that SA has compared the result, and then the READY signal becomes high.

[0086] like Figure 7BAs shown, the READY signal is the input clock of the first flip-flop DFF1 and the second flip-flop DFF2DFF, and the first flip-flop DFF1 starts to collect data. As a result, CK1 rises, and CK2 remains at 0;

[0087] like Figure 7C As shown, the input terminal CK1 of the third trigger DFF3 transmits OUT to the output terminal D1 through DFF3, and D1 rises to 1. At this time, the first comparison result has come out. Because the voltage of VBL is higher than VREF2, the data D1 stored in the ferroelectric memory cell is 1. Please continue to refer to Fig. 7A As shown, because CK1 is the control terminal of the voltage selection circuit, when CK1 is 1, the voltage selection circuit selects VREF_SEL as VREF3;

[0088] After a certain delay, the READY signal passes through the NOR (NOR gate) to pull CK_SA low. At this time, SA is reset, OUT and OUTN both become high, and then READY becomes low;

[0089] After a certain delay after READY becomes low, CK_SA is pulled high again through the NOR (NOR gate), SA works again, and the second comparison begins.

[0090] At this time, the VBL of the ferroelectric memory cell is compared with the third reference voltage VREF3. Since the ferroelectric memory cell stores 10, the value of VBL is smaller than the third reference voltage VREF3. At this time, the signal OUT output by the comparator is 0.

[0091] See also Figure 7B As shown, when the second comparison is completed, the output terminal CK2 of the second flip-flop DFF2 becomes 1.

[0092] See also Figure 7C As shown, when CK2 rises, the signal of OUT being 0 is transmitted to D0, and the data of D0 is 0. Then the data D1 read out at this time is 1, and D0 is 0, which means that the data stored in the ferroelectric memory cell is 10. At this time, the data can be output through the peripheral logic circuit (not shown);

[0093] Then READ_N goes high, resetting the DFF inside, and the read operation ends.

[0094] Figures 8A-8D A circuit diagram and a timing diagram of a write circuit 500 of a ferroelectric memory according to the present invention are shown.

[0095] in Fig. 8A This is a schematic diagram of the structure of the write drive circuit. Figure 8B is a schematic diagram of a driving circuit for a transistor of a bit line driving circuit in a write driving circuit, Figure 8CIt is a power generation circuit for the transistors in the bit line driver circuit in the write driver circuit.

[0096] like Fig. 8A As shown, the write drive circuit 800 includes a bit line drive circuit connected to the bit line BL, and the bit line drive circuit includes a first, a second, a third and a fourth transistor, wherein the gate of the first transistor PM1 is connected to the output terminal A of the first NAND gate, one of its drain and source is connected to the first voltage VCC1, and the other of its drain and source is connected to the bit line of the ferroelectric memory cell to be written, the gate of the second transistor PM2 is connected to the output terminal B of the second NAND gate, one of its drain and source is connected to the second voltage VCC2, and the other of its drain and source is connected to the bit line of the ferroelectric memory cell to be written, the gate of the third transistor PM3 is connected to the output terminal of the third NAND gate, one of its drain and source is connected to the third voltage, and the other of its drain and source is connected to the bit line of the ferroelectric memory cell to be written, and the gate of the fourth transistor PM4 is connected to the output terminal of the fourth NAND gate, one of its drain and source is connected to the fourth voltage, and the other of its drain and source is connected to the bit line of the ferroelectric memory cell to be written.

[0097] The write drive circuit also includes a plate line drive circuit 802 connected to a plate line PL connected to one plate of the ferroelectric capacitor, the plate line drive circuit 802 includes a fifth transistor PM5 and a sixth transistor NM6, wherein the gates of the fifth transistor PM5 and the sixth transistor NM6 are connected to the plate line input voltage PL_IN, the source of the fifth transistor is connected to the second voltage VCC2, and the drain of the fifth transistor is connected to the plate line PL. The source of the sixth transistor NM6 is grounded, and the drain of the sixth transistor is connected to the plate line PL.

[0098] See also Figure 8B As shown, it shows the power supply generation circuit 803 of the transistor of the bit line driving circuit in the write driving circuit. In the figure, VCC1, VCC2 and VCC3 are internal voltage sources generated by VEXT (chip external voltage) through LDO (low dropout linear regulator), where VCC3=VCC2-VCC1.

[0099] See also Figure 8C As shown, Figure 8CA schematic diagram of a driving circuit for transistors of a bit line driving circuit in a write driving circuit, wherein the bit line driving circuit 804 comprises a first, a second, a third and a fourth AND gate, wherein two input terminals of the first AND gate respectively input the inverted values ​​of the most significant bit and the least significant bit of a signal to be written, and its output terminal is connected to one of the input terminals of the first NAND gate, the input terminals of the second AND gate respectively input the most significant bit and the least significant bit of a signal to be written, and its output terminal is connected to one of the input terminals of the second NAND gate, the input terminals of the third AND gate respectively input the inverted value of the most significant bit and the least significant bit of a signal to be written, and its output terminal is connected to one of the input terminals of the third NAND gate, and the input terminals of the fourth AND gate respectively input the inverted value of the most significant bit and the inverted value of the least significant bit of a signal to be written, and its output terminal is connected to one of the input terminals of the fourth NAND gate; a second, a third and a fourth NAND gate, wherein the other of the input terminals of the first, the second, the third and the fourth NAND gate respectively input a write enable signal; in combination with Fig. 8A As shown, the output terminal A of the first NAND gate is connected to the gate of the first transistor PM1, the output terminal B of the second NAND gate is connected to the gate of the second transistor PM2, the output terminal C of the third NAND gate is connected to the gate of the third transistor PM3, and the output terminal D of the fourth NAND gate is connected to the gate of the fourth transistor PM4.

[0100] Fig.8D A timing diagram of the write circuit 500 is shown.

[0101] Combination Figure 8A-8D As shown, the writing method of the storage unit of the ferroelectric memory of the present invention is as follows:

[0102] When writing 00, the peripheral logic circuit (not shown) inputs D1D0=00. After WL rises, PL rises to VCC2. After the write enable signal WRITE (not shown) rises, the A, B, C, and D voltages all rise, and the BL voltage is pulled down to 0. At this time, the voltage across the FRAM capacitor is VCC2, and then the PL voltage drops to 0, and the FRAM capacitor voltage also drops to 0. Figure 3 It can be seen that the capacitor state is (Pr, 00) at this time;

[0103] When writing 01, the peripheral logic circuit input D1D0 = 01. After WL rises, PL rises to VCC2. After the WRITE signal rises, the A and B voltages rise, the C and D voltages decrease, and the BL voltage is pulled to VCC3. At this time, the voltage across the FRAM capacitor is VCC1, and then the PL and BL voltages decrease to 0, and the FRAM capacitor voltage also decreases to 0. Figure 3 It can be seen that the capacitor state is (Pr / 3,01) at this time;

[0104] When writing 10, the peripheral logic circuit input D1D0 = 10. After WL increases, PL increases to VCC2. After the WRITE signal increases, the B and C voltages increase, the A and D voltages decrease, and the BL voltage is pulled to VCC1. Then the PL voltage decreases to 0 first, at which time the FRAM capacitor voltage is -VCC1, and then the BL voltage decreases to 0, and the FRAM capacitor voltage also becomes 0. Figure 3 It can be seen that the capacitor state is (-Pr / 3,10) at this time;

[0105] When writing 11, the peripheral logic circuit input D1D0 = 11. After WL rises, PL rises to VCC2. After the WRITE signal rises, the A and C voltages rise, the B and D voltages become low, and the BL voltage is pulled to VCC2. Then the PL voltage first drops to 0, at which time the FRAM capacitor voltage is -VCC2, and then the BL voltage drops to 0, and the FRAM capacitor voltage also becomes 0. Figure 3 It can be seen that the capacitor state is (Pr / 3,11) at this time.

[0106] Although some embodiments of the present invention have been described in this application document, it will be appreciated by those skilled in the art that these embodiments are merely shown as examples. Those skilled in the art may conceive of numerous variations, alternatives, and improvements under the teachings of the present invention without departing from the scope of the present invention. The appended claims are intended to define the scope of the present invention and thus cover methods and structures within the scope of these claims themselves and their equivalents.

Claims

1. A ferroelectric memory, comprising: A plurality of ferroelectric memory cells, each ferroelectric memory cell comprising a ferroelectric capacitor, wherein the ferroelectric capacitor comprises an upper plate, a lower plate and a ferroelectric material located between the upper plate and the lower plate; A write circuit is configured to apply a first voltage and a second voltage to two plates of a ferroelectric capacitor of a ferroelectric memory cell in a forward direction and a reverse direction, respectively, so that the ferroelectric material has corresponding first, second, third and fourth remanent polarization intensity values, respectively, to write different storage data, wherein different remanent polarization intensity values ​​correspond to different storage data, wherein the write circuit comprises: a first, a second, a third and a fourth AND gate, wherein two input terminals of the first AND gate respectively input the inverted values ​​of the most significant bit and the least significant bit of the signal to be written, and an output terminal thereof is connected to one of the input terminals of the first NAND gate, an input terminal of the second AND gate respectively inputs the most significant bit and the least significant bit of the signal to be written, and an output terminal thereof is connected to one of the input terminals of the second NAND gate, an input terminal of the third AND gate respectively inputs the inverted value of the most significant bit and the least significant bit of the signal to be written, and an output terminal thereof is connected to one of the input terminals of the third NAND gate, and an input terminal of the fourth AND gate respectively inputs the inverted value of the most significant bit and the inverted value of the least significant bit of the signal to be written, and an output terminal thereof is connected to one of the input terminals of the fourth NAND gate, first, second, third and fourth NAND gates, wherein the other of the input terminals of the first, second, third and fourth NAND gates respectively inputs a write enable signal; and first, second, third and fourth transistors, wherein the gate of the first transistor is connected to the output terminal of the first NAND gate, one of its drain and source is connected to the first voltage, and the other of its drain and source is connected to the bit line of the ferroelectric memory cell to be written, the gate of the second transistor is connected to the output terminal of the second NAND gate, one of its drain and source is connected to the second voltage, and the other of its drain and source is connected to the bit line of the ferroelectric memory cell to be written, the gate of the third transistor is connected to the output terminal of the third NAND gate, one of its drain and source is connected to the third voltage, and the other of its drain and source is connected to the bit line of the ferroelectric memory cell to be written, and the gate of the fourth transistor is connected to the output terminal of the fourth NAND gate, one of its drain and source is connected to the fourth voltage, and the other of its drain and source is connected to the bit line of the ferroelectric memory cell to be written; as well as The reading circuit includes a reference voltage generating circuit and a voltage comparison circuit. The voltage comparison circuit can compare the collected voltage at one end of the ferroelectric capacitor of the ferroelectric storage unit with the reference voltage generated by the reference voltage generating circuit to output different comparison results to read different storage data.

2. The ferroelectric memory according to claim 1, wherein the values ​​of the third remanent polarization intensity and the fourth remanent polarization intensity corresponding to the second voltage applied to the ferroelectric capacitor by the write circuit are 1 / 3 of the values ​​of the first remanent polarization intensity and the second remanent polarization intensity corresponding to the first voltage applied to the ferroelectric capacitor by the write circuit.

3. The ferroelectric memory according to claim 1, wherein the read circuit comprises: four reference cells configured to generate first, second, third and fourth bit line voltages corresponding to 00, 01, 10 and 11 respectively on their bit lines when one of 00, 01, 10 and 11 is written, wherein the first, second, third and fourth bit line voltages increase in sequence; A first reference voltage generating circuit generates a first reference voltage according to the first and second bit line voltages, wherein the magnitude of the first reference voltage is between the magnitudes of the first and second bit line voltages; A second reference voltage generating circuit generates a second reference voltage according to the second and third bit line voltages, wherein the second reference voltage is between the second and third bit line voltages; as well as The third reference voltage generating circuit generates a third reference voltage according to the third and fourth bit line voltages, wherein a magnitude of the third reference voltage is between magnitudes of the third and fourth bit line voltages.

4. The ferroelectric memory according to claim 3, wherein the first reference voltage is the average value of the sum of the first bit line voltage and the second bit line voltage, the second reference voltage is the average value of the sum of the second bit line voltage and the third bit line voltage, and the third reference voltage is the average value of the sum of the third bit line voltage and the fourth bit line voltage.

5. The ferroelectric memory according to claim 3, wherein the voltage comparison circuit comprises three voltage comparators, wherein one input terminal of the first voltage comparator is connected to the first reference voltage, and another input terminal is connected to the bit line of the ferroelectric memory cell; One input terminal of the second voltage comparator is connected to the second reference voltage, and the other input terminal is connected to the bit line of the ferroelectric memory cell; One input terminal of the third voltage comparator is connected to the third reference voltage, and the other input terminal is connected to the bit line of the ferroelectric memory cell.

6. The ferroelectric memory according to claim 3, wherein the voltage comparison circuit comprises a voltage selection circuit and a voltage comparator, wherein three input terminals of the voltage selection circuit respectively input one of three reference voltages output by the reference voltage generation circuit, and an output terminal thereof is connected to an input terminal of the voltage comparator, Another of the input terminals of the voltage comparator is connected to the bit line of the ferroelectric memory cell, and its output terminal outputs the comparison result; The voltage comparison circuit also includes a voltage comparator clock signal control circuit, which includes a delay circuit and a NOT gate, wherein the input end of the delay circuit is connected to the output end of the voltage comparator, and the output end of the NOT gate is connected to the clock signal input end of the voltage comparator.

7. The ferroelectric memory according to claim 6, wherein the output end of the voltage comparator includes a first output end and a second output end, and the first output end and the second output end are compared with a ready signal through a NAND gate output; the reading circuit also includes a control signal generating circuit, and the control signal generating circuit includes a shift register composed of two interconnected D flip-flops, wherein the output end of the first D flip-flop is connected to the control signal input end of the voltage selection circuit, and the output end of the second D flip-flop is connected to the input end of the clock signal control circuit of the voltage comparator.

8. The ferroelectric memory according to claim 7, wherein the read circuit further comprises a read signal latch circuit, which comprises a third D flip-flop for latching the most significant bit of the read signal, and a fourth D flip-flop for latching the least significant bit of the read signal; wherein the output end of the voltage comparator is connected to the input end of the third D flip-flop and the fourth D flip-flop, the reverse signal for starting reading is connected to the reset end of the third D flip-flop and the fourth D flip-flop, the output end of the first D flip-flop is connected to the clock signal end of the third D flip-flop, and the output end of the second D flip-flop is connected to the clock signal end of the fourth D flip-flop.

9. A method for performing a write operation on the ferroelectric memory according to any one of claims 1 to 8, the method comprising: The write circuit is used to apply a first voltage and a second voltage to the two plates of the ferroelectric capacitor of the ferroelectric storage unit in the forward and reverse directions respectively, so that the ferroelectric material has corresponding first, second, third and fourth residual polarization intensity values ​​respectively, so as to write different storage data corresponding to different residual polarization intensity values ​​respectively.

10. A method for performing a reading operation on the ferroelectric memory according to any one of claims 1 to 6, the method comprising: The read circuit is used to generate three reference voltages. The bit line voltage of the ferroelectric memory cell collected by the reading circuit is compared with three reference voltages respectively, and the data stored in the ferroelectric memory cell is read out according to the comparison result.

11. A method for performing a reading operation on the ferroelectric memory according to any one of claims 1 to 5 and 7 to 8, the method comprising: The read circuit is used to generate three reference voltages, wherein the third reference voltage is greater than the second reference voltage, and the second reference voltage is greater than the first reference voltage; Comparing the bit line voltage of the ferroelectric memory cell to be read with the second reference voltage to obtain a first comparison result, and using the first comparison result as the most significant bit of the read result; as well as If the first comparison result is that the bit line voltage of the ferroelectric memory cell is greater than the second reference voltage, the bit line voltage is compared with the third reference voltage to obtain a second comparison result, and the second comparison result is used as the least significant bit of the read result; and if the first comparison result is that the bit line voltage of the ferroelectric memory cell is less than the second reference voltage, the bit line voltage is compared with the first reference voltage to obtain a third comparison result, and the third comparison result is used as the least significant bit of the read result.

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