Method, device and storage medium for performing dynamic and static testing of semiconductors

Abstract

The embodiments of the present invention provide a method, device and storage medium for performing dynamic and static testing of semiconductors, belonging to the field of semiconductor testing technology. The device includes: a bus capacitor; a first controllable switch; a load inductance switching module; a second controllable switch; a first signal enable module; a second signal enable module; a host computer, connected to the first signal enable module and the second signal enable module, for controlling the operation of the first signal enable module and the second signal enable module to complete the dynamic and static testing. The method, device and storage medium use the same set of equipment to simultaneously implement dynamic testing and static testing operations of semiconductors, thereby solving the technical problem in the prior art that two sets of equipment are required to perform dynamic testing and static testing, thereby improving the efficiency of semiconductor testing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing technology, and in particular to a method, device and storage medium for performing dynamic and static testing of a semiconductor. Background Art

[0002] The performance test of semiconductor power devices such as insulated gate bipolar transistor (IGBT) and metal-oxide semiconductor field-effect transistor (MOSFET) is generally divided into two parts, namely dynamic test and static test. The former tests and evaluates the switching characteristics of power devices and the reverse recovery characteristics of internal freewheeling diodes or parasitic diodes, while the latter tests and evaluates various static parameters of power devices such as on-state voltage drop and threshold voltage. The original power device test system has the following two problems:

[0003] (1) The automation level of the test process and data processing process is low, and the test working point needs to be switched manually, which greatly reduces the test efficiency;

[0004] (2) The complete performance test of the device requires the use of two systems: static test and dynamic test. That is, different hardware circuits and software systems are needed to test the device, resulting in problems such as high equipment cost, large size and low test efficiency. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide a method, device and storage medium for performing dynamic and static testing of semiconductors. The method, device and storage medium can simultaneously implement dynamic testing and static testing of semiconductors.

[0006] In order to achieve the above object, an embodiment of the present invention provides a device for performing dynamic and static testing of a semiconductor, the device comprising:

[0007] A bus capacitor, one end of which is used to be connected to the drain of the first device under test, and the other end of which is used to be connected to the source of the second device under test, wherein the source of the first device under test is connected to the drain of the second device under test;

[0008] A first controllable switch, one end of which is connected to one end of the bus capacitor;

[0009] a load inductance switching module, one end of which is used to be connected to the source of the first device under test, and the other end of which is connected to the other end of the first controllable switch;

[0010] a second controllable switch, one end of which is connected to the other end of the load inductance switching module, and the other end of which is used to be connected to the source of the second device under test;

[0011] A first signal enabling module, used to collect the current of the node between the drain of the first device under test and the bus capacitor, the voltage between the gate of the first device under test and the source of the first device under test, and the voltage between the source of the first device under test and the drain of the first device under test;

[0012] A second signal enabling module, used to collect the current of the node between the drain of the second device under test and the bus capacitor, the voltage between the gate of the second device under test and the source of the second device under test, and the voltage between the source of the second device under test and the drain of the second device under test;

[0013] A host computer is connected to the first signal enabling module and the second signal enabling module, and is used to control the operation of the first signal enabling module and the second signal enabling module to complete the dynamic and static tests.

[0014] Optionally, at least one of the first signal enabling module and the second signal enabling module includes:

[0015] A high-speed sampling board, used for collecting the current of the node between the drain of the first device under test / the second device under test and the bus capacitor, the voltage between the gate of the first device under test / the second device under test and the source of the first device under test / the second device under test, and the voltage between the source of the first device under test / the second device under test and the drain of the first device under test / the second device under test;

[0016] A first clamping circuit connected to a first end of the high-speed sampling board;

[0017] A second clamping circuit connected to the second end of the high-speed sampling board;

[0018] The isolation circuit has one end connected to the third end of the high-speed sampling board, and the other end is used to output the acquisition signal or receive the test signal input by the host computer.

[0019] Optionally, the device further comprises a first diode, an anode of which is used to be connected to a source of the first device under test, and a cathode of which is used to be connected to a drain of the first device under test.

[0020] Optionally, the device further comprises a second diode, an anode of which is used to be connected to a source of the second device under test, and a cathode of which is used to be connected to a drain of the second device under test.

[0021] Optionally, the load inductance switching module includes:

[0022] At least two inductors connected in series, one end of a first inductor being used to be connected to a source of the first device under test;

[0023] A third controllable switch corresponding to each of the inductors one by one, each of the inductors being connected to the other end of the first controllable switch through the corresponding third controllable switch.

[0024] Optionally, the device further comprises a temperature regulating module, which is connected to the host computer and is used to regulate the temperature of the first device under test / the second device under test.

[0025] In another aspect, the present invention further provides a method for performing dynamic and static testing of a semiconductor, the method comprising:

[0026] Get DoE parameters;

[0027] Select a test point from the DoE parameters in order;

[0028] Inputting the test point into the first signal enabling module / the second signal enabling module of any one of the above devices to perform the test;

[0029] receiving a result of the selected test point from the first signal enabling module / the second signal enabling module;

[0030] Determine whether the selected test point is the last test point;

[0031] In the case where it is determined that the selected test point is not the last test point, selecting a test point again from the DoE parameters in order until it is determined that the selected test point is the last test point;

[0032] In the case where it is determined that the selected test point is the last test point, performing a data batch processing operation on all the results, and extracting static characteristic parameters / dynamic characteristic parameters of the device;

[0033] Output static characteristic parameters / dynamic characteristic parameters of the first device under test / the second device under test.

[0034] Optionally, the receiving a result of the selected test point from the first signal enabling module / the second signal enabling module specifically includes:

[0035] The results are stored in a unified format.

[0036] Optionally, the DoE parameter includes at least one of a gate voltage, a test current and a test temperature.

[0037] In yet another aspect, the present invention further provides a storage medium storing instructions, wherein the instructions are used to be read by a machine so as to enable the machine to execute any of the above methods.

[0038] Through the above technical scheme, the method, device and storage medium for performing dynamic and static testing of semiconductors provided by the present invention use the same set of equipment to simultaneously implement dynamic testing and static testing operations of semiconductors, thereby solving the technical problem in the prior art that two sets of equipment are required to perform dynamic testing and static testing, and improving the efficiency of semiconductor testing.

[0039] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0041] Figure 1 is a circuit diagram of an apparatus for performing dynamic and static testing of semiconductors according to the present invention;

[0042] Figure 2 is a circuit diagram of an apparatus for performing dynamic and static testing of semiconductors according to the present invention; and

[0043] Figure 3 is a flow chart of a method for performing dynamic and static testing of a semiconductor according to the present invention. DETAILED DESCRIPTION

[0044] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0045] In the embodiments of the present invention, unless otherwise specified, directional words such as "up, down, top, bottom" are usually used with reference to the directions shown in the drawings or are used to describe the relative positional relationships of components in the vertical, perpendicular or gravity direction.

[0046] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0047] Figure 1 is a schematic diagram of an apparatus for performing dynamic and static testing of semiconductors according to one embodiment of the present invention. Figure 1 The device may include a bus capacitor C1, a first device under test Q1, a second device under test Q2, a first controllable switch S1, a second controllable switch S2, a load inductance switching module L, a first signal enabling module 01 and a second signal enabling module 02.

[0048] One end of the bus capacitor C1 can be used to connect to the drain of the first device under test Q1, and the other end can be used to connect to the source of the second device under test Q2. The source of the first device under test Q1 can be connected to the drain of the second device under test Q2.

[0049] One end of the first controllable switch S1 can be connected to one end of the bus capacitor C1. One end of the load inductance switching module L can be used to connect to the source of the first device under test Q1, and the other end can be connected to the other end of the first controllable switch S1.

[0050] One end of the second controllable switch S2 may be connected to the other end of the load inductance switching module L, and the other end may be used to be connected to the source of the second device under test Q2.

[0051] The first signal enabling module 01 can be used to collect the current (I D1 ,I D2 ), the voltage between the gate of the first device under test Q1 and the source of the first device under test Q1 (V GS1 、V GS2 ) and the voltage between the source of the first device under test Q1 and the drain of the first device under test Q1.

[0052] The second signal enabling module 02 can be used to collect the current of the node between the drain of the second device under test Q2 and the bus capacitor C1, the voltage between the gate of the second device under test Q2 and the source of the second device under test Q2, and the voltage between the source of the second device under test Q2 and the drain of the second device under test Q2.

[0053] Host computer 03( Figure 1 The first signal enabling module 01 and the second signal enabling module 02 may be connected to control the operation of the first signal enabling module 01 and the second signal enabling module 02 to complete dynamic and static testing of the semiconductor.

[0054] The specific forms of the first signal enabling module 01 and the second signal enabling module 02 may be various forms known to those skilled in the art. In a preferred example of the present invention, at least one of the first signal enabling module 01 and the second signal enabling module 02 may include a high-speed sampling board 023, a first clamping circuit 021, a second clamping circuit 022, and an isolation circuit 024.

[0055] The high-speed sampling board 023 can be used to collect the current (I D1 ,I D2 ), the voltage between the gate of the first device under test Q1 / the second device under test Q2 and the source of the first device under test Q1 / the second device under test Q2 (V GS1 、V GS2 ) and the voltage between the source of the first device under test Q1 / the second device under test Q2 and the drain of the first device under test Q1 / the second device under test Q2. The first clamping circuit 021 can be connected to the first end of the high-speed sampling board 023. The second clamping circuit 022 can be connected to the second end of the high-speed sampling board 023. One end of the isolation circuit 024 can be connected to the third end of the high-speed sampling board 023, and the other end is used to output the acquisition signal or receive the test signal input by the host computer 03.

[0056] In one embodiment of the present invention, the device may further include a first diode D1. The anode of the first diode D1 may be connected to the source of the first device under test Q1, and the cathode of the first diode D1 may be connected to the drain of the first device under test Q1.

[0057] In one embodiment of the present invention, the device may further include a second diode D2 , an anode of which is connected to the source of the second device under test Q2 , and a cathode of which is connected to the drain of the second device under test Q2 .

[0058] In this embodiment, the load inductance switching module L can be any form of structure known to those skilled in the art that can freely switch the load inductance. In a preferred example of the present invention, the load inductance switching module L can include at least two inductors L0 connected in series and a third controllable switch S3 corresponding to the inductors L0. Among them, one end of the first inductor L0 can be used to connect to the source of the first device under test Q1; each inductor L0 can be connected to the other end of the first controllable switch S1 through the corresponding third controllable switch S3. The host computer 03 can adjust the load inductance by controlling different third controllable switches S3, thereby realizing the test of the semiconductor device.

[0059] In one embodiment of the present invention, it is considered that dynamic and static testing of a portion of a semiconductor involves changes in temperature conditions. Figure 2 As shown, the device may further include a temperature adjustment module 04. The temperature adjustment module 04 may be connected to the host computer 03, and is used to adjust the temperature of the first device under test Q1 / the second device under test Q2.

[0060] In this embodiment, for Figure 1 or Figure 2 The control method of the device shown in can be in various forms known to those skilled in the art. In one embodiment of the present invention, the method may include, for example Figure 3 The steps shown. Figure 3 In, the method may include:

[0061] In step S10, a DoE parameter is obtained, wherein the DoE parameter may include at least one of a gate voltage, a test current and a test temperature.

[0062] In step S11, a test point is selected from the DoE parameters in order;

[0063] In step S12, the test point is input as follows Figure 1 or Figure 2 The first signal enabling module / the second signal enabling module of the device shown in is used to perform the test. Further, in order to facilitate the statistics of the results, the results can be stored in a unified format.

[0064] In step S13, receiving the result of the selected test point from the first signal enabling module / the second signal enabling module;

[0065] In step S14, it is determined whether the selected test point is the last test point;

[0066] When it is determined that the selected test point is not the last test point, a test point is selected again from the DoE parameters in order until it is determined that the selected test point is the last test point;

[0067] In step S15, when it is determined that the selected test point is the last test point, a data batch processing operation is performed on all results, and static characteristic parameters / dynamic characteristic parameters of the device are extracted;

[0068] In step S16 , the static characteristic parameters / dynamic characteristic parameters of the first device under test Q1 / the second device under test Q2 are output.

[0069] In another aspect, the present invention further provides a storage medium, which may store instructions for being read by a machine to cause the machine to execute Figure 3 The method shown.

[0070] Through the above technical scheme, the method, device and storage medium for performing dynamic and static testing of semiconductors provided by the present invention use the same set of equipment to simultaneously implement dynamic testing and static testing operations of semiconductors, thereby solving the technical problem in the prior art that two sets of equipment are required to perform dynamic testing and static testing, and improving the efficiency of semiconductor testing.

[0071] The optional implementation modes of the examples of the present invention are described in detail above in conjunction with the accompanying drawings; however, the implementation modes of the present invention are not limited to the specific details in the above implementation modes; within the technical concept of the implementation modes of the present invention, a variety of simple modifications can be made to the technical solutions of the implementation modes of the present invention, and these simple modifications all belong to the protection scope of the implementation modes of the present invention.

[0072] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the present invention will not further describe various possible combinations.

[0073] Those skilled in the art can understand that all or part of the steps in the above-mentioned implementation method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including several instructions for making a single-chip microcomputer, chip, etc. or processor (processor) execute all or part of the steps of the method described in each implementation of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0074] In addition, various different embodiments of the embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the embodiments of the present invention, they should also be regarded as the contents disclosed in the embodiments of the present invention.

Claims

1. A device for performing dynamic and static testing of semiconductors, characterized in that: The device comprises: A bus capacitor, one end of which is used to be connected to the drain of the first device under test, and the other end of which is used to be connected to the source of the second device under test, wherein the source of the first device under test is connected to the drain of the second device under test; A first controllable switch, one end of which is connected to one end of the bus capacitor; a load inductance switching module, one end of which is used to be connected to the source of the first device under test, and the other end of which is connected to the other end of the first controllable switch; a second controllable switch, one end of which is connected to the other end of the load inductance switching module, and the other end of which is used to be connected to the source of the second device under test; A first signal enabling module, used to collect the current of the node between the drain of the first device under test and the bus capacitor, the voltage between the gate of the first device under test and the source of the first device under test, and the voltage between the source of the first device under test and the drain of the first device under test; A second signal enabling module, used to collect the current of the node between the drain of the second device under test and the bus capacitor, the voltage between the gate of the second device under test and the source of the second device under test, and the voltage between the source of the second device under test and the drain of the second device under test; A host computer, connected to the first signal enabling module and the second signal enabling module, and used to control the operation of the first signal enabling module and the second signal enabling module to complete the dynamic and static tests; At least one of the first signal enabling module and the second signal enabling module comprises: A high-speed sampling board, used for collecting the current of the node between the drain of the first device under test / the second device under test and the bus capacitor, the voltage between the gate of the first device under test / the second device under test and the source of the first device under test / the second device under test, and the voltage between the source of the first device under test / the second device under test and the drain of the first device under test / the second device under test; A first clamping circuit connected to a first end of the high-speed sampling board; A second clamping circuit connected to the second end of the high-speed sampling board; The isolation circuit has one end connected to the third end of the high-speed sampling board, and the other end is used to output the acquisition signal or receive the test signal input by the host computer.

2. The device according to claim 1, characterized in that The device further includes a first diode, an anode of which is used to be connected to the source of the first device under test, and a cathode of which is used to be connected to the drain of the first device under test.

3. The device according to claim 1, characterized in that The device further includes a second diode, an anode of which is connected to the source of the second device under test, and a cathode of which is connected to the drain of the second device under test.

4. The device according to claim 1, characterized in that The load inductance switching module comprises: At least two inductors connected in series, one end of a first inductor being used to be connected to a source of the first device under test; A third controllable switch corresponding to each of the inductors one by one, each of the inductors being connected to the other end of the first controllable switch through the corresponding third controllable switch.

5. The device according to claim 1, characterized in that The device further comprises a temperature regulating module, which is connected to the host computer and is used to regulate the temperature of the first device under test / the second device under test.

6. A method for performing dynamic and static testing of a semiconductor, characterized in that The method comprises: Get DoE parameters; Select a test point from the DoE parameters in order; Inputting the test point into the first signal enabling module / the second signal enabling module of the device according to any one of claims 1 to 5 to perform the test; receiving a result of the selected test point from the first signal enabling module / the second signal enabling module; Determine whether the selected test point is the last test point; In the case where it is determined that the selected test point is not the last test point, selecting a test point again from the DoE parameters in order until it is determined that the selected test point is the last test point; In the case where it is determined that the selected test point is the last test point, performing a data batch processing operation on all the results, and extracting static characteristic parameters / dynamic characteristic parameters of the device; Output static characteristic parameters / dynamic characteristic parameters of the first device under test / the second device under test.

7. The method according to claim 6, characterized in that The result of receiving the selected test point from the first signal enabling module / the second signal enabling module specifically includes: The results are stored in a unified format.

8. The method according to claim 6, characterized in that The DoE parameter includes at least one of a gate voltage, a test current and a test temperature.

9. A storage medium, characterized in that: The storage medium stores instructions, and the instructions are used to be read by a machine so as to enable the machine to execute the method according to any one of claims 6 to 8.

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