Blood cell analyzer and control system, method, electronic device, and medium thereof

Abstract

The present application discloses a blood cell analyzer and its control system, method, electronic device, and medium. The system includes a host computer and a parallel execution device, wherein the host computer and the parallel execution device are connected by a PCI-E bus. The host computer sends a liquid circuit timing packet to the parallel execution device via the PCI-E bus. After receiving the liquid circuit timing packet, the parallel execution device controls the corresponding peripheral components to perform corresponding actions according to the content of the liquid circuit timing packet. It can be seen that by adopting the above technical solution, on the one hand, the liquid circuit timing packet is processed on the parallel execution device, and the parallel characteristics of the parallel execution device can be utilized, thereby overcoming the disadvantages of the serial mode of the host computer and improving the working efficiency of the system. On the other hand, the use of the PCI-E bus to transmit the liquid circuit timing packet can meet the requirements of high bandwidth and reliability, and the bus has mechanisms such as verification retransmission, addressing routing, and interruption.

Description

Technical Field

[0001] The present application relates to the field of electronic equipment, and in particular to a blood cell analyzer and its control system, method, electronic equipment, and medium. Background Art

[0002] To perform blood analysis in a blood cell analyzer, multiple peripheral components such as motors and solenoid valves need to be scheduled to jointly realize the function of blood cell analysis. When scheduling the control system, it is necessary to fully consider the logical relationship and time relationship between different components. The above relationship is defined as the liquid circuit sequence.

[0003] In the prior art, the control system of the liquid circuit timing is usually implemented by a host computer based on a serial operation architecture. Specifically, the liquid circuit timing is analyzed on the host computer to obtain the corresponding control commands, and scheduling is performed using a time slice polling method. The commands are then sent to the actuator through the serial peripheral interface (SPI) bus, so that the actuator controls the peripheral components to perform corresponding actions according to the received commands.

[0004] Since the host computer in the prior art adopts a serial operation architecture, thread blocking and competition may occur during the scheduling process, which will not guarantee the accuracy of the liquid circuit timing execution time, but will also increase the delay and reduce the work efficiency. In addition, the SPI bus has a slow transmission rate and does not have mechanisms such as verification retransmission, addressing routing, and interruption. For the transmission of large quantities of high-speed data, the bandwidth is difficult to meet and lacks reliability. Summary of the invention

[0005] The purpose of the present application is to provide a blood cell analyzer and its control system, method, electronic equipment, and medium, which are used to overcome the disadvantages of the serial mode of the host computer, improve the working efficiency of the system, and solve the reliability problems caused by insufficient SPI bus bandwidth and the lack of verification retransmission, addressing routing, information interruption and other mechanisms.

[0006] In order to solve the above technical problems, the present application provides a control system for a blood cell analyzer, including a host computer and a parallel execution device connected to the host computer, the host computer and the parallel execution device are connected using a PCI-E bus, the host computer sends a liquid circuit timing package to the parallel execution device through the PCI-E bus, and the parallel execution device controls corresponding peripheral components to perform corresponding actions according to the content of the liquid circuit timing package.

[0007] Preferably, the parallel execution device is a field programmable gate array.

[0008] Preferably, the interrupt pin of the parallel execution device is connected to the host computer through a signal line to send an interrupt signal to the host computer.

[0009] Preferably, the peripheral components include any one or more of a motor, a solenoid valve, an analog-to-digital converter, a liquid pump, and an air pump.

[0010] Preferably, the input end of the analog-to-digital converter is connected to the cell pulse detection module, and the output end of the analog-to-digital converter is connected to the FPGA so as to transmit the converted data to the host computer through the FPGA.

[0011] In order to solve the above technical problems, the present application also provides a blood cell analyzer, including the above control system.

[0012] In order to solve the above technical problems, the present application also provides a control method of a blood cell analyzer. Based on the control system of the blood cell analyzer, the method comprises:

[0013] Receive and store the liquid circuit timing package sent by the host computer through the PCI-E bus;

[0014] After receiving the driving instruction sent by the host computer, the corresponding target fluid circuit timing package is parsed, and the position relationship of each execution time on the fluid circuit timing time axis is determined according to the target fluid circuit timing package;

[0015] Starting a fluid circuit timing state machine to control corresponding peripheral components to perform corresponding actions according to the execution time on the fluid circuit timing time axis;

[0016] When an idle mark is detected on the fluid circuit timing time axis, the next target fluid circuit timing package is obtained, and the next fluid circuit timing state machine is started to control the corresponding peripheral components to perform corresponding actions according to the execution time of the next target fluid circuit timing package on the fluid circuit timing time axis.

[0017] Preferably, when it is detected that the idle mark exists on the liquid path timing time axis, the method further includes:

[0018] A first interrupt signal is sent to the host computer through a signal line.

[0019] Preferably, it also includes:

[0020] When a failure of the peripheral component is detected, a second interrupt signal is sent to the host computer through a signal line.

[0021] Preferably, it also includes:

[0022] The data converted by the analog-to-digital converter is sent to the host computer through the PCI-E bus, and auxiliary information corresponding to the data is sent through the MSI interrupt of the PCI-E bus.

[0023] In order to solve the above technical problems, the present application also provides a control device for a blood cell analyzer. Based on the control system of the blood cell analyzer, the device comprises:

[0024] A receiving unit, used for receiving and storing the liquid circuit timing package sent by the host computer through the PCI-E bus;

[0025] A parsing unit, configured to parse the corresponding target fluid circuit timing package after receiving the driving instruction sent by the host computer, and determine the position relationship of each execution time on the fluid circuit timing time axis according to the target fluid circuit timing package;

[0026] A start-up unit, used for starting a fluid circuit timing state machine to control corresponding peripheral components to perform corresponding actions according to the execution time on the fluid circuit timing time axis;

[0027] The detection unit is used to obtain the next target liquid circuit timing package and trigger the starting unit when an idle mark is detected on the liquid circuit timing time axis, so as to start the next liquid circuit timing state machine to control the corresponding peripheral components to perform corresponding actions according to the execution time of the next target liquid circuit timing package on the liquid circuit timing time axis.

[0028] To solve the above technical problems, the present application also provides an electronic device, including a memory for storing a computer program;

[0029] A processor is used to implement the steps of the control method of the blood cell analyzer when executing the computer program.

[0030] In order to solve the above technical problems, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the control method of the blood cell analyzer as described above are implemented.

[0031] The control system of the blood cell analyzer provided in the present application includes a host computer and a parallel execution device, wherein the host computer and the parallel execution device are connected by a PCI-E bus. The host computer sends the liquid circuit timing package to the parallel execution device via the PCI-E bus, and the parallel execution device controls the corresponding peripheral components to perform corresponding actions according to the content of the liquid circuit timing package after receiving the liquid circuit timing package. It can be seen that, by adopting the above-mentioned technical scheme, on the one hand, the liquid circuit timing package is processed on the parallel execution device, and the parallel characteristics of the parallel execution device can be utilized, thereby overcoming the drawbacks of the serial mode of the host computer and improving the system working efficiency. On the other hand, the PCI-E bus is used to transmit the liquid circuit timing package, which can meet the requirements of high bandwidth and reliability, and the bus has mechanisms such as verification retransmission, addressing routing, and interruption.

[0032] In addition, the data converted by the analog-to-digital converter is sent to the host computer through the PCI-E bus, and the auxiliary information corresponding to the data is sent in combination with the MSI interrupt, which can realize closed-loop control, and the problems of low resource utilization efficiency and poor reliability can be overcome through information feedback. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 A structural diagram of a control system of a blood cell analyzer provided in an embodiment of the present application;

[0035] Figure 2 A timing diagram of interaction between a host computer and FPGA in a blood cell analysis process provided in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of a liquid circuit timing package provided in an embodiment of the present application;

[0037] Figure 4 A flow chart of a control method for a blood cell analyzer provided in an embodiment of the present application;

[0038] Figure 5 A structural diagram of a control device of a blood cell analyzer provided in an embodiment of the present application;

[0039] Figure 6 A structural diagram of an electronic device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0041] The core of this application is to provide a blood cell analyzer and its control system, method, electronic equipment, and medium.

[0042] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0043] Figure 1This is a structural diagram of a control system of a blood cell analyzer provided in an embodiment of the present application. Figure 1 As shown, the system includes a host computer 10 and a parallel execution device 11 connected to the host computer 10. The host computer 10 and the parallel execution device 11 are connected using a PCI-E (PCI-Express) bus. The host computer 10 sends a liquid circuit timing packet to the parallel execution device 11 through the PCI-E bus, and the parallel execution device 11 controls corresponding peripheral components to perform corresponding actions according to the content of the liquid circuit timing packet.

[0044] The host computer is a device that runs in a serial operation architecture, so after the liquid circuit timing analysis, it can only send the corresponding commands to the execution device in a serial manner, so for the execution device, it is also impossible to perform parallel processing in a parallel processing manner. In this embodiment, the parallel execution device can be a field programmable gate array (FPGA), and the parallel execution device can process multiple liquid circuit timing packets in parallel at the same time. In a specific implementation, the host computer no longer parses the liquid circuit timing packet, but directly sends the liquid circuit timing packet to the parallel execution device, which parses the corresponding content and controls the corresponding peripheral components to perform corresponding actions. Since the host computer only needs to send the liquid circuit timing packet to the parallel execution device, which is controlled accordingly, the disadvantages of the serial operation architecture of the host computer can be overcome.

[0045] Among them, the host computer and parallel execution device are connected using the PCI-E bus. Compared with the SPI bus, PCI-E is a universal bus specification with the characteristics of high-speed transmission, full-duplex, check retransmission, addressing routing, interrupt triggering, etc., which can establish an efficient and stable data transmission channel between the host computer and FPGA.

[0046] Figure 2 The following is a timing diagram of the interaction between a host computer and an FPGA in the blood cell analysis process provided in an embodiment of the present application. The host computer and the FPGA in the blood cell analysis process are implemented by the following method:

[0047] S11: The host computer packages the fluid circuit timing package.

[0048] S12: The host computer sends the packaged liquid circuit timing package to the FPGA through the PCI-E bus.

[0049] S13: FPGA receives the liquid circuit timing package sent by the host computer and stores it.

[0050] S14: The host computer sends a driving instruction to the FPGA.

[0051] S15: FPGA parses the corresponding target fluid circuit timing package, and determines the positional relationship of each execution time on the fluid circuit timing time axis according to the target fluid circuit timing package, and starts a fluid circuit timing state machine to control the corresponding peripheral components to perform corresponding actions according to the execution time on the fluid circuit timing time axis.

[0052] S16: FPGA detects whether there is an idle mark on the liquid circuit timing timeline. If so, it obtains the next target liquid circuit timing package and starts the next liquid circuit timing state machine to control the corresponding peripheral components to perform corresponding actions according to the execution time of the next target liquid circuit timing package on the liquid circuit timing timeline.

[0053] In a specific implementation, the host computer can send multiple liquid circuit timing packages to the FPGA, or it can send only one at a time. If it is the former, then the start of each liquid circuit timing package requires the drive instruction of the host computer. If it is the latter, when the FPGA determines that there is an idle mark on the liquid circuit timing time axis, it is necessary to send a request to the host computer to obtain the next liquid circuit timing package. After receiving the request, the host computer will send the corresponding liquid circuit timing package to the FPGA. Then, after receiving this liquid circuit timing package, the FPGA stores it and executes according to step S15 after receiving the drive instruction. In addition, in this embodiment, the order of the liquid circuit timing packages obtained by the FPGA can be pre-set. It can be understood that the execution steps of the next target liquid circuit timing package in step S16 are actually the same as S15, but they are implemented on different state machines. In addition, in a specific implementation, before starting the next state machine, it is possible to first determine whether the current liquid path timing axis supports the start of the next state machine. If it does, it is started; if it does not, it is not started. In a specific implementation, the judgment can be made after determining that there is an idle mark on the liquid path timing axis. If it does, the next target liquid path timing package is obtained. In this way, the problem of execution confusion among multiple state machines can be prevented.

[0054] Figure 3 Schematic diagram of a liquid circuit timing package provided in an embodiment of the present application. Figure 3 As shown, a liquid circuit timing packet includes header information and n commands. The header information includes the packet sequence number, packet length and liquid circuit timing number, where the packet sequence number is the identifier of each data packet, the packet length indicates the number of commands in the current data packet, and the liquid circuit timing number is the identifier of the liquid circuit timing. Each command includes a command code, execution time and control information, where the command code is the unique identifier of each system component, the execution time indicates the time when a certain component runs to determine the logical relationship and time relationship between different components, and the control information provides the operation mode of a certain component.

[0055] When the FPGA receives the drive instruction from the host computer, it will obtain the corresponding target fluid circuit timing packet, and then parse the data packet, for example, how fast the motor is running, and according to Figure 3 The format of the data packet in the command is determined, the positional relationship of the execution time in each command on the liquid circuit timing time axis is determined, and a liquid circuit timing state machine is started to control the corresponding peripheral components to perform corresponding actions according to the execution time on the liquid circuit timing time axis. As a preferred embodiment, the peripheral components include any one or more of a motor, a solenoid valve, an analog-to-digital converter, a liquid pump, and an air pump. It can be understood that the above components are only a part and are not limited to the above. In a specific implementation, a target liquid circuit timing package may include the control content of one or more peripheral components. Taking a motor, a solenoid valve, and an analog-to-digital converter as an example, a target liquid circuit timing package may include control content for the motor, control content for the solenoid valve, and control content for the analog-to-digital converter.

[0056] The control system of the blood cell analyzer provided in this embodiment includes a host computer and a parallel execution device, wherein the host computer and the parallel execution device are connected by a PCI-E bus. The host computer sends the liquid circuit timing packet to the parallel execution device via the PCI-E bus, and the parallel execution device controls the corresponding peripheral components to perform corresponding actions according to the content of the liquid circuit timing packet after receiving the liquid circuit timing packet. It can be seen that by adopting the above technical solution, on the one hand, the liquid circuit timing packet is processed on the parallel execution device, and the parallel characteristics of the parallel execution device can be utilized, thereby overcoming the disadvantages of the serial mode of the host computer and improving the system working efficiency. On the other hand, the PCI-E bus is used to transmit the liquid circuit timing packet, which can meet the requirements of high bandwidth and reliability, and the bus has mechanisms such as verification retransmission, addressing routing, and interruption.

[0057] like Figure 1 As shown, based on the above embodiment, the interrupt pin of the parallel execution device 11 is connected to the host computer 10 through a signal line to send an interrupt signal to the host computer.

[0058] It is understandable that the type of interrupt signal here is not limited, and can be a general purpose input and output (GPIO) interrupt signal. In a specific implementation, the scenario of sending an interrupt signal can be: when the FPGA detects an idle mark on the liquid circuit timing time axis, or when the FPGA detects a peripheral component failure.

[0059] In this embodiment, the host computer and the FPGA can send interrupt signals through the signal line, so that the interrupt processing effect can be achieved, the hardware overhead is small, and the resource utilization efficiency is high.

[0060] Based on the above embodiment, the input end of the analog-to-digital converter is connected to the cell pulse detection module of the blood cell analyzer, and the output end of the analog-to-digital converter is connected to the FPGA so as to transmit the converted data to the host computer through the FPGA.

[0061] In a specific implementation, when the FPGA starts a liquid circuit timing state machine to control the corresponding peripheral components to perform corresponding actions according to the execution time on the liquid circuit timing time axis, the analog-to-digital converter performs batch data acquisition. After the FPGA obtains the acquisition results of the analog-to-digital converter, it can be transmitted to the host computer via the PCI-E bus, and the MSI (full name is Message Signaled Interrupt. MSI appears in the specifications of PCI 2.2 and PCI-E, and is an internal interrupt signal mechanism. Traditional interrupts have dedicated interrupt PINs. When an interrupt signal is generated, the interrupt PIN level changes, generally pulled low) interruption of the PCI-E bus provides acquisition auxiliary information so that the host computer can confirm the source of the data and implement multiple caches to improve storage reliability. The auxiliary information here may include acquisition objects, data volume, and command codes. In addition, during the execution of the liquid circuit timing, some components may fail. At this time, the FPGA can inform the host computer through the GPIO interrupt to achieve closed-loop control to improve the robustness of the system. For example, motors, driver chips, etc. have overcurrent, overheating and other faults.

[0062] In this embodiment, the cell pulse data can be collected through the analog-to-digital converter, and the host computer can obtain the analysis results of the blood cells based on these data. In addition, PFGA sends auxiliary information corresponding to the data through the MSI interrupt signal mechanism of the PCI-E bus, performs information feedback of the cell analysis process, and can realize closed-loop control.

[0063] In the above embodiments, the control system of the blood cell analyzer is described in detail. The present application also provides a blood cell analyzer including the system, which of course includes not only the system but also an analyzer body.

[0064] Since the control system of the blood cell analyzer has been described in detail in the above embodiments, it will not be described in detail in this embodiment.

[0065] The blood cell analyzer provided in this embodiment has a control system, including a host computer and a parallel execution device, wherein the host computer and the parallel execution device are connected by a PCI-E bus. The host computer sends the liquid circuit timing packet to the parallel execution device via the PCI-E bus, and the parallel execution device controls the corresponding peripheral components to perform corresponding actions according to the content of the liquid circuit timing packet after receiving the liquid circuit timing packet. It can be seen that by adopting the above technical solution, on the one hand, the liquid circuit timing packet is processed on the parallel execution device, and the parallel characteristics of the parallel execution device can be utilized, thereby overcoming the disadvantages of the serial mode of the host computer and improving the system working efficiency. On the other hand, the PCI-E bus is used to transmit the liquid circuit timing packet, which can meet the requirements of high bandwidth and reliability, and the bus has mechanisms such as verification retransmission, addressing routing, and interruption.

[0066] The present application also provides a control method for a blood cell analyzer, based on the control system of the blood cell analyzer provided in the above embodiment. Figure 4 A flow chart of a control method of a blood cell analyzer provided in an embodiment of the present application, such as Figure 4 As shown, the method includes:

[0067] S20: receiving the liquid circuit timing package sent by the host computer through the PCI-E bus and storing it.

[0068] S21: After receiving the driving instruction sent by the host computer, the corresponding target fluid circuit timing package is parsed, and the position relationship of each execution time on the fluid circuit timing time axis is determined according to the target fluid circuit timing package.

[0069] S22: Start a fluid circuit timing state machine to control corresponding peripheral components to perform corresponding actions according to the execution time on the fluid circuit timing time axis.

[0070] S23: When an idle mark is detected on the liquid circuit timing time axis, the next target liquid circuit timing package is obtained, and the next liquid circuit timing state machine is started to control the corresponding peripheral components to perform corresponding actions according to the execution time of the next target liquid circuit timing package on the liquid circuit timing time axis.

[0071] As a preferred implementation, when it is detected that there is an idle mark on the fluid path sequence time axis, the method further includes: sending a first interrupt signal to a host computer through a signal line.

[0072] As a preferred implementation, it also includes:

[0073] When a peripheral component failure is detected, a second interrupt signal is sent to the host computer through the signal line.

[0074] As a preferred implementation, it also includes:

[0075] The data converted by the analog-to-digital converter is sent to the host computer through the PCI-E bus, and the auxiliary information corresponding to the data is sent through the MSI interrupt of the PCI-E bus.

[0076] The above method is described with the parallel execution device as the execution subject. Since the embodiment of the control system of the blood cell analyzer is described in detail above, it will not be repeated in the control method of the blood cell analyzer.

[0077] In the control method of the blood cell analyzer provided in this embodiment, the host computer sends the liquid path timing package to the parallel execution device through the PCI-E bus. After receiving the liquid path timing package, the parallel execution device controls the corresponding peripheral components to perform corresponding actions according to the content of the liquid path timing package. It can be seen that by adopting the above technical solution, on the one hand, the liquid path timing package is processed on the parallel execution device, and the parallel characteristics of the parallel execution device can be utilized, thereby overcoming the disadvantages of the serial mode of the host computer and improving the system work efficiency. On the other hand, the use of the PCI-E bus to transmit the liquid path timing package can meet the requirements of high bandwidth and reliability, and the bus has mechanisms such as verification retransmission, addressing routing, and interruption.

[0078] In the above embodiments, the control method of the blood cell analyzer is described in detail. Based on the perspective of the functional modules, the present application also provides corresponding embodiments of the control device of the blood cell analyzer. Figure 5 A structural diagram of a control device of a blood cell analyzer provided in an embodiment of the present application, such as Figure 5 As shown, the embodiment of the present application also provides a control device for a blood cell analyzer, corresponding to the above method embodiment, the device includes:

[0079] The receiving unit 20 is used to receive and store the liquid circuit timing package sent by the host computer through the PCI-E bus;

[0080] The parsing unit 21 is used to parse the corresponding target fluid circuit timing package after receiving the driving instruction sent by the host computer, and determine the position relationship of each execution time on the fluid circuit timing time axis according to the target fluid circuit timing package;

[0081] A start unit 22, used to start a fluid circuit timing state machine to control corresponding peripheral components to perform corresponding actions according to the execution time on the fluid circuit timing time axis;

[0082] The detection unit 23 is used to obtain the next target liquid circuit timing package and trigger the starting unit 22 when an idle mark is detected on the liquid circuit timing time axis, so as to start the next liquid circuit timing state machine to control the corresponding peripheral components to perform corresponding actions according to the execution time of the next target liquid circuit timing package on the liquid circuit timing time axis.

[0083] The control device of the blood cell analyzer provided in this embodiment, the host computer sends the liquid circuit timing package to the receiving unit through the PCI-E bus, the parsing unit determines the positional relationship of each execution moment on the liquid circuit timing time axis according to the content of the liquid circuit timing package after receiving the liquid circuit timing package, and the starting unit starts a liquid circuit timing state machine to control the corresponding peripheral components to perform corresponding actions according to the execution moment on the liquid circuit timing time axis. It can be seen that by adopting the above technical solution, on the one hand, the liquid circuit timing package is processed on the parallel execution device, and the parallel characteristics of the parallel execution device can be utilized, thereby overcoming the disadvantages of the serial mode of the host computer and improving the system work efficiency. On the other hand, the use of the PCI-E bus to transmit the liquid circuit timing package can meet the requirements of high bandwidth and reliability, and the bus has mechanisms such as verification retransmission, addressing routing, and interruption.

[0084] Figure 6 A structural diagram of an electronic device provided in another embodiment of the present application, such as Figure 6 As shown, from the perspective of hardware entity, the present application also provides an electronic device, including a memory 30 for storing a computer program;

[0085] The processor 31 is used to implement the steps of the control method of the blood cell analyzer as described above when executing the computer program.

[0086] The electronic device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer.

[0087] Among them, the processor 31 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 31 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 31 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 31 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 31 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0088] The memory 30 may include one or more computer-readable storage media, which may be non-transitory. The memory 30 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 30 is at least used to store the following computer program 301, wherein, after the computer program is loaded and executed by the processor 31, the relevant steps of the control method of the blood cell analyzer disclosed in any of the aforementioned embodiments can be implemented. In addition, the resources stored in the memory 30 may also include an operating system 302 and data 303, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 302 may include Windows, Unix, Linux, etc. Data 303 may include, but is not limited to, data in a liquid circuit timing package, etc.

[0089] In some embodiments, the electronic device may further include a display screen 32 , an input / output interface 33 , a communication interface 34 , a power source 35 , and a communication bus 36 .

[0090] Those skilled in the art will understand that Figure 6 The structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure.

[0091] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps recorded in the above method embodiment are implemented.

[0092] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0093] The above is a detailed introduction to the blood cell analyzer and its control system, method, electronic device, and medium provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in the technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0094] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A control system for a blood cell analyzer, characterized in that: It includes a host computer and a parallel execution device connected to the host computer, wherein the host computer and the parallel execution device are connected by a PCI-E bus, the host computer sends a fluid circuit timing packet to the parallel execution device through the PCI-E bus, and the parallel execution device controls corresponding peripheral components to perform corresponding actions according to the content of the fluid circuit timing packet; The parallel execution device is specifically used for: Receive and store the liquid circuit timing package sent by the host computer through the PCI-E bus; After receiving the driving instruction sent by the host computer, the corresponding target fluid circuit timing package is parsed, and the position relationship of each execution time on the fluid circuit timing time axis is determined according to the target fluid circuit timing package; Starting a fluid circuit timing state machine to control corresponding peripheral components to perform corresponding actions according to the execution time on the fluid circuit timing time axis; When an idle mark is detected on the fluid circuit timing time axis, a first interrupt signal is sent to the host computer through a signal line to obtain a next target fluid circuit timing package, and start a next fluid circuit timing state machine to control corresponding peripheral components to perform corresponding actions according to the execution time of the next target fluid circuit timing package on the fluid circuit timing time axis; The liquid circuit timing packet includes header information and n commands; the header information includes a packet sequence number, a packet length and a liquid circuit timing number, wherein the packet sequence number is an identifier of each data packet, the packet length indicates the number of commands in the current data packet, and the liquid circuit timing number is an identifier of the liquid circuit timing; each of the commands includes a command code, an execution time and control information, wherein the command code is a unique identifier of each peripheral component of the system, the execution time indicates the time when each peripheral component runs to determine the logical relationship and time relationship between different peripheral components, and the control information provides the operating mode of the peripheral components.

2. The control system of the blood cell analyzer according to claim 1, characterized in that: The parallel execution device is a field programmable gate array.

3. The control system of the blood cell analyzer according to claim 2, characterized in that: The interrupt pin of the parallel execution device is connected to the host computer through a signal line to send an interrupt signal to the host computer.

4. The control system of the blood cell analyzer according to claim 1, characterized in that: The peripheral components include any one or more of a motor, a solenoid valve, an analog-to-digital converter, a liquid pump, and an air pump.

5. The control system of the blood cell analyzer according to claim 4, characterized in that: The input end of the analog-to-digital converter is connected to the cell pulse detection module, and the output end of the analog-to-digital converter is connected to the FPGA so as to transmit the converted data to the host computer through the FPGA.

6. A blood cell analyzer, characterized in that: A control system comprising any one of claims 1 to 5.

7. A control method for a blood cell analyzer, characterized in that: Based on the control system of the blood cell analyzer according to any one of claims 1 to 5, the method comprises: Receive and store the liquid circuit timing package sent by the host computer through the PCI-E bus; After receiving the driving instruction sent by the host computer, the corresponding target fluid circuit timing package is parsed, and the position relationship of each execution time on the fluid circuit timing time axis is determined according to the target fluid circuit timing package; Starting a fluid circuit timing state machine to control corresponding peripheral components to perform corresponding actions according to the execution time on the fluid circuit timing time axis; When an idle mark is detected on the fluid circuit timing time axis, a next target fluid circuit timing package is obtained, and a next fluid circuit timing state machine is started to control corresponding peripheral components to perform corresponding actions according to the execution time of the next target fluid circuit timing package on the fluid circuit timing time axis; When it is detected that the idle mark exists on the liquid path timing time axis, the method further includes: Sending a first interrupt signal to the host computer via a signal line; The liquid circuit timing packet includes header information and n commands; the header information includes a packet sequence number, a packet length and a liquid circuit timing number, wherein the packet sequence number is an identifier of each data packet, the packet length indicates the number of commands in the current data packet, and the liquid circuit timing number is an identifier of the liquid circuit timing; each of the commands includes a command code, an execution time and control information, wherein the command code is a unique identifier of each peripheral component of the system, the execution time indicates the time when each peripheral component runs to determine the logical relationship and time relationship between different peripheral components, and the control information provides the operating mode of the peripheral components.

8. The control method of the blood cell analyzer according to claim 7, characterized in that: Also includes: When a failure of the peripheral component is detected, a second interrupt signal is sent to the host computer through a signal line.

9. The control method of the blood cell analyzer according to claim 7, characterized in that: Also includes: The data converted by the analog-to-digital converter is sent to the host computer through the PCI-E bus, and auxiliary information corresponding to the data is sent through the MSI interrupt of the PCI-E bus.

10. A control device for a blood cell analyzer, characterized in that: A control system for a blood cell analyzer according to any one of claims 1 to 5, comprising: A receiving unit, used for receiving and storing the liquid circuit timing package sent by the host computer through the PCI-E bus; A parsing unit, configured to parse the corresponding target fluid circuit timing package after receiving the driving instruction sent by the host computer, and determine the position relationship of each execution time on the fluid circuit timing time axis according to the target fluid circuit timing package; A start-up unit, used for starting a fluid circuit timing state machine to control corresponding peripheral components to perform corresponding actions according to the execution time on the fluid circuit timing time axis; a detection unit, configured to, when detecting the presence of an idle mark on the fluid circuit timing time axis, obtain a next target fluid circuit timing package and trigger the start unit so as to start the next fluid circuit timing state machine to control the corresponding peripheral components to perform corresponding actions according to the execution time of the next target fluid circuit timing package on the fluid circuit timing time axis; The control device of the blood cell analyzer is further used to send a first interrupt signal to the host computer through a signal line when detecting the presence of the idle mark on the liquid circuit timing time axis; The liquid circuit timing packet includes header information and n commands; the header information includes a packet sequence number, a packet length and a liquid circuit timing number, wherein the packet sequence number is an identifier of each data packet, the packet length indicates the number of commands in the current data packet, and the liquid circuit timing number is an identifier of the liquid circuit timing; each of the commands includes a command code, an execution time and control information, wherein the command code is a unique identifier of each peripheral component of the system, the execution time indicates the time when each peripheral component runs to determine the logical relationship and time relationship between different peripheral components, and the control information provides the operating mode of the peripheral components.

11. An electronic device, characterized in that: comprising a memory for storing a computer program; A processor, configured to implement the steps of the method for controlling a blood cell analyzer as claimed in any one of claims 7 to 9 when executing the computer program.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the control method of the blood cell analyzer according to any one of claims 7 to 9 are implemented.

Images