Source driver and display device including the same

Abstract

A source driver and a display device including the source driver are disclosed. The source driver includes a gamma voltage generator, a digital-to-analog converter, an output buffer unit, and a chopping controller, wherein the gamma voltage generator generates gamma voltages having voltage levels different from each other, the digital-to-analog converter uses the gamma voltages to generate data voltages corresponding to grayscale values, the output buffer unit outputs the data voltages, and the chopping controller generates a chopping control signal and provides the chopping control signal to the output buffer unit. The output buffer unit includes an amplifier connected to an output terminal of the digital-to-analog converter, and a chopping circuit that periodically changes the polarity of an offset of the amplifier in response to the chopping control signal. The chopping controller changes the slew rate of the chopping control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0026473, filed on Mar. 7, 2019, and Korean Patent Application No. 10-2019-0141192, filed on Nov. 6, 2019, the contents of which are hereby incorporated by reference in their entirety. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a source driver and a display device including the source driver. Background Art

[0004] The display device includes a display panel and a driver. The display panel includes scan lines, data lines and pixels. The driver includes a scan driver and a source driver, wherein the scan driver sequentially provides scan signals to the scan lines, and the source driver provides data signals to the data lines. Each of the pixels can emit light with a desired brightness corresponding to the data signal provided by the corresponding data line in response to the scan signal provided by the corresponding scan line.

[0005] The source driver generates a data signal corresponding to the grayscale value of the image data, and provides the data signal to the data line through the output buffer. Because the amplifier included in (or configured to) the output buffer has an offset, the quality of the image (e.g., the image displayed corresponding to the data signal) may be reduced or degraded due to the offset. Therefore, the source driver may include a chopping circuit (or chopping function) that periodically changes the polarity of the offset of the amplifier.

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] The operation of the chopping circuit may induce noise in the data line, and the noise may affect other configurations, elements and / or components adjacent to the data line.

[0008] One or more exemplary embodiments of the present disclosure relate to a source driver capable of reducing noise generated in a data line and a display device including the same.

[0009] According to an embodiment of the present disclosure, a source driver includes a gamma voltage generator, a digital-to-analog converter, an output buffer unit, and a chopping controller, wherein the gamma voltage generator is configured to generate gamma voltages having voltage levels different from each other, the digital-to-analog converter is configured to use the gamma voltages to generate data voltages corresponding to grayscale values, the output buffer unit is configured to output the data voltages, and the chopping controller is configured to generate a chopping control signal and provide the chopping control signal to the output buffer unit. The output buffer unit includes an amplifier connected to an output terminal of the digital-to-analog converter, and a chopping circuit configured to periodically change the polarity of an offset of the amplifier in response to the chopping control signal. The chopping controller is configured to change the slew rate of the chopping control signal.

[0010] In an embodiment, the chopping circuit may include a first switch, a second switch, a third switch, and a fourth switch, wherein the first switch is connected between the input node and the first input terminal of the amplifier, the second switch is connected between the input node and the second input terminal of the amplifier, the third switch is connected between the first input terminal of the amplifier and the output terminal of the amplifier, and the fourth switch is connected between the second input terminal of the amplifier and the output terminal of the amplifier. The first to fourth switches may be configured to operate in response to a chopping control signal.

[0011] In an embodiment, a parasitic capacitor may be formed between an output node connected to an output terminal of the amplifier and a control line for transmitting the chopping control signal to the third switch.

[0012] In an embodiment, the chopping controller may include a logic control circuit, a level shifter, and a buffer circuit, wherein the logic control circuit is configured to generate a first control signal including a pulse, the level shifter is configured to generate a second control signal by shifting up the level of the first control signal, and the buffer circuit is configured to output the second control signal as a chopping control signal and change the buffer size.

[0013] In an implementation, the slew rate may correspond to a rate at which the chopping control signal follows the second control signal.

[0014] In an embodiment, the buffer circuit may include sub-buffers and sub-switches, wherein the sub-buffers are connected in parallel to the chopping circuit, and the sub-switches respectively connect the sub-buffers to the output terminals of the level shifter. At least one of the sub-switches may be configured to be turned on in response to a selection signal.

[0015] In an embodiment, the sub-buffers may have the same buffer size as each other.

[0016] In an embodiment, the sub-buffers may have different buffer sizes from each other.

[0017] In an implementation, the slew rate of the chopping control signal may decrease as the buffer size of the buffer circuit decreases.

[0018] In an embodiment, the chopping controller may include a logic control circuit, a level shifter, a buffer circuit, and an analog filter, wherein the logic control circuit is configured to generate a first control signal in the form of a square wave, the level shifter is configured to generate a second control signal by shifting up the level of the first control signal, the buffer circuit is configured to output the second control signal as a chopping control signal, and the analog filter is connected between an output terminal of the buffer circuit and the chopping circuit to variably filter a high-frequency component of the chopping control signal.

[0019] In an embodiment, the analog filter may include a variable resistor connected between the buffer circuit and the chopping circuit, and a variable capacitor connected between the chopping circuit and the reference voltage line.

[0020] In an embodiment, the chopping controller may include a logic control circuit, a level shifter, a buffer circuit, and a delay element, wherein the logic control circuit is configured to generate a first control signal in the form of a square wave, the level shifter is configured to generate a second control signal by shifting up the level of the first control signal, the buffer circuit is configured to output the second control signal as a chopping control signal, and the delay element is connected between the output terminal of the buffer circuit and the chopping circuit.

[0021] In an embodiment, the delay element may include a resistor connected between the buffer circuit and the chopping circuit, and a switch and a diode connected in parallel with the resistor, while the switch and the diode are connected in series with each other.

[0022] According to an embodiment of the present disclosure, a display device includes a display panel and a source driver, wherein the display panel includes a data line and a pixel connected to the data line, and the source driver is configured to provide a data voltage to the data line, and the source driver includes a digital-to-analog converter, an output buffer unit, and a chopping controller, wherein the digital-to-analog converter is configured to generate a data voltage, the output buffer unit is configured to output the data voltage to the data line, and the chopping controller is configured to generate a chopping control signal and provide the chopping control signal to the output buffer unit. The output buffer unit includes an amplifier and a chopping circuit, wherein the amplifier is connected between the digital-to-analog converter and the data line, and the chopping circuit is configured to periodically change the polarity of the offset of the amplifier in response to the chopping control signal, and the chopping controller is configured to change the slew rate of the chopping control signal.

[0023] In an embodiment, the chopping circuit may include a first switch, a second switch, a third switch, and a fourth switch, wherein the first switch is connected between the input node and the first input terminal of the amplifier, the second switch is connected between the input node and the second input terminal of the amplifier, the third switch is connected between the first input terminal of the amplifier and the output terminal of the amplifier, and the fourth switch is connected between the second input terminal of the amplifier and the output terminal of the amplifier. The first to fourth switches may be configured to operate in response to a chopping control signal.

[0024] In an embodiment, the chopping controller may include a logic control circuit, a level shifter, and a buffer circuit, wherein the logic control circuit is configured to generate a first control signal including a pulse, the level shifter is configured to generate a second control signal by shifting up the level of the first control signal, and the buffer circuit is configured to output the second control signal as a chopping control signal and change the buffer size.

[0025] In an embodiment, the display device may further include a touch sensing unit including a touch electrode, and a buffer size of the buffer circuit may be controlled according to noise of the touch electrode caused by the chopping control signal.

[0026] In an implementation, the buffer size of the buffer circuit may decrease as the noise increases.

[0027] In an embodiment, the buffer size of the buffer circuit may be set to be maximum within a range where noise does not occur.

[0028] In an embodiment, the buffer circuit may include sub-buffers and sub-switches, wherein the sub-buffers are connected in parallel to the chopping circuit, and the sub-switches respectively connect the sub-buffers to the output terminals of the level shifter. At least one of the sub-switches may be configured to be turned on in response to a selection signal.

[0029] According to one or more embodiments of the present disclosure, a source driver and a display device including the source driver can reduce noise generated in a data line and / or other configurations, elements and / or components adjacent to the data line by changing the slew rate of a chopping control signal of a chopping circuit that controls a change (e.g., periodically) in the polarity of an offset of a source amplifier (e.g., a source amplifier that outputs a data signal). BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present invention will become more apparent to those skilled in the art through the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0031] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0032] Figure 2 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device;

[0033] Figure 3 It is shown that the Figure 1 A block diagram of an example of a source driver in a display device;

[0034] Figure 4 It is shown that the Figure 3 A circuit diagram of an example of an output buffer in a source driver;

[0035] Figure 5 It is shown Figure 4 A circuit diagram of an example of an output buffer;

[0036] Figure 6 It is shown Figure 5 A waveform diagram of an example of a signal measured in an output buffer of;

[0037] Figure 7 It is shown that the Figure 3 A block diagram of an example of a chopper controller in a source driver of;

[0038] Figure 8 It is shown that the Figure 7 A circuit diagram of an example of a buffer circuit in a chopper controller;

[0039] Fig. 9 It is shown from Figure 8 A waveform diagram of an example of a chopping control signal output by a buffer;

[0040] Fig.10 It is shown that the Figure 3 A block diagram of another example of a chopper controller in a source driver of;

[0041] Fig.11 It is shown that the Figure 3 A block diagram of another example of a chopper controller in a source driver of;

[0042] Fig.12 is a view showing a display device according to another embodiment of the present disclosure;

[0043] Fig.13 It is shown Fig.12 A cross-sectional view of an example of a display device;

[0044] Fig.14 It is shown that the Fig.13 A plan view of an example of a touch sensing layer in a display device of FIG.

[0045] Fig.15 It is shown Fig.13 A cross-sectional view of an example of a display device; and

[0046] Fig.16 It is shown by Fig.14 FIG. 1 is a view of an example of a sense signal measured by a touch sensing layer. DETAILED DESCRIPTION

[0047] Hereinafter, exemplary embodiments will be described in more detail with reference to the accompanying drawings, wherein the same reference numerals represent the same elements throughout. However, the present disclosure can be implemented in various forms and should not be construed as being limited only to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects and features of the present disclosure will be fully communicated to those skilled in the art. Accordingly, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, the same reference numerals indicate the same elements throughout the drawings and written descriptions, and therefore their descriptions may not be repeated.

[0048] In the accompanying drawings, for the sake of clarity, the relative sizes of elements, layers and regions can be enlarged and / or simplified. Spatial relative words such as "beneath", "below", "lower", "under", "above", "upper" etc. can be used in this article for the convenience of explanation to describe the relationship between an element or feature and another element or feature as shown in the figure. It should be understood that, in addition to the orientation shown in the accompanying drawings, spatial relative words are intended to also include different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as "below", "beneath" or "under" of other elements or features will be subsequently oriented to "above" of other elements or features. Therefore, the exemplary wording "below" can include both the orientations of the upper and lower sides. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0049] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part without departing from the spirit and scope of the present disclosure.

[0050] It should be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer may be directly on, directly connected to, or coupled to the other element or layer, or intervening elements or layers may be present. Additionally, it should be understood that when an element or layer is referred to as being “between” two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may be present.

[0051] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present disclosure. Unless otherwise clearly indicated in the context, the singular forms "a" and "an" as used herein are also intended to include plural forms. It should also be understood that when the terms "comprise", "comprising", "include", "including", "has", "have" and "having" are used in this specification, the existence of the stated features, integers, steps, operations, elements and / or parts is indicated, but the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or their clusters is not excluded. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. The expression "at least one" after a column of elements modifies the entire column of elements, rather than the individual elements in the column.

[0052] As used herein, the terms "substantially", "about", and similar terms are used as approximate terms rather than exact terms, and are intended to take into account the inherent deviations of measurements or calculations that one of ordinary skill in the art will recognize. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered to be synonymous with the terms "utilize," "utilizing," and "utilized," respectively. In addition, the term "exemplary" is intended to indicate an example or illustration.

[0053] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as they have in the context of the relevant technology and / or specification, and should not be interpreted in an idealized or overly formal sense.

[0054] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0055] Reference Figure 1 , the display device 100 may include a display unit (e.g., or a display panel) 110, a scan driver (e.g., or a gate driver) 120, a source driver (e.g., or a data driver) 130, and a timing controller 140. In addition, in some embodiments, the display device 100 may further include a light emitting driver (e.g., or an emission driver) 150.

[0056] The display unit 110 may include scan lines (e.g., or gate lines) SL1 to SLn, data lines DL1 to DLm, light emission control lines EL1 to ELn, and pixels PXL, where n is a positive integer and m is a positive integer. The pixels PXL may be arranged at (e.g., in or on) a region (e.g., a pixel region) divided by the scan lines SL1 to SLn, the data lines DL1 to DLm, and the light emission control lines EL1 to ELn. For example, in some embodiments, each of the data lines DL1 to DLm may extend in a first direction (e.g., a column direction), and each of the scan lines SL1 to SLn and the light emission control lines EL1 to ELn may extend in a second direction (e.g., a row direction) intersecting the first direction.

[0057] Each of the pixels PXL may be connected to at least one of the scan lines SL1 to SLn, one of the data lines DL1 to DLm, and at least one of the light emission control lines EL1 to ELn. For example, a pixel arranged at the i-th row and the j-th column among the pixels PXL may be connected to the i-th scan line SLi, the previous scan line SLi-1 adjacent to the i-th scan line SLi, the j-th data line DLj, and the i-th light emission control line ELi, where i and j are each a positive integer. Hereinafter, for the convenience of description, as a representative example of each of the pixels PXL, a pixel arranged at the i-th row and the j-th column may be referred to as a pixel PXL.

[0058] The pixel PXL can be initialized in response to a scan signal (e.g., a previous scan signal or a previous gate signal) provided through a previous scan line SLi-1 (e.g., a scan signal or a gate signal provided at a previous time point), can store or record a data signal provided through the data line DLj in response to a scan signal (e.g., a current scan signal or a current gate signal) provided through the scan line SLi (e.g., a scan signal or a gate signal provided at a current time point), and can emit light with a brightness corresponding to the stored data signal (e.g., or emit light having the brightness) in response to a light emitting control signal provided through the light emitting control line ELi.

[0059] The display unit 110 may be provided with a first power supply voltage VDD and a second power supply voltage VSS. The first power supply voltage VDD and the second power supply voltage VSS may be suitable voltages for the operation of the pixel PXL, and the first power supply voltage VDD may have a voltage level greater than (or higher than) the second power supply voltage VSS. In addition, the display unit 110 may be provided with an initialization power supply voltage Vint. The first power supply voltage VDD, the second power supply voltage VSS, and the initialization power supply voltage Vint may be provided to the display unit 110 from a separate power supply.

[0060] The scan driver 120 may generate a scan signal based on the scan control signal SCS, and may provide (e.g., may sequentially provide) the scan signal to the scan lines SL1 to SLn. The scan control signal SCS may include a start signal, one or more clock signals, and / or the like, and may be provided from the timing controller 140. For example, the scan driver 120 may include a shift register (or stage), wherein the shift register (or stage) generates and outputs (e.g., sequentially generates and outputs) a scan signal (e.g., a pulse type or a scan signal having a pulse type) corresponding to a start signal (e.g., a pulse type or a start signal having a pulse type) using one or more clock signals.

[0061] The light emitting driver 150 may generate a light emitting control signal according to (e.g., or based on) the light emitting driving control signal ECS, and may provide (e.g., sequentially provide or simultaneously provide) the light emitting control signal to the light emitting control lines EL1 to ELn. The light emitting driving control signal ECS may include a light emitting start signal, a light emitting clock signal, and / or the like, and may be provided from the timing controller 140. For example, the light emitting driver 150 may include a shift register, wherein the shift register generates and outputs (e.g., sequentially generates and outputs) a light emitting control signal (e.g., a light emitting control signal of a pulse type or a light emitting control signal of a pulse type) corresponding to a light emitting start signal (e.g., a light emitting start signal of a pulse type or a light emitting start signal of a pulse type) using a light emitting clock signal.

[0062] The source driver 130 may generate a data signal according to (e.g., or based on) the image data DATA2 and the data control signal DCS provided from the timing controller 140, and may provide the data signal to the display unit 110 (or the pixel PXL). The data control signal DCS may be a signal for controlling the operation of the data driver 130, and may include a load signal (e.g., or a data enable signal) for instructing the output of a valid data signal.

[0063] In some embodiments, the source driver 130 may output data signals (or data voltages) to the data lines DL1 to DLm through a plurality of source amplifiers, respectively, and may include a chopping circuit and a chopping controller. The chopping circuit may change (e.g., may periodically change) the polarity of the source amplifier in response to the chopping control signal. The chopping controller may generate a chopping control signal (e.g., a square wave or a chopping control signal having a square wave), and may change (or may vary) the slew rate or conversion speed of the chopping control signal. For example, the slew rate may indicate the rate at which the output signal (e.g., the chopping control signal) follows the input signal, or the rate of change of the chopping control signal according to time. The slew rate of the chopping control signal may be controlled (e.g., or set) during the manufacturing process of the display device 100 in consideration of the noise generated by the chopping control signal in the data lines DL1 to DLm.

[0064] The following will refer to Figures 3 to 11 An exemplary configuration of the source driver 130 (as well as exemplary configurations of the chopping circuit and the chopping controller) is described in more detail.

[0065] The timing controller 140 may receive input image data DATA1 and a control signal CS from the outside (e.g., from a graphics processor), may generate a scan control signal SCS and a data control signal DCS according to (e.g., based on) the control signal CS, and may generate image data DATA2 by converting the input image data DATA1. The control signal CS may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock (CLK), and / or the like. For example, the timing controller 140 may convert the input image data DATA1 (e.g., input image data DATA1 in an RGB format or having an RGB format) into image data DATA2 (e.g., image data DATA2 in an RGBG format or having an RGBG format) according to (e.g., or corresponding to) a pixel arrangement of pixels PXL at (e.g., in or on) the display unit 110.

[0066] In various embodiments, at least one of the scan driver 120, the source driver 130, the timing controller 140, and the light emitting driver 150 may be formed at (e.g., in or on) the display unit 110, or may be implemented as an integrated circuit IC and may be connected to the display unit 110 in a tape carrier package type and / or the like. For example, in some embodiments, at least two of the scan driver 120, the source driver 130, the timing controller 140, and the light emitting driver 150 may be implemented on the same IC (e.g., implemented as a single IC).

[0067] Figure 2 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0068] Reference Figure 2 , the pixel PXL may include first to seventh transistors T1 to T7 , a storage capacitor Cst, and a light emitting element LD.

[0069] Each of the first to seventh transistors T1 to T7 may be implemented as a P-type transistor, but the present disclosure is not limited thereto. For example, at least some of the first to seventh transistors T1 to T7 may be implemented as N-type transistors.

[0070] The first electrode of the first transistor (e.g., or the driving transistor) T1 may be connected to the second node N2 (e.g., or may be connected to the first power line (e.g., the power line to which the first power voltage VDD is applied) through the fifth transistor T5). The second electrode of the first transistor T1 may be connected to the first node N1 (e.g., or may be connected to the anode of the light emitting element LD through the sixth transistor T6). The gate electrode of the first transistor T1 may be connected to the third node N3. The first transistor T1 may control the amount of current flowing from the first power line through the light emitting element LD to the second power line (e.g., the power line for transmitting the second power voltage VSS) corresponding to the voltage of the third node N3.

[0071] The second transistor (e.g., or a switching transistor) T2 may be connected between the data line DLj and the second node N2. The gate electrode of the second transistor T2 may be connected to the scan line SLi. When a scan signal is supplied to the scan line SLi, the second transistor T2 may be turned on to electrically connect the data line DLj and the first electrode of the first transistor T1 to each other.

[0072] The third transistor T3 may be connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 may be connected to the scan line SLi. When the scan signal is supplied to the scan line SLi, the third transistor T3 may be turned on to electrically connect the first node N1 and the third node N3 to each other. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode. In other words, when the third transistor T3 is turned on, the first transistor T1 may be connected by a diode.

[0073] The storage capacitor Cst may be connected between the first power line and the third node N3. The storage capacitor Cst may store a voltage corresponding to the data signal and the threshold voltage of the first transistor T1.

[0074] The fourth transistor T4 may be connected between the third node N3 and an initialization power line (e.g., a power line for transmitting an initialization power voltage Vint). A gate electrode of the fourth transistor T4 may be connected to a previous scan line SLi-1. When a scan signal is supplied to the previous scan line SLi-1, the fourth transistor T4 may be turned on to supply the initialization power voltage Vint to the third node N3. Here, the initialization power voltage Vint may have (e.g., or may be set to have) a voltage level lower than a voltage level of the data signal.

[0075] The fifth transistor T5 may be connected between the first power line and the second node N2. A gate electrode of the fifth transistor T5 may be connected to the light emitting control line ELi. When the light emitting control signal is supplied to the light emitting control line ELi, the fifth transistor T5 may be turned off, and in other cases (for example, when the light emitting control signal is not supplied to the light emitting control line ELi, or when the light emitting control signal having a gate-on level is supplied to the light emitting control line ELi), the fifth transistor T5 may be turned on.

[0076] The sixth transistor T6 may be connected between the first node N1 and the light emitting element LD. The gate electrode of the sixth transistor T6 may be connected to the light emitting control line ELi. When the light emitting control signal is supplied to the light emitting control line ELi, the sixth transistor T6 may be turned off, and in other cases (for example, when the light emitting control signal is not supplied to the light emitting control line ELi, or when the light emitting control signal with a gate-on level is supplied to the light emitting control line ELi), the sixth transistor T6 may be turned on.

[0077] The seventh transistor T7 may be connected between the initialization power line and the anode of the light emitting element LD. The gate electrode of the seventh transistor T7 may be connected to the scan line SLi. When the scan signal is supplied to the scan line SLi, the seventh transistor T7 may be turned on to supply the initialization power voltage Vint to the anode of the light emitting element LD.

[0078] The anode of the light emitting element LD may be connected to the first transistor T1 through the sixth transistor T6, and the cathode of the light emitting device LD may be connected to the second power supply line. The light emitting element LD may generate light having a desired brightness (e.g., having a predetermined brightness) corresponding to the current supplied from the first transistor T1. The first power supply voltage VDD may have (e.g., or may be set to have) a voltage level greater than (e.g., or higher than) the voltage level of the second power supply voltage VSS so that current flows to (e.g., or flows through) the light emitting element LD.

[0079] Figure 3 It is shown that the Figure 1 A block diagram of an example of a source driver in a display device.

[0080] Reference Figure 1 and Figure 3 , the source driver 130 may include a controller (e.g., or a control unit) 310, a chopping controller (e.g., or a chopping control unit) 320, a gamma voltage generator (e.g., or a gamma voltage generating unit) 330, a shift register 340, a latch 350, a decoder (e.g., or a digital-to-analog converter, a digital-to-analog conversion unit and / or the like) 360 and an output buffer (e.g., or an output buffer unit) 370.

[0081] The controller 310 may receive the data control signal DCS from the timing controller 140 .

[0082] The controller 310 may generate a first control signal CCCS according to (eg, or based on) the data control signal DCS. The first control signal CCCS may include a pulse and may be used to change (eg, periodically change) the polarity of an offset of a source amplifier included in (eg, configuring) the output buffer 370.

[0083] In addition, the controller 310 may generate a bias control signal according to (eg, or based on) the data control signal DCS. The bias control signal may be used to control a bias voltage applied to the output buffer 370 (or source amplifier).

[0084] The controller 310 may generate a gamma enable signal G_EN. The gamma enable signal G_EN may control the gamma voltage generator 330 to generate gamma voltages VG0 to VG2047. The gamma voltages VG0 to VG2047 may be used to convert data DATA (eg, reference Figure 1 For example, in an embodiment, the gamma voltages VG0 to VG2047 may include 2048 gamma voltages corresponding to 11-bit data, but this is a non-limiting example and the gamma voltages VG0 to VG2047 are not limited thereto.

[0085] The controller 310 may receive serial data from the timing controller 140 and may change the serial data into parallel data DATA. The controller 310 may provide the parallel data DATA to the shift register 340 (or the latch 350).

[0086] The chopping controller 320 may generate a chopping control signal CCS according to (eg, or based on) the first control signal CCCS, and may provide the chopping control signal CCS to the output buffer 370 .

[0087] In addition, the chopper controller 320 may generate a bias voltage having various suitable voltage levels in response to the bias control signal. However, the present disclosure is not limited thereto, and in an embodiment, the bias voltage may be generated by a separate bias voltage generator independent of the chopper controller 320 (e.g., or separated from the chopper controller 320).

[0088] In various embodiments, the chopping controller 320 may control the slew rate of the chopping control signal CCS, or may control (e.g., may change or vary) the switching speed of the chopping control signal CCS. For example, when the chopping control signal CCS is a square wave or includes a plurality of pulses, the chopping controller 320 may change (e.g., or may vary) the speed at which the voltage level of the chopping control signal CCS changes.

[0089] As will be described in more detail below, components (e.g., a touch panel) and / or their arrangement (e.g., or arrangement) included in the display device 100 or a product including the display device 100 may be modified in various ways. Therefore, depending on the configuration of the display device 100, various components may be affected by the display device 100 (e.g., or the data lines DL1 to DLm (refer to Figure 1 For example, the slew rate or switching speed of the chopping control signal CCS may be controlled (e.g., settable) during a manufacturing process of the display device 100 (or during a manufacturing process of a product including the display device 100) in consideration of arrangements between components (e.g., arrangement and / or distances between the data lines DL1 to DLm and electrodes of the touch panel) and / or the like, or in consideration of measurement results of possible influences on components (e.g., noise generated in the touch panel due to the data lines DL1 to DLm).

[0090] The gamma voltage generator 330 may receive the gamma enable signal G_EN to generate the gamma voltages VG0 to VG2047 having various suitable voltage levels.

[0091] The shift register 340 may provide the parallel data DATA to the latch 350. The shift register 340 may generate a latch clock signal and may provide the latch clock signal to the latch 350. The latch clock signal may be used to control the timing of outputting the parallel data DATA.

[0092] The latch 350 may latch or temporarily store data received (eg, sequentially received) from the shift register 340 , and may transfer the data to the decoder 360 .

[0093] The decoder 360 may convert the received data into a data signal using the gamma voltages VG0 to VG2047. For example, the decoder 360 may receive data in a first format (e.g., in a digital format, such as grayscale values ​​or grayscale values ​​of the parallel data DATA), and may convert the received data into a data signal in a second format different from the first format (e.g., a data signal in an analog format, such as a data voltage) using the gamma voltages VG0 to VG2047.

[0094] The output buffer 370 may receive the data signal and may output the data signal to the data lines DLs (eg, refer to Figure 1 The output buffer 370 may include source amplifiers connected to the data lines DL1 to DLm of the display unit 110 described above.

[0095] Although the chopper controller 320 Figure 3310 and the output buffer 370 (e.g., or separate from the controller 310 and the output buffer 370), but the present disclosure is not limited thereto. For example, in some embodiments, the chopper controller 320 may be included as part of the controller 310, or as part of the output buffer (e.g., or output buffer unit) 370.

[0096] Figure 4 It is shown that the Figure 3 A circuit diagram of an example of an output buffer in a source driver. Figure 4 , a portion of the output buffer 370 is shown with Figure 1 The circuit (eg, or source amplifier) ​​connected to the data line DLj shown in FIG.

[0097] Reference Figure 3 and Figure 4 , the output buffer 370 may include an amplifier (eg, or a source amplifier) ​​AMP and a chopping circuit SW.

[0098] The amplifier AMP may be connected to the output terminal of the decoder 360 or may be connected between the decoder 360 and the data line DLj.

[0099] The chopping circuit SW may change (eg, may periodically change) the polarity of the offset of the amplifier AMP in response to a chopping control signal CCS. The chopping control signal CCS is provided by a chopping controller (eg, or chopping control unit) 320 and may include a pulse having a turn-on voltage level.

[0100] The chopping circuit SW may include first to fourth switches SW1 to SW4 .

[0101] The first switch SW1 may be connected between the input node N_IN and the first input terminal (e.g., the first input node N_P) of the amplifier AMP. The second switch SW2 may be connected between the input node N_IN and the second input terminal (e.g., the second input node N_N) of the amplifier AMP. The third switch SW3 may be connected between the first input terminal (or the first input node N_P) of the amplifier AMP and the output terminal (e.g., the output node N_OUT) of the amplifier AMP. The fourth switch SW4 may be connected between the second input terminal (or the second input node N_N) of the amplifier AMP and the output terminal (e.g., the output node N_OUT) of the amplifier AMP.

[0102] The first switch SW1 to the fourth switch SW4 may be operated or turned on in response to the chopping control signal CCS. In this case, the chopping control signal CCS may include a first chopping control signal CCS1, a second chopping control signal CCS2, a third chopping control signal CCS3, and a fourth chopping control signal CCS4. For example, the first switch SW1 may be turned on in response to the first chopping control signal CCS1 having a turn-on voltage level, the second switch SW2 may be turned on in response to the second chopping control signal CCS2 having a turn-on voltage level, the third switch SW3 may be turned on in response to the third chopping control signal CCS3 having a turn-on voltage level, and the fourth switch SW4 may be turned on in response to the fourth chopping control signal CCS4 having a turn-on voltage level.

[0103] The first switch SW1 and the fourth switch SW4 may be turned on at a first time (e.g., during) (e.g., or during a first cycle) in response to the first chopping control signal CCS1 and the fourth chopping control signal CCS4 having a turn-on voltage level. The second switch SW2 and the third switch SW3 may be turned on at a second time (e.g., during) (e.g., or during a second cycle) different from the first time in response to the second chopping control signal CCS2 and the third chopping control signal CCS3 having a turn-on voltage level. For example, the first time and the second time may be turned on in each frame period (e.g., in the display device 100 (refer to Figure 1 ) alternates in each frame period of displaying a frame image, but the present disclosure is not limited to this.

[0104] For example, at a first time (or during), the data signal may be output through the first input terminal of the amplifier AMP with an offset having a first polarity, and at a second time (or during), the data signal may be output through the second input terminal of the amplifier AMP with an offset having a second polarity (e.g., an offset having the same or substantially the same magnitude as the offset of the first polarity and having a polarity different from the polarity of the offset of the first polarity).

[0105] Figure 5 It is shown Figure 4 The circuit diagram of an example of an output buffer. Figure 5 In Figure 4 The third switch SW3 shown in FIG. 3 is a portion of the output buffer 370 shown at the center.

[0106] Reference Figure 4 and Figure 5 As a non-limiting example, the third switch SW3 may include (or may be) an N-type transistor (e.g., an N-channel metal oxide semiconductor (NMOS) transistor or an oxide semiconductor transistor), but the present disclosure is not limited thereto. For example, in another embodiment, the third switch SW3 may include (or may be) a P-type transistor.

[0107] A first parasitic capacitor Cpar1 may be formed between an output node N_OUT connected to the output terminal of the amplifier AMP and a control line CL for transmitting the third chopping control signal CCS3 to the third switch SW3. For example, a wiring connected to the output node N_OUT may overlap or be adjacent to the control line CL, and thus, the first parasitic capacitor Cpar1 may be formed between the wiring connected to the output node N_OUT and the control line CL.

[0108] The high frequency component of the third chopping control signal CCS3 may be transmitted to the output node N_OUT through the first parasitic capacitor Cpar1 and may appear as noise to the data signal transmitted through the data line DLj.

[0109] although Figure 5 The first parasitic capacitor Cpar1 is shown to be formed corresponding to the third switch SW3 (e.g., formed at or in the third switch SW3), but the present disclosure is not limited thereto. For example, the parasitic capacitor may be formed corresponding to the fourth switch SW4 (e.g., formed at or in the fourth switch SW4), and / or the parasitic capacitor may be formed corresponding to the first switch SW1 and the second switch SW2 (e.g., formed at or in the first switch SW1 and the second switch SW2), respectively (e.g., see Figure 4 ). Therefore, the first chopping control signal CCS1, the second chopping control signal CCS2, the third chopping control signal CCS3 and the fourth chopping control signal CCS4 (for example, see Figure 4 ) may appear as noise to the data signal.

[0110] Figure 6 It is shown Figure 5 Figure 2 is a waveform diagram of an example of a signal measured in the output buffer of a controller.

[0111] Reference Figure 5 and Figure 6 , the third chopping control signal CCS3 may be converted from a turn-off voltage level (e.g., a logic low level or a gate turn-off voltage level) to a turn-on voltage level (e.g., a logic high level or a gate turn-on voltage level) at a first time point t1, and may be converted to a turn-off voltage level at a second time point t2. Here, the turn-off voltage level may be used to enable Figure 5 The on-voltage level may be a suitable voltage level for turning off the transistor (eg, the third switch SW3) shown in FIG. 1 , and the on-voltage level may be a suitable voltage level for turning on the transistor (eg, the third switch SW3).

[0112] At (or during) the first time point t1, noise (e.g., noise in a pulse form or having a pulse form) corresponding to a change in the third chopping control signal CCS3 (e.g., conversion from an off voltage level to an on voltage level) may occur in the data signal DATAj transmitted through the data line DLj.

[0113] Similarly, at (or during) the second time point t2, noise (e.g., noise in a pulse form or having a pulse form) corresponding to a change in the third chopping control signal CCS3 (e.g., conversion from an on-voltage level to an off-voltage level) may occur in the data signal DATAj transmitted through the data line DLj.

[0114] The effect of this noise on the data signal stored in the pixel can be minimal. Figure 2 As described, because the data signal DATAj is stored in the storage capacitor Cst of the pixel PXL, and / or because the storage capacitor Cst is charged during a specific time in response to the scan signal transmitted through the scan line SLi, the influence of noise on the pixel PXL can be excluded (or ignored). For example, the noise of the pixel PXL can be excluded by making the conversion time points of the data signal DATAj (e.g., the first time point t1 and the second time point t2) not overlap with the scan signal of the turn-on voltage level (e.g., when the scan signal has the turn-on voltage level).

[0115] However, as will be referred to below Figures 12 to 15 Described in more detail, one or more other components that may be included in the display device 100 or may be included in a product including the display device 100 (e.g., a touch panel that is not synchronized with the source driver 130) may be affected by the noise generated in the data line DLj and therefore may not operate properly (or may not be able to perform a function).

[0116] Therefore, according to various embodiments of the present disclosure, the chopper controller 320 (eg, referring to Figure 4) can vary (e.g., can change) the slew rate or conversion speed of the chopping control signal CCS (e.g., the third chopping control signal CCS3). For example, when the slew rate or conversion speed of the chopping control signal CCS is reduced, the high-frequency component of the chopping control signal CCS can be reduced, and thus the noise of the data signal DATAj can be reduced. However, as the slew rate or conversion speed of the chopping control signal CCS is reduced, the time for stabilizing or substantially stabilizing the output buffer 370 may increase (e.g., additional time for stabilizing or substantially stabilizing the output buffer 370 may be required or desired). Therefore, the slew rate or conversion speed of the chopping control signal CCS can be varied (e.g., can be changed) to a suitable slew rate or conversion speed that does not generate noise in other components (e.g., touch panel). For example, the slew rate or conversion speed of the chopping control signal CCS can be set to have the highest slew rate or fastest conversion speed within a suitable range that does not generate noise in other components (e.g., touch).

[0117] Figure 7 It is shown that the Figure 3 A block diagram of an example of a chopper controller in a source driver.

[0118] Reference Figure 3 , Figure 4 and Figure 7 , the chopping controller 320 may include a logic control circuit (eg, a logic controller or a logic control block) 710 , a level shifter 720 , and a buffer circuit (eg, a buffer or a buffer block) 730 .

[0119] The logic control circuit 710 may generate a first control signal including a pulse. For example, the first control signal may be Figure 3 The first control signal CCCS described above may be the same or substantially the same as the first control signal CCCS described above, and in this case, the logic control circuit 710 may be included in (eg, as a part of) the controller 310 .

[0120] The level shifter 720 may shift the level of the first control signal to generate the second control signal. For example, the level shifter 720 may shift the level of the first control signal upward to generate the second control signal.

[0121] The buffer circuit 730 may output the second control signal as the chopping control signal CCS, and may change the slew rate of the chopping control signal CCS. For example, the slew rate may indicate the rate at which the chopping control signal CCS follows the second control signal, or the rate of change of the chopping control signal CCS according to time. The chopping control signal CCS output from the buffer circuit 730 may be provided to the chopping circuit SW.

[0122] In some embodiments, the buffer circuit 730 may include sub-buffers connected in parallel to the chopping circuit SW, and sub-switches respectively connecting the sub-buffers in series to the level shifter 720 .

[0123] Figure 8 It is shown that the Figure 7 A circuit diagram of an example of a buffer circuit in a chopper controller.

[0124] Reference Figure 8 , the buffer circuit 730 may include first to fourth sub-buffers BUF_S1 to BUF_S4 and first to fourth sub-switches SW_S1 to SW_S4.

[0125] The first sub-buffer BUF_S1 and the first sub-switch SW_S1 may be connected in series between the level shifter 720 and the chopping circuit SW. Similarly, the second sub-buffer BUF_S2 and the second sub-switch SW_S2 may be connected in series between the level shifter 720 and the chopping circuit SW, the third sub-buffer BUF_S3 and the third sub-switch SW_S3 may be connected in series between the level shifter 720 and the chopping circuit SW, and the fourth sub-buffer BUF_S4 and the fourth sub-switch SW_S4 may be connected in series between the level shifter 720 and the chopping circuit SW.

[0126] Each of the first to fourth sub-buffers BUF_S1 to BUF_S4 may be connected in series between the first driving voltage V_TOP and the second driving voltage GND, and may include (eg, may be configured by) an N-type transistor M1 and a P-type transistor M2. Figure 8 As shown in , each of the first sub-buffer BUF_S1 to the fourth sub-buffer BUF_S4 may include transistors M1 and M2 connected in series between a first driving voltage V_TOP and a second driving voltage GND. The gate electrode of each of the transistors M1 and M2 may be connected to an input terminal IN of the corresponding sub-buffer. The input terminal IN of the corresponding sub-buffer may be connected to a corresponding sub-switch, and the output terminal OUT of the corresponding sub-buffer may be connected to the chopping circuit SW. The first sub-buffer BUF_S1 to the fourth sub-buffer BUF_S4 may have the same or substantially the same buffer size as each other, but the present disclosure is not limited thereto. For example, at least one of the first sub-buffer BUF_S1 to the fourth sub-buffer BUF_S4 may have a buffer size different from the buffer size of at least one of the other sub-buffers (e.g., buffer sizes different from each other).

[0127] Each of the first to fourth sub-switches SW_S1 to SW_S4 may include (e.g., may be implemented as) an N-type transistor, but the present disclosure is not limited thereto. At least one of the first to fourth sub-switches SW_S1 to SW_S4 may be controlled (e.g., may be turned on) according to (e.g., based on) the selection signal CHOP_SLOPE_CON[1:0]. The selection signal CHOP_SLOPE_CON[1:0] may be a control signal from the controller 310 (e.g., see Figure 3 ) or the like.

[0128] although Figure 8 The buffer circuit 730 is shown as a non-limiting example including four pairs of sub-buffers and sub-switches, but the present disclosure is not limited thereto, and the buffer circuit 730 may include any suitable number of sub-buffers and sub-switch pairs. For example, the buffer circuit 730 may include two pairs of sub-buffers and sub-switches, three pairs of sub-buffers and sub-switches, five or more pairs of sub-buffers and sub-switches, and / or the like.

[0129] Fig. 9 It is shown from Figure 8 FIG. 1 is a waveform diagram of an example of a chopping control signal at the buffer output.

[0130] Reference Figure 8 and Fig. 9 , when the selection signal CHOP_SLOPE_CON[1:0] has a first value (eg, 00), each (eg, all) of the first to fourth sub switches SW_S1 to SW_S4 may be turned on.

[0131] In this case, as referenced Figure 6 As described, the chopping control signal CCS may be converted (eg, may be converted quickly) from the off voltage level to the on voltage level at the first time point t1, and may be converted (eg, may be converted quickly) from the on voltage level to the off voltage level at the second time point t2.

[0132] When the selection signal CHOP_SLOPE_CON[1:0] has the second value (eg, 01), three (eg, the first to third sub-switches SW_S1 to SW_S3 ) of the first to fourth sub-switches SW_S1 to SW_S4 may be turned on.

[0133] In this case, the chopping control signal CCS may be converted from the off voltage level to the on voltage level during a period between the first time point t1 and the third time point t3 (for example, in this period), and may be converted from the on voltage level to the off voltage level during a period between the second time point t2 and the sixth time point t6 (for example, in this period).

[0134] The slope of the chopping control signal CCS (or the slope of a rising edge of a pulse and / or a falling edge of a pulse) when the selection signal CHOP_SLOPE_CON[1:0] has the second value may be smaller (e.g., gentler) than the slope of the chopping control signal CCS when the selection signal CHOP_SLOPE_CON[1:0] has the first value.

[0135] When the selection signal CHOP_SLOPE_CON[1:0] has a third value (e.g., 10), two of the first to fourth sub-switches SW_S1 to SW_S4 (e.g., the first sub-switch SW_S1 and the second sub-switch SW_S2) may be turned on. In this case, the chopping control signal CCS may be converted from the off voltage level to the on voltage level during a period between the first time point t1 and the fourth time point t4 (e.g., in the period), and may be converted from the on voltage level to the off voltage level during a period between the second time point t2 and the seventh time point t7 (e.g., in the period). The slope of the chopping control signal CCS in the case where the selection signal CHOP_SLOPE_CON[1:0] has the third value may be smaller (e.g., gentler) than the slope of the chopping control signal CCS in the case where the selection signal CHOP_SLOPE_CON[1:0] has the second value.

[0136] When the selection signal CHOP_SLOPE_CON[1:0] has a fourth value (e.g., 11), one of the first to fourth sub-switches SW_S1 to SW_S4 (e.g., the first sub-switch SW_S1) may be turned on. In this case, the chopping control signal CCS may be converted from the off voltage level to the on voltage level during a period between the first time point t1 and the fifth time point t5 (e.g., in this period), and may be converted from the on voltage level to the off voltage level during a period between the second time point t2 and the eighth time point t8 (e.g., in this period). The slope of the chopping control signal CCS in the case where the selection signal CHOP_SLOPE_CON[1:0] has the fourth value may be smaller (e.g., gentler) than the slope of the chopping control signal CCS in the case where the selection signal CHOP_SLOPE_CON[1:0] has the third value.

[0137] Accordingly, the buffer size of the buffer circuit 730 may be varied (e.g., changeable) according to the selection signal CHOP_SLOPE_CON[1:0] (e.g., by controlling the sub-switches SW_S1 to SW_S4), and the slew rate (e.g., conversion speed or slope) of the chopping control signal CCS output by the buffer circuit 730 may be controlled. For example, as the buffer size of the buffer circuit 730 decreases, the slew rate of the chopping control signal CSS may decrease.

[0138] According to one or more embodiments of the present disclosure, Figure 1 During the manufacturing process of the display device 100 (e.g., in the manufacturing process), the noise generated in other components (e.g., the touch panel) may be measured while changing the value of the selection signal CHOP_SLOPE_CON[1:0]. According to the measurement result of the noise, a suitable or optimal value of the selection signal CHOP_SLOPE_CON[1:0] (e.g., a value that maximizes the slope of the chopping control signal CCS without generating noise) may be selected or set. In other words, the buffer size of the buffer circuit 730 may be changed (e.g., may be set) to have a maximum size within a range (e.g., in a range) where noise does not occur.

[0139] although Fig. 9 The first to fourth sub-buffers BUF_S1 to BUF_S4 are shown to have the same or substantially the same size (or buffer size) as each other, but the present disclosure is not limited thereto. For example, the size of the second sub-buffer BUF_S2 may be twice that of the first sub-buffer BUF_S1, and the size of the third sub-buffer BUF_S3 may be twice that of the second sub-buffer BUF_S2. In this case, only the first sub-switch SW_S1 corresponding to the first sub-buffer BUF_S1 can be turned on corresponding to the fourth value (for example, 11) of the selection signal CHOP_SLOPE_CON[1:0], only the second sub-switch SW_S2 corresponding to the second sub-buffer BUF_S2 can be turned on corresponding to the third value (for example, 10) of the selection signal CHOP_SLOPE_CON[1:0], only the first sub-buffer BUF_S1 and the second sub-buffer BUF_S2 can be turned on corresponding to the second value (for example, 01) of the selection signal CHOP_SLOPE_CON[1:0], and only the third sub-buffer BUF_S3 can be turned on corresponding to the first value (for example, 00) of the selection signal CHOP_SLOPE_CON[1:0].

[0140] Fig.10 It is shown that the Figure 3 A block diagram of another example of a chopper controller in a source driver.

[0141] Reference Figure 7 and Fig.10 , Fig.10 The chopper controller 320 with Figure 7 The difference of the chopper controller 320 is that Fig.10 The chopper controller 320 also includes an analog filter (or low-pass filter) 740 . Fig.10 The other elements and components of the chopper controller 320 may be Figure 7The elements and components of the present invention are the same or substantially the same, and thus, redundant descriptions thereof may be simplified or may not be repeated.

[0142] The buffer circuit 730 may output the second control signal provided from the level shifter 720 as the chopping control signal CCS. Figure 7 Unlike the buffer circuit 730 described above, Fig.10 The buffer circuit 730 shown in FIG. 7 may not change the slew rate of the chopping control signal CCS, but the present disclosure is not limited thereto.

[0143] The analog filter 740 may be connected between the output terminal of the buffer circuit 730 and the chopping circuit SW, and may filter (e.g., may be able to filter variably) the high frequency component of the chopping control signal CCS. In other words, the analog filter 740 may control the cut-off frequency, and therefore, the slope of the chopping control signal CCS may vary (e.g., may be changed).

[0144] The analog filter 740 may include a variable resistor R1 and a variable capacitor C1. The variable resistor R1 may be connected between the buffer circuit 730 and the chopping circuit SW, and the variable capacitor C1 may be connected between the chopping circuit SW and a reference voltage line VREF (e.g., ground). The variable resistor R1 may include a plurality of resistors and a switching element (e.g., which may be implemented therewith). The variable capacitor C1 may include a plurality of capacitors and a switching element (e.g., which may be implemented therewith).

[0145] At least one of the resistance of the variable resistor R1 and the capacitance of the variable capacitor C1 may be changed (eg, variable) according to (eg, based on) the selection signal CHOP_SLOPE_CON[1:0]. Fig. 9 For example, when the selection signal CHOP_SLOPE_CON[1:0] has a first value (e.g., 00), each of the resistance of the variable resistor R1 and the capacitance of the variable capacitor C1 may be minimum. As another example, when the selection signal CHOP_SLOPE_CON[1:0] has a fourth value (e.g., 11), each of the resistance of the variable resistor R1 and the capacitance of the variable capacitor C1 may be maximum.

[0146] Fig.11 It is shown that the Figure 3 A block diagram of another example of a chopper controller in a source driver.

[0147] Reference Figure 7 , Fig.10 and Fig.11 , Fig.11 The chopper controller 320 with Figure 7 and Fig.10 The difference of the chopper controller 320 is that Fig.11The chopper controller 320 also includes a delay element 750 (eg, in place of the analog filter 740 ). Fig.11 The other elements and components of the chopper controller 320 may be Figure 7 and Fig.10 The elements and components of the present invention are the same or substantially the same, and thus, redundant descriptions thereof may be simplified or may not be repeated.

[0148] The delay element 750 may be connected between the buffer circuit 730 and the chopping circuit SW.

[0149] The delay element 750 may include a resistor R, a first diode D1 and a second diode D2, and a first delay switch element SW_D1 and a second delay switch element SW_D2. The resistor R may be connected between the buffer circuit 730 and the chopper circuit SW. The first diode D1 and the first delay switch element SW_D1 may be connected in series with each other and may be connected in parallel to the resistor R. The second diode D2 and the second delay switch element SW_D2 may be connected in series with each other and may be connected in parallel to the resistor R. The first delay switch element SW_D1 and the second delay switch element SW_D2 may be controlled (e.g., may be turned on or off) in response to a selection signal (e.g., a preset or predetermined selection signal).

[0150] The resistor R may include a variable resistor (eg, may be configured by the resistor R). The resistor R may delay and transmit the chopping control signal CCS provided from the buffer circuit 730 (eg, a rising edge and / or a falling edge of the chopping control signal CCS). However, the present disclosure is not limited thereto. For example, instead of the resistor R, refer to Fig.10 The described analog filter 740 may be applied.

[0151] The first diode D1 and the second diode D2 may be connected in different directions (or different polarities) from each other. The first diode D1 may transmit the chopping control signal CCS provided from the buffer circuit 730 without delay of the rising edge of the chopping control signal CCS, and the second diode D2 may transmit the chopping control signal CCS without delay of the falling edge of the chopping control signal CCS.

[0152] In other words, the delay element 750 may delay the chopping control signal CCS or control the slew rate of the chopping control signal CCS using the resistor R, and may control the slew rate of at least one of the rising and falling edges of the chopping control signal CCS using the first diode D1 and the second diode D2.

[0153] Fig.12 is a view showing a display device according to another embodiment of the present disclosure. Fig.13 It is shown Fig.12 A cross-sectional view of an example of a display device.

[0154] Reference Fig.12 and Fig.13 , the display device 1 can display an image. The display device 1 may be included in (e.g., may be a part of) a portable terminal (e.g., a portable electronic device) such as a tablet computer, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a watch-type electronic device (e.g., a smart watch, a fitness watch, a health watch, and / or the like), a game console, and / or the like. However, the display device 1 is not limited thereto. For example, the display device 1 may be included in (e.g., may be a part of) a large electronic device such as a television, an external billboard, and / or the like, or may be included in (e.g., may be a part of) a small or medium-sized electronic device such as a personal computer, a laptop computer, a car navigation device, a camera, and / or the like.

[0155] The display device 1 may include a display area DA and a non-display area NDA. The display area DA may be defined as a portion of the display device 1 that displays an image, and the non-display area NDA may be defined as a portion of the display device 1 that does not display an image.

[0156] The display area DA may be located (e.g., may be positioned) at a central portion (or central area) of the display device 1, and may have an area larger (e.g., a relatively large area) than that of the non-display area NDA. The display area DA may include (e.g., may be provided with) a reference Figure 1 The described display unit 110 , or the display area DA may correspond to the display unit 110 .

[0157] The non-display area NDA may be located (e.g., may be positioned) at least one side of the display area DA (e.g., in or on it), or may be located near (e.g., in or on) the display area DA. The non-display area NDA may correspond to (e.g., may be) an area (e.g., a frame area) extending from an outer boundary of the display area DA (e.g., from the periphery) to an edge (e.g., periphery or frame) of the display device 1. For example, in some embodiments, the non-display area NDA may surround the display area DA (e.g., around it). Referring to Figure 1 The described scan driver 120 , source driver 130 , timing controller 140 , and / or light emitting driver 150 may be disposed on (eg, in or on) the non-display area NDA.

[0158] The display device 1 may include a base layer (eg, substrate) SUB, a display layer (eg, display panel) DISP, and a touch sensing layer (eg, touch panel) TSP.

[0159] The base layer SUB may include (eg, may be formed of) an insulating material such as glass, resin, and / or the like. The base layer SUB may include (eg, may be formed of) a material having flexibility so that it is bendable or foldable, and may have a single-layer structure or a multi-layer structure.

[0160] The display layer DISP may be formed on the base layer SUB (eg, in the third direction DR3 of the base layer SUB or in the thickness direction DR3). The display layer DISP may be similar to the above-mentioned Figure 1 The described display apparatus 100 is the same or substantially the same, and thus, a redundant description thereof may not be repeated.

[0161] The touch sensing layer TSP may be disposed on the display layer DISP. The touch sensing layer TSP may be disposed at (e.g., on or in) the non-display area NDA (or non-sensing area) and the display area DA (or sensing area). The touch sensing layer TSP may include touch electrodes and sensing lines connected to the touch electrodes.

[0162] The touch sensing layer TSP may be integrally formed with or directly formed on the display layer DISP. However, the present disclosure is not limited thereto. For example, the touch sensing layer TSP may be manufactured as a separate touch panel independent of (e.g., different from) the display layer DISP (or display panel), and may be coupled to the display layer DISP via an adhesive layer (e.g., optically clear resin (OCR), optically clear adhesive (OCA), and / or the like).

[0163] Fig.14 It is shown that the Fig.13 A plan view of an example of a touch sensing layer in a display device.

[0164] Reference Fig.13 and Fig.14 , the touch sensing layer TSP may include a sensing area SA and a non-sensing area NSA. The sensing area SA may correspond to the display area DA of the display device 1 , and the non-sensing area NSA may correspond to the non-display area NDA of the display device 1 .

[0165] The touch electrode TE may be disposed at (eg, in or on) the sensing area SA, and the sensing line SSL and the pad portion PD may be disposed at (eg, in or on) the non-sensing area NSA.

[0166] The touch electrode TE may include first touch electrodes TE1 and second touch electrodes TE2. The first touch electrodes TE1 and the second touch electrodes TE2 may be alternately arranged and may be connected in different directions (eg, in directions different from each other).

[0167] The first touch electrodes TE1 may be arranged in a matrix form and may be electrically connected to each other along a second direction (e.g., a second forward direction) DR2 to form a plurality of parallel touch electrode rows. The first touch electrode TE1 of one touch electrode row may be electrically connected to an adjacent first touch electrode TE1 of one touch electrode row through a first connection pattern (or a first bridge pattern) CNP1.

[0168] The second touch electrodes TE2 may be arranged in a matrix form and may be electrically connected to each other along a first direction DR1 intersecting the second direction DR2 to form a plurality of parallel touch electrode columns. The second touch electrode TE2 of one touch electrode column may be electrically connected to an adjacent second touch electrode TE2 of one touch electrode column through a second connection pattern (or second bridge pattern) CNP2.

[0169] Each of the first touch electrodes TE1 (or touch electrode rows) and the second touch electrodes TE2 (or touch electrode columns) may be electrically connected to a corresponding sensing pad included at (eg, in or on) the pad portion PD through a corresponding sensing line SSL.

[0170] In an embodiment, each of the touch electrode TE and the connection patterns CNP1 and CNP2 may include a plurality of conductive lines (eg, a plurality of conductive thin lines). Fig.14 As shown in the enlarged view of the touch area EA in FIG. 1 , each of the touch electrode TE and the connection patterns CNP1 and CNP2 may include a plurality of first conductive thin wires extending in one direction and parallel or substantially parallel to each other, and a plurality of second conductive thin wires extending in another direction intersecting the first conductive thin wires and parallel or substantially parallel to each other. In other words, each of the touch electrode TE and the connection patterns CNP1 and CNP2 may have a mesh structure.

[0171] However, the touch electrode TE and the connection patterns CNP1 and CNP2 are not limited thereto. For example, the touch electrode TE and the connection patterns CNP1 and CNP2 may include a transparent conductive material such as ITO and / or IZO.

[0172] The sensing line SSL may electrically connect the touch electrode TE and the driving circuit to each other. The sensing line SSL may transmit a sensing input signal from the driving circuit to the touch electrode TE, or may transmit a sensing output signal from the touch electrode TE to the driving circuit.

[0173] Fig.15 It is shown Fig.13 A cross-sectional view of an example of a display device. Fig.15 An enlarged portion (eg, pixel) of a display area DA of the display device 1 is shown.

[0174] Reference Figures 13 to 15, the display layer DISP may be disposed on the base layer SUB. The display layer DISP may include a pixel circuit layer PCL and a light emitting element layer (or display element layer) LDL.

[0175] The pixel circuit layer PCL may be disposed on the base layer SUB. The pixel circuit layer PCL may include at least one transistor TR disposed at (eg, in or on) the display area DA of the base layer SUB, and one or more lines (eg, Figure 1 One of the data lines DL1 to DLm described above corresponds to the data line DL).

[0176] The pixel circuit layer PCL may include a buffer layer BUF, a semiconductor layer, a first insulating layer INS1, a first conductive layer GAT, a second insulating layer INS2, a second conductive layer SD, and a third insulating layer INS3.

[0177] The buffer layer BUF may be arranged on a surface (e.g., the entire surface) of the base layer SUB. The buffer layer BUF may perform a surface flattening function, prevent or substantially prevent the diffusion of impurity ions, and / or prevent or substantially prevent the penetration of moisture or external air. The buffer layer BUF may include, for example, silicon nitride, silicon oxide, silicon oxynitride, and / or the like. However, the present disclosure is not limited thereto, and, for example, the buffer layer BUF may be omitted as needed or necessary, depending on the type of the base layer SUB, process conditions, and / or the like.

[0178] The semiconductor layer may be arranged on the buffer layer BUF (or on the base layer SUB). The semiconductor layer may include (for example, may be) an active layer forming a channel of the transistor TR. The semiconductor layer may include a source region and a drain region contacting the source electrode SE and the drain electrode DE, respectively, which will be described in more detail below. The region between the source region and the drain region may be a channel region ACT.

[0179] The semiconductor layer may include polycrystalline silicon, amorphous silicon, an oxide semiconductor, or the like. The channel region ACT of the semiconductor pattern may include (e.g., may be) a semiconductor pattern not doped with impurities, and may be, for example, an intrinsic semiconductor. The source region and the drain region may include (e.g., may be) a semiconductor pattern doped with impurities. For example, impurities such as n-type impurities, p-type impurities, other metals, and / or the like may be used to dope the semiconductor pattern of the source region and the drain region.

[0180] The first insulating layer (or gate insulating layer) INS1 may be disposed on the semiconductor layer and the buffer layer BUF (or on the base layer SUB). The first insulating layer INS1 may be disposed above the surface of the base layer SUB (eg, may be disposed generally above the entire surface). The first insulating layer INS1 may include (eg, may be) a gate insulating film having a gate insulating function.

[0181] The first insulating layer INS1 may include an inorganic insulating material such as a silicon compound, a metal oxide, and / or the like. For example, the first insulating layer INS1 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, and / or the like, or a combination thereof. The first insulating layer INS1 may include (e.g., may be) a single-layer film, or a multi-layer film including (e.g., formed of) a plurality of stacked films of different materials.

[0182] The first conductive layer GAT may be disposed on the first insulating layer INS1. The first conductive layer GAT may include a gate electrode GE. The gate electrode GE may be disposed to overlap the semiconductor layer (or overlap the channel area ACT of the semiconductor layer).

[0183] The first conductive layer GAT may include one or more metals selected from, for example, molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer GAT may have a single film structure or a multi-layer film structure.

[0184] The second insulating layer (or interlayer insulating layer) INS2 may be disposed on the first conductive layer GAT. The second insulating layer INS2 may be disposed over the surface of the base layer SUB (e.g., may be disposed generally over the entire surface). The second insulating layer INS2 may insulate the first conductive layer GAT and the second conductive layer SD from each other, and may include (e.g., may be) an interlayer insulating film.

[0185] The second insulating layer INS2 may include an inorganic insulating material or an organic insulating material. The second insulating layer INS2 may include (eg, may be) a single-layer film, or a multi-layer film including (eg, formed of) a plurality of stacked films of different materials.

[0186] The second conductive layer SD may be disposed on the second insulating layer INS2. The second conductive layer SD may include a source electrode (eg, a first transistor electrode) SE, a drain electrode (eg, a second transistor electrode) DE, and a data line DL.

[0187] The source electrode SE and the drain electrode DE may respectively contact the source region and the drain region of the semiconductor pattern through contact holes extending through (eg, through) the second insulating layer INS2 and the first insulating layer INS1 .

[0188] Similar to the first conductive layer GAT, the second conductive layer SD may include one or more metals selected from, for example, molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second conductive layer SD may have a single film structure or a multi-layer film structure.

[0189] A third insulating layer (or protective layer) INS3 may be positioned on the second conductive layer SD.

[0190] The light emitting element layer LDL may be disposed on the pixel circuit layer PCL. The light emitting element layer LDL may include at least one light emitting element EL and an encapsulation layer TFE disposed at (eg, in or on) the display area DA and connected to at least one transistor TR.

[0191] The light emitting element EL may be disposed on the third insulating layer INS3.

[0192] The light emitting element EL (or the light emitting element layer LDL) may include a first electrode (or a lower electrode) LE, a second electrode (or an upper electrode) UE, and a light emitting layer (or an intermediate layer) IL. In addition, the light emitting element EL (or the light emitting element layer LDL) may further include a pixel defining film PDL. One of the first electrode LE and the second electrode UE may be an anode, and the other of the first electrode LE and the second electrode UE may be a cathode. For example, the first electrode LE may be an anode, and the second electrode UE may be a cathode.

[0193] The first electrode LE may be electrically connected to the drain electrode DE of the transistor TR through a contact hole extending through (eg, through) the third insulating layer INS3 .

[0194] The pixel defining film PDL may be arranged along an edge of the first electrode LE (e.g., along a plurality of edges), and the pixel defining film PDL may include an organic insulating material. For example, the pixel defining film PDL may be arranged on the first electrode LE and may have an opening exposing at least a portion of the first electrode LE (e.g., a surface portion between the edges).

[0195] The light emitting layer IL may be disposed on the first electrode LE exposed by the pixel defining film PDL. The light emitting layer IL may include a low molecular material or a high molecular material.

[0196] The second electrode UE may be disposed on the light emitting layer IL. The second electrode UE may be a common electrode completely formed on the light emitting layer IL and the pixel defining film PDL. The second electrode UE may be a transparent electrode or a semi-transparent electrode.

[0197] The encapsulation layer TFE may be arranged on the second electrode UE. The encapsulation layer TFE may prevent or substantially prevent moisture, air and / or the like that may be introduced from the outside from penetrating into the light emitting element EL. The encapsulation layer TFE may include a thin film encapsulation structure (e.g., may be formed thereof), and may include one or more organic films and one or more inorganic films.

[0198] although Fig.15 It is illustrated that the light emitting element layer LDL includes an organic light emitting element, but the present disclosure is not limited thereto. For example, in another embodiment, the light emitting element layer LDL may include any suitable kind of light emitting element, such as an inorganic light emitting element and / or the like.

[0199] The touch sensing layer TSP may be disposed on the light emitting element layer LDL. The touch sensing layer TSP may include a touch electrode TE disposed at (eg, in or on) the display area DA (or at the sensing area SA).

[0200] The touch sensing layer TSP may include a third conductive layer YTML1 , a fourth insulating layer INS4 , a fourth conductive layer YTML2 , and a fifth insulating layer INS5 .

[0201] The third conductive layer YTML1 may be disposed on the encapsulation layer TFE, and may include a first connection pattern CNP1.

[0202] The fourth insulating layer INS4 may be disposed on the third conductive layer YTML1. In addition, the fourth insulating layer INS4 may be disposed on the third conductive layer YTML1 and on the encapsulation layer TFE partially exposed by the third conductive layer YTML1.

[0203] The fourth conductive layer YTML2 may be disposed on the fourth insulating layer INS4, and may include the first touch electrode TE1, the second connection pattern CNP2, and the second touch electrode TE2 (eg, refer to FIG. 1 ). Fig.14 ). The first touch electrode TE1 may make contact with or be connected to the first connection pattern CNP1 through a contact hole extending through (eg, passing through) the fourth insulating layer INS4.

[0204] The fifth insulating layer INS5 may be disposed on the fourth conductive layer YTML2 , and may be disposed over a surface (eg, over the entire surface) of the encapsulation layer TFE.

[0205] The data line DL and the touch electrode TE (eg, Fig.15 A second parasitic capacitor Cpar2 may be formed between the data line DL and the touch electrode TE (eg, TE1 in FIG. 1 ). Fig.15TE1 in the figure), and at least one insulating layer (eg, a third insulating layer INS3, a pixel defining film PDL, and / or the like) arranged between the data line DL and the touch electrode TE may configure (eg, may form) a second parasitic capacitor Cpar2.

[0206] As mentioned above Figure 5 As described, when the chopper controller 320 of the source driver 130 (eg, referring to Figure 3 ) operation and through the output buffer 370 (for example, refer to Figure 3 )When noise occurs in the data line DL (or in the data signal transmitted through the data line DL), the second parasitic capacitor Cpar2 may affect the touch electrode TE (or the driving signal and / or the sensing signal flowing through the touch electrode TE), or may correspond to (e.g., may act as) touch noise.

[0207] The touch sensing layer TSP may be driven independently (e.g., separately) from the display layer DISP. For example, a period for scanning the touch sensing layer TSP (or a time point for outputting a sensing signal) may not be synchronized (e.g., may not correspond) with a driving period (or a time point for transmitting a chopping control signal) of the display layer DISP. In this case, it may be difficult to exclude (e.g., remove or ignore) touch noise due to noise of the data line DL.

[0208] According to various embodiments of the present disclosure, the amplitude of the touch noise may be changed for each display device, and the touch noise may not occur, depending on the structure of the display layer DISP, the arrangement of the data lines DL at (e.g., in or on) the display layer DISP, the structure of the touch sensing layer TSP, the connection structure of the touch sensing layer TSP to the display layer DISP, and / or the like.

[0209] Therefore, as reference Figures 7 to 11 As described, the display device 1 according to various embodiments of the present disclosure may include a chopping controller 320, wherein the chopping controller 320 is capable of varying (or changing) the slew rate or conversion speed of the chopping control signal CCS during the manufacturing process of the display device 1, and the chopping controller 320 may operate based on the set slew rate (or the set value of the selection signal CHOP_SLOPE_CON[1:0]). For example, in various embodiments, the chopping controller 320 may set the slew rate of the chopping control signal CCS (or the selection signal CHOP_SLOPE_CON[1:0] for determining the slew rate (for example, refer to Fig. 9 )). In various embodiments, the slew rate can decrease as the touch noise increases.

[0210] Fig.16It is shown by Fig.14 FIG. 1 is a view of an example of a sense signal measured by a touch sensing layer. Fig.16 shows the flow through the reference Fig.14 The sensing signal of the touch electrode TE (eg, a touch electrode column configured by the second touch electrode TE2) described above may be sequentially transmitted along the touch electrode column.

[0211] Reference Fig.15 and Fig.16 , when due to (for example, due to) Figure 7 When noise occurs in the data line DL due to the operation of the chopper controller 320 , touch noise may occur in a sensing signal output through the touch electrode columns overlapping the data line DL at a corresponding time point.

[0212] Therefore, the display device 1 according to various embodiments of the present disclosure can change the chopping control signal CCS (for example, refer to Figure 7 ) to reduce or eliminate touch noise.

[0213] Although one or more exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings, it should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various modifications in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A source driver, comprising: a gamma voltage generator configured to generate gamma voltages having voltage levels different from each other; a digital-to-analog converter configured to generate a data voltage corresponding to a grayscale value using the gamma voltage; an output buffer unit, the output buffer unit being configured to output the data voltage; as well as a chopping controller configured to generate a chopping control signal and provide the chopping control signal to the output buffer unit; Wherein, the output buffer unit comprises: an amplifier connected to an output terminal of the digital-to-analog converter; and a chopping circuit configured to periodically change the polarity of the offset of the amplifier in response to the chopping control signal, wherein the chopper controller is configured to vary a slew rate of the chopper control signal, and Wherein, the chopper controller comprises: a logic control circuit configured to generate a first control signal including a pulse; a level shifter configured to generate a second control signal by shifting up a level of the first control signal; and A buffer circuit is configured to output the second control signal as the chopping control signal.

2. The source driver according to claim 1, wherein: The chopper circuit comprises: a first switch connected between an input node and a first input terminal of the amplifier; a second switch connected between the input node and a second input terminal of the amplifier; a third switch connected between the first input terminal of the amplifier and an output terminal of the amplifier; and a fourth switch connected between the second input terminal of the amplifier and the output terminal of the amplifier, and Wherein, the first to fourth switches are configured to operate in response to the chopping control signal.

3. The source driver according to claim 2, wherein: A parasitic capacitor is formed between an output node connected to the output terminal of the amplifier and a control line for transmitting the chopping control signal to the third switch.

4. The source driver according to claim 1, wherein: The buffer circuit is also configured to vary the buffer size.

5. The source driver according to claim 4, wherein: The slew rate corresponds to a rate at which the chopping control signal follows the second control signal.

6. The source driver according to claim 4, wherein: The buffer circuit comprises: a sub-buffer connected in parallel to the chopper circuit; and sub switches that respectively connect the sub buffers to output terminals of the level shifter, and At least one of the sub-switches is configured to be turned on in response to a selection signal.

7. The source driver according to claim 6, wherein: The sub-buffers have the same buffer size as each other.

8. The source driver according to claim 6, wherein: The sub-buffers have different buffer sizes from each other.

9. The source driver according to claim 4, wherein: The slew rate of the chopping control signal decreases as the buffer size of the buffer circuit decreases.

10. A display device, comprising: A display panel, the display panel comprising data lines and pixels connected to the data lines; as well as A source driver configured to provide a data voltage to the data line, the source driver comprising: a digital-to-analog converter configured to generate the data voltage; an output buffer unit configured to output the data voltage to the data line; and a chopping controller configured to generate a chopping control signal and provide the chopping control signal to the output buffer unit, Wherein, the output buffer unit comprises: an amplifier connected between the digital-to-analog converter and the data line; and a chopping circuit configured to periodically change the polarity of the offset of the amplifier in response to the chopping control signal, wherein the chopper controller is configured to vary a slew rate of the chopper control signal, and Wherein, the chopping control comprises: a logic control circuit configured to generate a first control signal including a pulse; a level shifter configured to generate a second control signal by shifting up a level of the first control signal; and A buffer circuit is configured to output the second control signal as the chopping control signal.

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