Switching regulator and method of operating the same

Abstract

A switching regulator configured to generate a level-controlled output voltage based on an input voltage, the switching regulator comprising: an inductor; an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor; at least two flying capacitors; and a plurality of switches configured to form an electrical connection when the switching regulator operates in a first operating mode to alternately charge each of the at least two flying capacitors using the input voltage, and to provide a first boosted voltage to the inductor using the charged flying capacitors of the at least two flying capacitors.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0027642 filed on March 11, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to generation of a power supply voltage, and more particularly, to a switching regulator and an operating method thereof. Background Art

[0004] A power supply voltage can be generated to power an electronic component, and the level of the power supply voltage provided to the electronic component can be changed to reduce the power consumption of the electronic component. For example, in the case of a digital circuit that processes a digital signal, a low level of power supply voltage can be provided when relatively low performance is expected, and a high level of power supply voltage can be provided when relatively high performance is expected. Therefore, a switching regulator that generates power supply voltages of various levels can be used, and the switching regulator can quickly change the voltage level and generate a power supply voltage with reduced noise in a limited design space. Therefore, a compact switching regulator that realizes efficient generation of power supply voltages of various levels has been studied. Summary of the invention

[0005] The inventive concept provides a switching regulator for improving reliability and efficiency of a voltage conversion operation for generating an output voltage and a method of operating the switching regulator.

[0006] According to one aspect of the inventive concept, a switching regulator is provided, which is configured to generate a level-controlled output voltage according to an input voltage. The switching regulator includes: an inductor; an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor; at least two flying capacitors; and a plurality of switches configured to form an electrical connection when the switching regulator operates in a first operating mode to alternately charge each of the at least two flying capacitors using the input voltage, and to provide a first boosted voltage to the inductor using the charged flying capacitors of the at least two flying capacitors.

[0007] According to an aspect of the inventive concept, there is provided a switching regulator configured to generate a level-controlled output voltage according to an input voltage. The switching regulator includes: an inductor; an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor; a first flying capacitor configured to provide a first boosted voltage to the inductor; a second flying capacitor configured to provide a second boosted voltage to the inductor; a first switching circuit connected to the first flying capacitor and configured to form an electrical connection to perform the following operations: connecting the first flying capacitor to the inductor when the switching regulator operates in a first phase of a first operating mode, the first operating mode is based on an interleaved switching control scheme, and charging the first flying capacitor using the input voltage when the switching regulator operates in a second phase of the first operating mode; and a second switching circuit connected to the second flying capacitor and configured to form an electrical connection to perform the following operations: charging the second flying capacitor using the input voltage when the switching regulator operates in the first phase of the first operating mode; and connecting the second flying capacitor to the inductor when the switching regulator operates in the second phase of the first operating mode.

[0008] According to one aspect of the present invention, a switching regulator is provided, which is configured to generate an output voltage according to an input voltage. The switching regulator includes: an inductor; an output capacitor configured to generate the output voltage based on a current flowing through the inductor; a plurality of first flying capacitors; and a first switching circuit configured to provide the inductor with a first boosted voltage boosted from the input voltage in one of a buck-boost mode or a boost mode by forming an electrical connection to perform the following operations: charging each of the plurality of first flying capacitors using the input voltage in a first stage, and connecting the plurality of first flying capacitors in series to the inductor in a second stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Some example embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a switching regulator according to an example embodiment;

[0011] FIG. 2A to FIG. 3B is a schematic diagram of a switching regulator according to an example embodiment;

[0012] Figure 4 is a circuit diagram of a switching regulator 20 according to an example embodiment;

[0013] FIG. 5A to FIG. 5D is a circuit diagram of a switching regulator 20 operating in a second boost mode as a first operation mode according to an example embodiment, and Figure 5E is a timing diagram illustrating the operation of the switching regulator 20 in the second boost mode according to some example embodiments, wherein FIG. 5A to FIG. 5D The corresponding states of are repeated sequentially;

[0014] Fig. 6A and Figure 6B is a circuit diagram of a switching regulator 20 operating in a buck mode as a second operation mode according to an example embodiment, and Figure 6C is a timing diagram showing the operation of the switching regulator 20 in the buck mode, wherein Fig. 6A and Figure 6B The corresponding state is repeated;

[0015] 7A to 7C is a circuit diagram of a switching regulator 20 operating in a buck-boost mode as a second operation mode according to an example embodiment, and Fig.7D is a timing diagram illustrating the operation of the switching regulator 20 in the buck-boost mode according to some example embodiments, wherein 7A to 7C The corresponding states of are repeated sequentially;

[0016] Fig. 8A and Figure 8B is a circuit diagram of a switching regulator 20 operating in a first boost mode as a second operation mode according to an example embodiment, and Figure 8C is a diagram showing a method according to some example embodiments Fig. 8A and Figure 8B A timing diagram of the operation of the switching regulator 20;

[0017] Fig. 9 is a circuit diagram of a switching regulator 30 including a single switching circuit according to an example embodiment;

[0018] Fig. 10A and Fig. 10B is a circuit diagram of a switching regulator 30 including a single switching circuit operating in a second boost mode according to an example embodiment, and Fig. 10C is a diagram showing a method according to some example embodiments Fig. 10A and Fig. 10B A timing diagram of the operation of the switching regulator 30 including a single switching circuit;

[0019] Fig.11 is a circuit diagram of a switching regulator 30 including two switching circuits according to an example embodiment;

[0020] Fig.12is a table of conditions for setting an operation mode of a switching regulator according to an example embodiment;

[0021] Fig.13 is a flow chart of a method of operating a switching regulator according to an example embodiment;

[0022] Fig.14 According to an example embodiment Fig.13 Detailed flowchart of operation S140 in FIG.

[0023] Fig.15 is a schematic diagram of a system according to an example embodiment; and

[0024] Fig.16 is a block diagram of a wireless communication device according to an example embodiment. DETAILED DESCRIPTION

[0025] In this specification, the on-state of a switch may refer to a state in which both ends of the switch are electrically connected to each other, and the off-state of a switch may refer to a state in which both ends of the switch are electrically disconnected from each other. In addition, at least two elements electrically connected to each other via a switch in an on state and / or a conductive line may be simply referred to as "connected", and at least two elements always electrically connected to each other via a conductive line or the like may be referred to as "coupled".

[0026] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0027] Figure 1 is a block diagram of a switching regulator 10 according to an example embodiment. The switching regulator 10 may receive an input voltage VIN through an input node 13 and output an output voltage VO through an output node 14. The output voltage VO may be used as a power supply voltage for other electronic components (and / or loads).

[0028] like Figure 1As shown in , the switching regulator 10 may include a switching circuit 11, a controller 12, a plurality of flying capacitors (e.g., a first flying capacitor CFa and a second flying capacitor CFb), an inductor L and / or an output capacitor CO. In some embodiments, the elements of the switching regulator 10 may be included in a single semiconductor package. In some embodiments, the switching regulator 10 may include a printed circuit board (PCB), and at least two elements of the switching regulator 10 may be mounted on the PCB as separate semiconductor packages. According to some example embodiments, the operations described herein as being performed by the controller 12 may be performed by a processing circuit. As used in the present disclosure, the term "processing circuit" may refer to, for example, hardware including a logic circuit; a hardware / software combination such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. According to some example embodiments, the operations described herein as being performed by the switching regulator 10 may be performed based on a control signal generated by the controller 12.

[0029] The switching regulator 10 may refer to an electronic circuit configured to generate an output voltage VO by turning on or off an element. For example, the switching circuit 11 of the switching regulator 10 may turn on or off at least one switch included in the switching circuit 11 based on a switching control signal CS_SW from the controller 12, and thus may control a path of an inductor current IL flowing through the inductor L. Through the operation of the switching circuit 11, the switching regulator 10 may operate as various converters, which will be described below.

[0030] As an example of the switching regulator 10, a direct current (DC)-DC converter can generate a DC voltage (e.g., an output voltage VO) based on a DC voltage (e.g., an input voltage VIN). For example, a buck converter can generate an output voltage VO of a lower level than the input voltage VIN, and can be referred to as a buck converter. A boost converter can generate an output voltage VO of a higher level than the input voltage VIN, and can be referred to as a boost converter. In addition, the boost converter can operate in multiple boost modes. For example, the boost converter can operate in such a boost mode, in which the ratio of the level of the input voltage VIN to the level of the output voltage VO is equal to or lower than a reference value, or the boost converter can operate in such a boost mode, in which the ratio of the level of the input voltage VIN to the level of the output voltage VO exceeds a reference value. A buck-boost (or boost / buck) converter can generate an output voltage VO of a lower or higher level than the input voltage VIN. In the following, the switching regulator 10 will be described mainly with reference to a buck-boost DC-DC converter that generates an output voltage in various operating modes, but it should be understood that the example embodiments can be applied to different types of switching regulators 10, such as an AC-DC converter in which the input voltage VIN is an alternating current (AC) voltage. According to some example embodiments, the reference value can be a design parameter determined through empirical research.

[0031] In some embodiments, the switching regulator 10 can be set in a buck mode, a buck-boost mode, and / or one of multiple boost modes according to a target level of the output voltage VO. For example, the controller 12 can set the mode of the switching regulator 10 based on the input voltage VIN and the reference voltage VREF. In some embodiments, when the level of the output voltage VO is lower than about 90% of the input voltage VIN, the controller 12 may set the switching regulator 10 in the buck mode, when the level of the output voltage VO is equal to or higher than about 110% of the input voltage VIN and lower than about 150% of the input voltage VIN, the controller 12 may set the switching regulator 10 in the first boost mode (or normal boost mode), when the level of the output voltage VO is equal to or higher than about 150% of the input voltage VIN, the controller 12 may set the switching regulator 10 in the second boost mode (or extended boost mode), and when the level of the output voltage VO is equal to or higher than about 90% of the input voltage VIN and lower than more than 110% of the input voltage VIN, the controller 12 may set the switching regulator 10 in the buck-boost mode. Since the switching regulator 10 supports all modes in the buck mode, the buck-boost mode, and the boost mode, the level of the output voltage VO may vary in a wide range. According to some example embodiments, the reference voltage VREF may be a design parameter determined through empirical research.

[0032] The switch circuit 11 may include a connection switch CSW. Figure 1 In the embodiment shown in the accompanying drawings of , the connection switch CSW is implemented as an N-channel metal oxide semiconductor (NMOS) transistor, but this is merely an example embodiment, and the inventive concept is not limited thereto. The connection switch CSW may be implemented as various semiconductor elements. Hereinafter, the connection switch CSW is a semiconductor element that may connect one end of each of the first flying capacitor CFa and the second flying capacitor CFb to the input node 13. The output terminal of the connection switch CSW may be branched into at least two current paths. For example, the current path may include a path for a current that charges each of the first flying capacitor CFa and the second flying capacitor CFb and a path for the inductor current IL toward the inductor L. Although for ease of description, in Figure 1 Only one connection switch CSW is shown in the figure, but according to some example embodiments, the switch circuit 11 may include more connection switches. According to some example embodiments, an appropriate switch control scheme may be applied to the switch circuit 11 in a specific operation mode to prevent or reduce excessive current flow in the connection switch CSW. According to some example embodiments, an appropriate circuit configuration may be applied to the switch circuit 11 in a specific operation mode to prevent or reduce excessive current flow in the connection switch CSW.

[0033] According to the example embodiment, the switch circuit 11 can be controlled using different switch control schemes according to the operation mode of the switching regulator 10, and thus the current flowing in the connection switch CSW can be prevented from exceeding a predetermined or determined level, or the occurrence of the current flowing in the connection switch CSW exceeding a predetermined or determined level can be reduced regardless of the operation mode (or the level of the output voltage VO) of the switching regulator 10. In other words, the current load on the connection switch CSW is reduced, the miniaturization of the connection switch CSW can be achieved, the design advantage of the switching regulator 10 can be brought, and the switching regulator 10 can perform reliable and efficient voltage conversion operations even at a high switching frequency, thereby widening the level range of the output voltage VO.

[0034] According to some embodiments, when the target level of the output voltage VO is equal to or higher than a reference level (e.g., a reference voltage level), the switch circuit 11 may be controlled by the controller 12 in a corresponding operation mode using a first switch control scheme. For example, when the target level of the output voltage VO is equal to or higher than the reference level, the controller 12 may set the switching regulator 10 in a second boost mode, and may provide a switch control signal CS_SW generated based on the first switch control scheme to the switch circuit 11 to generate an output voltage VO of a target level. In some phases of the switching cycle, the switch circuit 11 may perform a switching operation based on the switch control signal CS_SW, and may control the switch circuit 11 to output a current through one of a plurality of paths passing through the connection switch CSW. For example, the path may include a path toward each of the first flying capacitor CFa and the second flying capacitor CFb and a path toward the inductor L. According to some example embodiments, the reference level may be a design parameter determined by empirical research.

[0035] According to some embodiments, when the target level of the output voltage VO is lower than the reference level, the switch circuit 11 may be controlled by the controller 12 using the second switch control scheme in the corresponding operation mode. For example, when the target level of the output voltage VO is lower than the reference level, the controller 12 may set the switching regulator 10 in the buck mode, the buck-boost mode, or the first boost mode according to the target level, and may provide the switch control signal CS_SW generated based on the second switch control scheme to the switch circuit 11 to generate the output voltage VO of the target level. In some phases of the switching cycle, the switch circuit 11 may perform a switching operation based on the switch control signal CS_SW, and may control the switch circuit 11 to output current through at least two of a plurality of paths including the connection switch CSW.

[0036] As described above, when the target level of the output voltage VO is equal to or higher than the reference level (or when the switching regulator 10 operates in the second boost mode), the first switching control scheme may be used to control the switch circuit 11, thereby limiting the level of the current flowing in the connection switch CSW. When the target level of the output voltage VO is lower than the reference level (or when the switching regulator 10 operates in the buck mode, the buck-boost mode, or the first boost mode), the second switching control scheme may be used to control the switch circuit 11, because the level of the current flowing in the connection switch CSW is not sufficient to trigger the limitation.

[0037] According to some example embodiments, the switch circuit 11 may, under the control of the controller 12, provide the voltage boosted using the first flying capacitor CFa and the second flying capacitor CFb as the applied voltage VX to the inductor L in some phases of the switching cycle in a specific operation mode. In some embodiments, the applied voltage VX may be about at least three times the input voltage VIN. However, this is merely an example embodiment, and the inventive concept is not limited thereto. The switch circuit 11 may be connected to more flying capacitors and may provide the voltage boosted in proportion to the number of flying capacitors as the applied voltage VX to the inductor L. As described above, when the switch circuit 11 applies the voltage boosted to a high level to the inductor L in one phase of the switching cycle in a specific operation mode, the duration (or time) of the phase is reduced, and thus the important duration of the phase for charging each of the first flying capacitor CFa and the second flying capacitor CFb may be ensured, thereby allowing the level of the current passing through the connection switch CSW to charge each of the first flying capacitor CFa and the second flying capacitor CFb to be reduced. Therefore, the current load on the connection switch CSW can be reduced in the stage for charging each of the first flying capacitor CFa and the second flying capacitor CFb. Fig. 9 The accompanying drawings describe this in detail.

[0038] Hereinafter, the operation of the switching regulator 10 will be described in detail.

[0039] The switch circuit 11 may receive a switch control signal CS_SW from the controller 12 and may further include a plurality of switches that are turned on or off in response to the switch control signal CS_SW. The switch circuit 11 may control the inductor current IL flowing through the inductor L by controlling the voltage provided to the inductor L based on the switch control signal CS_SW. For example, the switch circuit 11 may sense the inductor current IL in response to the switch control signal CS_SW to charge the output capacitor CO, and may control the inductor current IL in response to the switch control signal CS_SW to prevent the output capacitor CO from being overcharged or to reduce the occurrence of overcharging of the output capacitor CO. When there is a load (e.g., Figure 4 When the load LD is provided, at least a portion of the inductor current IL can be provided to the load. Figure 4 An example of the switching circuit 11 is described in the accompanying drawings.

[0040] The inductor L and the output capacitor CO may be connected in series with each other, and thus the inductor current IL may be the same or substantially the same as the output transfer current ID when the current flowing to the controller 12 is ignored. The inductor current IL may depend on the voltage applied to the inductor L by the switch circuit 11 (eg, Figure 1 Here, the voltage of the node connected to the switching circuit 11 and the inductor L may be referred to as an applied voltage VX. In some embodiments, the capacitance of the output capacitor CO may be determined based on the current supplied to (or consumed by) a load connected to the output terminal 14 of the switching regulator 10. In some embodiments, the inductance of the inductor L may be determined based on the capacitance of the output capacitor CO and / or the switching frequency. In some embodiments, the capacitance of the first flying capacitor CFa and the second flying capacitor CFb may be determined based on the current supplied to the load, the switching frequency, the input voltage VIN, and / or the output voltage VO.

[0041] The controller 12 may generate a switch control signal CS_SW based on a reference voltage VREF and an output voltage VO. For example, the controller 12 may generate a feedback voltage by dividing the output voltage VO using at least two resistors, compare the feedback voltage with the reference voltage VREF, and generate a switch control signal CS_SW having an adjusted duty cycle, the adjusted duty cycle making the feedback voltage equal to or close to the reference voltage VREF, wherein the duty cycle involves on / off control. Therefore, the level of the output voltage VO may be determined based on the level of the reference voltage VREF, and the level of the output voltage VO may be changed by changing the level of the reference voltage VREF. In some embodiments, in order to perform the above operations, the controller 12 may detect the inductor current IL or the output transfer current II) and generate a switch control signal CS_SW based on the detected current level. In some embodiments, the controller 12 may generate a switch control signal CS_SW based on the output voltage VO and the current of the output node 14. In some embodiments, the controller 12 may include at least one comparator and at least one logic gate.

[0042] The controller 12 may generate a switch control signal CS_SW so that the switch circuit 11 and the first flying capacitor CFa and the second flying capacitor CFb connected to the switch circuit 11 are used as a charge pump, and the applied voltage VX boosted by the charge pump may be provided to the inductor L in one phase of the switching cycle. In some embodiments, the boost voltage may be a multiple of the input voltage VIN according to the connection between the switch circuit 11 and the first flying capacitor CFa and the second flying capacitor CFb. By such a configuration of the switch circuit 11, the output transfer current ID provided to the output capacitor CO and the load may be continuously changed. With the continuous change of the output transfer current ID, the level of the output transfer current ID may change rapidly, and the noise of the output voltage VO may be reduced.

[0043] The output voltage VO generated by the switching regulator 10 may be used as a power supply voltage for providing power to electronic components, which may be referred to as loads of the switching regulator 10. For example, the output voltage VO may be provided to a digital circuit that processes a digital signal, an analog circuit that processes an analog signal, and / or a radio frequency (RF) circuit that processes an RF signal.

[0044] FIG. 2A to FIG. 3B is a schematic diagram of a switching regulator according to an example embodiment. Specifically, Figure 2A and Figure 2B is a circuit diagram showing the operation of the switching regulator 20 in the first operation mode MODE_1, and Figure 3A and Figure 3B 2 is a circuit diagram showing the operation of the switching regulator 20 in the second operation mode MODE_2. FIG. 2A to FIG. 3B When describing, redundant descriptions are omitted.

[0045] Reference Figure 2A, the switching regulator 20 may include a first switching circuit 21_1, a second switching circuit 21_2, a controller 22, an input node 23, an output node 24, a first flying capacitor CFa, a second flying capacitor CFb, an inductor L and / or an output capacitor CO. The first switching circuit 21_1 may include a first connection switch CSW1 and / or a plurality of switches, and may be connected to the first flying capacitor CFa. The first connection switch CSW1 may selectively connect one end of the first flying capacitor CFa to the input node 23. The second switching circuit 21_2 may include a second connection switch CSW2 and / or a plurality of switches, and may be connected to the second flying capacitor CFb. The second connection switch CSW2 may selectively connect one end of the second flying capacitor CFb to the input node 23. According to some example embodiments, the operations described herein as being performed by the controller 22 may be performed by a processing circuit. According to some example embodiments, the operations described herein as being performed by the switching regulator 20 may be performed based on a control signal generated by the controller 22.

[0046] According to an embodiment, the first switch circuit 21_1 and the second switch circuit 21_2 may be connected in parallel to each other between the input node 23 and the inductor L. The controller 22 may control the first switch circuit 21_1 and the second switch circuit 21_2 individually. The first switch circuit 21_1 and the second switch circuit 21_2 controlled using an interleaved switching control scheme when the switching regulator 20 operates in the first operation mode MODE_1 will be described below. It is assumed that the first operation mode MODE_1 is a mode (e.g., a second boost mode) set when the target level of the output voltage VO is equal to or higher than the reference level as described above. However, this is merely an example embodiment, and the inventive concept is not limited thereto. The first operation mode MODE_1 may also include at least one operation mode of various operation modes including a buck-boost mode and a first boost mode.

[0047] In the first phase of the switching cycle, the first switch circuit 21_1 may be controlled based on the first switch control signal CS_SW1 received from the controller 22 to allow a first current I11 to pass through the first connection switch CSW1, wherein the first current I11 is used to provide the voltage boosted by the first flying capacitor CFa as the applied voltage VX to the inductor L. In the first phase, the second switch circuit 21_2 may be controlled based on the second switch control signal CS_SW2 received from the controller 22 to allow a second current I22 to pass through the second connection switch CSW2, wherein the second current I22 is used to charge the second flying capacitor CFb.

[0048] Reference Figure 2B, in the second phase of the switching cycle, the first switch circuit 21_1 may be controlled based on the first switch control signal CS_SW1 received from the controller 22 to allow the third current I12 to pass through the first connection switch CSW1, wherein the third current I12 is used to charge the first flying capacitor CFa. In the second phase, the second switch circuit 21_2 may be controlled based on the second switch control signal CS_SW2 received from the controller 22 to allow the fourth current I21 to pass through the second connection switch CSW2, wherein the fourth current I21 is used to provide the voltage boosted by the second flying capacitor CFb as the applied voltage VX to the inductor L. As described above, the controller 22 performs switching control so that each of the first connection switch CSW1 and the second connection switch CSW2 can pass the current (e.g., I11 and I22, or I12 and I21) through the corresponding path in the first phase and the second phase, respectively, thereby reducing the current load on each of the first connection switch CSW1 and the second connection switch CSW2.

[0049] In the embodiment, according to the reference Figure 2A and Figure 2B The interleaved switching control scheme described, wherein the phase in which the first flying capacitor CFa connected to the first switch circuit 21_1 is connected to the inductor L may be different from the phase in which the second flying capacitor CFb connected to the second switch circuit 21_2 is connected to the inductor L, and wherein the phase in which the first flying capacitor CFa is charged using the input voltage VIN may be different from the phase in which the second flying capacitor CFb is charged using the input voltage VIN. In other words, the interleaved switching control scheme may refer to a method in which the first switch circuit 21_1 and the second switch circuit 21_2 are controlled so that the first flying capacitor CFa and the second flying capacitor CFb are alternately charged using the input voltage BIN and the first flying capacitor CFa and the second flying capacitor CFb are alternately connected to the inductor L in different phases of the switching cycle.

[0050] The following will refer to Figure 3A and Figure 3B The first switch circuit 21_1 and the second switch circuit 21_2 controlled using the synchronous switch control scheme when the switching regulator 20 operates in the second operation mode MODE_2 are described. It is assumed that the second operation mode MODE_2 is a mode (e.g., buck mode, buck-boost mode, or first boost mode) set when the target level of the output voltage VO is lower than the reference level as described above. However, this is only an example embodiment, and the inventive concept is not limited thereto. The second operation mode MODE_2 may include other operation modes in addition to the first operation mode MODE_1.

[0051] Reference Figure 3A , in a specific phase of the switching cycle, the first switch circuit 21_1 can be controlled based on the first switch control signal CS_SW1' received from the controller 22 to allow the first current I11' and the second current I12' to pass through the first connection switch CSW1. The first current I11' is used to provide the input voltage VIN to the inductor L, and the second current I12' is used to charge the first flying capacitor CFa. In the first phase, the second switch circuit 21_2 can be controlled based on the second switch control signal CS_SW2' to allow the third current I21' and the fourth current I22' to pass through the second connection switch CSW2. The third current I21' is used to provide the input voltage VIN to the inductor L, and the fourth current I22' is used to charge the second flying capacitor CFb. As described above, in the second operating mode MODE_2 in which the current load on each of the first connecting switch CSW1 and the second connecting switch CSW2 is not expected to be too large, the controller 22 can perform switching control so that each of the first connecting switch CSW1 and the second connecting switch CSW2 can allow current (e.g., I11', I12', I21' and I22') to pass through the corresponding path in one stage.

[0052] The synchronous switching control scheme may refer to a method of identically or similarly controlling the first and second switching circuits 21_1 and 21_2 so that the first and second flying capacitors CFa and CFb are charged and / or connected to the inductor L in one phase.

[0053] Reference Figure 3B In some embodiments, when the switching regulator 20 is in the second operating mode MODE_2, the controller 22 may select one of the first switching circuit 21_1 and the second switching circuit 21_2 and use the selected switching circuit to generate the output voltage VO. Specifically, the controller 22 may select the first switching circuit 21_1 and provide the first switching control signal CS_SW1″ to the first switching circuit 21_1, so that the first switching circuit 21_1 is controlled to use the first current I11′ for providing the input voltage VIN to the inductor L and the second current I12′ for charging the first flying capacitor CFa through the first connecting switch CSW1 in a specific phase of the switching cycle. The controller 22 may disable the second switching circuit 21_2 (e.g., disconnect the second switching circuit 21_2 from the input voltage VIN and / or the inductor L) by providing the second switching control signal CS_SW2″ to the second switching circuit 21_2. The switching regulator 20 may reduce power consumption by disabling unselected switching circuits in the second operating mode MODE_2.

[0054] Figure 4 is a block diagram of a switching regulator 20 according to an example embodiment.

[0055] Reference Figure 4 , the switching regulator 20 may include a first switching circuit 21_1, a second switching circuit 21_2, a controller 22, a first flying capacitor CFa, a second flying capacitor CFb, an inductor L and / or an output capacitor CO. A load LD may be connected to the switching regulator 20. The components already referred to will be omitted. FIG. 2A to FIG. 3B Redundant description given. Figure 4 The switches shown in the drawings of FIG. 21 may all have a structure that electrically connects or disconnects both ends according to a switch control signal (eg, CS_SW1 or CS_SW2) provided from the controller 22. The first switch SW1_1 of the first switch circuit 21_1 may correspond to Figure 2A The first connection switch CSW1 in the embodiment, and the fifth switch SW2_1 may correspond to Figure 2A The second connecting switch CSW2 in.

[0056] The first switch circuit 21_1 may include first to fourth switches SW1_1 to SW1_4. The first switch SW1_1 and the second switch SW1_2 may be sequentially connected in series between the input node and one end of the inductor L, and the third switch SW1_3 and the fourth switch SW1_4 may be sequentially connected in series between the input node and the ground node. The first flying capacitor CFa may have one end connected to the first switch SW1_1 and the second switch SW1_2 and one end connected to the third switch SW1_3 and the fourth switch SW1_4.

[0057] The second switch circuit 21_2 may include a fifth switch SW2_1 to a ninth switch SW2_5. The fifth switch SW2_1 and the sixth switch SW2_2 may be sequentially connected in series between the input node and the inductor L, the seventh switch SW2_3 and the eighth switch SW2_4 may be sequentially connected in series between the input node and the ground node, and the ninth switch SW2_5 may be connected between one end of the sixth switch SW2_2 and the ground node. According to some example embodiments, as described below, the controller 22 may generate a first switch control signal CS_SW1 and a second switch control signal CS_SW2 so that the first flying capacitor CFa, the first switch circuit 21_1, the second flying capacitor CFb, and the second switch circuit 21_2 are used as a charge pump. The controller 22 may generate a first switch control signal CS_SW1 and a second switch control signal CS_SW2 so that the applied voltage VX boosted by the charge pump is applied to the inductor L.

[0058] In an embodiment, the controller 22 may control the first switch circuit 21_1 and the second switch circuit 21_2 using different switch control schemes according to the operation mode of the switching regulator 20. In other words, the controller 22 may reduce the current load on the first switch SW1_1 of the first switch circuit 21_1 and the fifth switch SW2_1 of the second switch circuit 21_2 by limiting the current flowing in the first switch SW1_1 and the fifth switch SW2_1 in multiple phases of the switching cycle in the first operation mode (e.g., the second boost mode).

[0059] FIG. 5A to FIG. 5D is a circuit diagram of a switching regulator 20 operating in a second boost mode as a first operation mode according to an example embodiment, and Figure 5E is a timing diagram illustrating the operation of the switching regulator 20 in the second boost mode according to some example embodiments, wherein FIG. 5A to FIG. 5D The corresponding states are repeated sequentially. Figure 5A The switching regulator 20 is shown in the first phase P1. Figure 5B FIG. 2 shows the switching regulator 20 in the second phase P2. Figure 5C The switching regulator 20 is shown in the third phase P3, and Figure 5D FIG. 2 shows the switching regulator 20 in the fourth phase P4. FIG. 5A to FIG. 5D In FIG. 1 , the path through which the current flows and the switch in the on state are shown in bold.

[0060] Reference Figure 5A In the second boost mode, the controller 22 can generate a first switch control signal CS_SW1a and a second switch control signal CS_SW2a in the first stage P1, so that the second switch SW1_2 and the third switch SW1_3 of the first switch circuit 21_1 and the fifth switch SW2_1 and the eighth switch SW2_4 of the second switch circuit 21_2 are turned on, and other switches (for example, the first switch SW1_1, the fourth switch SW1_4, the sixth switch SW2_2, the seventh switch SW2_3 and the ninth switch SW2_5) are turned off.

[0061] Both ends of the first flying capacitor CFa may be connected to the input node and the inductor L, respectively. The applied voltage VX boosted by the first flying capacitor CFa may be provided to the inductor L through the second switch SW1_2 in the on state. Both ends of the second flying capacitor CFb may be connected to the input node and the ground node, respectively, and the second flying capacitor CFb may be charged with the input voltage VIN. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the third switch SW1_3, the first flying capacitor CFa, and the second switch SW1_2. Therefore, as Figure 5EAs shown, the inductor current IL may gradually increase in the first phase P1 , and the applied voltage VX provided to the inductor L may be equal to or close to the boost voltage, for example, a voltage equal to approximately twice the input voltage VIN.

[0062] Reference Figure 5B In the second boost mode, the controller 22 can generate the first switch control signal CS_SW1b and the second switch control signal CS_SW2b in the second stage P2, so that the first switch SW1_1 and the second switch SW1_2 of the first switch circuit 21_1 and the fifth switch SW2_1 and the eighth switch SW2_4 of the second switch circuit 21_2 are turned on, and the other switches (for example, the third switch SW1_3, the fourth switch SW1_4, the sixth switch SW2_2, the seventh switch SW2_3 and the ninth switch SW2_5) are turned off.

[0063] In the second phase P2, both ends of the first flying capacitor CFa may be floated, and both ends of the second flying capacitor CFb may be connected to the input node and the ground node, respectively, as in the first phase P1, and thus the second flying capacitor CFb may be charged using the input voltage VIN. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the first switch SW1_1 and the second switch SW1_2 in the on state. Therefore, as Figure 5E As shown in , the inductor current IL may gradually decrease in the second phase P2 , and the applied voltage VX provided to the inductor L may be equal to or close to the input voltage VIN.

[0064] Reference Figure 5C In the second boost mode, the controller 22 can generate a first switch control signal CS_SW1c and a second switch control signal CS_SW2c in the third stage P3, so that the first switch SW1_1 and the fourth switch SW1_4 of the first switch circuit 21_1 and the sixth switch SW2_2 and the seventh switch SW2_3 of the second switch circuit 21_2 are turned on, and other switches (for example, the second switch SW1_2, the third switch SW1_3, the fifth switch SW2_1, the eighth switch SW2_4 and the ninth switch SW2_5) are turned off.

[0065] Both ends of the first flying capacitor CFa may be connected to the input node and the ground node, respectively, and the first flying capacitor CFa may be charged using the input voltage VIN. Both ends of the second flying capacitor CFb may be connected to the input node and the inductor L, respectively, and the applied voltage VX boosted by the second flying capacitor CFb is provided to the inductor L through the sixth switch SW2_2 in the on state. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the seventh switch SW2_3, the second flying capacitor CFb, and the sixth switch SW2_2. Therefore, as Figure 5E As shown in , the inductor current IL may gradually increase in the third phase P3 , and the applied voltage VX provided to the inductor L may be equal to or close to the boost voltage, for example, a voltage equal to approximately twice the input voltage VIN.

[0066] Reference Figure 5D In the second boost mode, the controller 22 can generate a first switch control signal CS_SW1d and a second switch control signal CS_SW2d in the fourth stage P4, so that the first switch SW1_1 and the fourth switch SW1_4 of the first switch circuit 21_1 and the fifth switch SW2_1 and the sixth switch SW2_2 of the second switch circuit 21_2 are turned on, and other switches (for example, the second switch SW1_2, the third switch SW1_3, the seventh switch SW2_3, the eighth switch SW2_4 and the ninth switch SW2_5) are turned off.

[0067] In the fourth phase P4, both ends of the first flying capacitor CFa may be connected to the input node and the ground node, respectively, as in the third phase P3, and thus the first flying capacitor CFa may be charged using the input voltage VIN. Both ends of the second flying capacitor CFb may float. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the fifth switch SW2_1 and the sixth switch SW2_2 in the on state. Therefore, as Figure 5E As shown in , the inductor current IL may gradually decrease in the fourth phase P4, and the applied voltage VX provided to the inductor L may be equal to or close to the input voltage VIN.

[0068] As described above, in the second boost mode, the controller 22 may control the first switch circuit 21_1 and the second switch circuit 21_2 based on the interleaved switch control scheme so that the first flying capacitor CFa and the second flying capacitor CFb are alternately charged and connected to the inductor L in different phases. FIG. 5A to FIG. 5D The operation of the switching regulator 20 in the first stage P1 to the fourth stage P4 shown in FIG. 1 is only an example embodiment, and the inventive concept is not limited thereto. Figure 5D The operation of the switching regulator 20 is replaced by Figure 5B The switching regulator 20 operates in the second phase P2 and can be used Figure 5B The operation of the switching regulator 20 is replaced by Figure 5D The switching regulator 20 operates in the fourth phase P4.

[0069] Fig. 6A and Figure 6B is a circuit diagram of a switching regulator 20 operating in a buck mode as a second operation mode according to an example embodiment, and Figure 6C is a timing diagram showing the operation of the switching regulator 20 in the buck mode, wherein Fig. 6A and Figure 6B The corresponding status is repeated. Fig. 6A The switching regulator 20 is shown in the first phase P1, and Figure 6B The switching regulator 20 is shown in the second phase P2. Fig. 6A and Figure 6B In FIG. 1 , the path through which the current flows and the switch in the on state are shown in bold.

[0070] Reference Fig. 6A In the buck mode, the controller 22 can generate a first switch control signal CS_SW1a and a second switch control signal CS_SW2a in the first stage P1, so that the first switch SW1_1, the second switch SW1_2 and the fourth switch SW1_4 of the first switch circuit 21_1 and the fifth switch SW2_1, the sixth switch SW2_2 and the eighth switch SW2_4 of the second switch circuit 21_2 are turned on, and other switches (for example, the third switch SW1_3, the seventh switch SW2_3 and the ninth switch SW2_5) are turned off.

[0071] Both ends of each of the first flying capacitor CFa and the second flying capacitor CFb may be connected to the input node and the ground node, respectively. The inductor L may be connected to the input node through the first switch circuit 21_1 and the second switch circuit 21_2 and thereby receive the applied voltage VX corresponding to the input voltage VIN. FIG. 5A to FIG. 5D Different, in Fig. 6A In the embodiment, the current for charging the first flying capacitor CFa and the current flowing to the inductor L may flow through the first switch SW1_1 simultaneously or at the same time, and the current for charging the second flying capacitor CFb and the current flowing to the inductor L may flow through the fifth switch SW2_1 simultaneously or at the same time. Figure 6C As shown in , the inductor current IL can gradually increase, and the applied voltage VX can be equal to or close to the input voltage VIN.

[0072] Reference Figure 6BIn the buck mode, the controller 22 can generate a first switch control signal CS_SW1b and a second switch control signal CS_SW2b in the second stage P2, so that the first switch SW1_1 and the fourth switch SW1_4 of the first switch circuit 21_1 and the fifth switch SW2_1, the eighth switch SW2_4 and the ninth switch SW2_5 of the second switch circuit 21_2 are turned on, and other switches (for example, the second switch SW1_2, the third switch SW1_3, the sixth switch SW2_2 and the seventh switch SW2_3) are turned off.

[0073] Both ends of each of the first flying capacitor CFa and the second flying capacitor CFb can be connected to the input node and the ground node, respectively. The inductor L can be connected to the ground node through the second switch circuit 21_2 and thereby receive an applied voltage VX corresponding to the ground voltage. Figure 6C As shown in , the inductor current IL can gradually decrease, and the applied voltage VX can be equal to or close to the ground voltage.

[0074] 7A to 7C is a circuit diagram of a switching regulator 20 operating in a buck-boost mode as a second operation mode according to an example embodiment, and Fig.7D is a timing diagram illustrating the operation of the switching regulator 20 in the buck-boost mode according to some example embodiments, wherein 7A to 7C The corresponding states are repeated sequentially. Fig. 7A The switching regulator 20 is shown in the first phase P1. Figure 7B The switching regulator 20 is shown in the second phase P2, and Figure 7C FIG. 2 shows the switching regulator 20 in the third phase P3. Fig. 7A to Figure 7C In FIG. 1 , the path through which the current flows and the switch in the on state are shown in bold.

[0075] Reference Fig. 7A In the buck-boost mode, the controller 22 can generate a first switch control signal CS_SW1a and a second switch control signal CS_SW2a in the first stage P1, so that the second switch SW1_2 and the third switch SW1_3 of the first switch circuit 21_1 and the sixth switch SW2_2 and the seventh switch SW2_3 of the second switch circuit 21_2 are turned on, and other switches (for example, the first switch SW1_1, the fourth switch SW1_4, the fifth switch SW2_1, the eighth switch SW2_4 and the ninth switch SW2_5) are turned off.

[0076] Both ends of each of the first flying capacitor CFa and the second flying capacitor CFb may be connected to the input node and the inductor L, respectively. The applied voltage VX boosted by the first flying capacitor CFa and the second flying capacitor CFb may be provided to the inductor L through the second switch SW1_2 and the sixth switch SW2_2 in the on state. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the first switch circuit 21_1 and the second switch circuit 21_2. Therefore, as Fig.7D As shown in , the inductor current IL may gradually increase in the first phase P1 , and the applied voltage VX provided to the inductor L may be equal to or close to the boost voltage, for example, a voltage equal to approximately twice the input voltage VIN.

[0077] Reference Figure 7B In the buck-boost mode, the controller 22 can generate a first switch control signal CS_SW1b and a second switch control signal CS_SW2b in the second stage P2, so that the first switch SW1_1, the second switch SW1_2 and the fourth switch SW1_4 of the first switch circuit 21_1 and the fifth switch SW2_1, the sixth switch SW2_2 and the eighth switch SW2_4 of the second switch circuit 21_2 are turned on, and other switches (for example, the third switch SW1_3, the seventh switch SW2_3 and the ninth switch SW2_5) are turned off.

[0078] Both ends of each of the first flying capacitor CFa and the second flying capacitor CFb can be connected to the input node and the ground node, respectively, and the first flying capacitor CFa and the second flying capacitor CFb can be charged using the input voltage VIN. The inductor current IL can flow from the input node to the output capacitor CO and the load LD through the first switch circuit 21_1 and the second switch circuit 21_2. Therefore, as Fig.7D As shown in , the inductor current IL may be kept substantially constant in the second phase P2 , and the applied voltage VX may be equal to or close to the input voltage VIN.

[0079] Reference Figure 7C In the buck-buck mode, the controller 22 can generate a first switch control signal CS_SW1c and a second switch control signal CS_SW2c in the third stage P3, so that the first switch SW1_1 and the fourth switch SW1_4 of the first switch circuit 21_1 and the fifth switch SW2_1, the eighth switch SW2_4 and the ninth switch SW2_5 of the second switch circuit 21_2 are turned on, and other switches (for example, the second switch SW1_2, the third switch SW1_3, the sixth switch SW2_2 and the seventh switch SW2_3) are turned off.

[0080] Both ends of each of the first flying capacitor CFa and the second flying capacitor CFb may be connected to the input node and the ground node, respectively. The inductor L may be connected to the ground node through the second switch circuit 21_2 and may receive an applied voltage VX corresponding to the ground voltage. Fig.7D As shown in , the inductor current IL can gradually decrease, and the applied voltage VX can be equal to or close to the ground voltage.

[0081] As described above, the controller 22 may control the connection relationship of the first flying capacitor CFa and the connection relationship of the second flying capacitor CFb identically or similarly in one stage during the buck mode, and may generate the output voltage VO lower than the input voltage VIN.

[0082] FIG. 8A to FIG. 8B is a circuit diagram of a switching regulator 20 operating in a first boost mode as a second operation mode according to an example embodiment, and Figure 8C is a diagram showing a method according to some example embodiments Fig. 8A and Figure 8B FIG8A shows the switching regulator 20 in the first phase P1, and ... Figure 8B The switching regulator 20 is shown in the second phase P2. Fig. 8A and Figure 8B In FIG. 1 , the path through which the current flows and the switch in the on state are shown in bold.

[0083] Reference Fig. 8A In the first boost mode, the controller 22 can generate a first switch control signal CS_SW1a and a second switch control signal CS_SW2a in the first stage P1, so that the second switch SW1_2 and the third switch SW1_3 of the first switch circuit 21_1 and the sixth switch SW2_2 and the seventh switch SW2_3 of the second switch circuit 21_2 are turned on, and other switches (for example, the first switch SW1_1, the fourth switch SW1_4, the fifth switch SW2_1, the eighth switch SW2_4 and the ninth switch SW2_5) are turned off.

[0084] Both ends of each of the first flying capacitor CFa and the second flying capacitor CFb may be connected to the input node and the inductor L, respectively. The applied voltage VX boosted by the first flying capacitor CFa and the second flying capacitor CFb may be provided to the inductor L through the second switch SW1_2 and the sixth switch SW2_2 in the on state. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the first switch circuit 21_1 and the second switch circuit 21_2. Therefore, as Figure 8CAs shown, the inductor current IL may gradually increase in the first phase P1, and the applied voltage VX provided to the inductor L may be equal to or close to the boost voltage, for example, a voltage equal to approximately twice the input voltage VIN.

[0085] Reference Figure 8B In the first boost mode, the controller 22 can generate a first switch control signal CS_SW1b and a second switch control signal CS_SW2b in the second stage P2, so that the first switch SW1_1, the second switch SW1_2 and the fourth switch SW1_4 of the first switch circuit 21_1 and the fifth switch SW2_1, the sixth switch SW2_2 and the eighth switch SW2_4 of the second switch circuit 21_2 are turned on, and other switches (for example, the third switch SW1_3, the seventh switch SW2_3 and the ninth switch SW2_5) are turned off.

[0086] Both ends of each of the first flying capacitor CFa and the second flying capacitor CFb can be connected to the input node and the ground node, respectively, and the first flying capacitor CFa and the second flying capacitor CFb can be charged using the input voltage VIN. The inductor current IL can flow from the input node to the output capacitor CO and the load LD through the first switch circuit 21_1 and the second switch circuit 21_2. Therefore, as Figure 8C As shown in , the inductor current IL may gradually decrease in the second phase P2 , and the applied voltage VX may be equal to or close to the input voltage VIN.

[0087] As mentioned above 6A to 8C As described above, the controller 22 may control the first switch circuit 21_1 and the second switch circuit 21_2 based on a synchronous switch control scheme so that the connection structure of the first flying capacitor CFa is the same as or similar to the connection structure of the second flying capacitor CFb in one phase.

[0088] although Figure 5E , Figure 6C , Fig.7D and Figure 8C The phases are shown to have the same period or similar period in one switching cycle, but this is only for the convenience of explanation. The phases may have different periods from each other. For example, Figure 5E The duration of each of the first phase P1 and the third phase P3 in Figure 8C Therefore, Figure 5E The period of each of the second stage P2 and the fourth stage P4 in FIG. 8C may be shorter than the period of the second stage P2 in FIG. 8C . In other words, Figure 5E The time period of each stage in the first stage P1 and the third stage P3 (or Figure 8CThe duty cycle of the first phase P1 in the second boost mode may be proportional to the duty cycle, and the controller 22 may control the first switch circuit 21_1 and the second switch circuit 21_2 based on a duty cycle in the second boost mode that is greater than the duty cycle in the first boost mode.

[0089] Fig. 9 is a circuit diagram of a switching regulator 30 according to an example embodiment.

[0090] Reference Fig. 9 , the switching regulator 30 may include a switching circuit 31, a controller 32, a first flying capacitor CFa, a second flying capacitor CFb, an inductor L and / or an output capacitor CO. A load LD may be connected to the switching regulator 30. The first switch SW1 of the switching circuit 31 may correspond to Figure 1 The connection switch CSW in.

[0091] The switch circuit 31 may include a first switch SW1 to a ninth switch SW9. The first switch SW1 and the fourth switch SW4 may be sequentially connected in series between the input node and the inductor L, and one end of each of the sixth switch SW6 to the eighth switch SW8 may be connected to the input node. The other end of the sixth switch SW6 may be connected to one end of the first flying capacitor CFa. The other end of the seventh switch SW7 may be connected to one end of the second flying capacitor CFb. The other end of the eighth switch SW8 may be connected to the other end of the second flying capacitor CFb. The third switch SW3 may be connected between the other end of the second flying capacitor CFb and the ground node. The second switch SW2 may be connected between one end of the first flying capacitor CFa and one end of the second flying capacitor CFb. The fifth switch SW5 may be connected between one end of the first flying capacitor CFa and the ground node. The ninth switch SW9 may be connected between one end of the inductor L and the ground node. As described below, the controller 32 may generate a switch control signal CS_SW so that the first flying capacitor CFa, the second flying capacitor CFb and the switch circuit 31 are used as a charge pump. The controller 32 may generate a switch control signal CS_SW so that the applied voltage VX boosted by the charge pump is applied to the inductor L. According to some example embodiments, the operations described herein as being performed by the controller 32 may be performed by a processing circuit. According to some example embodiments, the operations described herein as being performed by the switching regulator 30 may be performed based on a control signal generated by the controller 32.

[0092] In an embodiment, the controller 32 may generate a switch control signal CS_SW so that an applied voltage VX boosted to three times the input voltage VIN using the first flying capacitor CFa and the second flying capacitor CFb is applied to the inductor L. However, this is merely an example embodiment, and the inventive concept is not limited thereto. The switching regulator 30 may have a structure that includes more flying capacitors and switches and allows a boosted voltage (e.g., an applied voltage VX equal to N times the input voltage VIN, where N is an integer equal to or greater than 4) to be applied to the inductor L. Hereinafter, the description will focus on the case where the switching regulator 30 operates in the second boost mode, but it should be understood that the switching regulator 30 may operate in various modes.

[0093] Fig. 10A and Fig. 10B is a circuit diagram of a switching regulator 30 operating in a second boost mode according to an example embodiment, and Fig. 10C 10A and 10B are diagrams showing Fig. 10B A timing diagram of the operation of the switching regulator 30 is shown. Fig. 10A The switching regulator 30 is shown in the first phase P1, and Fig. 10B The switching regulator 30 is shown in the second phase P2. Fig. 10A and Fig. 10B In FIG. 1 , the path through which the current flows and the switch in the on state are shown in bold.

[0094] Reference Fig. 10A In the second boost mode, the controller 32 can generate a switch control signal CS_SWa in the first stage P1, so that the second switch SW2, the fourth switch SW4 and the eighth switch SW8 of the switch circuit 31 are turned on, and other switches (for example, the first switch SW1, the third switch SW3, the fifth switch SW5, the sixth switch SW6, the seventh switch SW7 and the ninth switch SW9) are turned off.

[0095] The second flying capacitor CFb and the first flying capacitor CFa may be sequentially connected in series between the input node and the inductor L. The applied voltage VX boosted by the first flying capacitor CFa and the second flying capacitor CFb may be provided to the inductor L through the second switch SW2, the fourth switch SW4, and the eighth switch SW8 in the on state. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the switch circuit 31. Therefore, as Fig. 10C As shown in , the inductor current IL may gradually increase in the first phase P1 , and the applied voltage VX provided to the inductor L may be equal to or close to the boost voltage, for example, a voltage equal to approximately three times the input voltage VIN.

[0096] Reference Fig. 10B In the second boost mode, the controller 32 can generate a switch control signal CS_SWb in the second stage P2, so that the first switch SW1, the third switch SW3, the fourth switch SW4, the fifth switch SW5 and the seventh switch SW7 of the switch circuit 31 are turned on, and the other switches (for example, the second switch SW2, the sixth switch SW6, the eighth switch SW8 and the ninth switch SW9) are turned off.

[0097] Both ends of each of the first flying capacitor CFa and the second flying capacitor CFb can be connected to the input node and the ground node, respectively, and the first flying capacitor CFa and the second flying capacitor CFb can be charged using the input voltage VIN. The inductor current IL can flow from the input node to the output capacitor CO and the load LD through the switch circuit 31. Therefore, as Fig. 10C As shown in , the inductor current IL can gradually decrease, and the applied voltage VX can be equal to or close to the input voltage VIN.

[0098] As above reference Fig. 10A As described above, an applied voltage VX equal to three times the input voltage VIN can be provided to the inductor L in the first phase P1, and thus the period of the first phase P1 can be reduced. In other words, as the level of the applied voltage VX provided to the inductor L in the first phase P1 increases, the period of the first phase P1 can be reduced. For example, Fig. 10C The first phase P1 can be shorter than Figure 5E The time period of each stage in the first stage P1 and the third stage P3. Therefore, Fig. 10C The period of the second phase in FIG. 5E may be longer than the period of each of the second phase P2 and the fourth phase P4 in FIG. 5E , and thus may be Fig. 10B The charging time of the first flying capacitor CFa and the second flying capacitor CFb is fully guaranteed in the second phase P2. Therefore, it is possible to prevent an abnormally large current from flowing into the first switch SW1, or to reduce the occurrence of an abnormally large current flowing into the first switch SW1.

[0099] Fig.11 is a circuit diagram of a switching regulator 30 according to an example embodiment.

[0100] refer to Fig.11, the switching regulator 30 may include a first switching circuit 31_1, a second switching circuit 31_2, a controller 32, an inductor L, an output capacitor CO and / or first to fourth flying capacitors CFa1, CFa2, CFb1 and CFb2. A load LD may be connected to the switching regulator 30. The first switch SW11 of the first switching circuit 31_1 and the tenth switch SW21 of the second switching circuit 31_2 may correspond to FIG. 2A to FIG. 2B The first connecting switch CSW1 and the second connecting switch CSW2 in the embodiment.

[0101] The first switch circuit 31_1 may include a first switch SW11 to a ninth switch SW19 (e.g., SW11, SW12, SW13, SW14, SW15, SW16, SW17, SW18, and SW19) and may be connected to the first flying capacitor CFa1 and the second flying capacitor CFb1. The second switch circuit 31_2 may include a tenth switch SW21 to an eighteenth switch SW29 (e.g., SW21, SW22, SW23, SW24, SW25, SW26, SW27, SW28, and SW29) and may be connected to the third flying capacitor CFa2 and the fourth flying capacitor CFb2. The structures of the first switch circuit 31_1 and the second switch circuit 31_2 are similar to those described above. Fig. 9 The structure of the switch circuit 31 described in detail is the same or similar, and thus a redundant description will be omitted.

[0102] The controller 32 may control the first switch circuit 31_1 and the second switch circuit 31_2 using different switch control schemes according to the operation mode of the switching regulator 30. In an embodiment, the controller 32 may control the first switch circuit 31_1 and the second switch circuit 31_2 based on the staggered switch control scheme in the first operation mode, so that the first to fourth flying capacitors CFa1, CFa2, CFb1, and CFb2 are alternately charged and connected to the inductor L in different stages. The controller 32 may control the first switch circuit 31_1 and the second switch circuit 31_2 identically or similarly based on the synchronous switch control scheme in the second operation mode. Since reference has been made to the embodiments including Figure 4 The detailed description thereof is given in the accompanying drawings and thus redundant description will be omitted.

[0103] Fig.12 is a table of conditions for setting an operating mode of a switching regulator according to an example embodiment. In the following, for the sake of clarity, it is assumed that "a" is 0.1 and "b" is 0.5. However, this is only an example for illustration, and "a" and "b" are not limited thereto and may be set differently.

[0104] refer to Fig.12, when the target level of the output voltage VO is less than (1-a) times the input voltage VIN, the switching regulator can be set in the buck mode. When the target level of the output voltage VO is equal to or greater than (1-a) times the input voltage VIN and less than (1+a) times the input voltage VIN, the switching regulator can be set in the buck-boost mode. When the target level of the output voltage VO is equal to or greater than (1+a) times the input voltage VIN and less than (1+b) times the input voltage VIN, the switching regulator can be set in the first boost mode. When the target level of the output voltage VO is equal to or greater than (1+b) times the input voltage VIN, the switching regulator can be set in the second boost mode.

[0105] In an embodiment, when the switching regulator is set in the second boost mode, the switch of the switching regulator can be controlled based on an interleaved switch control scheme. When the switching regulator is set in the first boost mode, the buck mode, or the buck-boost mode, the switch of the switching regulator can be controlled based on a synchronous switch control scheme. However, this is merely an example embodiment, and the inventive concept is not limited thereto. When the switching regulator is set in the first boost mode, the switch of the switching regulator can be controlled based on an interleaved switch control scheme. In addition, the switching regulator can be set in more operating modes, and a variety of switch control schemes can be used according to the operating mode to reduce the current load on the connection switch.

[0106] Fig.13 is a flow chart of a method of operating a switching regulator according to an example embodiment.

[0107] refer to Fig.13 In operation S100, the switching regulator may identify a target level of an output voltage. In operation S120, an operation mode of the switching regulator may be set based on the target level of the output voltage. In operation S140, the switching regulator may generate an output voltage by performing a voltage conversion operation based on a switching control scheme corresponding to the operation mode.

[0108] Fig.14 According to an example embodiment Fig.13 Detailed flowchart of operation S140 in FIG.

[0109] refer to Fig.14 , in operation S120( Fig.13), in operation S142, the switching regulator may check whether the switching regulator is set in the second boost mode. When the switching regulator is in the second boost mode in operation S142 (e.g., in the case of "yes"), in operation S144, the switching regulator may perform a voltage conversion operation based on an interleaved switching control scheme. When the switching regulator is not in the second boost mode in operation S142 (e.g., in the case of "no"), in operation S146, the switching regulator may perform a voltage conversion operation based on a synchronous switching control scheme.

[0110] Fig.15 is a schematic diagram of a system 100 according to an example embodiment. System 100 may be implemented as a single semiconductor integrated circuit, such as a system on a chip (SoC), in some embodiments, or may include a printed circuit board (PCB) and a package mounted on the PCB in some embodiments. Fig.15 As shown in , the system 100 may include first to fourth functional blocks 110 to 140 (eg, the first functional block 110 , the second functional block 120 , the third functional block 130 , and the fourth functional block 140 ) and / or a power management integrated circuit (PMIC) 150 .

[0111] Each of the first to fourth functional blocks 110 to 140 may operate based on power provided by a corresponding one of the first to fourth power supply voltages VDD1 to VDD4 (e.g., VDD1, VDD2, VDD3, and VDD4) output from the PMIC 150. For example, at least one of the first to fourth functional blocks 110 to 140 may include a digital circuit that processes a digital signal, such as an application processor (AP), or an analog circuit that processes an analog signal, such as an amplifier. At least one of the first to fourth functional blocks 110 to 140 may include a circuit that processes a mixed signal, such as an analog-to-digital converter (ADC). Although in Fig.15 In the embodiment shown, the system 100 includes four functional blocks, but in some embodiments, the system 100 may include fewer or more functional blocks.

[0112] The PMIC 150 may generate first to fourth power supply voltages VDD1 to VDD4 according to an input voltage VIN, and change the level of at least one of the first to fourth power supply voltages VDD1 to VDD4 in response to a voltage control signal C_V. At least one of the first to fourth functional blocks 110 to 140 may receive a power supply voltage having a level that dynamically changes with the performance and power consumption of at least one of the first to fourth functional blocks 110 to 140. For example, the first functional block 110 may include an image processor that processes image data. The first functional block 110 may receive a first power supply voltage VDD1 having a high level when processing a video including a series of images. The first functional block 110 may receive a first power supply voltage VDD1 having a low level when processing a photo including a single image. The PMIC 150 may receive a voltage control signal C_V corresponding to the performance and power consumption of the first functional block 110, and may increase or decrease the level of the first power supply voltage VDD1 based on the voltage control signal C_V. As described above, the method of dynamically changing the level of the power supply voltage of the functional block may be referred to as dynamic voltage scaling.

[0113] The PMIC 150 may include any switching regulator (e.g., the switching regulator 10, the switching regulator 20, and / or the switching regulator 30) described above with reference to the accompanying drawings. According to some example embodiments, the PMIC 150 may generate a first power supply voltage VDD1 to a fourth power supply voltage VDD4 according to an input voltage VIN, and change the level of at least one of the first power supply voltage VDD1 to the fourth power supply voltage VDD4 in response to a voltage control signal C_V using a switching regulator. Therefore, when the first power supply voltage VDD1 is maintained at a certain level, the first power supply voltage VDD1 may have reduced noise. Since the noise in the first power supply voltage VDD1 is reduced, the operational reliability of the first functional block 110 and the system 100 may be improved. In addition, the level of the first power supply voltage VDD1 may be changed quickly. In some embodiments, the first functional block 110 may stop operating when the level of the first power supply voltage VDD1 is being changed, and may restart operating after the level of the first power supply voltage VDD1 is changed. Therefore, when the level of the first power supply voltage VDD1 is changed quickly, the operation time of the first functional block 110 may be reduced. Therefore, the system 100 may provide improved performance. In addition, the PMIC 150 may include elements (eg, connection switches) having a reduced size, and thus the PMIC 150 may be easily integrated with the first to fourth functional blocks 110 to 140 in a single package.

[0114] Fig.16 is a block diagram of a wireless communication device 200 according to an example embodiment. Specifically, Fig.16 A user equipment (UE) (or user terminal) powered by a battery 250 is shown. In some embodiments, the wireless communication device 200 may be included in a wireless communication system such as a fifth generation (5G) or long term evolution (LTE) using a cellular network, a wireless local area network (WLAN) system, or another wireless communication system. In the wireless communication device 200, a switching regulator according to an example embodiment may be used to supply variable power to a power amplifier (PA) 216. Fig.16 As shown in , the wireless communication device 200 may include a transceiver 210 , a baseband processor 220 , an antenna 230 , a power circuit 240 and / or a battery 250 .

[0115] The transceiver 210 may include an antenna interface (IF) circuit 211, a receiver, and / or a transmitter. The receiver may include an input circuit 212, a low noise amplifier (LNA) 213, and / or a receiver (RX) circuit 214. The transmitter may include a transmitter (TX) circuit 215, a PA 216, and / or an output circuit 217. The antenna IF circuit 211 may connect the transmitter and / or the receiver to the antenna 230 according to the TX mode and / or the RX mode. In some embodiments, the input circuit 212 may include a matching circuit or a filter, the LNA 213 may amplify the output signal of the input circuit 212, and / or the RX circuit 214 may include a mixer for down-conversion. In some embodiments, the TX circuit 215 may include a mixer for up-conversion, the PA 216 may amplify the output signal of the TX circuit 215, and / or the output circuit 217 may include a matching circuit and / or a filter.

[0116] The baseband processor 220 may send and / or receive baseband signals to and / or from the transceiver 210, and may perform modulation, demodulation, encoding, and / or decoding. In some embodiments, the baseband processor 220 may be referred to as a modem. The baseband processor 220 may generate a setting signal SET, which is used to set an average power tracking mode and / or an envelope tracking mode, and / or to change the level of the output voltage VO.

[0117] The power circuit 240 may receive an input voltage VIN from the battery 250 and generate an output voltage VO for supplying power to the PA 216. The power circuit 240 may include any switching regulator (e.g., the switching regulator 10, the switching regulator 20, and / or the switching regulator 30) described above with reference to the accompanying drawings, and may enable the level of the output voltage VO to be changed quickly and maintained stable. According to some example embodiments, the power circuit 240 generates the output voltage VO according to the input voltage VIN, and enables the level of the output voltage VO to be changed quickly and maintained stable by using the switching regulator.

[0118] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A switching regulator, configured to generate a level-controlled output voltage according to an input voltage, the switching regulator comprising: an input node configured to receive the input voltage; an output node configured to output the level-controlled output voltage; an inductor having one end connected to the output node; an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor; a first flying capacitor and a second flying capacitor; a first switch circuit including a plurality of first switches connected to the first flying capacitor and connected to the input node and the other end of the inductor; a second switch circuit including a plurality of second switches connected to the second flying capacitor and connected to the input node and the other end of the inductor; a controller configured to control switching operations of the first switching circuit and the second switching circuit based on a selected operation mode among a plurality of operation modes, The controller controls the first flying capacitor and the second flying capacitor to be charged synchronously in at least one stage or to be charged in a staggered manner in a plurality of stages based on a selected operation mode and a target level of the output voltage of the level control.

2. The switching regulator according to claim 1, wherein: When the selected operating mode is buck mode, the controller: In a first phase, the first flying capacitor and the second flying capacitor are controlled to be charged synchronously, and the input voltage is applied to the other end of the inductor through the first switching circuit and the second switching circuit, and In the second phase, the first flying capacitor and the second flying capacitor are controlled to be charged synchronously, the connection between the first switch circuit and the other end of the inductor is disconnected, and the other end of the inductor is grounded through the second switch circuit.

3. The switching regulator according to claim 1, wherein: When the selected operating mode is buck-boost mode, the controller: In a first stage, the input voltage is controlled to be boosted through the first flying capacitor and the second flying capacitor and applied to the other end of the inductor, In a second phase, the first flying capacitor and the second flying capacitor are controlled to be charged synchronously, and the input voltage is applied to the other end of the inductor through the first switching circuit and the second switching circuit, and In the third phase, the first flying capacitor and the second flying capacitor are controlled to be charged synchronously, the connection between the first switch circuit and the other end of the inductor is disconnected, and the other end of the inductor is grounded through the second switch circuit.

4. The switching regulator according to claim 1, wherein: When the selected operation mode is the boost mode and the target level is less than a reference level, the controller: In a first stage, the input voltage is controlled to be boosted through the first flying capacitor and the second flying capacitor and applied to the other end of the inductor, and In a second phase, the first flying capacitor and the second flying capacitor are controlled to be synchronously charged, and the input voltage is applied to the other end of the inductor through the first switching circuit and the second switching circuit.

5. The switching regulator according to claim 1, wherein: When the selected operation mode is boost mode: When the target level is less than a reference level, the controller controls the first flying capacitor and the second flying capacitor to be charged synchronously, and When the target level is greater than or equal to the reference level, the controller controls the first flying capacitor and the second flying capacitor to be charged in an interleaved manner.

6. The switching regulator according to claim 1, wherein: When the selected operation mode is the buck mode or the buck-boost mode, the controller controls the first flying capacitor and the second flying capacitor to be charged synchronously.

7. The switching regulator according to claim 1, wherein: When the selected operation mode is the boost mode and the target level is greater than or equal to the reference level, the controller: In a first stage, the input voltage is controlled to be boosted through the first flying capacitor and applied to the other end of the inductor, and the second flying capacitor is controlled to be charged. In a second phase, the input voltage is controlled to be applied to the other end of the inductor through the first switch circuit, and the second flying capacitor is controlled to be charged. In a third phase, the first flying capacitor is controlled to be charged, and the input voltage is boosted by the second flying capacitor and applied to the other end of the inductor, and In a fourth phase, the controller controls the first flying capacitor to be charged, and applies the input voltage to the other end of the inductor through the second flying capacitor.

8. The switching regulator according to claim 7, wherein: The controller controls the first flying capacitor to float in the second stage, and controls the second flying capacitor to float in the fourth stage.

9. A switching regulator configured to generate a level-controlled output voltage according to an input voltage, the switching regulator comprising: an input node configured to receive the input voltage; an output node configured to output the level-controlled output voltage; an inductor having one end connected to the output node; an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor; a first flying capacitor configured to provide a first boosted voltage to the inductor; a second flying capacitor configured to provide a second boosted voltage to the inductor; a first switch circuit connected to the first flying capacitor, including a first connection switch coupled to the input node and a plurality of first switches, and the first switch circuit is connected to the input node and the other end of the inductor; as well as a second switch circuit connected to the second flying capacitor, including a second connection switch coupled to the input node and a plurality of second switches, and the second switch circuit is connected to the input node and the other end of the inductor; as well as a controller configured to control switching operations of the first switching circuit and the second switching circuit based on a selected operation mode among a plurality of operation modes, Wherein, the controller controls the first current path and the second current path and the third current path and the fourth current path to be synchronously formed in the first connecting switch and the second connecting switch during at least one stage or to be formed in the first connecting switch and the second connecting switch in an interlaced manner during multiple stages based on the selected operating mode and the target level of the output voltage of the level control, wherein the first current path and the second current path are respectively used to charge the first flying capacitor and the second flying capacitor with the input voltage, and the third current path and the fourth current path are respectively used to apply the input voltage to the other end of the inductor through the first switching circuit and the second switching circuit.

10. The switching regulator according to claim 9, wherein: When the selected operation mode is the buck mode or the buck-boost mode, the controller controls the first current path and the third current path to be synchronously formed in the first connection switch, and controls the second current path and the fourth current path to be synchronously formed in the second connection switch.

11. The switching regulator according to claim 9, wherein: When the selected operating mode is the boost mode and the target level is less than a reference level, the controller controls the first current path and the third current path to be synchronously formed in the first connecting switch at a certain stage, and controls the second current path and the fourth current path to be synchronously formed in the second connecting switch at the certain stage.

12. The switching regulator according to claim 9, wherein: When the selected operation mode is the boost mode and the target level is greater than or equal to a reference level, the controller controls the first current path and the third current path to be formed in the first connecting switch in an interlaced manner, and controls the second current path and the fourth current path to be formed in the second connecting switch in an interlaced manner.

13. The switching regulator according to claim 9, wherein: The controller controls a current less than or equal to a threshold value to flow through the first connection switch and the second connection switch.

14. The switching regulator according to claim 9, wherein: The controller disables one of the first switching circuit and the second switching circuit when the selected operation mode is the buck mode or the buck-boost mode.

15. The switching regulator according to claim 9, wherein: The controller disables one of the first switching circuit and the second switching circuit when the selected operation mode is a boost mode and the target level is less than a reference level.

16. A switching regulator configured to generate a level-controlled output voltage according to an input voltage, the switching regulator comprising: an input node configured to receive the input voltage; an output node configured to output the level-controlled output voltage; an inductor having one end connected to the output node; an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor; a first flying capacitor and a second flying capacitor configured to provide a boosted voltage to one end of the inductor; as well as a switching circuit including a plurality of switches and coupled to the first flying capacitor and the second flying capacitor, the other end of the inductor, and ground; as well as a controller configured to control a switching operation of the switching circuit based on a selected operation mode among a plurality of operation modes, Wherein, when the selected operation mode is the boost mode and the target level of the output voltage of the level control is greater than or equal to the reference level, the controller: In the first stage, the input voltage is controlled to be boosted by the first flying capacitor and the second flying capacitor connected in series with each other and applied to the other end of the inductor, and In a second phase, the first flying capacitor and the second flying capacitor are controlled to be charged, and the input voltage is applied to the other end of the inductor through the switching circuit.

17. The switching regulator according to claim 16, wherein: The plurality of switches include first to ninth switches, wherein one end of the first switch is connected to the input node, and the other end of the first switch is connected to one end of the first flying capacitor, One end of the second switch is connected to the other end of the first flying capacitor, and the other end of the second switch is connected to one end of the second flying capacitor, One end of the third switch is connected to the other end of the second flying capacitor, and the other end of the third switch is grounded, One end of the fourth switch is connected to the one end of the first flying capacitor, and the other end of the fourth switch is connected to the other end of the inductor, One end of the fifth switch is connected to the other end of the first flying capacitor, and the other end of the fifth switch is grounded, One end of the sixth switch is connected to the input node, and the other end of the sixth switch is connected to the other end of the first flying capacitor, One end of the seventh switch is connected to the input node, and the other end of the seventh switch is connected to the one end of the second flying capacitor, One end of the eighth switch is connected to the input node, and the other end of the eighth switch is connected to the other end of the second flying capacitor, and One end of the ninth switch is connected to the other end of the inductor, and the other end of the ninth switch is grounded.

18. The switching regulator according to claim 17, wherein: In the first stage, the controller controls the first switch, the third switch, the fifth switch, the sixth switch, the seventh switch and the ninth switch to be turned off, and the second switch, the fourth switch and the eighth switch to be turned on, and in the second stage, the controller controls the second switch, the sixth switch, the eighth switch and the ninth switch to be turned off, and the first switch, the third switch, the fourth switch, the fifth switch and the seventh switch to be turned on.

19. The switching regulator according to claim 17, wherein: The controller controls a period of the second phase to be longer than a period of the first phase.

20. The switching regulator of claim 16, wherein: In the first stage, the input voltage is boosted to have a level more than twice an initial level.

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