Level shift circuit

Abstract

The present application provides a level shift circuit, including: a first P-channel field effect transistor, whose source is connected to a first voltage, whose drain is connected to point A, and whose gate is connected to point B; a second P-channel field effect transistor, whose source is connected to the first voltage, whose drain is connected to point B, and whose gate is connected to point A; a first N-channel field effect transistor, whose drain is connected to point A, and whose gate is connected to a first control signal; a second N-channel field effect transistor, whose drain is connected to point B, and whose gate is connected to a second control signal; a voltage output unit, whose input end is connected to point B, and whose output end is used to output a shifted target signal according to the voltage at point B; a first switch tube, whose input end is connected to a first voltage, whose output end is connected to point B, and whose gate is connected to a third control signal; and the first switch tube is used to turn on after the second N-channel field effect transistor is turned off. The present application can improve efficiency by setting the first switch tube to directly pull up the potential at point B.

Description

Technical Field

[0001] The present application relates to the technical field of voltage conversion, and in particular to a level shifting circuit. Background Art

[0002] The potential shift circuit is a common circuit in the field of integrated circuits. The level shift circuit is used to shift the input level to a higher level, and can also be used to shift the input level to a lower level, so as to meet the needs of different functional modules in the integrated circuit for level signals of different amplitudes.

[0003] like Figure 1 As shown, in a potential shifting circuit in the prior art, an inverter U11, an inverter U21, a P-channel field effect transistor P11, a P-channel field effect transistor P12, an N-channel field effect transistor N11, and an N-channel field effect transistor N12 are included. The source of the P-channel field effect transistor P11 is connected to the voltage VDDH, the drain of the P-channel field effect transistor P11 and the drain of the N-channel field effect transistor N11 are connected to the A0 point, and the source of the N-channel field effect transistor N11 is grounded. The source of the P-channel field effect transistor P21 is connected to the voltage VDDH, the drain of the P-channel field effect transistor P21 and the drain of the N-channel field effect transistor N21 are connected to the B0 point, and the source of the N-channel field effect transistor N21 is grounded. The gate of the P-channel field effect transistor P11 is connected to the B0 point, and the P-channel field effect transistor P21 is connected to the A0 point. The output end of the inverter U11 is connected to the gate of the N-channel field effect transistor N11, and the input end of the inverter U11 is connected to the gate of the N-channel field effect transistor N21. Figure 1 The disadvantage of the prior art shown is that if the P21 point wants to raise the potential of the B0 point, the P-channel field effect transistor P21 at the A0 point must be turned on, which is time-consuming and results in low efficiency and slow speed of the potential shifting circuit.

[0004] There is currently no effective technical solution to the above problems. Summary of the invention

[0005] An object of the embodiments of the present application is to provide a level shift circuit, which can improve the efficiency of the level shift circuit.

[0006] An embodiment of the present application provides a level shift circuit, including:

[0007] A first P-channel field effect transistor, whose source is connected to the first voltage, whose drain is connected to point A, and whose gate is connected to point B;

[0008] A second P-channel field effect transistor, whose source is connected to the first voltage, whose drain is connected to point B, and whose gate is connected to point A;

[0009] A first N-channel field effect transistor, whose drain is connected to point A, whose gate is connected to the first control signal, and whose source is connected to a preset low voltage;

[0010] A second N-channel field effect transistor, whose drain is connected to point B, whose gate is connected to the second control signal, and whose source is connected to a preset low voltage;

[0011] A voltage output unit, whose input terminal is connected to point B, and whose output terminal is used to output the shifted target signal according to the voltage at point B;

[0012] The first switch tube has an input terminal connected to the first voltage, an output terminal connected to point B, and a gate connected to the third control signal; the first switch tube is used to be turned on after the second N-channel field effect transistor is turned off to increase the potential of point B.

[0013] The level shift circuit provided in the embodiment of the present application adopts the method of setting the first switch tube to be turned on after the first N-channel field effect transistor is turned off, thereby directly raising the potential of point B. There is no need to wait for the potential of point A to rise to turn on the second P-channel field effect transistor before starting to raise the potential of point B. The time consumed in raising the potential can be increased, thereby improving the efficiency of the level shift circuit.

[0014] Optionally, the level shift circuit described in the embodiment of the present application further includes:

[0015] The second switch tube has an input terminal connected to the first voltage, an output terminal connected to point A, and a control terminal connected to the second control signal. The switching state of the second switch tube is the same as that of the first N-channel field effect transistor.

[0016] The level shift circuit provided in the embodiment of the present application adopts the second switch tube to directly raise the potential of point A when the second switch tube is turned on, without having to wait until point B turns on the first P-channel field effect transistor before starting to raise the potential. This can increase the time consumed for raising the potential of point A, thereby achieving the beneficial effect of improving the efficiency of the level shift circuit.

[0017] Optionally, the level shift circuit described in the embodiment of the present application further includes:

[0018] A third P-channel field effect transistor, whose source is connected to the first voltage, whose drain is connected to the input end of the first switch tube and the input end of the second switch tube, and whose gate is connected to the control signal; the first switch tube and the second switch tube are both N-channel field effect transistors, the third P-channel field effect transistor is a P-channel field effect transistor, and the third control signal is the same as the first control signal.

[0019] The level shift circuit provided in the embodiment of the present application uses the third P-channel field effect transistor to isolate the power supply of the VDDH voltage from the second switch tube and the first switch tube to achieve indirect connection, thereby protecting the first switch tube and the second switch tube and improving the stability of the switching characteristics of the first switch tube and the second switch tube.

[0020] Optionally, in the level shift circuit described in the embodiment of the present application, the level shift circuit further includes:

[0021] A third P-channel field effect transistor, whose source is connected to the first voltage, whose drain is connected to the input end of the first switch tube, and whose gate is connected to the control signal; the first switch tube is an N-channel field effect transistor, the third P-channel field effect transistor is a P-channel field effect transistor, and the third control signal is the same as the first control signal.

[0022] The level shift circuit provided in the embodiment of the present application uses the third P-channel field effect transistor to isolate the power supply of the VDDH voltage from the first switch tube to achieve indirect connection, thereby protecting the first switch tube and improving the stability of the switching characteristics of the first switch tube.

[0023] Optionally, in the level shift circuit described in the embodiment of the present application, the gate of the third P-channel field effect transistor is connected to the point B, so as to access the voltage of the point B as the control signal.

[0024] The embodiment of the present application connects the gate of the third P-channel field effect transistor to the point B, thereby avoiding leakage current flowing to the point B when the second N-channel field effect transistor pulls down the voltage at the point B, thereby reducing power consumption and the time consumed to lower the potential of the point B, thereby achieving the beneficial effect of improving the efficiency of the level shifting circuit.

[0025] Optionally, in the level shift circuit described in the embodiment of the present application, the gate of the third P-channel field effect transistor is connected to a control signal to remain normally open.

[0026] Optionally, in the level shift circuit described in the embodiment of the present application, the level shift circuit further includes:

[0027] A voltage input unit is respectively connected to the first N-channel field effect transistor, the second N-channel field effect transistor and the first switch tube to respectively provide a corresponding first control signal and a second control signal.

[0028] Optionally, in the level shift circuit described in the embodiment of the present application, the voltage input unit includes a first inverter;

[0029] The input terminal of the first inverter is connected to a second control signal;

[0030] The output end of the first inverter is connected to the gate end of the third P-channel field effect transistor and the gate end of the first N-channel field effect transistor respectively, and the output end of the output end of the first inverter outputs a first control signal.

[0031] The level shift circuit provided in the embodiment of the present application realizes the timing control of opening and closing the first switch tube and the second N-channel field effect transistor through the first inverter, ensuring that the second N-channel field effect transistor is turned off first and the first switch tube is turned on later, thereby reducing power consumption.

[0032] Optionally, in the level shift circuit described in the embodiment of the present application, the amplitude value of the target signal is equal to the first voltage.

[0033] Optionally, in the level shift circuit described in the embodiment of the present application, the voltage output unit includes a second inverter, the input end of the second inverter is connected to point B, and the output end of the second inverter outputs an inverted voltage of the voltage at point B.

[0034] Optionally, in the level shift circuit described in the embodiment of the present application, the level shift circuit further includes:

[0035] A fourth P-channel field effect transistor, the first P-channel field effect transistor is connected to point A through the fourth P-channel field effect transistor, the source of the fourth P-channel field effect transistor is connected to the drain of the first P-channel field effect transistor, the drain of the fourth P-channel field effect transistor is connected to point A, and the gate of the fourth P-channel field effect transistor is connected to the gate of the first N-channel field effect transistor.

[0036] The level shift circuit provided in the embodiment of the present application is provided with the fourth P-channel field effect transistor, and the fourth P-channel field effect transistor is used to be turned off when the first N-channel field effect transistor is turned on, and to be turned on when the first N-channel field effect transistor is turned off, thereby avoiding competition at the point A, that is, avoiding the first P-channel field effect transistor from raising the potential of the point A when the first N-channel field effect transistor lowers the potential of the point A, thereby reducing power consumption and improving efficiency.

[0037] Optionally, in the level shift circuit described in the embodiment of the present application, the level shift circuit further includes:

[0038] A fifth P-channel field effect transistor, the second P-channel field effect transistor is connected to point B through the fifth P-channel field effect transistor, the source of the fifth P-channel field effect transistor is connected to the drain of the second P-channel field effect transistor, the drain of the fifth P-channel field effect transistor is connected to point B, and the gate of the fifth P-channel field effect transistor is connected to the gate of the second N-channel field effect transistor.

[0039] The level shift circuit provided in the embodiment of the present application is provided with the fifth P-channel field effect transistor, and the fifth P-channel field effect transistor is used to be turned off when the second N-channel field effect transistor is turned on, and to be turned on when the second N-channel field effect transistor is turned off, thereby avoiding competition at the point B, that is, avoiding the second P-channel field effect transistor from raising the potential of the point B when the second N-channel field effect transistor lowers the potential of the point A, thereby reducing power consumption and improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 The present invention is a schematic diagram of a structure of a level shift circuit in the prior art.

[0042] Figure 2 This is a first structural diagram of a level shift circuit in some embodiments of the present application.

[0043] Figure 3 It is a structural schematic diagram of the second inverter of the level shift circuit in some embodiments of the present application.

[0044] Figure 4 This is a second structural diagram of the level shift circuit in some embodiments of the present application.

[0045] Figure 5 This is a third structural diagram of the level shift circuit in some embodiments of the present application.

[0046] Figure 6 This is a fourth structural diagram of the level shift circuit in some embodiments of the present application.

[0047] Figure 7 This is a fifth structural diagram of the level shift circuit in some embodiments of the present application.

[0048] Figure 8This is a sixth structural diagram of the level shift circuit in some embodiments of the present application.

[0049] Fig. 9 This is a seventh structural diagram of the level shift circuit in some embodiments of the present application.

[0050] Fig.10 This is an eighth structural diagram of the level shift circuit in some embodiments of the present application.

[0051] Fig.11 This is a ninth structural diagram of the level shift circuit in some embodiments of the present application.

[0052] Fig.12 This is a tenth structural schematic diagram of a level shift circuit in some embodiments of the present application.

[0053] Fig.13 This is an eleventh structural diagram of the level shift circuit in some embodiments of the present application. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0055] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "inside", "outside", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, in the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" or "second" may include one or more of the features explicitly or implicitly. In the description of the present invention, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0056] It should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0057] The embodiment of the present application provides a level shift circuit, which is used to shift the input level to a higher level, and can also be used to shift the input level to a lower level, so as to meet the needs of different functional modules in the integrated circuit for level signals of different amplitudes. Figure 1 As for the technical solution in the present application, the first switch tube is set to be turned on after the first N-channel field effect transistor is turned off, so as to directly raise the potential of point B, without waiting for the potential of point A to rise to turn on the second P-channel field effect transistor to start raising the potential of point B, which can increase the time consumed for raising the potential, thereby improving the efficiency of the pad shift circuit. The circuit structure and principle of the level shift circuit are described in detail below.

[0058] Please refer to Figure 2 , Figure 2 1 is a schematic diagram of a level shift circuit in some embodiments of the present application. The level shift circuit includes: a first P-channel field effect transistor P1, a second P-channel field effect transistor P2, a first N-channel field effect transistor N1, a second N-channel field effect transistor N2, a voltage output unit 102 and a first switch tube T1.

[0059] Among them, the source of the first P-channel field effect transistor P1 is connected to the first voltage VDDH, the drain of the first P-channel field effect transistor is connected to point A, and the gate of the first P-channel field effect transistor P1 is connected to point B. The source of the second P-channel field effect transistor P2 is connected to the first voltage VDDH, the drain of the second P-channel field effect transistor P2 is connected to point B, and the gate of the second P-channel field effect transistor P2 is connected to point A. The drain of the first N-channel field effect transistor N1 is connected to point A, the gate of the first N-channel field effect transistor N1 is connected to the first control signal Xh1, and the source of the first N-channel field effect transistor N1 is connected to a preset low voltage. The drain of the second N-channel field effect transistor N2 is connected to point B, the gate of the second N-channel field effect transistor N2 is connected to the second control signal Xh2, and the source of the second N-channel field effect transistor N2 is connected to a preset low voltage. The input end of the first switch tube T1 is connected to the first voltage VDDH, the output end of the first switch tube T1 is connected to the point B, and the switch state of the first switch tube T1 is the same as the switch state of the first N-channel field effect transistor N1. The input end of the voltage output unit 102 is connected to the point B, and the output end of the voltage output unit 102 is used to output a target signal based on the voltage at the point B.

[0060] Specifically, the first P-channel field effect transistor P1 is used to switch on and off under the control of the potential of the point B, and the first P-channel field effect transistor P1 is used to pull the voltage of the point A to the first voltage VDDH when it is turned on. The first voltage VDDH is equal to the voltage amplitude of the target signal finally outputted. The first voltage VDDH is a constant voltage signal.

[0061] The second P-channel field effect transistor P2 switches between on and off under the control of the potential at point A, and the second P-channel field effect transistor P2 is used to pull the voltage at point B to the first voltage VDDH when it is turned on. The first P-channel field effect transistor P1 and the second P-channel field effect transistor P2 form a common latch circuit.

[0062] The first N-channel field effect transistor N1 switches between on and off under the control of the first control signal Xh1. The preset low voltage is less than the first voltage VDDH, and the preset low voltage can be the zero potential of the ground point. The first N-channel field effect transistor N1 is used to pull the voltage of point A down to the preset low voltage when it is turned on.

[0063] The second N-channel field effect transistor N2 is switched on and off under the control of the second control signal Xh2. The second N-channel field effect transistor N2 is used to pull down the voltage at the point B to the preset low voltage when it is turned on.

[0064] The voltage output unit 102 may include one or more second inverters U2 connected in series. The target signal is a signal obtained after the voltage at point B is inverted by the one or more second inverters U2. The number of the second inverters U2 is an odd number. Figure 3 , the second inverter U2 includes a zeroth P-channel field effect transistor P0 and a zeroth N-channel field effect transistor N0, the gate of the zeroth P-channel field effect transistor P0 is connected to the gate of the zeroth N-channel field effect transistor N0 and connected to point B, the source of the zeroth P-channel field effect transistor P0 is connected to the first voltage VDDH, the drain of the zeroth P-channel field effect transistor P0 is connected to the drain of the zeroth N-channel field effect transistor N0, and the source of the zeroth N-channel field effect transistor N0 is connected to a preset low voltage. Of course, it can be understood that the second inverter U2 can also adopt an inverting circuit in other prior arts.

[0065] Of course, it is understandable that in some embodiments, the voltage output unit 102 may also include only one signal output pin, which does not process the voltage at point B.

[0066] The input end of the first switch tube T1 is connected to the first voltage VDDH, the output end of the first switch tube is connected to point B, and the gate of the first switch tube T1 is connected to the control signal to pull the voltage at point B to the first voltage when turned on. The first switch tube T1 is used to turn on within a preset time period after the second N-channel field effect transistor N2 is turned off. The preset time period may be 0 or may not be 0.

[0067] The first switch tube T1 may be an N-channel field effect transistor, and correspondingly, the third control signal is the same as the first control signal Xh1. Alternatively, the first switch tube T1 may be a P-channel field effect transistor, and correspondingly, the third control signal is an inverted signal of the first control signal Xh1.

[0068] In the embodiment of the present application, a voltage input unit 101 may be provided to provide the first switch tube T1, the first N-channel field effect transistor N1 and the second N-channel field effect transistor N2 with a third control signal, a first control signal Xh1 and a second control signal Xh2 respectively.

[0069] Specifically, in some embodiments, the voltage input unit 101 includes one or more first inverters U1 connected in series, wherein the number of the first inverters U1 is an odd number.

[0070] When the first switch tube T1 is an N-channel field effect transistor (of course, Figure 2When the first switch tube T1 in the circuit is an N-channel field effect transistor), the first control signal Xh2 is the same as the third control signal. The input end of the voltage input unit 101 is connected to the second control signal Xh2, and the output end of the voltage input unit 101 outputs the first control signal Xh1. The input end of the voltage input unit 101 is connected to the gate of the second N-channel field effect transistor N2, and the output end of the voltage input unit 101 is electrically connected to the gate of the first N-channel field effect transistor N1 and the gate of the first switch tube T1.

[0071] When the first switch tube T1 is a P-channel field effect transistor, the input end of the voltage input unit 101 is connected to the second control signal Xh2, and the output end of the voltage input unit 101 outputs the first control signal Xh1. The input end of the voltage input unit 101 is respectively connected to the gate of the second N-channel field effect transistor N2 and the gate of the first switch tube T1, and the output end of the voltage input unit 101 is connected to the gate of the first N-channel field effect transistor N1.

[0072] Should Figure 2 As shown in the circuit diagram, when the first control signal Xh1 is at a high level and the second control signal Xh2 is at a low level, the first N-channel field effect transistor N1 is turned on, the second N-channel field effect transistor N2 is turned off, the first switch tube T1 is turned on, the potential at point A is 0, the potential at point B is VDDH, and the potential at the output end of the voltage output unit 102 is 0.

[0073] When the first control signal Xh1 is at a low level and the second control signal Xh2 is at a high level, the first N-channel field effect transistor N1 is turned off, the second N-channel field effect transistor N2 is turned on, the first switch tube T1 is turned off, the potential at point A is VDDH, the potential at point B is 0, and the potential at the output end of the voltage output unit 102 is VDDH. When the first control signal Xh1 is at a high level and the second control signal Xh2 is at a low level, the first switch tube T1 is turned on to charge the point B, and there is no need to wait until the potential at point A rises to turn on the second P-channel field effect transistor P2 before raising the potential at point B. Since point B starts to be pulled up after the first switch tube T1 is turned on, the voltage received by its gate is VDDL, which is not enough to make the first switch tube T1 enter the saturation region. Therefore, the subsequent stage of pulling up is the same as the traditional potential shifting circuit, and the second P-channel field effect transistor P2 is required to pull the voltage at point B up to VDDH. Finally, the voltage rising speed at point B and the time consumed for voltage pull-up are improved, thereby improving the efficiency of the level shift circuit and improving the periodicity. In addition, due to the delay effect of the first inverter U1, the gate of the second N-channel field effect transistor N2 first receives a low-level signal to turn off, and then the gate of the first switch tube T1 receives a high-level signal to turn on. Therefore, competition at point B can be avoided, resulting in the voltage at point B being pulled up by the first switch tube T1 while being pulled down by the second N-channel field effect transistor N2, thereby reducing power consumption.

[0074] In some embodiments, please refer to Figure 4 ,exist Figure 2 On the basis of the illustrated embodiment, the potential shifting circuit further includes a third P-channel field effect transistor P3, wherein the first switch tube T1 is an N-channel field effect transistor. The drain of the first switch tube T1 is connected to the first voltage VDDH through the third P-channel field effect transistor P3. The drain of the third P-channel field effect transistor P3 is connected to the first voltage VDDH, the source of the third P-channel field effect transistor is connected to the drain of the first switch tube T1, and the source of the first switch tube T1 is connected to the point B. The third P-channel field effect transistor P3 can be connected to a control signal to keep it normally open, which can protect the first switch tube T1, prevent the first switch tube T1 from being directly connected to the power supply, and improve the switching performance of the first switch tube T1.

[0075] Understandably, please refer to Figure 5 The gate of the third P-channel field effect transistor P3 can also be connected to the point B to access the control signal. When working, when the potential of the point B gradually rises, until the potential of the point B reaches the first voltage VDDH, the third P-channel field effect transistor P3 is turned off. This solution is Figure 4Further improvement of the scheme shown can avoid leakage current from the first switch tube T1 to the point B when the first switch tube T1 is in the off state, thereby increasing the time consumed when the potential of the point B is pulled down, and can improve the smoothness of the target signal output by the voltage output unit.

[0076] In some embodiments, please refer to Figure 6 ,exist Figure 2 On the basis of the technical solution shown, the level shift circuit also includes a second switch tube T2, the input end of the second switch tube T2 is connected to the first voltage, the output end of the second switch tube T2 is connected to point A, the control end of the second switch tube T2 is connected to the second control signal, and the switching state of the second switch tube T2 is the same as that of the second N-channel field effect transistor N2.

[0077] When the second switch tube T2 is an N-channel field effect transistor, its gate is connected to the second control signal to switch between on and off under the control of the second control signal. Figure 6 In the embodiment, the second switch tube T2 is an N-channel field effect transistor. The second switch tube T2 can increase the voltage pull-up speed of the point A, thereby increasing the opening speed of the second P-channel field effect transistor P2. Thus, the voltage pull-up efficiency of the point B is also improved to a certain extent. Of course, it can be understood that when the second switch tube T2 is a P-channel field effect transistor, its gate can be connected to the first control signal.

[0078] It can be understood that in some embodiments, such as Figure 7 As shown, in this Figure 6 On the basis of the illustrated embodiment, the level shift circuit further includes a third P-channel field effect transistor P3. Correspondingly, the first switch tube T1 and the second switch tube T2 are both N-channel field effect transistors. The source of the third P-channel field effect transistor P3 is connected to the first voltage VDDH, the drain of the third P-channel field effect transistor P3 is connected to the drain of the first switch tube T1 and the second switch tube T2 respectively, the source of the first switch tube T1 is connected to point B, and the source of the second switch tube T2 is connected to point A. The gate of the third P-channel field effect transistor P3 is connected to a control signal; the third control signal is the same as the first control signal. The gate of the second switch tube T2 is connected to a second control signal. Among them, the gate of the third P-channel field effect transistor P3 can be connected to a control signal to keep it normally open, which can protect the first switch tube T1 and the second switch tube T2 and improve the switching performance of the first switch tube T1 and the second switch tube T2.

[0079] Please refer to Figure 8 As shown, Figure 8It is a schematic diagram of the structure of a level shift circuit in some other embodiments of the present application. The level shift circuit includes: a first P-channel field effect transistor P1, a second P-channel field effect transistor P2, a first N-channel field effect transistor N1, a second N-channel field effect transistor N2, a fourth P-channel field effect transistor P4, a fifth P-channel field effect transistor P5, a voltage output unit 102 and a first switch tube T1.

[0080] Among them, the source of the first P-channel field effect transistor P1 is connected to the first voltage VDDH, and the drain of the first P-channel field effect transistor is connected to the point A through the fourth P-channel field effect transistor P4. Specifically, the drain of the fourth P-channel field effect transistor P4 is connected to the source of the first P-channel field effect transistor P1, and the source of the fourth P-channel field effect transistor is connected to the point A. The gate of the first P-channel field effect transistor P1 is connected to the point B. The gate of the fourth P-channel field effect transistor P4 is connected to the gate of the first N-channel field effect transistor N1. The drain of the first N-channel field effect transistor N1 is connected to the point A, the gate of the first N-channel field effect transistor N1 is connected to the first control signal Xh1, and the source of the first N-channel field effect transistor N1 is connected to the preset low voltage. The input end of the voltage output unit 102 is connected to the point B, and the output end of the voltage output unit 102 is used to output the target signal based on the voltage of the point B.

[0081] The source of the second P-channel field effect transistor P2 is connected to the first voltage VDDH, the drain of the second P-channel field effect transistor P2 is connected to point B through the fifth P-channel field effect transistor P5, and the gate of the second P-channel field effect transistor P2 is connected to point A. The drain of the second P-channel field effect transistor P2 is connected to the source of the fifth P-channel field effect transistor P5, and the drain of the fifth P-channel field effect transistor P5 is connected to point B. The drain of the second N-channel field effect transistor N2 is connected to point B, the gate of the second N-channel field effect transistor N2 is connected to the gate of the fifth P-channel field effect transistor P5 to access the second control signal Xh2, and the source of the second N-channel field effect transistor N2 is connected to the preset low voltage. The input end of the first switch tube T1 is connected to the first voltage VDDH, the output end of the first switch tube T1 is connected to point B, and the switch state of the first switch tube T1 is the same as the switch state of the first N-channel field effect transistor N1.

[0082] The first P-channel field effect transistor P1 is used to switch between on and off under the control of the potential at the point B, and the first P-channel field effect transistor P1 is used to pull the voltage at the point A to the first voltage VDDH when turned on.

[0083] The second P-channel field effect transistor P2 is switched on and off under the control of the potential at the point A, and the second P-channel field effect transistor P2 is used to pull the voltage at the point B to the first voltage VDDH when it is turned on.

[0084] The first N-channel field effect transistor N1 switches between on and off under the control of the first control signal Xh1. The voltage of the preset low voltage is less than the first voltage VDDH, and the preset low voltage can be a ground point. The first N-channel field effect transistor N1 is used to pull the voltage of point A down to the preset low voltage when it is turned on.

[0085] The fourth P-channel field effect transistor is used to be turned off when the first N-channel field effect transistor N1 is turned on, and turned on when the first N-channel field effect transistor N1 is turned off. By setting the fourth P-channel field effect transistor P4, competition can be avoided at the point A, that is, when the first N-channel field effect transistor N1 pulls down the potential of the point A, the first P-channel field effect transistor P1 can be prevented from pulling up the potential of the point A.

[0086] The second N-channel field effect transistor N2 is switched on and off under the control of the second control signal Xh2. The second N-channel field effect transistor N2 is used to pull down the voltage at the point B to the preset low voltage when it is turned on.

[0087] The fifth P-channel field effect transistor is used to be turned off when the second N-channel field effect transistor N2 is turned on, and the fifth P-channel field effect transistor is used to be turned on when the second N-channel field effect transistor N2 is turned off. By setting the fifth P-channel field effect transistor P5, competition can be avoided at the point B, that is, when the second N-channel field effect transistor N2 pulls down the potential of the point B, the second P-channel field effect transistor P2 can be prevented from pulling up the potential of the point B.

[0088] The input end of the voltage output unit 102 is connected to point B, and the output end of the voltage output unit 102 is used to output the shifted target signal according to the voltage at point B. The voltage output unit 102 may include one or more second inverters U2 connected in series. The number of second inverters U2 is an odd number. The voltage at point B and the target signal are inverted signals. The amplitude value of the target signal is equal to the first voltage VDDH.

[0089] Of course, it is understandable that in some embodiments, the voltage output unit 102 may also include only one signal output pin, which does not process the voltage at point B.

[0090] Among them, the input end of the first switch tube T1 is connected to the first voltage VDDH, the output end of the first switch tube is connected to point B, and the gate of the first switch tube T1 is connected to the third control signal, so as to pull the voltage at point B to the first voltage when it is turned on; the on-off state of the first switch tube T1 is the same as that of the first N-channel field effect transistor N1, and is opposite to the on-off state of the second N-channel field effect transistor N2.

[0091] The first switch tube T1 may be an N-channel field effect transistor, and correspondingly, the third control signal is the same as the first control signal Xh1. Alternatively, the first switch tube T1 may be a P-channel field effect transistor, and correspondingly, the third control signal is opposite to the first control signal Xh1. In the embodiment of the present application, a voltage input unit 101 may be provided to provide the third control signal, the first control signal Xh1, and the second control signal Xh2 to the first switch tube T1, the first N-channel field effect transistor N1, and the second N-channel field effect transistor N2, respectively.

[0092] Specifically, in some embodiments, the voltage input unit 101 includes one or more first inverters U1 connected in series, wherein the number of the first inverters U1 is an odd number.

[0093] When the first switch tube T1 is an N-channel field effect transistor, the first control signal Xh2 is the same as the third control signal. The input end of the voltage input unit 101 is connected to the second control signal Xh2, and the output end of the voltage input unit 101 outputs the first control signal Xh1. The input end of the voltage input unit 101 is connected to the gate of the second N-channel field effect transistor N2, and the output end of the voltage input unit 101 is respectively connected to the gate of the first N-channel field effect transistor N1 and the gate of the first switch tube T1.

[0094] When the first switch tube T1 is a P-channel field effect transistor, the input end of the voltage input unit 101 is connected to the second control signal Xh2, and the output end of the voltage input unit 101 outputs the first control signal Xh1. The input end of the voltage input unit 101 is respectively connected to the gate of the second N-channel field effect transistor N2 and the gate of the first switch tube T1, and the output end of the voltage input unit 101 is connected to the gate of the first N-channel field effect transistor N1.

[0095] Should Figure 8In the circuit diagram shown, when the first control signal Xh1 is at a high level and the second control signal Xh2 is at a low level, the first N-channel field effect transistor N1 is turned on, the second N-channel field effect transistor N2 is turned off, the first switch tube T1 is turned on, the potential at point A is 0, the potential at point B is VDDH, and the potential at the output end of the voltage output unit 102 is 0. When the first control signal Xh1 is at a low level and the second control signal Xh2 is at a high level, the first N-channel field effect transistor N1 is turned off, the second N-channel field effect transistor N2 is turned on, the first switch tube T1 is turned off, the potential at point A is VDDH, the potential at point B is 0, and the potential at the output end of the voltage output unit 102 is VDDH.

[0096] Among them, when the first control signal Xh1 is at a high level and the second control signal Xh2 is at a low level, the first switch tube T1 is turned on to charge the point B. There is no need to wait until the potential at point A rises to turn on the second P-channel field effect transistor P2 before raising the potential at point B. Therefore, the potential at point B can quickly reach VDDH, reducing the time consumed by raising the voltage at point B and having little impact on the time consumed by lowering the voltage at point B, thereby improving the efficiency of the level shifting circuit and improving the periodicity.

[0097] Since point B starts to be pulled up after the first switch tube T1 is turned on, because the voltage received by its gate is VDDL, which is not enough to make the first switch tube T1 enter the saturation region, the subsequent stage of pulling up is still the same as the traditional potential shifting circuit, and the second P-channel field effect transistor P2 is required to pull up the voltage of point B to VDDH. Finally, the voltage rising speed of point B and the time consumed by the voltage pull-up are improved, so that the efficiency of the level shifting circuit is improved and the periodicity is better. In addition, due to the delay effect of the first inverter U1, the gate of the second N-channel field effect transistor N2 first receives a low-level signal to turn off, and then the gate of the first switch tube T1 receives a high-level signal to turn on. Therefore, it can avoid the competition phenomenon at point B, resulting in the voltage at point B being pulled up by the first switch tube T1 and pulled down by the second N-channel field effect transistor N2 at the same time, which can reduce power consumption. Furthermore, since the fourth P-channel field effect transistor P4 and the fifth P-channel field effect transistor P5 are in the off state when the first N-channel field effect transistor N1 and the second N-channel field effect transistor N2 are turned on, it is possible to avoid competition when the voltage at point B is pulled down by the second N-channel field effect transistor N2, and the second P-channel field effect transistor will not have a pull-up effect on the voltage at point B. Therefore, power consumption can be reduced and the time consumed for pulling down the voltage at point B can be increased.

[0098] It is understandable that in some embodiments, please refer to Fig. 9 ,exist Figure 8 On the basis of the illustrated embodiment, the potential shifting circuit further includes a third P-channel field effect transistor P3, wherein the first switch tube T1 is an N-channel field effect transistor. The drain of the first switch tube T1 is connected to the first voltage VDDH through the third P-channel field effect transistor P3. The source of the third P-channel field effect transistor P3 is connected to the first voltage VDDH, the source of the third P-channel field effect transistor is connected to the drain of the first switch tube T1, and the source of the first switch tube T1 is connected to the point B. The third P-channel field effect transistor P3 can be connected to a control signal to keep it normally open, which can protect the first switch tube T1 and improve the switching performance of the first switch tube T1.

[0099] Understandably, please refer to Fig.10 The gate of the third P-channel field effect transistor P3 can also be connected to the point B to access the control signal. During operation, when the potential of the point B gradually rises, the third P-channel field effect transistor P3 is gradually turned off until the potential of the point B reaches the first voltage VDDH, and the third P-channel field effect transistor P3 is completely turned off. This solution is Fig. 9 Further improvement of the scheme shown can avoid leakage current from the first switch tube T1 to the point B when the first switch tube T1 is in the off state, thereby increasing the time consumed when the potential of the point B is pulled down, and can improve the smoothness of the target signal output by the voltage output unit.

[0100] In some embodiments, please refer to Fig.11 ,exist Figure 8 Based on the technical solution shown, the level shift circuit also includes a second switch tube T2, the input end of the second switch tube T2 is connected to the first voltage, the output end of the second switch tube T2 is connected to point A, and the control end of the second switch tube T2 is connected to the second control signal or the first control signal.

[0101] When the second switch tube T2 is an N-channel field effect transistor, its gate is connected to the second control signal, and when the second switch tube T2 is a P-channel field effect transistor, its gate is connected to the first control signal. Fig.12 In the embodiment, the second switch tube T2 is an N-channel field effect transistor. The second switch tube T2 can increase the voltage pull-up speed of the point A, thereby increasing the opening speed of the second P-channel field effect transistor P2. Thus, the voltage pull-up efficiency of the point B is also improved to a certain extent.

[0102] It can be understood that in some embodiments, Fig.11 Based on the embodiment shown, Fig.12As shown, the level shift circuit also includes a third P-channel field effect transistor P3. Correspondingly, the first switch tube T1 and the second switch tube T2 are both N-channel field effect transistors. The source of the third P-channel field effect transistor P3 is connected to the first voltage VDDH, the drain of the third P-channel field effect transistor P3 is connected to the drain of the first switch tube T1 and the drain of the second switch tube T2 respectively, and the gate of the third P-channel field effect transistor P3 is connected to the control signal; the third control signal is the same as the first control signal. The gate of the second switch tube T2 is connected to the second control signal. Among them, the gate of the third P-channel field effect transistor P3 can be connected to the control signal to keep it normally open, which can protect the first switch tube T1 and the second switch tube T2 and improve the switching performance of the first switch tube T1 and the second switch tube T2.

[0103] Understandably, if Fig.13 As shown, in some embodiments, in the Fig.11 On the basis of the embodiment shown, the level shift circuit further includes a third P-channel field effect transistor P3 and a sixth P-channel field effect transistor P6, the source of the third P-channel field effect transistor P3 is connected to the first voltage VDDH, the drain of the third P-channel field effect transistor P3 is connected to the drain of the first switch tube T1, and the gate of the third P-channel field effect transistor P3 is connected to point B. The gate of the first switch tube T1 is connected to the second control signal. The source of the sixth P-channel field effect transistor P6 is connected to the first voltage VDDH, the drain of the sixth P-channel field effect transistor P6 is connected to the drain of the second switch tube T2, and the gate of the sixth P-channel field effect transistor P6 is connected to point A. The gate of the second switch tube T2 is connected to the first control signal. The third P-channel field effect transistor P3 and the sixth P-channel field effect transistor P6 can respectively protect the first switch tube T1 and the second switch tube T2, and improve the switching performance of the first switch tube T1 and the second switch tube T2. Furthermore, during operation, when the potential at point B gradually rises, the third P-channel field effect transistor P3 is gradually turned off until the potential at point B reaches the first voltage VDDH, and the third P-channel field effect transistor P3 is completely turned off. This solution can avoid the leakage current of the first switch tube T1 flowing to point B when the first switch tube T1 is in the off state, thereby increasing the time consumed when the potential at point B is pulled down, and can improve the smoothness of the target signal output by the voltage output unit. Similarly, the sixth P-channel field effect transistor P6 can also reduce the leakage current of the second switch tube flowing to point A when the second switch tube T2 is in the off state.

[0104] The level shift circuit provided in the embodiment of the present application adopts the first switch tube to be turned on after the first N-channel field effect transistor is turned off, thereby directly raising the potential of point B, without waiting for the potential of point A to rise to turn on the second P-channel field effect transistor before starting to raise the potential of point B, which can increase the time consumed by the potential raising, thereby improving the efficiency of the level shift circuit. In addition, since the present application also adopts the fourth P-channel field effect transistor, the fourth P-channel field effect transistor is used to turn off when the first N-channel field effect transistor is turned on, and turn on when the first N-channel field effect transistor is turned off, thereby avoiding the competition phenomenon at point A, that is, avoiding the first P-channel field effect transistor from raising the potential of point A when the first N-channel field effect transistor pulls down the potential of point A. By providing the fifth P-channel field effect transistor, the fifth P-channel field effect transistor is used to be turned off when the second N-channel field effect transistor is turned on, and turned on when the second N-channel field effect transistor is turned off, so as to avoid competition at the point B, that is, to avoid the second P-channel field effect transistor pulling up the potential of the point B when the second N-channel field effect transistor pulls down the potential of the point A. Thus, the power consumption can be further reduced and the efficiency can be improved.

[0105] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A level shift circuit, It is characterized in that include: A first P-channel field effect transistor, whose source is connected to the first voltage, whose drain is connected to point A, and whose gate is connected to point B; A second P-channel field effect transistor, whose source is connected to the first voltage, whose drain is connected to point B, and whose gate is connected to point A; A first N-channel field effect transistor, whose drain is connected to point A, whose gate is connected to the first control signal, and whose source is connected to a preset low voltage; A second N-channel field effect transistor, whose drain is connected to point B, whose gate is connected to the second control signal, and whose source is connected to a preset low voltage; A voltage output unit, whose input terminal is connected to point B, and whose output terminal is used to output the shifted target signal according to the voltage at point B; A first switch tube, whose input end is connected to a first voltage, whose output end is connected to point B, and whose gate is connected to a third control signal; the first switch tube is used to be turned on before the second P-channel field effect transistor is turned on after the second N-channel field effect transistor is turned off, so as to raise the potential of point B, and after the second P-channel field effect transistor is turned on, the first switch tube raises the potential of point B together with the second P-channel field effect transistor.

2. The level shift circuit according to claim 1, It is characterized in that Also includes: The second switch tube has an input terminal connected to the first voltage, an output terminal connected to point A, and a control terminal connected to the second control signal. The switching state of the second switch tube is the same as that of the first N-channel field effect transistor.

3. The level shift circuit according to claim 2, It is characterized in that Also includes: A third P-channel field effect transistor, whose source is connected to the first voltage, whose drain is connected to the input end of the first switch tube and the input end of the second switch tube, and whose gate is connected to the control signal; the first switch tube and the second switch tube are both N-channel field effect transistors, the third P-channel field effect transistor is a P-channel field effect transistor, and the third control signal is the same as the first control signal.

4. The level shift circuit according to claim 1, It is characterized in that The level shift circuit further comprises: A third P-channel field effect transistor, whose source is connected to the first voltage, whose drain is connected to the input end of the first switch tube, and whose gate is connected to the control signal; the first switch tube is an N-channel field effect transistor, the third P-channel field effect transistor is a P-channel field effect transistor, and the third control signal is the same as the first control signal.

5. The level shift circuit according to claim 3 or 4, It is characterized in that The gate of the third P-channel field effect transistor is connected to the point B, so that the voltage at the point B is connected as the control signal.

6. The level shift circuit according to claim 3 or 4, It is characterized in that The gate of the third P-channel field effect transistor is connected to a control signal to keep it normally open.

7. The level shift circuit according to claim 3 or 4, It is characterized in that The level shift circuit further comprises: A voltage input unit is respectively connected to the first N-channel field effect transistor, the second N-channel field effect transistor and the first switch tube to respectively provide a corresponding first control signal and a second control signal.

8. The level shift circuit according to claim 7, It is characterized in that The voltage input unit includes a first inverter; The input terminal of the first inverter is connected to a second control signal; The output end of the first inverter is connected to the gate end of the third P-channel field effect transistor and the gate end of the first N-channel field effect transistor respectively, and the output end of the output end of the first inverter outputs a first control signal.

9. The level shift circuit according to any one of claims 1 to 4, It is characterized in that The amplitude value of the target signal is equal to the first voltage.

10. The level shift circuit according to claim 9, It is characterized in that The voltage output unit includes a second inverter, an input terminal of the second inverter is connected to point B, and an output terminal of the second inverter outputs an inverted voltage of the voltage at point B.

11. The level shift circuit according to any one of claims 1 to 4, It is characterized in that The level shift circuit further comprises: A fourth P-channel field effect transistor, the first P-channel field effect transistor is connected to point A through the fourth P-channel field effect transistor, the source of the fourth P-channel field effect transistor is connected to the drain of the first P-channel field effect transistor, the drain of the fourth P-channel field effect transistor is connected to point A, and the gate of the fourth P-channel field effect transistor is connected to the gate of the first N-channel field effect transistor.

12. The level shift circuit according to any one of claims 1 to 4, It is characterized in that The level shift circuit further comprises: A fifth P-channel field effect transistor, the second P-channel field effect transistor is connected to point B through the fifth P-channel field effect transistor, the source of the fifth P-channel field effect transistor is connected to the drain of the second P-channel field effect transistor, the drain of the fifth P-channel field effect transistor is connected to point B, and the gate of the fifth P-channel field effect transistor is connected to the gate of the second N-channel field effect transistor.

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