LED display system and control method thereof

Abstract

The present invention discloses an LED display system and a control method thereof. The display system comprises: a control card, outputting multiple clock signals and data signals; at least one drive circuit group, connected to the control card, each drive circuit group comprising multiple cascaded drive circuits, each drive circuit group receiving one clock signal and data signal and transmitting them in multiple drive circuits, at least one drive circuit in each drive circuit group comprising an inverter, the inverter inverting the clock signal received by the drive circuit at this level to obtain an inverted clock signal. The LED display system of the present invention can effectively avoid excessive attenuation of the clock signal in the cascaded drive circuit, ensure the correctness of data sampling based on the clock signal, and ensure the display effect of the LED display screen.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display system of an LED display screen and a control method thereof. Background Art

[0002] Traditional LED (Light Emitting Diode) display systems such as Figure 1 As shown, the LED display system 100 generally includes a control card 110 and a plurality of drive circuits 120. The control card 110 provides multiple signals, each of which controls a corresponding plurality of drive circuits 120 connected in series. As the number of drive circuits 120 connected in series in the system increases, the signal provided by the control card 110 will gradually attenuate due to the increase in load, wherein the attenuation of the clock signal is particularly obvious during the transmission process.

[0003] The clock signal is a signal that switches back and forth between high and low levels. When the clock signal decays, the duty cycle of the clock signal will change. If the clock signal, which is the basis for data sampling, keeps decaying, other digital signals will not be read correctly, affecting the display effect of the LED display. Summary of the invention

[0004] In view of the above problems, an object of the present invention is to provide an LED display system and a control method thereof, so as to avoid excessive attenuation of the clock signal and ensure the display effect of the LED display screen.

[0005] According to one aspect of the present invention, there is provided an LED display system, comprising: a control card, outputting multiple clock signals and data signals; at least one drive circuit group, connected to the control card, each drive circuit group comprising a plurality of cascaded drive circuits, each drive circuit group receiving one clock signal and one data signal and transmitting them among the plurality of drive circuits, at least one drive circuit in each drive circuit group comprising an inverter, the inverter inverting the clock signal received by the drive circuit at this stage to obtain an inverted clock signal.

[0006] Optionally, each of the driving circuits further includes: a communication unit connected to the control card or the previous driving circuit to receive the clock signal and the data signal, decode the data signal according to the clock signal, and transmit the data signal to the next driving circuit.

[0007] Optionally, each of the driving circuits of the at least one driving circuit group includes the inverter.

[0008] Optionally, the data signal includes display data, parameter values ​​and an ID of a driving circuit.

[0009] Optionally, each of the driving circuits also includes: a comparison and selection unit, connected to the communication unit to receive the decoded data signal, and according to the ID and parameter value of the driving circuit, selecting to provide the inverted clock signal or the clock signal received by the current level driving circuit to the next level driving circuit, and the parameter value is a positive integer.

[0010] Optionally, the comparison and selection unit includes: a comparator, connected to the communication unit to receive the parameter value and the ID of the driving circuit at this level, and provide a comparison result of the parameter value and the ID of the driving circuit; a selector, a first input end connected to the inverter to receive the inverted clock signal, a second input end to receive the clock signal of the driving circuit at this level, a control end connected to the output end of the comparator to receive the comparison result, and an output end to output the inverted clock signal or the clock signal of the driving circuit at this level to the next level of driving circuit.

[0011] Optionally, the IDs of the driving circuits in each driving circuit group are 1, 2, 3 . . . X or a cycle of 1 to N, wherein X is a positive integer and N is the parameter value.

[0012] Optionally, when the comparison result of the comparator is that the ID of the drive circuit is equal to the parameter value or an integer multiple of the parameter value, the selector uses the inverted clock signal as the clock signal of the next-level drive circuit; when the comparison result of the comparator is that the ID of the drive circuit is not equal to the parameter value or an integer multiple of the parameter value, the selector uses the clock signal of the current-level drive circuit as the clock signal of the next-level drive circuit.

[0013] Optionally, the communication unit comprises a decoder.

[0014] Optionally, the inverter is a NOT gate.

[0015] Optionally, each of the driving circuits further includes: a driving unit connected to the communication unit to receive the decoded display data.

[0016] According to one aspect of the present invention, there is provided a control method for a display system, comprising: providing multiple clock signals and data signals; each driving circuit group receives one of the clock signals and the data signals and transmits them in multiple driving circuits, at least one driving circuit in each driving circuit group inverts the clock signal received by the driving circuit at this level to obtain an inverted clock signal, wherein each driving circuit group includes multiple cascaded driving circuits.

[0017] Optionally, the method further includes: each of the driving circuits decodes the data signal according to the received clock signal, and transmits the data signal to the next-stage driving circuit.

[0018] Optionally, each driving circuit in each driving circuit group performs inversion processing on a clock signal received by the driving circuit at the same stage to obtain an inverted clock signal.

[0019] Optionally, the data signal includes display data, parameter values ​​and an ID of a driving circuit.

[0020] Optionally, it also includes: each driving circuit selects to provide the inverted clock signal or the clock signal received by the driving circuit at this stage to the next stage driving circuit according to the ID of the driving circuit and a parameter value, and the parameter value is a positive integer.

[0021] Optionally, the IDs of the driving circuits in each driving circuit group may be 1, 2, 3 . . . X or a cycle of 1 to N, wherein X is a positive integer and N is the parameter value.

[0022] Optionally, when the ID of the driving circuit is equal to the parameter value or an integer multiple of the parameter value, the inverted clock signal is used as the clock signal of the next-level driving circuit; when the ID of the driving circuit is not equal to the parameter value or an integer multiple of the parameter value, the clock signal of the current-level driving circuit is used as the clock signal of the next-level driving circuit.

[0023] The LED display system provided by the present invention provides an inverter in at least one driving circuit in each group of cascaded multiple driving circuits to invert the clock signal and provide the inverted clock signal to the next level driving circuit. This embodiment can effectively avoid excessive attenuation of the clock signal in the cascaded driving circuit through simple hardware design, ensure the correctness of data sampling based on the clock signal, and ensure the display effect of the LED display screen.

[0024] Preferably, an inverter is added in each driving circuit to invert the clock signal of this stage to obtain an inverted clock signal and provide it to the next stage driving circuit, which can effectively avoid excessive attenuation of the clock signal in the cascaded driving circuit, and can also improve the designability of the driving circuit and the flexibility of the LED display system. Further, a comparison and selection unit is also provided in each driving circuit. The comparison and selection unit of each driving circuit provides the clock signal of the driving circuit of this stage or the inverted clock signal obtained after processing by the inverter to the next stage driving circuit based on the parameter value provided by the control card and the ID of each driving circuit, so that in the LED display system, after each transmission through the driving circuit of the set parameter value, the inverted clock signal is provided to the next stage driving circuit, and the clock signal of the previous stage driving circuit is provided to the driving circuits of the remaining stages. The above-mentioned set parameter values ​​can be flexibly adjusted according to the clock signal attenuation rate of the actual circuit to be suitable for a variety of application environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0026] Figure 1 Shown is a structural block diagram of an LED display system according to the prior art;

[0027] Figure 2 It shows a structural block diagram of an LED display system according to a first embodiment of the present invention;

[0028] Figure 3 It shows a schematic structural diagram of an LED display system according to a second embodiment of the present invention;

[0029] Figure 4 A schematic diagram showing the working principle of a driving circuit in an LED display system according to a second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0030] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0031] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0032] Figure 2 A structural block diagram of an LED display system according to a first embodiment of the present invention is shown.

[0033] like Figure 2 As shown, the LED display system 200 includes a control card 110, and a plurality of drive circuit groups respectively connected to the control card 110, each drive circuit group including a plurality of cascaded drive circuits 220. The LED display system 200 also includes a plurality of LED light groups connected to the drive circuits 220, wherein the plurality of light groups constitute an LED display screen. The control card 110 provides a plurality of control signals, each of which controls a corresponding plurality of cascaded drive circuits 220, and each of which includes a data signal for driving the LED light group and a clock signal for indicating a timing logic, and the data signal at least includes display data.

[0034] The at least one driving circuit 220 includes a driving unit 221 , an inverter 222 , and a communication unit 223 .

[0035] The communication unit 223 is connected to the control card 110 or the previous level driving circuit 220 to receive the clock signal and the data signal, and decodes the data signal in cooperation with the clock signal, and then sends the display data required by the current level driving circuit 220 to the driving unit 221. The communication unit 324 further transmits the data signal to the communication unit of the next level driving circuit 220. The inverter 223 is connected to the control card 110 or the previous level driving circuit 220 to receive the clock signal, and performs inversion processing on the received clock signal to obtain the inverted clock signal to provide to the next level driving circuit 220.

[0036] The LED display system 200 includes at least one drive circuit 220 provided with an inverter 222, and the drive circuit 220 can be any level of drive circuit in the LED display system 200. Further, the remaining drive circuits in the LED display system 200 that do not have the inversion processing capability only include a communication unit 223 and a drive unit 222, wherein the communication unit 223 is connected to the control card 110 or the upper level drive circuit to receive the clock signal and the data signal and transmit the clock signal and the data signal to the next level drive circuit, and decodes the data signal in cooperation with the clock signal, and then sends the display data required by the current level drive circuit to the drive unit 221.

[0037] Preferably, if Figure 2 As shown, each stage of the driving circuit in the LED display system 200 is a driving circuit 220 with an inversion processing capability.

[0038] The LED display system 200 can effectively avoid the continuous attenuation of the clock signal in multiple cascaded driving circuits. For example, when the clock signal with a duty cycle of 50% decays to 40% after passing through one or more driving circuits, the clock signal with a duty cycle of 40% is inverted at this time, and the high and low levels are reversed, and its duty cycle becomes 60%, avoiding excessive attenuation of the duty cycle, ensuring that the data sampling based on the clock signal can be accurately sampled, ensuring that the LED display system correctly reads the data signal, solving the attenuation problem, and ensuring the display effect of the LED display screen. Less hardware is used in the driving circuit of this embodiment to achieve efficient attenuation processing, saving costs.

[0039] Figure 3 A schematic structural diagram of an LED display system according to a second embodiment of the present invention is shown.

[0040] like Figure 3As shown, the LED display system 300 includes a control card 310, and a plurality of drive circuit groups respectively connected to the control card 310, each drive circuit group including a plurality of cascaded drive circuits 320. The LED display system 300 also includes a plurality of LED lamp groups connected to the drive circuit 320, wherein the plurality of lamp groups constitute an LED display screen. Compared with the LED display system 200 in which at least one drive circuit performs inversion processing on the received clock signal and outputs the inverted clock signal to the next drive circuit, in the LED display system 300 of this embodiment, each drive circuit 320 in each drive circuit group performs inversion processing on the received clock signal and selects the received clock signal or the inverted clock signal as the clock signal received by the next drive circuit 320. Specifically, after the clock signal is transmitted via the set parameter value drive circuit 320, the inverted clock signal is used as the clock signal received by the next drive circuit 320.

[0041] The control card 310 provides multiple control signals, each of which controls multiple cascaded drive circuits 320 in each drive circuit group. Each control signal includes a data signal for driving the LED light group and a clock signal for indicating the timing logic. The control card 310 sets the parameter value N and configures an ID (Identity document) for each level of drive circuit 320. The parameter value N determines that when the ID of the drive circuit is N or a multiple of N, the inverted clock signal is output as the clock signal received by the next level of drive circuit, wherein the parameter value N is a positive integer. Further, the ID of the drive circuit 320 is used to indicate the relative position of the drive circuit 320 in the LED display system. For example, when the drive circuit 320 is located in the third level in the drive circuit group that receives the control signal output by a certain routing control card 310, the ID assigned to it by the control card 310 is 3.

[0042] The driving circuit 320 includes a driving unit 321 , an inverter 322 , a communication unit 324 , and a comparison and selection unit 323 . The comparison and selection unit 323 includes a comparator 3231 and a selector 3232 .

[0043] The inverter 322 is connected to the control card 310 or the upper-level driving circuit 320 to receive a clock signal, and performs inversion processing on the received clock signal to obtain an inverted clock signal.

[0044] The communication unit 324 is connected to the control card 310 or the previous level driving circuit 320 to receive the clock signal and the data signal, wherein the data signal at least includes the display data, the ID of each level driving circuit 320 and the parameter value N. The data signal is decoded with the cooperation of the clock signal, and then the display data required by the current level driving circuit 320 is sent to the driving unit 321. The communication unit 324 further transmits the control signal including the data signal to the communication unit of the next level driving circuit 320. The communication unit 324 provides the parameter value N obtained by decoding the data signal and the ID assigned to the current level driving circuit 320 to the comparison and selection unit 323 of the current level driving circuit 320.

[0045] The comparator 3231 of the comparison selection unit 323 is connected to the communication unit 324 to receive the decoded ID of the current stage driving circuit 320 and the parameter value N set by the control card 310, and outputs the comparison result of the ID of the current stage driving circuit 320 and the parameter value N.

[0046] The first input terminal of the selector 3232 of the comparison selection unit 323 is connected to the inverter 322, and the second input terminal receives the clock signal. The control terminal of the selector 3232 is connected to the output terminal of the comparator 3231 to receive the comparison result, and the output terminal of the selector 3232 provides the next-stage driving circuit 320 with the clock signal inverted by the inverter 322 or the clock signal received by the current-stage driving circuit 320 as the clock signal received by the next-stage driving circuit 320. When the comparison result indicates that the ID of the driving circuit 320 is the parameter value N or a multiple of the parameter value N, the selector 3232 outputs the inverted clock signal, otherwise the received clock signal is provided to the next stage.

[0047] In the LED display system 300 of the present embodiment, each level of driving circuit 320 inverts the received clock signal to obtain an inverted clock signal, and provides the received clock signal or the inverted clock signal to the next level of driving circuit 320 according to the comparison result of its own ID and parameter value N, wherein the clock signal provides an inverted clock signal to the next level after passing through N levels of driving circuits, the value of parameter value N can be determined according to the clock signal attenuation rate of the actual circuit, and the value of parameter value N is determined by the control card 310, and is not an immutable fixed value, but can be flexibly adjusted to be suitable for a variety of application environments.

[0048] Specifically, Figure 4 A schematic diagram showing the working principle of a driving circuit in an LED display system according to a second embodiment of the present invention is shown.

[0049] like Figure 4 As shown, the following steps are included. It should be noted that the working principle of the driving circuit is described in the form of a flow chart, which is only for a more detailed explanation of this embodiment.

[0050] S01: The control card sets the parameter value N and configures an ID for each level of the driving circuit. N is a positive integer. There are two ID configuration schemes for the driving circuit. Scheme 1: Assuming that each signal of the control card 310 is provided to a driving circuit group composed of X driving circuits in cascade, each level of the driving circuit 320 in each driving circuit group is sequentially configured with IDs of 1, 2, 3...X; Scheme 2: Assuming that each signal of the control card 310 is provided to a driving circuit group composed of X driving circuits in cascade, each level of the driving circuit 320 in each driving circuit group is sequentially configured with IDs of 1 to N in a cyclic manner. Wherein, X is a positive integer.

[0051] S02: The inverter of each stage of the driving circuit outputs an inverted clock signal. The inverter 322 of the driving circuit 320 of this stage inverts the received clock signal to obtain an inverted clock signal. The inverter 322 can be a simple logic element NOT gate.

[0052] S03: Compare the ID of the driving circuit with the parameter value N. The comparator 3231 receives the ID and the parameter value N decoded by the communication unit 324. The communication unit 324 implements decoding by, for example, setting a decoder.

[0053] S04: Determine whether the ID of the driving circuit is equal to the parameter value N or equal to an integral multiple of the parameter value N. The above solution is executed by the comparator 3231 .

[0054] S05: If the ID of the driving circuit is equal to the parameter value N or an integer multiple of the parameter value N, the inverted clock signal is provided to the next stage driving circuit. If the comparison result of the comparator 3231 is that the ID of the driving circuit is equal to the parameter value N or an integer multiple of the parameter value N, the selector 3232 provides the inverted clock signal of the inverter 322 to the next stage driving circuit 320.

[0055] S06: If the ID of the driving circuit is not equal to the parameter value N nor equal to an integer multiple of the parameter value N, the clock signal received at this stage is provided to the next stage driving circuit. The comparison result of the comparator 3231 is that the ID is not equal to the parameter value N nor equal to an integer multiple of the parameter value N, and the selector 3232 directly provides the clock signal received by the driving circuit 320 at this stage to the driving circuit 320 at the next stage.

[0056] According to ID configuration scheme 1, determine whether the ID is equal to an integer multiple of parameter value N; according to ID configuration scheme 2, determine whether the ID is equal to parameter value N.

[0057] The LED display system of the embodiment of the present invention can effectively avoid the continuous attenuation of the clock signal. For example, the duty cycle of a clock signal with a 50% duty cycle is attenuated to 40% after passing through one or more driving circuits. At this time, the clock signal with a 40% duty cycle is inverted, and the high and low levels are reversed, and its duty cycle becomes 60%, avoiding excessive attenuation of the duty cycle, ensuring that data sampling based on the clock signal works effectively, ensuring that the system reads digital signals correctly, ensuring the display effect of the LED display screen, and solving the attenuation problem.

[0058] The LED display system of this embodiment is provided with a comparison selection unit and an inverter for each stage of the driving circuit. In actual equipment, there are many stages of driving circuits. The comparison selection units and inverters can also be arranged at intervals in the cascaded driving circuits to reduce hardware costs. At the same time, the intervals can be reasonably designed according to the attenuation rate. For example, a comparison selection unit and an inverter can be arranged for each stage of driving circuits with an interval of one or ten stages. The lower the attenuation rate of the system, the larger the interval can be. A design with a small interval is suitable for a system with a high attenuation rate and can also be suitable for a system with a low attenuation rate.

[0059] The present application also provides a control method, which is applied to the above-mentioned display system.

[0060] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An LED display system, characterized in that: include: Control card, output multiple clock signals and data signals; At least one drive circuit group is connected to the control card, each drive circuit group includes a plurality of cascaded drive circuits, each drive circuit group receives one channel of the clock signal and the data signal and transmits them among the plurality of drive circuits, at least one drive circuit in each drive circuit group includes an inverter, the inverter inverts the clock signal received by the drive circuit at this stage to obtain an inverted clock signal, The data signal includes display data, parameter values ​​and the ID of the driving circuit. Each of the driving circuits also includes a comparison and selection unit. The comparison and selection unit is connected to the communication unit to receive the decoded data signal. According to the ID and parameter value of the driving circuit, the comparison and selection unit selects the inverted clock signal or the clock signal received by the current level driving circuit to be provided to the next level driving circuit. The parameter value is a positive integer.

2. The LED display system according to claim 1, characterized in that: Each of the driving circuits further comprises: A communication unit is connected to the control card or the upper-level driving circuit to receive the clock signal and the data signal, decodes the data signal according to the clock signal, and transmits the data signal to the next-level driving circuit.

3. The LED display system according to claim 2, characterized in that: Each of the driving circuits of the at least one driving circuit group includes the inverter.

4. The LED display system according to claim 2, characterized in that: The comparison and selection unit comprises: A comparator connected to the communication unit to receive the parameter value and the ID of the driving circuit at this stage, and provide a comparison result of the parameter value and the ID of the driving circuit; A selector, wherein the first input end is connected to the inverter to receive the inverted clock signal, the second input end receives the clock signal of the current stage driving circuit, the control end is connected to the output end of the comparator to receive the comparison result, and the output end outputs the inverted clock signal or the clock signal of the current stage driving circuit to the next stage driving circuit.

5. The LED display system according to claim 1, characterized in that: The IDs of the driving circuits in each driving circuit group are 1, 2, 3, ..., X or a cycle of 1 to N, wherein X is a positive integer and N is the parameter value.

6. The LED display system according to claim 4, characterized in that: When the comparison result of the comparator is that the ID of the drive circuit is equal to the parameter value or an integer multiple of the parameter value, the selector uses the inverted clock signal as the clock signal of the next-level drive circuit; when the comparison result of the comparator is that the ID of the drive circuit is not equal to the parameter value or an integer multiple of the parameter value, the selector uses the clock signal of the current-level drive circuit as the clock signal of the next-level drive circuit.

7. The LED display system according to claim 2, characterized in that: The communication unit includes a decoder.

8. The LED display system according to claim 1, characterized in that: The inverter is a NOT gate.

9. The LED display system according to claim 2, characterized in that: Each of the driving circuits further comprises: The driving unit is connected to the communication unit to receive the decoded display data.

10. A method for controlling a display system, characterized in that: include: Providing multiple clock signals and data signals, wherein the data signals include display data, parameter values ​​and IDs of driving circuits; Each driving circuit group receives one channel of the clock signal and the data signal and transmits them in a plurality of driving circuits, and at least one driving circuit in each driving circuit group inverts the clock signal received by the driving circuit at the same level to obtain an inverted clock signal; Each driving circuit selects to provide the inverted clock signal or the clock signal received by the driving circuit of the current stage to the driving circuit of the next stage according to the ID and parameter value of the driving circuit, and the parameter value is a positive integer. Each driving circuit group includes a plurality of cascaded driving circuits.

11. The control method according to claim 10, characterized in that: Also includes: Each of the driving circuits decodes the data signal according to the received clock signal and transmits the data signal to the next-stage driving circuit.

12. The control method according to claim 11, characterized in that: Each driving circuit in each driving circuit group performs inversion processing on the clock signal received by the driving circuit at the same stage to obtain an inverted clock signal.

13. The control method according to claim 10, characterized in that: The IDs of the driving circuits in each driving circuit group may be 1, 2, 3, ..., X, or a cycle of 1 to N, wherein X is a positive integer and N is the parameter value.

14. The control method according to claim 10, characterized in that: When the ID of the driving circuit is equal to the parameter value or an integer multiple of the parameter value, the inverted clock signal is used as the clock signal of the next-level driving circuit; when the ID of the driving circuit is not equal to the parameter value or an integer multiple of the parameter value, the clock signal of the current-level driving circuit is used as the clock signal of the next-level driving circuit.

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