FDSOI MOSFET model generation method and device based on BSIMIMG

Abstract

The invention discloses a method and device for generating a FDSOI MOSFET model based on BSIMIMG, which is applied to the field of integrated circuit design, and includes: a BSIMIMG back channel device model and a BSIMIMG positive channel device model, wherein the BSIMIMG back channel device model is merged into the BSIMIMG positive channel device model in the form of a controlled source; wherein the BSIMIMG positive channel device model is generated based on a new BSIMIMG standard model and positive channel device model parameters extracted from an FDSOI MOSFET device, and the BSIMIMG back channel device model is generated based on a new BSIMIMG standard model and back channel device model parameters extracted from an FDSOI MOSFET device, and the new BSIMIMG standard model is obtained by modifying the Verilog‑a code of the BSIMIMG standard model. The device model accuracy when the back channel is turned on is improved by the invention.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a method and apparatus for generating FDSOI MOSFET models based on BSIMIMG. Background Technology

[0002] With the development and increasingly widespread application of integrated circuit technology, the requirements for high reliability, high performance, and low cost must be considered during integrated circuit design. This has led to higher demands on the functionality and accuracy of IC CAD software in areas such as statistical tolerance analysis, design optimization, yield analysis, cost analysis, and reliability prediction. In IC CAD software, the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device model is a crucial link between IC design and the functionality and performance of IC products. As integrated device sizes shrink, integration scales increase, and integrated circuit processes become more complex, the accuracy requirements for device models also rise. Today, obtaining an accurate MOSFET model has undoubtedly become a primary problem for IC CAD designers and remains a key research focus and hot topic internationally.

[0003] Currently, the accuracy of FDSOI MOSFET models established in the industry deteriorates drastically when the back gate bias is large enough to enable the back channel. Summary of the Invention

[0004] In view of the above-mentioned technical problems in the prior art, the present invention provides a method and apparatus for generating FDSOIMOSFET models based on BSIMIMG.

[0005] In a first aspect, embodiments of the present invention provide a method for generating an FDSOI MOSFET model based on BSIMIMG, comprising:

[0006] Modify the Verilog-a code of the BSIMIMG standard model to obtain the new BSIMIMG standard model;

[0007] Extract the positive channel device model parameters and the back channel device model parameters from the FDSOI MOSFET device;

[0008] A BSIMIMG positive channel device model is generated based on the positive channel device model parameters and the new BSIMIMG standard model; and a BSIMIMG back channel device model is generated based on the back channel device model parameters and the new BSIMIMG standard model.

[0009] The BSIMIMG back-channel device model is merged into the BSIMIMG front-channel device model in a controlled source manner to obtain a synthetic model;

[0010] Adjust the model parameters of the synthesized model to obtain the target FDSOI MOSFET model.

[0011] Optionally, the extraction of the positive channel device model parameters and the back channel device model parameters of the FDSOI MOSFET device includes:

[0012] With the back channel of the FDSOI MOSFET device in an off state, extract the positive channel device model parameters of the FDSOI MOSFET device;

[0013] With the positive channel of the FDSOI MOSFET device in an off state, the back channel device model parameters of the FDSOI MOSFET device are extracted.

[0014] Optionally, the extraction of the back-channel device model parameters of the FDSOI MOSFET device includes:

[0015] The back gate oxide thickness of the FDSOI MOSFET device is extracted as the positive gate oxide thickness of the BSIMIMG back-channel device model, and

[0016] The positive gate oxide thickness of the FDSOI MOSFET device is extracted as the back gate oxide thickness of the BSIMIMG back channel device model, and

[0017] The back channel current of the FDSOI MOSFET device is extracted as the positive channel current of the BSIMIMG back channel device model.

[0018] Optionally, the step of merging the BSIMIMG back-channel device model into the BSIMIMG front-channel device model in a controlled-source manner to obtain a synthetic model includes:

[0019] A positive gate voltage is applied to the back gate of the BSIMIMG back channel device model, a back gate voltage is applied to the positive gate of the BSIMIMG back channel device model, and a drain voltage is applied to the drain of the BSIMIMG back channel device model.

[0020] A controlled source is connected in parallel on the BSIMIMG positive channel device model, wherein the controlled source is a voltage-controlled current source or a current-controlled current source;

[0021] The back-channel current of the BSIMIMG back-channel device model is introduced into the controlled source, and the total current of the synthesized model is the sum of the current of the BSIMIMG back-channel device model and the current of the BSIMIMG positive-channel device model.

[0022] Optionally, introducing the back-channel current of the BSIMIMG back-channel device model into the controlled source includes:

[0023] A first resistor is provided at the drain of the BSIMIMG back-channel device model;

[0024] The current or voltage across the first resistor is introduced into the controlled source.

[0025] Optionally, modifying the Verilog-a code of the BSIMIMG standard model to obtain a new BSIMIMG standard model includes:

[0026] The effective back gate voltage in the Verilog-a code is modified as follows: when the back gate voltage is greater than the back trench threshold voltage, the effective back gate voltage is equal to the back trench threshold voltage; when the back gate voltage is less than the back trench accumulated voltage, the effective back gate voltage is equal to the back trench accumulated voltage.

[0027] Optionally, adjusting the model parameters of the synthetic model to obtain the target FDSOI MOSFET model includes:

[0028] Adjust the positive gate threshold voltage and the back gate threshold voltage of the synthetic model.

[0029] Secondly, embodiments of the present invention provide an FDSOI MOSFET model generation device based on BSIMIMG, comprising:

[0030] The code modification unit is used to modify the Verilog-a code of the BSIMIMG standard model to obtain a new BSIMIMG standard model.

[0031] The model parameter extraction unit is used to extract the positive channel device model parameters and the back channel device model parameters from the FDSOI MOSFET device;

[0032] The model generation unit is used to generate a BSIMIMG positive channel device model based on the positive channel device model parameters and the new BSIMIMG standard model, and to generate a BSIMIMG back channel device model based on the back channel device model parameters and the new BSIMIMG standard model.

[0033] The model synthesis unit is used to merge the BSIMIMG back-channel device model into the BSIMIMG front-channel device model in a controlled source form to obtain a synthesized model.

[0034] The model parameter adjustment unit is used to adjust the model parameters of the synthesized model to obtain the target FDSOI MOSFET model.

[0035] Thirdly, embodiments of the present invention provide an FDSOI MOSFET model based on BSIMIMG, including: a BSIMIMG back-channel device model and a BSIMIMG front-channel device model, wherein the BSIMIMG back-channel device model is merged into the BSIMIMG front-channel device model in the form of controlled sources; wherein, the BSIMIMG front-channel device model is generated based on a new BSIMIMG standard model and front-channel device model parameters extracted from FDSOI MOSFET devices, and the BSIMIMG back-channel device model is generated based on the new BSIMIMG standard model and back-channel device model parameters extracted from FDSOI MOSFET devices, wherein the new BSIMIMG standard model is obtained by modifying the Verilog-a code of the BSIMIMG standard model.

[0036] The technical solution provided by this invention, based on the industry-standard SOI device model BSIMIMG, obtains a synthetic model by merging the BSIMIMG back-channel device model into the BSIMIMG front-channel device model in the form of a controlled source. This achieves the introduction of back-channel current into the BSIMIMG front-channel device model in the form of a controlled source, thereby simultaneously modifying the Veriloga code of the BSIMIMG standard model and adjusting the model parameters. As a result, it can cope with the changes in the coupling characteristics of the back gate bias to the front channel when the back channel is turned on, thus significantly improving the accuracy of the device model under the back-channel turned-on condition. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0038] Figure 1 A flowchart illustrating the method for generating a BSIMIMG-based FDSOI MOSFET device model according to an embodiment of the present invention;

[0039] Figure 2This is the equivalent circuit diagram of the FDSOI MOSFET model in the embodiment of the present invention;

[0040] Figure 3 This is a comparison of simulation and test data of the FDSOI MOSFET model generated in the embodiments of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Unless otherwise specified, the embodiments of the present invention and the technical features thereof can be combined with each other. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] In a first aspect, embodiments of the present invention provide a method for generating an FDSOI MOSFET model based on BSIMIMG (Berkeley Short-channel IGFET Model IMG). (See reference...) Figure 1 As shown, the generation method provided in this embodiment of the invention includes the following steps:

[0043] S1: Modify the Verilog-a code of the BSIMIMG standard model to obtain the new BSIMIMG standard model.

[0044] It should be noted that the BSIMIMG standard model is an industry-standard SOI device model. Verilog-A, on the other hand, is an industry-standard modeling language for analog circuits, used to describe the BSIMIMG standard model. Specifically, modifying the Verilog-A code of the BSIMIMG standard model involves modifying the effective back-gate voltage. In this embodiment of the invention, the effective back-gate voltage is modified as follows: when the back-gate voltage is greater than the back-channel threshold voltage, the effective back-gate voltage equals the back-channel threshold voltage; when the back-gate voltage is less than the back-channel accumulated voltage, the effective back-gate voltage equals the back-channel accumulated voltage.

[0045] S2. Extract the positive channel device model parameters and the back channel device model parameters from the FDSOI MOSFET device.

[0046] Specifically, the front channel device model parameters of the FDSOI MOSFET device need to be extracted when the back channel of the FDSOI MOSFET device is in the off state; and the back channel device model parameters need to be extracted when the front channel of the FDSOI MOSFET device is in the off state.

[0047] Specifically, there are many types of parameters to extract from the model parameters of forward-channel devices and back-channel devices. Therefore, existing technologies can be consulted to determine which model parameters to extract. Below, only some important model parameters are listed: back-channel threshold voltage (VTHINV), back-channel accumulation voltage (VTHACC), model flag (LEVEL), well type (WELLTYPE), top silicon film thickness (Tsi), back gate oxide thickness (EOT2); forward gate oxide thickness (EOT1), inversion layer channel doping concentration (Nbody), etc.

[0048] In the specific implementation, the positive gate oxide thickness is extracted as the positive gate oxide thickness of the BSIMIMG positive channel device model, and used as the back gate oxide thickness of the BSIMIMG back channel device model; conversely, the back gate oxide thickness is extracted as the back gate oxide thickness of the BSIMIMG positive channel device model, and used as the positive gate oxide thickness of the BSIMIMG back channel device model. Specific numerical values ​​are as follows:

[0049] The extracted values ​​of the parameters of each positive channel device model are as follows: VTHINV = 7; VTHACC = -15; LEVEL = 78; VERSION = 102.6; TYPE = 1; WELLTYPE = -1; EOT1 = 4.5E-9; EOT2 = 1.45E-7; TSI = 5E-8; NBODY = 1E22.

[0050] The extracted values ​​of the parameters for each back-channel device model are as follows: VTHINV = 0.69244; VTHACC = -0.6; LEVEL = 78; VERSION = 102.6; TYPE = 1; WELLTYPE = -1; EOT2 = 4.5E-9; EOT1 = 1.45E-7; TSI = 5E-8; NBODY = 1E22.

[0051] S3. Generate a BSIMIMG positive channel device model based on the positive channel device model parameters and the new BSIMIMG standard model, and generate a BSIMIMG back channel device model based on the back channel device model parameters and the new BSIMIMG standard model.

[0052] For the BSIMIMG positive channel device model, the extracted back gate oxide thickness of the FDSOI MOSFET device is used as the back gate oxide thickness of the BSIMIMG positive channel device model, the extracted positive gate oxide thickness of the FDSOI MOSFET device is used as the positive gate oxide thickness of the BSIMIMG positive channel device model, and the extracted back channel current of the FDSOI MOSFET device is used as the back channel current of the BSIMIMG back channel device model.

[0053] For the BSIMIMG back-channel device model, the extracted back gate oxide thickness of the FDSOI MOSFET device is used as the gate oxide thickness of the BSIMIMG back-channel device model, the extracted gate oxide thickness of the FDSOI MOSFET device is used as the back gate oxide thickness of the BSIMIMG back-channel device model, and the extracted back-channel current of the FDSOI MOSFET device is used as the positive channel current of the BSIMIMG back-channel device model.

[0054] S4. The BSIMIMG back-channel device model is merged into the BSIMIMG front-channel device model in a controlled source form to obtain a synthetic model.

[0055] The back-channel current of the BSIMIMG back-channel device model is introduced into the BSIMIMG front-channel device model as a controlled source to obtain the synthetic model.

[0056] In step S4, a back gate voltage is applied to the back gate of the BSIMIMG positive channel device model, a positive gate voltage is applied to the positive gate of the BSIMIMG positive channel device model, and a drain voltage is applied to the drain of the BSIMIMG back channel device model. A controlled source is connected in parallel with the BSIMIMG positive channel device model. The back channel current of the BSIMIMG back channel device model is introduced into the controlled source, so that the total current of the synthesized model is the sum of the current of the BSIMIMG back channel device model and the current of the BSIMIMG positive channel device model.

[0057] The following is for reference. Figure 2 The equivalent circuit diagram of the synthetic model is shown below. Figure 2 In this model, M1 represents the BSIMIMG positive channel device model, and M2 represents the BSIMIMG back channel device model. (Reference) Figure 2As shown, paralleling a controlled source on the BSIMSOI positive channel device model means connecting a controlled source in parallel between the source and drain of M1. This applies the positive gate voltage to the back gate of the BSIMSOI back channel device model, the back gate voltage to the positive gate of the BSIMSOI back channel device model, and the drain voltage to the drain of the BSIMSOI back channel device model. Below, we will combine... Figure 2 Detailed explanation of step S4:

[0058] In order to introduce back channel current into M1, a first resistor R1 is set at the drain of the back channel device model M2. Specifically, the resistance value of the first resistor R1 is less than a preset threshold, for example, the resistance value of the first resistor R1 is 1 ohm, so that the voltage and current on R1 are equal.

[0059] The current F1 in the parallel current-controlled current source M1 is connected to the current-controlled current source R1, such that F1 = i R1 Alternatively, the voltage across the first resistor R1 can be connected to the controlled source in parallel with M1 (G1 = V). R1 Instead of direct parallel connection between device models, the controlled source is a voltage-controlled current source G1 or a current-controlled current source F1. By setting a first resistor R1 at the drain D of the back-channel device model M2 and connecting the voltage-controlled current source G1 (or current-controlled current source F1) in parallel with the positive-channel device model M1, the back-channel current of M2 is introduced into M1. This ensures that the total current of the synthesized model includes both the positive-channel current and the back-channel current, thus addressing the change in the coupling characteristics of the back gate bias to the positive channel when the back-channel is turned on, thereby significantly improving the model accuracy under the back-channel-on condition.

[0060] S5: Adjust the model parameters of the synthesis model to obtain the target FDSOI MOSFET model.

[0061] Specifically, the adjusted model parameters include the positive gate threshold voltage and the back gate threshold voltage. Since the back gate threshold voltage and the back gate threshold voltage will change due to the superposition effect after the two models are merged as controlled sources, it is necessary to adjust the positive gate threshold voltage and the back gate threshold voltage to correct these changes and obtain more accurate positive gate threshold voltage and back gate threshold voltage for the synthesized model.

[0062] refer to Figure 3 The comparison of simulation and test data of the FDSOI MOSFET device model shown indicates that, under different VBS (substrate bias voltage), the Id-Vg characteristic data obtained by simulating the FDSOI MOSFET device model obtained in this embodiment of the invention (shown as simulation result A) are close to the Id-Vg curve obtained based on the test data, even when the VBS is large enough to enable the back channel (see Figure 1). Figure 3The Id-Vg characteristic data shown (for Vbs=10V and Vbs=9V) are very close to the Id-Vg curves obtained based on test data. Therefore, the FDSOI MOSFET device model established in this embodiment of the invention has higher accuracy.

[0063] This allows for the merging of the BSIMIMG back-channel device model and the BSIMIMG front-channel device model into a single model in the form of sub-circuits. The resulting composite model simultaneously includes both the front-channel current and the back-channel current. Since this embodiment of the invention does not simply merge the devices, it avoids affecting the device capacitance.

[0064] Secondly, based on the same inventive concept, embodiments of the present invention provide an FDSOI MOSFET model generation apparatus based on BSIMIMG, comprising:

[0065] The model code modification unit is used to modify the Verilog-a code of the BSIMIMG standard model to obtain a new BSIMIMG standard model.

[0066] The model parameter extraction unit is used to extract the model parameters of the positive channel device and the back channel device from the FDSOI MOSFET device;

[0067] The model generation unit is used to generate a BSIMIMG positive channel device model based on the positive channel device model parameters and the new BSIMIMG standard model, and to generate a BSIMIMG back channel device model based on the back channel device model parameters and the new BSIMIMG standard model.

[0068] The model synthesis unit is used to merge the BSIMIMG back-channel device model into the BSIMIMG front-channel device model in a controlled source form to obtain a synthesized model.

[0069] The model parameter adjustment unit is used to adjust the model parameters of the synthesized model to obtain the target FDSOI MOSFET model.

[0070] In one specific implementation, the model parameter extraction unit is specifically used for:

[0071] With the back channel of the FDSOI MOSFET device in an off state, extract the positive channel device model parameters of the FDSOI MOSFET device;

[0072] With the positive channel of the FDSOI MOSFET device in an off state, the back channel device model parameters of the FDSOI MOSFET device are extracted.

[0073] In one specific implementation, the model parameter extraction unit is specifically used to extract the back gate oxide thickness of the FDSOI MOSFET device as the positive gate oxide thickness of the BSIMIMG back channel device model, extract the positive gate oxide thickness of the FDSOI MOSFET device as the back gate oxide thickness of the BSIMIMG back channel device model, and extract the back channel current of the FDSOI MOSFET device as the positive channel current of the BSIMIMG back channel device model.

[0074] In one specific implementation, the model synthesis unit is specifically used for:

[0075] A positive gate voltage is applied to the back gate of the BSIMIMG back channel device model, a back gate voltage is applied to the positive gate of the BSIMIMG back channel device model, and a drain voltage is applied to the drain of the BSIMIMG back channel device model.

[0076] A controlled source is connected in parallel on the BSIMIMG positive channel device model, wherein the controlled source is a voltage-controlled current source or a current-controlled current source;

[0077] The back-channel current of the BSIMIMG back-channel device model is introduced into the controlled source, and the total current of the synthesized model is the sum of the current of the BSIMIMG back-channel device model and the current of the BSIMIMG positive-channel device model.

[0078] In one specific implementation, the model synthesis unit is specifically used for:

[0079] A first resistor is provided at the drain of the BSIMIMG back-channel device model;

[0080] The current or voltage across the first resistor is introduced into the controlled source.

[0081] In one specific implementation, the model code modification unit is specifically used for:

[0082] The effective back gate voltage in the Verilog-a code is modified as follows: when the back gate voltage is greater than the back trench threshold voltage, the effective back gate voltage is equal to the back trench threshold voltage; when the back gate voltage is less than the back trench accumulated voltage, the effective back gate voltage is equal to the back trench accumulated voltage.

[0083] In one specific implementation, the model parameter adjustment unit is specifically used to adjust the positive gate threshold voltage and the back gate threshold voltage of the synthesized model.

[0084] It should be noted that the implementation details of the FDSOI MOSFET model generation device based on BSIMIMG in the embodiments of the present invention can be referred to the implementation details in the foregoing method embodiments, and will not be repeated here for the sake of brevity.

[0085] Thirdly, based on the same inventive concept, embodiments of the present invention provide an FDSOI MOSFET model based on BSIMIMG, including: a BSIMIMG back-channel device model and a BSIMIMG front-channel device model, wherein the BSIMIMG back-channel device model is merged into the BSIMIMG front-channel device model in the form of controlled sources; wherein, the BSIMIMG front-channel device model is generated based on a new BSIMIMG standard model and front-channel device model parameters extracted from FDSOI MOSFET devices, and the BSIMIMG back-channel device model is generated based on the new BSIMIMG standard model and back-channel device model parameters extracted from FDSOI MOSFET devices, wherein the new BSIMIMG standard model is obtained by modifying the Verilog-a code of the BSIMIMG standard model.

[0086] It should be noted that the implementation details of the FDSOI MOSFET model generation device based on BSIMIMG in the embodiments of the present invention can be referred to the implementation details in the foregoing method embodiments, and will not be repeated here for the sake of brevity.

[0087] The FDSOI MOSFET model based on BSIMIMG in the above embodiments of the present invention is a composite model obtained by merging the BSIMIMG back-channel device model into the BSIMIMG front-channel device model in the form of a controlled source, based on the industry-standard SOI device model BSIMIMG. This achieves the introduction of back-channel current into the BSIMIMG front-channel device model in the form of a controlled source, thereby being able to cope with the change in the coupling characteristics of the back gate bias to the front channel when the back channel is turned on, and thus significantly improving the accuracy of the device model under the condition of back-channel being turned on.

[0088] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0089] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for generating a FDSOIMOSFET model based on BSIMIMG, characterized in that: include: Modify the Verilog-a code of the BSIMIMG standard model to obtain a new BSIMIMG standard model, including: modifying the effective back gate voltage in the Verilog-a code to: when the back gate voltage is greater than the back channel threshold voltage, the back gate effective voltage is equal to the back channel threshold voltage; when the back gate voltage is less than the back channel accumulation voltage, the back gate effective voltage is equal to the back channel accumulation voltage; Extracting positive channel device model parameters and back channel device model parameters from the FDSOI MOSFET device includes: extracting the positive channel device model parameters of the FDSOI MOSFET device when the back channel of the FDSOI MOSFET device is in a non-open state; extracting the back channel device model parameters of the FDSOI MOSFET device when the positive channel of the FDSOI MOSFET device is in a non-open state; wherein, extracting the back channel device model parameters of the FDSOI MOSFET device includes: extracting the back gate oxide thickness of the FDSOI MOSFET device as the positive gate oxide thickness of the BSIMIMG back channel device model, extracting the positive gate oxide thickness of the FDSOI MOSFET device as the back gate oxide thickness of the BSIMIMG back channel device model, and extracting the back channel current of the FDSOI MOSFET device as the positive channel current of the BSIMIMG back channel device model; Generate a BSIMIMG positive channel device model based on the positive channel device model parameters and the new BSIMIMG standard model, and generate a BSIMIMG back channel device model based on the back channel device model parameters and the new BSIMIMG standard model; The BSIMIMG back channel device model is merged into the BSIMIMG positive channel device model in the form of a controlled source to obtain a synthetic model, including: adding a positive gate voltage to the back gate of the BSIMIMG back channel device model, adding a back gate voltage to the positive gate of the BSIMIMG back channel device model, and adding a drain voltage to the drain of the BSIMIMG back channel device model; connecting a controlled source in parallel to the BSIMIMG positive channel device model, wherein the controlled source is a voltage-controlled current source or a current-controlled current source; introducing the back channel current of the BSIMIMG back channel device model into the controlled source, and obtaining a total current of the synthetic model as the sum of the current of the BSIMIMG back channel device model and the current of the BSIMIMG positive channel device model; The model parameters of the synthesis model are adjusted to obtain a target FDSOIMOSFET model.

2. The method according to claim 1, characterized in that The step of introducing the back channel current of the BSIMIMG back channel device model into the controlled source comprises: Setting a first resistor at the drain of the BSIMIMG back-channel device model; A current across the first resistor or a voltage across the first resistor is introduced into the controlled source.

3. The method according to claim 1, characterized in that The step of adjusting the model parameters of the synthesis model to obtain a target FDSOIMOSFET model includes: The positive gate threshold voltage and the back gate threshold voltage of the synthetic model are adjusted.

4. A FDSOIMOSFET model generation device based on BSIMIMG, characterized in that: include: A code modification unit, used for modifying the Verilog-a code of the BSIMIMG standard model to obtain a new BSIMIMG standard model, including: an effective back gate voltage in the Verilog-a code, modifying the effective back gate voltage to: when the back gate voltage is greater than the back channel threshold voltage, the back gate effective voltage is equal to the back channel threshold voltage; when the back gate voltage is less than the back channel accumulation voltage, the back gate effective voltage is equal to the back channel accumulation voltage; A model parameter extraction unit, used to extract positive channel device model parameters and back channel device model parameters from the FDSOIMOSFET device, including: extracting the positive channel device model parameters of the FDSOIMOSFET device when the back channel of the FDSOIMOSFET device is in a non-open state; extracting the back channel device model parameters of the FDSOI MOSFET device when the positive channel of the FDSOI MOSFET device is in a non-open state; wherein the extracting the back channel device model parameters of the FDSOIMOSFET device includes: extracting the back gate oxide thickness of the FDSOIMOSFET device as the positive gate oxide thickness of the BSIMIMG back channel device model, extracting the positive gate oxide thickness of the FDSOI MOSFET device as the back gate oxide thickness of the BSIMIMG back channel device model, and extracting the back channel current of the FDSOIMOSFET device as the positive channel current of the BSIMIMG back channel device model; A model generating unit, configured to generate a BSIMIMG positive channel device model based on the positive channel device model parameters and the new BSIMIMG standard model, and to generate a BSIMIMG back channel device model based on the back channel device model parameters and the new BSIMIMG standard model; A model synthesis unit, used for merging the BSIMIMG back channel device model into the BSIMIMG positive channel device model in the form of a controlled source to obtain a synthesized model, including: adding a positive gate voltage to the back gate of the BSIMIMG back channel device model, adding a back gate voltage to the positive gate of the BSIMIMG back channel device model, and adding a drain voltage to the drain of the BSIMIMG back channel device model; connecting a controlled source in parallel to the BSIMIMG positive channel device model, wherein the controlled source is a voltage-controlled current source or a current-controlled current source; introducing a back channel current of the BSIMIMG back channel device model into the controlled source, so that the total current of the synthesized model is the sum of the current of the BSIMIMG back channel device model and the current of the BSIMIMG positive channel device model; The model parameter adjustment unit is used to adjust the model parameters of the synthesis model to obtain a target FDSOIMOSFET model.

5. A FDSOIMOSFET model based on BSIMIMG, characterized in that: include: A BSIMIMG back channel device model and a BSIMIMG positive channel device model, wherein the BSIMIMG back channel device model is merged into the BSIMIMG positive channel device model in the form of a controlled source, including: adding a positive gate voltage to the back gate of the BSIMIMG back channel device model, adding a back gate voltage to the positive gate of the BSIMIMG back channel device model, and adding a drain voltage to the drain of the BSIMIMG back channel device model; connecting a controlled source in parallel to the BSIMIMG positive channel device model, wherein the controlled source is a voltage-controlled current source or a current-controlled current source; introducing the back channel current of the BSIMIMG back channel device model into the controlled source, and obtaining a total current of the synthetic model as the sum of the current of the BSIMIMG back channel device model and the current of the BSIMIMG positive channel device model; Wherein, the BSIMIMG positive channel device model is generated based on the new BSIMIMG standard model and the positive channel device model parameters extracted from the FDSOIMOSFET device, the BSIMIMG back channel device model is generated based on the new BSIMIMG standard model and the back channel device model parameters extracted from the FDSOIMOSFET device, and the new BSIMIMG standard model is obtained by modifying the Verilog-a code of the BSIMIMG standard model; the effective back gate voltage in the Verilog-a code modifies the effective back gate voltage as follows: when the back gate voltage is greater than the back channel threshold voltage, the back gate effective voltage is equal to the back channel threshold voltage; when the back gate voltage is less than the back channel accumulation voltage, the back gate effective voltage is equal to the back channel accumulation voltage; The positive channel device model parameters are extracted when the back channel of the FDSOIMOSFET device is in a non-open state. The back channel device model parameters are the back gate oxide thickness of the FDSOIMOSFET device extracted when the positive channel of the FDSOIMOSFET device is in a non-open state as the positive gate oxide thickness of the BSIMIMG back channel device model, the extracted positive gate oxide thickness of the FDSOIMOSFET device is used as the back gate oxide thickness of the BSIMIMG back channel device model, and the extracted back channel current of the FDSOIMOSFET device is used as the positive channel current of the BSIMIMG back channel device model.

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