Vertical Memory Devices

Abstract

A vertical memory device includes a gate electrode on a substrate. The gate electrodes are spaced apart from each other in a vertical direction. A channel penetrates the gate electrode and extends in the vertical direction. A tunnel insulation pattern is formed on an outer sidewall of the channel. A charge trapping pattern structure is formed on an outer sidewall of the tunnel insulation pattern adjacent to the gate electrode in a horizontal direction. The charge trapping pattern structure includes an upper charge trapping pattern and a lower charge trapping pattern. A blocking pattern is formed between each of the adjacent gate electrodes and the charge trapping pattern structure. An upper surface of the upper charge trapping pattern is higher than an upper surface of an adjacent gate electrode. A lower surface of the lower charge trapping pattern is lower than a lower surface of an adjacent gate electrode.

Description

Technical Field

[0001] The present inventive concept relates to a vertical memory device and more particularly to a vertical memory device having a vertical channel. Background Art

[0002] To increase the integration density of vertical memory devices, the size of each layer stacked vertically in the device can be reduced. However, there may be process limitations in scaling down vertical memory devices beyond a certain level. Summary of the invention

[0003] Exemplary embodiments of the inventive concept provide a vertical memory device having improved electrical characteristics.

[0004] According to an exemplary embodiment of the present invention, a vertical memory device includes a gate electrode on a substrate. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. A channel penetrates the gate electrode and extends in a vertical direction. A tunnel insulating pattern is formed on an outer sidewall of the channel. A charge trapping pattern structure is formed on an outer sidewall of the tunnel insulating pattern adjacent to the gate electrode in a horizontal direction substantially parallel to an upper surface of the substrate. The charge trapping pattern structure includes an upper charge trapping pattern and a lower charge trapping pattern. A blocking pattern is formed between each of the gate electrodes adjacent to the charge trapping pattern structure and the charge trapping pattern structure. An upper surface of the upper charge trapping pattern is higher than an upper surface of a gate electrode adjacent to the charge trapping pattern structure. A lower surface of the lower charge trapping pattern is lower than a lower surface of a gate electrode adjacent to the charge trapping pattern structure.

[0005] According to an exemplary embodiment of the present invention, a vertical memory device includes a gate electrode on a substrate. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. A channel penetrates the gate electrode and extends in a vertical direction. A tunnel insulating pattern is formed on an outer sidewall of the channel. A charge trapping pattern structure is formed on an outer sidewall of the tunnel insulating pattern adjacent to the gate electrode in a horizontal direction substantially parallel to an upper surface of the substrate. The charge trapping pattern structure includes an upper charge trapping pattern and a lower charge trapping pattern. A blocking pattern is formed between each of the gate electrodes adjacent to the charge trapping pattern structure and the charge trapping pattern structure. The blocking pattern covers the upper and lower surfaces of each gate electrode.

[0006] According to an exemplary embodiment of the present invention, a vertical memory device includes a gate electrode on a substrate. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. A channel penetrates the gate electrode and extends in a vertical direction. A tunnel insulation pattern is formed on an outer sidewall of the channel. The tunnel insulation pattern includes a protrusion protruding in a horizontal direction substantially parallel to an upper surface of the substrate. A charge trapping pattern structure is formed on an outer sidewall of the tunnel insulation pattern adjacent to the gate electrode in a horizontal direction. The charge trapping pattern structure includes an upper charge trapping pattern and a lower charge trapping pattern spaced apart from each other in a vertical direction by the protrusion of the tunnel insulation pattern. The blocking pattern has a sidewall having a convex shape toward each gate electrode. The convex shape corresponds to the protrusion of the tunnel insulation pattern.

[0007] A vertical memory device according to an exemplary embodiment of the inventive concept may include a tunnel insulating pattern, a charge trapping pattern structure, and a blocking pattern sequentially formed on an outer sidewall of a channel, the channel extending through gate electrodes and the insulating patterns alternately and repeatedly formed in a vertical direction substantially perpendicular to an upper surface of a substrate, and the charge trapping pattern structure may include an upper charge trapping pattern and a lower charge trapping pattern spaced apart from each other in the vertical direction.

[0008] Therefore, a plurality of charge trap patterns may be arranged in one transistor so that the integration of a vertical memory device including the transistor may be improved, and electrons may be efficiently injected through the plurality of charge trap patterns so that electrical characteristics of the vertical memory device may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a top plan view illustrating a vertical memory device according to an exemplary embodiment of the inventive concept.

[0010] Figure 2 FIG. 2 is a diagram showing a vertical memory device according to an exemplary embodiment of the inventive concept. Figure 1 A cross-sectional view taken along line AA'.

[0011] Figure 3 According to an exemplary embodiment of the present invention, Figure 2 An enlarged cross-sectional view of area X in FIG.

[0012] Figure 4-7 , Fig. 9 , Fig.11 , Fig.13 , Fig.14 , Fig.16 , Fig.18 and Fig. 20 is a diagram showing stages of a method of manufacturing a vertical memory device according to an exemplary embodiment of the inventive concept. Figure 1The cross-sectional view corresponds to the cross-sectional view taken along the line AA'.

[0013] Figure 8 , Fig.10 , Fig.12 , Fig.15 , Fig.17 , Fig.19 and Fig.21 2 is an enlarged cross-sectional view illustrating stages of a method of manufacturing a vertical memory device according to an exemplary embodiment of the inventive concept.

[0014] Figure 22-24 is a diagram showing stages of a method of manufacturing a vertical memory device according to an exemplary embodiment of the inventive concept. Figure 1 The cross-sectional view corresponds to the cross-sectional view taken along the line AA'.

[0015] Figure 25-29 2 is an enlarged cross-sectional view illustrating stages of a method of manufacturing a vertical memory device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0016] A vertical memory device and a method of manufacturing the vertical memory device according to exemplary embodiments of the inventive concept will hereinafter be described more fully with reference to the accompanying drawings.

[0017] Figure 1 is a top plan view illustrating a vertical memory device according to an exemplary embodiment of the inventive concept. Figure 2 FIG. 2 is a diagram showing a vertical memory device according to an exemplary embodiment of the inventive concept. Figure 1 A cross-sectional view taken along line AA'. Figure 3 According to an exemplary embodiment of the present invention, Figure 2 An enlarged cross-sectional view of area X in FIG.

[0018] Hereinafter, a vertical direction substantially perpendicular to the upper surface of the substrate is defined as a first direction, and two directions intersecting each other among horizontal directions substantially parallel to the upper surface of the substrate are defined as a second direction and a third direction, respectively. Figure 1 As shown in the exemplary embodiment of FIG. 1 , the second direction and the third direction may be orthogonal to each other.

[0019] Reference Figures 1 to 3, the vertical memory device may include an insulating pattern 115, a gate electrode, a channel 225, a tunnel insulating pattern 205, a charge trapping pattern structure 185, and a first barrier pattern 177 on a substrate 100. The vertical memory device may also include a semiconductor pattern 150, a buried pattern 230, a pad 240, a second barrier pattern 285, a second spacer 300, a common source line (CSL) 310, first to fourth insulating interlayers 130, 250, 320, and 340, a contact plug 330, and a bit line 350.

[0020] In an exemplary embodiment, the substrate 100 may include silicon, germanium, silicon germanium, or a III-V compound such as GaP, GaAs, GaSb, etc. In some exemplary embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. However, exemplary embodiments of the inventive concept are not limited thereto.

[0021] The insulating pattern 115 may be formed at multiple levels along the first direction and may be spaced apart from each other. For example, the insulating pattern 115 may have different distances in the first direction between the upper surface of the substrate 100 and the lower surface of the insulating pattern 115, and such distances may be referred to as heights. The insulating pattern 115 may have different thicknesses along the first direction depending on the heights formed. For example, the lowest insulating pattern 115 formed at the lowest height along the first direction from the upper surface of the substrate 100 may have the smallest thickness. The insulating pattern 115 formed at the second height from the upper surface of the substrate 100 may have the largest thickness. The uppermost insulating pattern 115 (e.g., Figure 2 The eighth insulating pattern from the upper surface of the substrate having the largest distance in the first direction between the lower surface of the insulating pattern and the upper surface of the substrate may have the second largest thickness. The insulating patterns 115 formed at the remaining intermediate heights excluding the second height from the upper surface of the substrate between the uppermost insulating pattern 115 formed at the uppermost height and the lowermost insulating pattern 115 formed at the lowermost height (for example, Figure 2 Each of the third to seventh insulating patterns from the upper surface of the substrate shown in the exemplary embodiment of the present invention may have a third maximum thickness. The insulating patterns at intermediate heights other than the second height from the upper surface of the substrate may have substantially similar thicknesses (e.g., lengths in the first direction). However, the exemplary embodiments of the present inventive concept are not limited thereto, and in other exemplary embodiments, the thicknesses of the insulating patterns may have different arrangements. In addition, Figure 2 The number of insulating patterns in the exemplary embodiment is not limiting and may vary in other exemplary embodiments.

[0022] Each gate electrode may be formed between the insulating patterns 115 (eg, in the first direction). The gate electrodes may be formed at multiple heights and spaced apart from each other (eg, in the first direction). Figure 2 As shown in the exemplary embodiment of FIG. 1 , the insulating pattern 115 and the gate electrode may be alternately and repeatedly stacked in the first direction on the substrate 100. Each gate electrode may extend in the second direction, and a plurality of gate electrodes may be arranged in the third direction and may be spaced apart from each other. Each gate electrode extending in the second direction may be spaced apart from each other in the third direction by the second spacer 300 and the CSL 310 formed in the second opening 260.

[0023] The gate electrode may include first to third gate electrodes 293, 295, and 297 sequentially formed along the first direction. In an exemplary embodiment, the first gate electrode 293 may be used as a ground selection line (GSL), the second gate electrode 295 may be used as a word line, and the third gate electrode 297 may be used as a string selection line (SSL). The first gate electrode 293, the second gate electrode 295, and the third gate electrode 297 may each be formed at one height or multiple heights. In addition, one or more dummy word lines may be formed between the first gate electrode 293 and the second gate electrode 295 and / or between the second gate electrode 295 and the third gate electrode 297.

[0024] exist Figure 2 In the exemplary embodiment shown, the first gate electrode 293 may be formed at the lowest height (e.g., the minimum distance between the lower surface of the gate electrode and the upper surface of the substrate 100 in the first direction), the third gate electrode 297 may be formed at the highest height and a height directly therebelow, and the second gate electrode 295 may be formed at multiple heights between the first gate electrode 293 and the third gate electrode 297 (e.g., at Figure 2 Thus, the first gate electrode 293 may be formed adjacent to the semiconductor pattern 150 (eg, in the third direction), and each of the second gate electrode 295 and the third gate electrode 297 may be formed adjacent to the channel 225 (eg, in the third direction).

[0025] In an exemplary embodiment, the first gate electrode 293 may include a first gate conductive pattern and a first gate barrier pattern, the first gate barrier pattern covering the upper and lower surfaces of the first gate conductive pattern (e.g., opposite to each other in the first direction) and a portion of the sidewall of the first gate conductive pattern. The second gate electrode 295 may include a second gate conductive pattern and a second gate barrier pattern, the second gate barrier pattern covering the upper and lower surfaces of the second gate conductive pattern (e.g., opposite to each other in the first direction) and a portion of the sidewall of the second gate conductive pattern. The third gate electrode 297 may include a third gate conductive pattern and a third gate barrier pattern, the third gate barrier pattern covering the upper and lower surfaces of the third gate conductive pattern (e.g., opposite to each other in the first direction) and a portion of the sidewall of the third gate conductive pattern.

[0026] The upper surface, the lower surface, and the sidewalls of the adjacent semiconductor pattern 150 or the channel 225 of each gate electrode may be covered by the second barrier pattern 285. The second barrier pattern 285 may also cover a portion of the sidewalls of each of the gate insulating patterns 115, the sidewalls of each of the first insulating interlayer 130 and the second insulating interlayer 250, and a portion of the upper surface of the substrate 100.

[0027] In an exemplary embodiment, a sidewall of each of the second gate electrode 295 and the third gate electrode 297 closest to the channel (eg, and opposite to the channel) in the third direction may have a concave or convex shape toward the channel 225 as a whole.

[0028] The channel 225 may extend in the first direction on the semiconductor pattern 150 formed on the upper surface of the substrate 100 , and may extend through the alternately and repeatedly stacked insulating patterns 115 and the second and third gate electrodes 295 and 297 .

[0029] In an exemplary embodiment, the semiconductor pattern 150 may have a pillar shape, for example, a cylindrical shape.

[0030] In an exemplary embodiment, the semiconductor pattern 150 may be formed such that its upper surface is positioned between upper and lower surfaces of the insulating pattern 115 having the largest thickness among the insulating patterns 115 formed at a second height from the upper surface of the substrate 100 in the first direction.

[0031] The channel 225 may extend through the second and third gate electrodes 295 and 297 and the insulating pattern 115 formed on the first gate electrode 293. In an exemplary embodiment, the channel 225 may have a cup shape, and an inner space of the cup shape may be filled with the buried pattern 230 having a pillar shape. Alternatively, the channel 225 may have a pillar shape, and the buried pattern 230 may not be formed.

[0032] A plurality of channels 225 may be formed in the second direction and the third direction, and thus a channel array may be defined.

[0033] The tunnel insulating pattern 205 may have a cup shape having a central portion that surrounds the outer sidewall of the channel 225 and extends in the first direction and is penetrated. In an exemplary embodiment, the inner sidewall (e.g., adjacent to the channel 225) and the outer sidewall (e.g., closest to the gate electrode and the insulating pattern 115) of the portion of the tunnel insulating pattern 205 formed between each insulating pattern 115 and the channel 225 may have a vertical slope (e.g., at a right angle) relative to the upper surface of the substrate 100. However, in an exemplary embodiment, the inner sidewall and the outer sidewall of the portion of the tunnel insulating pattern 205 formed between each of the first to third gate electrodes 293, 295, and 297 and the channel 225 may at least partially have a slope that is not vertical (e.g., at a right angle) but varies (e.g., is inclined to different degrees) relative to the upper surface of the substrate 100.

[0034] A charge trapping pattern structure 185 including an upper charge trapping pattern 185a and a lower charge trapping pattern 185b may be formed between a second barrier pattern 285 covering a sidewall of each gate electrode and an outer sidewall of the tunnel insulating pattern 205. A first barrier pattern 177 having a thin thickness may be formed between the charge trapping pattern structure 185 and an insulating pattern 115 formed on and below the charge trapping pattern structure 185 (e.g., in a first direction). In an exemplary embodiment, an outer sidewall of the tunnel insulating pattern 205 may further protrude from an outer sidewall of each of the upper charge trapping pattern 185a and the lower charge trapping pattern 185b toward the gate electrode in a third direction. For example, as shown in FIG. Figure 2 As shown in the exemplary embodiment of FIG. 2 , a middle portion (eg, in the first direction) of each of the portions of the tunnel insulation pattern 205 between the gate electrode and the channel 225 may protrude from the outer sidewall.

[0035] In an exemplary embodiment, the lowermost first barrier pattern 177 in the first direction may partially cover the surface of the insulating pattern 115 having the largest thickness at the second height from the upper surface of the substrate 100 and the upper surface of the semiconductor pattern 150. The uppermost first barrier pattern 177 in the first direction may partially cover the surface of the insulating pattern 115 having the second largest thickness at the uppermost height and the lower surface of the pad 240. The remaining first barrier pattern 177 may partially cover the surface of the insulating pattern 115 at the remaining height. For example, the first barrier pattern 177 may cover the outer sidewalls of the insulating pattern 115 at the remaining height extending in the first direction, and portions of the upper and lower surfaces of the insulating pattern 115 at the remaining height adjacent to the outer sidewalls.

[0036] Each of the upper charge trapping pattern 185a and the lower charge trapping pattern 185b may have a sidewall that is not vertical (e.g., at a right angle) but varies (e.g., is inclined to different degrees) with respect to the upper surface of the substrate 100. Each of the upper charge trapping pattern 185a and the lower charge trapping pattern 185b may have a symmetrical shape along the first direction based on an outer sidewall of each of the upper charge trapping pattern 185a and the lower charge trapping pattern 185b that further protrudes toward the gate electrode in the third direction from an outer sidewall of each of the upper charge trapping pattern 185a and the lower charge trapping pattern 185b. In an exemplary embodiment, an upper surface of the upper charge trapping pattern 185a contacting the first barrier pattern 177 and a lower surface of the lower charge trapping pattern 185b contacting the first barrier pattern 177 may have substantially the same width in the third direction.

[0037] In an exemplary embodiment, the thickness of the upper charge trapping pattern 185a in the third direction may gradually decrease from top toward bottom, and the thickness of the lower charge trapping pattern 185b in the third direction may gradually increase from top toward bottom.

[0038] In an exemplary embodiment, the charge trapping pattern structure 185 may be disposed between the channel 225 and each of the second and third gate electrodes 295 and 297 (eg, in the third direction). The upper charge trapping pattern 185a may be disposed between the channel 225 and each of the second and third gate electrodes 295 and 297 (eg, in the third direction). Fig.14 ) An outer sidewall exposed by the gap 270 may have a slope gradually decreasing toward the top, and an outer sidewall of the lower charge trapping pattern 185b exposed by the gap 270 during formation thereof may have a slope gradually decreasing toward the bottom.

[0039] In an exemplary embodiment, the upper charge trapping pattern 185a and the lower charge trapping pattern 185b may be formed on a space between each of the second and third gate electrodes 295 and 297 and the channel 225 (eg, in the third direction). Figure 2-3 As shown in the exemplary embodiment of the present invention, the upper surface of the upper charge trapping pattern 185a can be higher (e.g., in the first direction) than the upper surfaces of the second and third gate electrodes 295 and 297 adjacent thereto, and the lower surface of the lower charge trapping pattern 185b can be lower than the lower surfaces of the second and third gate electrodes 295 and 297 adjacent thereto.

[0040] In an exemplary embodiment, the first barrier pattern 177 may include an oxide such as silicon oxide, and each of the upper and lower charge trapping patterns 185a and 185b may include a nitride such as silicon nitride. However, exemplary embodiments of the inventive concept are not limited thereto.

[0041] The first insulating interlayer 130 may be formed on the first structure including the charge trapping pattern structure 185, the tunnel insulating pattern 205, and the channel 225, and the uppermost insulating pattern 115 formed at the uppermost height, and the pad 240 may extend through the first insulating interlayer 130 to contact the upper surface of the first structure. The second insulating interlayer 250 may be formed on the first insulating interlayer 130 and the pad 240.

[0042] The second spacer 300 may be formed on the sidewall of the second opening 260 extending through the insulating pattern 115 and the first to third gate electrodes 293, 295 and 297 to expose the upper surface of the substrate 100. The second spacer 300 may extend in the second direction. The CSL 310 may fill the remaining portion of the second opening 260.

[0043] The third insulating interlayer 320 may be formed on the second insulating interlayer 250, the CSL 310, the second spacer 300, and the second barrier pattern 285. The contact plug 330 may extend through the second insulating interlayer 250 and the third insulating interlayer 320 to contact the upper surface of the pad 240. The bit line 350 may extend through the fourth insulating interlayer 340 to contact the upper surface of the contact plug 330. In an exemplary embodiment, the bit line 350 may extend in the third direction, and a plurality of bit lines 350 may be formed along the second direction.

[0044] As described above, the charge trapping pattern structure 185 formed between each of the second to third gate electrodes 295 and 297 and the channel 225 among the gate electrodes may include an upper charge trapping pattern 185a and a lower charge trapping pattern 185b spaced apart from each other along the first direction. Therefore, a plurality of charge trapping patterns may be arranged in one transistor. Therefore, the integration of a vertical memory device including a transistor may be improved. Moreover, electrons may be efficiently injected into the second to third gate electrodes 295 and 297 through each of the upper charge trapping pattern 185a and the lower charge trapping pattern 185b. Therefore, the electrical characteristics of the vertical memory device may be improved.

[0045] Since the second to third gate electrodes 295 and 297 and the insulating pattern 115 may be formed to have a concavo-convex shape in the first direction as a whole, the charge trapping pattern structure 185 may be at least partially interposed between the second to third gate electrodes 295 and 297 along the first direction, thereby minimizing interference between adjacent second to third gate electrodes 295 and 297. Therefore, coupling between the second gate electrodes 295 used as word lines may be reduced.

[0046] Figures 4 to 21 are cross-sectional views illustrating stages of a method of manufacturing a vertical memory device according to an exemplary embodiment of the inventive concept. Figure 4-7 , Fig. 9 , Fig.11 , Fig.13 , Fig.14 , Fig.16 , Fig.18 and Fig. 20 is along Figure 1 The cross-sectional view corresponds to the cross-sectional view taken along the line AA'. Figure 8 , Fig.10 , Fig.12 , Fig.15 , Fig.17 , Fig.19 and Fig.21 They are enlarged cross-sectional views of the region X corresponding to the cross-sectional views.

[0047] Reference Figure 4 , the insulating layers 110 and the sacrificial layers 120 may be alternately and repeatedly stacked on the substrate 100 (eg, in the first direction). Thus, a plurality of insulating layers 110 and a plurality of sacrificial layers 120 may be alternately stacked in the first direction. Figure 4 In the exemplary embodiment shown, eight heights of the insulating layer 110 and seven heights of the sacrificial layer 120 are alternately formed on the substrate 100. However, exemplary embodiments of the inventive concept are not limited thereto, and the number of the insulating layer 110 and the sacrificial layer 120 may be greater or less than Figure 4 The number shown in the exemplary embodiment.

[0048] In an exemplary embodiment, the insulating layer 110 and the sacrificial layer 120 may be formed by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, etc. In an exemplary embodiment, the lowermost insulating layer 110 directly formed on the upper surface of the substrate 100 may also be formed by a thermal oxidation process of the upper surface of the substrate 100.

[0049] The insulating layer 110 may include silicon oxide, such as plasma enhanced tetraethyl orthosilicate (PE-TEOS), high density plasma (HDP) oxide, plasma enhanced oxide (PEOX), etc. The sacrificial layer 120 may include a material having an etching selectivity with respect to the insulating layer 110, such as silicon nitride. However, exemplary embodiments of the inventive concept are not limited thereto, and the insulating layer 110 and the sacrificial layer 120 may be formed of various other materials.

[0050] In an exemplary embodiment, the lowermost insulating layer 110 formed at a first height along the first direction from the upper surface of the substrate 100 may have a minimum thickness (e.g., in the first direction) compared to the insulating layers 110 at other heights. The insulating layer 110 formed at a second height along the first direction from the upper surface of the substrate 100 may have a maximum thickness (e.g., in the first direction) compared to the insulating layers 110 at other heights.

[0051] Reference Figure 5 After forming the first insulating interlayer 130 on the uppermost insulating layer 110, an etching process using an etching mask may be performed to etch the first insulating interlayer 130, the insulating layer 110, and the sacrificial layer 120 below the etching mask. A channel hole 140 extending through the first insulating interlayer 130, the insulating layer 110, and the sacrificial layer 120 may be formed to expose the upper surface of the substrate 100.

[0052] In an exemplary embodiment, the channel hole 140 may also partially extend through an upper portion of the substrate 100 .

[0053] The semiconductor pattern 150 may be formed to partially fill the channel hole 140 .

[0054] For example, in an exemplary embodiment, a selective epitaxial growth (SEG) process using the upper surface of the substrate 100 exposed by the channel hole 140 as a seed may be performed. The SEG process forms the semiconductor pattern 150 that may fill the lower portion of the channel hole 140. Therefore, the semiconductor pattern 150 may include single crystal silicon or single crystal germanium according to the material of the substrate 100, and may be doped with impurities.

[0055] In another exemplary embodiment, the semiconductor pattern 150 may be formed by forming an amorphous silicon layer filling the channel hole 140 and performing a laser epitaxial growth (LEG) process or a solid phase epitaxy (SPE) process on the amorphous silicon layer.

[0056] In an exemplary embodiment, the upper surface of the semiconductor pattern 150 may be disposed between the upper surface and the lower surface of the insulating layer 110 at a second height from the upper surface of the substrate 100 among the insulating layer 110 (e.g., the insulating layer second closest to the upper surface of the substrate 100 in the first direction).

[0057] The semiconductor pattern 150 may be used as a channel 225 (see Fig.13 ) channel, and thus can be called the lower channel.

[0058] Reference Figure 6 , the sidewalls of the sacrificial layer 120 exposed by the channel holes 140 may be partially removed to form the first recess 160 .

[0059] In an exemplary embodiment, the first recess 160 may be formed by a dry etching process or a wet etching process.

[0060] In an exemplary embodiment, each first recess 160 may be formed by partially removing each sacrificial layer 120 while maintaining a portion of the sacrificial layer. The first recess 160 may have a depth in the third direction. Therefore, the insulating layer 110 and the sacrificial layer 120, which are alternately and repeatedly stacked, may have a concavo-convex shape along the first direction as a whole.

[0061] In an exemplary embodiment, the first recess 160 may not be formed on the lowermost sacrificial layer 120. The lowermost sacrificial layer 120 may include a sidewall covered by the semiconductor pattern 150 formed on the lower portion of the channel hole 140. Figure 6 As shown in the exemplary embodiment of FIG. 1 , the semiconductor pattern 150 may have a relatively flat sidewall extending in the first direction and have a constant width in the third direction at a portion adjacent to the sacrificial layer 120 .

[0062] Reference Figure 7 and Figure 8 The first blocking layer 170 and the charge trapping layer 180 may be sequentially formed on the sidewalls of the channel hole 140 , the inner sidewalls of each first recess 160 , the upper surface of the semiconductor pattern 150 , and the upper surface of the first insulating interlayer 130 .

[0063] The first barrier layer 170 may be formed along the exposed surfaces of the alternately and repeatedly stacked insulating layers 110 and sacrificial layers 120 and the exposed surface of the first insulating interlayer 130. For example, the first barrier layer 170 may be formed to cover the sidewalls of the insulating layers 110 and sacrificial layers 120 extending in the first direction and the portions of the upper and lower surfaces of the insulating layers 110 extending in the third direction adjacent to the sidewalls. The first barrier layer 170 may be conformally formed to cover the inner sidewalls of each first recess 160 and to have a very small thickness. Since the alternately and repeatedly stacked insulating layers 110 and sacrificial layers 120 may have a concave-convex shape along the first direction as a whole, the first barrier layer 170 may also have a concave-convex shape corresponding thereto along the first direction as a whole.

[0064] The charge trapping layer 180 may be formed on the first barrier layer 170 and may be adjacent to the surfaces of the alternately and repeatedly stacked insulating layers 110 and sacrificial layers 120 covered by the first barrier layer 170, and may fill each of the first recesses 160. The sidewalls of the portion of the charge trapping layer 180 formed on the sidewalls of the channel hole 140 may have a slope that is substantially perpendicular to the upper surface of the substrate 100 in the first direction. However, the sidewalls of the portion of the charge trapping layer 180 may also have portions each having a slope that is not perpendicular (e.g., at a right angle) but varies (e.g., is inclined to different degrees) relative to the upper surface of the substrate 100 and corresponds to the shape of each of the first recesses 160. For example, in Figure 7 In the illustrated exemplary embodiment, a portion of the charge trapping layer 180 corresponding to a central portion of each first recess 160 in the first direction may have a concave shape toward the channel hole 140 (eg, a convex shape toward the sacrificial layer 120 ).

[0065] In an exemplary embodiment, the first blocking layer 170 may have a constant thickness, and each of the portions of the charge trapping layer 180 formed adjacent to the sidewalls of each insulating layer 110, the upper surface and sidewalls of the first insulating interlayer 130, and the upper surface of the semiconductor pattern 150 may also have a constant thickness. However, the portion of the charge trapping layer 180 adjacent to each first recess 160 may not have a constant thickness, and may have a greater thickness than other portions thereof having a constant thickness.

[0066] The first blocking layer 170 may include an oxide such as silicon oxide, and the charge trapping layer 180 may include a nitride such as silicon nitride.

[0067] Reference Fig. 9 and Fig.10 In an exemplary embodiment, the charge trapping layer 180 may be etched by a wet etching process or a dry etching process until a portion of the first blocking layer 170 formed on the sidewall of each insulating layer 110 may be exposed and the charge trapping layer 180 may remain only in each first recess 160 .

[0068] By performing the removal process, a portion of the charge trapping layer 180 having a relatively small thickness, such as a portion of the charge trapping layer 180 formed on the sidewall of each insulating layer 110, the upper surface and the sidewall of the first insulating interlayer 130, and the upper surface of the semiconductor pattern 150, may be completely removed. A portion of the charge trapping layer 180 having a relatively large thickness, such as a portion of the charge trapping layer 180 adjacent to each first recess 160, may not be completely removed but may partially remain. Since a portion of the charge trapping layer 180 adjacent to each first recess 160 may have a concave shape toward the channel hole 140, a second recess 190 having a concave shape toward the channel hole 140 may be formed on the sidewall of the remaining charge trapping layer 180 after the removal process.

[0069] In an exemplary embodiment, the width of the remaining charge trapping layer 180 in the third direction may vary along the first direction and may gradually increase as it approaches the adjacent insulating layer 110 in the first direction. For example, a portion of the charge trapping layer 180 in the middle in the first direction may have the smallest width in the third direction.

[0070] exist Fig. 9 and Fig.10 In the illustrated exemplary embodiment, the remaining charge trapping layer 180 is not separated in the first direction by the second recess 190. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the remaining charge trapping layer 180 may be separated in the first direction by the second recess 190, and the surface of the first barrier layer 170 formed on the sidewall of each sacrificial layer 120 may be exposed by the second recess 190.

[0071] Reference Fig.11 and Fig.12 , the tunnel insulating layer 200 and the first spacer layer 210 may be sequentially formed on the exposed surface of the first barrier layer 170 and the exposed surface of the charge trapping layer 180 .

[0072] Each of the sidewalls of the tunnel insulating layer 200 and the sidewalls of the first spacer layer 210 may have a slope that is perpendicular (e.g., at a right angle) to the upper surface of the substrate 100 in a first direction. However, each of the sidewalls of the tunnel insulating layer 200 and the first spacer layer 210 adjacent to the second recess 190 may have a slope that is not perpendicular to the upper surface of the substrate 100 and may vary (e.g., be inclined to different degrees).

[0073] For example, in Fig.11In the illustrated exemplary embodiment, portions of the tunnel insulating layer 200 and the first spacer layer 210 adjacent to the second recess 190 may have a concave shape in the third direction toward the channel hole 140. For example, portions of the tunnel insulating layer 200 and the first spacer layer 210 adjacent to the second recess 190 may have a convex shape in the third direction toward the sacrificial layer 120. The concave portion of the first spacer layer 210 may have a shape that is relatively less concave than the concave portion of the tunnel insulating layer 200.

[0074] In an exemplary embodiment, the tunnel insulating layer 200 may include silicon oxide or the like, and the first spacer layer 210 may include silicon nitride or the like.

[0075] Reference Fig.13 , the first spacer layer 210 may be anisotropically etched to form a first spacer formed only on the sidewalls of the channel hole and exposing the tunnel insulating layer 200 under the first spacer layer 210. The tunnel insulating layer 200 and the first barrier layer 170 may be etched using the first spacer as an etching mask.

[0076] Therefore, portions of the tunnel insulation layer 200 and the first barrier layer 170 on the upper surface of the semiconductor pattern 150 may be partially removed, portions of the tunnel insulation layer 200 and the first barrier layer 170 on the upper surface of the first insulating interlayer 130 may be removed, and the upper portion of the semiconductor pattern 150 may also be partially removed.

[0077] The etching process may transform the tunnel insulating layer 200 into the tunnel insulating pattern 205, and the first barrier layer 170 may be transformed into the initial first barrier pattern 175. In an exemplary embodiment, each of the tunnel insulating pattern 205 and the initial first barrier pattern 175 may have a cup shape in which a central portion is penetrated. The charge trapping layer 180 may have a ring shape.

[0078] After removing the first spacer to expose the tunnel insulating pattern 205, a channel layer may be formed on the exposed tunnel insulating pattern 205, the semiconductor pattern 150, and the first insulating interlayer 130. A buried layer may be formed on the channel layer to sufficiently fill the remaining portion of the channel hole 140.

[0079] In an exemplary embodiment, the channel layer may include amorphous silicon, or polycrystalline silicon doped with impurities or undoped. In an exemplary embodiment where the channel layer includes amorphous silicon, a laser epitaxial growth (LEG) process or a solid phase epitaxy (SPE) process may be further performed to transform the amorphous silicon into crystalline silicon. The buried layer may include an oxide such as silicon oxide.

[0080] The buried layer and the channel layer may be planarized until an upper surface of the first insulating interlayer 130 may be exposed. A buried pattern 230 filling a remaining portion of each channel hole 140 may be formed, and the channel layer may be transformed into a channel 225.

[0081] Thus, the initial first barrier pattern 175, the tunnel insulating pattern 205, the channel 225, and the buried pattern 230 may be sequentially stacked on the sidewall of each channel hole 140. Each of the initial first barrier pattern 175 and the tunnel insulating pattern 205 may have a cup shape in which a central portion is penetrated. The channel 225 may have a cup shape, and the buried pattern 230 may have a pillar shape.

[0082] A plurality of channels 225 may be formed in each of the second direction and the third direction to form a channel array.

[0083] A charge trapping layer 180 may be formed on sidewalls of each sacrificial layer 120 adjacent to sidewalls of the channel 225 between the preliminary first barrier pattern 175 and the tunnel insulating pattern 205. The preliminary first barrier pattern 175, the charge trapping layer 180, the tunnel insulating pattern 205, and the channel 225 may be sequentially stacked in the third direction.

[0084] The buried pattern 230 , the channel 225 , the tunnel insulating pattern 205 , and upper portions of the preliminary first barrier pattern 175 may be removed to form a trench, and a pad 240 may be formed to fill the trench.

[0085] For example, after each of the upper portions of the buried pattern 230, the channel 225, the tunnel insulating pattern 205, and the initial first barrier pattern 175 is removed by an etch-back process to form a trench, a pad layer filling the trench may be formed on the buried pattern 230, the channel 225, the tunnel insulating pattern 205, the initial first barrier pattern 175, and the first insulating interlayer 130. The upper portion of the pad layer may be planarized until the upper surface of the first insulating interlayer 130 may be exposed to form the pad 240. In an exemplary embodiment, the pad layer may include amorphous silicon or polysilicon doped with impurities. In an exemplary embodiment in which the pad layer includes amorphous silicon, a process of crystallizing the pad layer may be further performed.

[0086] Reference Fig.14 and Fig.15, the second insulating interlayer 250 is formed on the upper surface (e.g., facing the first direction) of the first insulating interlayer 130 and the pad 240. A second opening 260 extending through the first insulating interlayer 130 and the second insulating interlayer 250, the insulating layer 110, and the sacrificial layer 120 may be formed to expose the upper surface of the substrate 100. In an exemplary embodiment, the second opening 260 is formed by performing an etching process using an etching mask. However, exemplary embodiments of the inventive concept are not limited thereto.

[0087] In an exemplary embodiment, the second opening 260 may extend in the second direction, and a plurality of second openings 260 may be formed along the third direction.

[0088] As the second openings 260 are formed, the insulating layer 110 may be transformed into the insulating pattern 115 , and the sacrificial layer 120 may be transformed into the sacrificial pattern.

[0089] The sacrificial pattern exposed by the second opening 260 may be removed to form a gap 270 between the insulating patterns 115 of adjacent heights (e.g., in the first direction). A portion of the outer sidewall of the initial first barrier pattern 175 and a portion of the sidewall of the semiconductor pattern 150 may be exposed by the gap 270. In an exemplary embodiment, the sacrificial pattern exposed by the second opening 260 may be removed by a wet etching process using an etchant including phosphoric acid or sulfuric acid. However, exemplary embodiments of the inventive concept are not limited thereto.

[0090] Reference Fig.16 and Fig.17 , the initial first barrier pattern 175 exposed by the gap 270 may be etched to expose the outer sidewall of the charge trapping layer 180 (e.g., the sidewall farthest from the tunnel insulating pattern 205 in the third direction). The exposed outer sidewall of the charge trapping layer 180 may be partially etched. Therefore, the initial first barrier pattern 175 may be transformed into the first barrier pattern 177, and the upper and lower portions of the charge trapping layer 180 may be separated and transformed into the charge trapping pattern structure 185.

[0091] In an exemplary embodiment, the etching of the charge trapping layer 180 may be performed by a wet etching process to selectively etch the nitride. Although the initial first barrier pattern 175 includes oxide, the initial first barrier pattern 175 may have a very small thickness and thus may be removed by the etching process. However, since the exposed portion of the initial first barrier pattern 175 contacting each insulating pattern 115 may have a large thickness in the direction in which the etching process is performed, for example, in the third direction, even if the exposed portion of the initial first barrier pattern 175 is partially removed by the etching process, it may partially remain to form the first barrier pattern 177. The surface of the first barrier pattern 177 may be partially exposed by the gap 270.

[0092] In an exemplary embodiment, the lowermost first barrier pattern 177 in the first direction may partially cover each of the surface of the insulating pattern 115 at the second height from the upper surface of the substrate 100, which may have the largest thickness (e.g., in the first direction), and the upper surface of the semiconductor 150. The uppermost first barrier pattern 177 in the first direction may partially cover the surface of the uppermost insulating pattern 115, which may have the second largest thickness, and the lower surface of the pad 240. For example, the uppermost first barrier pattern 177 may cover a sidewall of the insulating pattern 115 adjacent to the trench 225 at the eighth height from the upper surface of the substrate 100 and a portion of the lower surface of the pad 240. The first barrier patterns 177 at the remaining intermediate heights may partially cover the surfaces of the insulating pattern 115 at the remaining heights except for the lowermost height, respectively.

[0093] The etching process may be performed to etch the charge trapping layer 180 until the outer sidewall of the tunnel insulating pattern 205 (e.g., the sidewall farthest from the channel 225 in the third direction) may be partially exposed. Thus, the charge trapping layer 180 may be separated in the first direction by the exposed outer sidewall of the tunnel insulating pattern 205 to form a charge trapping pattern structure 185. The charge trapping pattern structure 185 formed above the exposed outer sidewall of the tunnel insulating pattern 205 (e.g., in the first direction) may be referred to as an upper charge trapping pattern 185a, and the charge trapping pattern structure 185 formed below the exposed outer sidewall of the tunnel insulating pattern 205 (e.g., in the first direction) may be referred to as a lower charge trapping pattern 185b. The charge trapping pattern structure 185, the tunnel insulating pattern 205, and the channel 225 together may form a first structure. However, in another exemplary embodiment, three or more separated charge trapping patterns may be formed.

[0094] Each of the upper charge trapping pattern 185a and the lower charge trapping pattern 185b may have a sidewall that is not vertical (e.g., at a right angle) but varies (e.g., is inclined to different degrees) with respect to the upper surface of the substrate 100, and may have a symmetrical shape along the first direction based on the exposed outer sidewall of the tunnel insulating pattern 205. In an exemplary embodiment, an upper surface of the upper charge trapping pattern 185a contacting the first barrier pattern 177 and a lower surface of the lower charge trapping pattern 185b contacting the first barrier pattern 177 may have substantially the same width in the third direction.

[0095] In an exemplary embodiment, the etching degree of the charge trapping layer 180 may be greater in a portion closer to each insulating pattern 115 along the first direction. Therefore, the outer sidewall of the upper charge trapping pattern 185a exposed by the gap 270 may have a slope gradually decreasing toward the top, and the outer sidewall of the lower charge trapping pattern 185b exposed by the gap 270 may have a slope gradually decreasing toward the bottom.

[0096] In an exemplary embodiment, the thickness of the upper charge trapping pattern 185a in the third direction may gradually decrease from top toward bottom, and the thickness of the lower charge trapping pattern 185b in the third direction may gradually increase from top toward bottom.

[0097] In an exemplary embodiment, the exposed outer sidewall of the tunnel insulation pattern 205 may protrude beyond the exposed outer sidewall of the charge trapping pattern structure 185 in the third direction. Fig.16 As shown in the exemplary embodiment of FIG. 1 , in a middle portion (eg, in the first direction) of the charge trapping pattern structure 185 , the exposed outer sidewalls of the tunnel insulation pattern 205 may protrude beyond the exposed outer sidewalls of the charge trapping pattern structure 185 in the third direction.

[0098] Reference Fig.18 and Fig.19 , the second barrier layer 280 can be formed to cover the inner wall of the gap 270 (for example, the exposed outer side walls of the tunnel insulation pattern 205 and the charge trapping pattern structure 185 and portions of the lower and upper surfaces of the insulation pattern 115), the side walls of the second opening 260, the upper surface of the substrate 100 exposed by the second opening 260, and the upper surface of the second insulating interlayer 250.

[0099] The second barrier layer 280 may cover the exposed upper surface of the substrate 100, the exposed sidewalls of the semiconductor pattern 150, the exposed surface of each insulating pattern 115, the exposed surface of each first barrier pattern 177, the exposed outer sidewall of each charge trapping pattern structure 185, the exposed outer sidewall of each tunnel insulating pattern 205, the sidewalls of the first insulating interlayer 130, and the sidewalls and upper surface of the second insulating interlayer 250. The second barrier layer 280 may contact the exposed outer sidewall of each tunnel insulating pattern 205.

[0100] In an exemplary embodiment, the second barrier layer 280 may be conformally formed to have a constant thickness, and may have a greater thickness than the first barrier pattern 177 .

[0101] In an exemplary embodiment, corresponding to the shapes of the outer sidewalls of the charge trapping pattern structure 185 and the outer sidewalls of the tunnel insulation pattern 205, the sidewalls of the second barrier layer 280 adjacent to the tunnel insulation pattern 205 between the insulation patterns 115 at the upper height and the lower height may have a shape in which a central portion in the first direction protrudes more than other portions in the third direction.

[0102] exist Fig.19 In the illustrated exemplary embodiment, a lower surface of the second barrier layer 280 exposed by the gap 270 of an upper portion contacting the insulating pattern 115 formed at an upper height (hereinafter referred to as the upper insulating pattern 115) may be formed lower (e.g., in the first direction) than a lower surface of the first barrier pattern 177 contacting the upper insulating pattern 115, and an upper surface of the second barrier layer 280 exposed by the gap 270 of a lower portion contacting the insulating pattern 115 formed at a lower height (hereinafter referred to as the lower insulating pattern 115) may be formed higher (e.g., in the first direction) than an upper surface of the first barrier pattern 177 contacting the lower insulating pattern 115. In an exemplary embodiment, each of the lower surface of the upper portion of the second barrier layer 280 and the upper surface of the lower portion of the second barrier layer 280 may have a slope substantially parallel to the upper surface of the substrate 100.

[0103] In an exemplary embodiment, the second barrier layer 280 may have substantially the same material as the first barrier pattern 177, for example, an oxide such as silicon oxide, and thus may be merged with the first barrier pattern 177. However, embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the second barrier layer 280 may have a structure in which a first layer including an oxide such as silicon oxide and a second layer including a metal oxide such as aluminum oxide, hafnium oxide, zirconium oxide, etc. are sequentially stacked.

[0104] Reference Fig. 20 and Fig.21, a gate electrode layer may be formed on the second barrier layer 280 to fill the remaining portion of the gap 270 .

[0105] In an exemplary embodiment, the gate electrode layer may include a gate barrier layer and a gate conductive layer stacked in sequence. The gate conductive layer may include a metal with low resistance, such as tungsten, titanium, tantalum, platinum, etc., and the gate barrier layer may include a metal nitride, such as titanium nitride, tantalum nitride, etc. However, exemplary embodiments of the inventive concept are not limited thereto.

[0106] In an exemplary embodiment, an upper surface of the gate electrode layer adjacent to the upper insulating pattern 115 may be formed lower in the first direction than a lower surface of the first barrier pattern 177 contacting the upper insulating pattern 115, and a lower surface of the gate electrode layer adjacent to the lower insulating pattern 115 may be formed higher in the first direction than an upper surface of the first barrier pattern 177 contacting the lower insulating pattern 115. Each of the upper and lower surfaces of the gate electrode layer may have a slope substantially parallel to the upper surface of the substrate 100 (e.g., extending in the third direction).

[0107] The gate electrode layer may be partially removed to form a gate conductive pattern and a gate barrier pattern in the gap 270, and the gate conductive pattern and the gate barrier pattern together may form a gate electrode. In an exemplary embodiment, the gate conductive pattern and the gate barrier pattern may be partially removed by a wet etching process.

[0108] The gate electrode may extend in the second direction, and a plurality of gate electrodes may be formed along the third direction. For example, the plurality of gate electrodes extending in the second direction may be spaced apart from each other in the third direction by the second opening 260 .

[0109] The gate electrode may include first to third gate electrodes 293 , 295 , and 297 sequentially formed along the first direction.

[0110] In an exemplary embodiment, an upper surface of the gate electrode adjacent to the upper insulating pattern 115 may be formed lower than a lower surface of the first barrier pattern 177 contacting the upper insulating pattern 115. A lower surface of the gate electrode adjacent to the lower insulating pattern 115 may be formed higher than an upper surface of the first barrier pattern 177 contacting the lower insulating pattern 115. Each of the upper and lower surfaces of the gate electrode may have a slope substantially parallel to the upper surface of the substrate 100 (e.g., extending in the third direction).

[0111] In an exemplary embodiment, a central portion (e.g., in the first direction) of a sidewall of the gate electrode that contacts an outer sidewall of the second barrier layer 280 between the upper insulating pattern 115 and the lower insulating pattern 115 and is adjacent to the channel 225 (e.g., with the tunnel insulating pattern 205 and the charge trapping pattern structure 185 therebetween) may have a shape that is concave toward the channel 225 compared to other portions of the sidewall of the gate electrode. For example, the central portion of the sidewall of the gate electrode may protrude further away from the channel 225 than other portions.

[0112] In an exemplary embodiment, the upper charge trapping pattern 185a and the lower charge trapping pattern 185b may be formed on a space between each of the second and third gate electrodes 295 and 297 and the tunnel insulating pattern 205. An upper surface of the upper charge trapping pattern 185a may be higher (e.g., in the first direction) than upper surfaces of the second and third gate electrodes 295 and 297 adjacent thereto. A lower surface of the lower charge trapping pattern 185b may be lower (e.g., in the first direction) than lower surfaces of the second and third gate electrodes 295 and 297 adjacent thereto.

[0113] Impurities may be implanted into the exposed upper portion of the substrate 100 to form the impurity region 105. Then, a second spacer layer may be formed on the exposed surface of the second barrier layer 280 and the exposed surface of the gate electrode. The second spacer layer may be anisotropically etched to form a second spacer 300 on the sidewall of the second opening 260. Thus, the impurity region 105 on the upper portion of the substrate 100 may be partially exposed.

[0114] The impurities may include n-type impurities such as phosphorus, arsenic, and the like, and the second spacer layer may include an oxide such as silicon oxide, and the like.

[0115] The CSL 310 may be formed on the exposed impurity region 105 to fill the remaining portion of the second opening 260 .

[0116] In an exemplary embodiment, the CSL 310 may be formed by forming a conductive layer on the exposed impurity region 105, the second spacer 300, and the second barrier layer 280 to fill the second opening 260. Then, an upper portion of the conductive layer may be planarized until an upper surface of the second insulating interlayer 250 is exposed. A portion of the second barrier layer 280 formed on an upper surface of the second insulating interlayer 250 may also be removed. Thus, the second barrier layer 280 may be transformed into a second barrier pattern 285. In an exemplary embodiment, the conductive layer may include a metal, a metal nitride, and / or a metal silicide.

[0117] Refer again Figures 1 to 3After forming a third insulating interlayer 320 on the second insulating interlayer 250 , the CSL 310 , the second spacer 300 , and the second barrier pattern 285 , a contact plug 330 extending through the third insulating interlayer 320 and the second insulating interlayer 250 and contacting an upper surface of the pad 240 may be formed.

[0118] A fourth insulating interlayer 340 may be formed on the third insulating interlayer 320 and the contact plug 330. A bit line 350 extending through the fourth insulating interlayer 340 and contacting an upper surface of the contact plug 330 may be formed to complete the manufacture of the vertical memory device.

[0119] The third insulating interlayer 320 and the fourth insulating interlayer 340 may include oxides such as silicon oxide, and the contact plug 330 and the bit line 350 may include metals such as copper, aluminum, tungsten, titanium, tantalum, etc. and / or metal nitrides such as titanium nitride, tantalum nitride, tungsten nitride, etc.

[0120] In an exemplary embodiment, the bit line 350 may extend in the third direction, and a plurality of the bit lines 350 may be arranged along the second direction.

[0121] As described above, the charge trapping pattern structure 185 formed between each of the second to third gate electrodes 295 and 297 and the channel 225 among the gate electrodes may include an upper charge trapping pattern 185a and a lower charge trapping pattern 185b spaced apart from each other along the first direction. A plurality of charge trapping patterns may be arranged in one transistor. Therefore, the integration of a vertical memory device including a transistor may be increased. In addition, electrons may be efficiently injected into the second to third gate electrodes 295 and 297 through each of the upper charge trapping pattern 185a and the lower charge trapping pattern 185b, thereby improving the electrical characteristics of the vertical memory device.

[0122] Since the second to third gate electrodes 295 and 297 and the insulating pattern 115 may be formed to have a concavo-convex shape in the first direction as a whole, the charge trapping pattern structure 185 may be at least partially interposed between the second to third gate electrodes 295 and 297 along the first direction, thereby minimizing interference between adjacent second to third gate electrodes 295 and 297. Therefore, coupling between the second gate electrodes 295 used as word lines may be reduced.

[0123] Fig. 22 and Fig.23 are cross-sectional views illustrating stages of a method of manufacturing a vertical memory device according to an exemplary embodiment of the inventive concept. Fig. 22 and Fig.23 is along Figure 1 The cross-sectional view corresponds to the cross-sectional view taken along the line AA'.

[0124] The method of manufacturing a vertical memory device comprises: Figures 4 to 21 and Figures 1 to 3 The processes described in the foregoing are substantially the same or similar processes. Therefore, the detailed description thereof is omitted here.

[0125] Reference Fig. 22 , can be executed with Figures 4 to 6 The process described in is substantially the same as or similar to the process described in.

[0126] However, before forming the semiconductor pattern 150 , the sidewall of the sacrificial layer exposed by the channel hole 140 may be partially removed to form the first recess 160 .

[0127] Therefore, the first recess 160 may be formed on all the sacrificial layers 120 including the lowermost sacrificial layer 120 , and the semiconductor pattern 150 may be formed to fill the first recess 160 that may be formed on the lowermost sacrificial layer 120 .

[0128] The upper and lower portions of the semiconductor pattern 150 may have substantially the same width. However, at least the central portion may have a greater width than each of the upper and lower portions. Therefore, the sidewall of the semiconductor pattern 150 may have a shape in which the central portion in the first direction further protrudes toward the sacrificial layer 120 than the other portions. For example, the central portion of the sidewall of the semiconductor pattern 150 may further protrude toward the sacrificial layer 120 in the third direction by an amount equal to the depth of the first recess 160. In an exemplary embodiment, an air gap may be formed on the central portion of the semiconductor pattern 150.

[0129] Reference Fig.23 , can be executed with Figures 7 to 21 and Figures 1 to 3 The processes described in the accompanying drawings are substantially the same as or similar to those described in the accompanying drawings to complete the manufacture of the vertical memory device.

[0130] Fig.24 and Fig.25 are cross-sectional views illustrating stages of a method of manufacturing a vertical memory device according to an exemplary embodiment of the inventive concept. Fig.24 is along Figure 1 The cross-sectional view corresponding to the cross-sectional view taken along the line A-A', Fig.25 is Fig.24 An enlarged cross-sectional view of area X in FIG.

[0131] The method of manufacturing a vertical memory device comprises: Figures 4 to 21 and Figures 1 to 3 The processes described in the foregoing are substantially the same or similar processes. Therefore, the detailed description thereof is omitted here.

[0132] Reference Fig.24 and Fig.25 , the vertical memory device may further include a third barrier pattern 289 formed between the second barrier pattern 285 and the gate electrode. The third barrier pattern 289 may cover upper and lower surfaces of the gate electrode and a sidewall of the gate electrode adjacent to the channel 225.

[0133] In an exemplary embodiment, a third barrier pattern 289 may also be formed between the second barrier pattern 285 and the second spacer 300 .

[0134] In an exemplary embodiment, the third barrier pattern 289 may be conformally formed to have a constant thickness. In an exemplary embodiment, the thickness of the third barrier pattern 289 may be substantially the same as that of the second barrier pattern 285 and may be greater than that of the first barrier pattern 177 .

[0135] The third barrier pattern 289 may include metal oxide such as aluminum oxide, hafnium oxide, zirconium oxide, or the like.

[0136] Fig.26 and Fig. 27 are cross-sectional views illustrating stages of a method of manufacturing a vertical memory device according to an exemplary embodiment of the inventive concept. Fig.26 is with Figure 2 The enlarged cross-sectional view corresponding to area X in Fig. 27 is with Figure 2 The enlarged cross-sectional view corresponding to the area X in FIG.

[0137] The method of manufacturing a vertical memory device comprises: Figures 4 to 21 and Figures 1 to 3 The processes described in the foregoing are substantially the same or similar processes. Therefore, the detailed description thereof is omitted here.

[0138] Reference Fig.26 , can be executed with Figures 4 to 17 The process described in is substantially the same as or similar to the process described in.

[0139] However, when etching the initial first barrier pattern 175 exposed by the gap 270 to expose the outer sidewall of the charge trapping layer 180 and then partially etching the exposed outer sidewall of the charge trapping layer 180 to form the first barrier pattern 177 and the charge trapping pattern structure 185, the etching process may be performed to a greater extent on a central portion of the outer sidewall of the charge trapping layer 180 in the first direction than on other portions. Therefore, the charge trapping pattern structure 185 may be etched to a greater extent as the portion of the outer sidewall having a shape protruding more away from the channel 225 in the third direction is closer to the tunnel insulating pattern 205 in the first direction. For example, the charge trapping pattern structure 185 may be etched to a greater extent as the middle portion of the charge trapping pattern structure 185 is closer in the first direction.

[0140] In an exemplary embodiment, the outer sidewall of the tunnel insulation pattern 205 may protrude beyond the lower portion of the outer sidewall of the upper charge trapping pattern 185 a and the upper portion of the outer sidewall of the lower charge trapping pattern 185 b in the third direction.

[0141] In an exemplary embodiment, an outer sidewall of the upper charge trapping pattern 185a may have a slope decreasing toward the top, and an outer sidewall of the lower charge trapping pattern 185b may have a slope decreasing toward the bottom.

[0142] Reference Fig. 27 , can be executed with Figures 18 to 21 and Figures 1 to 3 The processes described in the accompanying drawings are substantially the same as or similar to those described in the accompanying drawings to complete the manufacture of the vertical memory device.

[0143] A sidewall of the second barrier pattern 285 adjacent to the channel 225 and a sidewall of each of the second and third gate electrodes 295 and 297 adjacent to the channel 225 may have a shape corresponding to an outer sidewall of the tunnel insulating pattern 205 and an outer sidewall of the charge trapping pattern structure 185. For example, a middle portion (e.g., in the first direction) of the sidewalls of the second barrier pattern 285, the second gate electrode 295, and the third gate electrode 297 adjacent to the channel 225 may have a concave shape in the third direction toward the channel 225.

[0144] Fig.28 and Fig.29 are cross-sectional views illustrating stages of a method of manufacturing a vertical memory device according to an exemplary embodiment of the inventive concept. Fig.28 is with Figure 2 The enlarged cross-sectional view corresponding to the area X in FIG. Fig.29 is with Figure 2 The enlarged cross-sectional view corresponding to the area X in FIG.

[0145] The method of manufacturing a vertical memory device comprises: Figures 4 to 21 and Figures 1 to 3 The processes described in the foregoing are substantially the same or similar processes. Therefore, the detailed description thereof is omitted here.

[0146] Reference Fig.28 , can be executed with Figures 4 to 17 The process described in is substantially the same as or similar to the process described in.

[0147] However, when etching the initial first barrier pattern 175 exposed by the gap 270 to expose the outer sidewall of the charge trapping layer 180 and then partially etching the exposed outer sidewall of the charge trapping layer 180 to form the first barrier pattern 177 and the charge trapping pattern structure 185, the etching process may be performed to a greater extent on the upper portion, the lower portion, and the central portion of the outer sidewall of the charge trapping layer 180 in the first direction. The etching process may be performed to a lesser extent on each of the first portion of the outer sidewall of the charge trapping layer 180 disposed between the upper portion and the central portion thereof and the second portion of the outer sidewall of the charge trapping layer 180 disposed between the central portion and the lower portion thereof. Therefore, the charge trapping pattern structure 185 including the upper charge trapping pattern 185a and the lower charge trapping pattern 185b may have a curved shape as a whole.

[0148] In an exemplary embodiment, an outer sidewall of the tunnel insulating pattern 205 (e.g., a sidewall farthest from the channel 225) may protrude in the third direction beyond each of the upper and lower portions of the outer sidewall of the upper charge trapping pattern 185a and each of the upper and lower portions of the outer sidewall of the lower charge trapping pattern 185b. In some exemplary embodiments, the outer sidewall of the tunnel insulating pattern 205 may protrude less than a first portion of the outer sidewall of the upper charge trapping pattern 185a between the upper and lower portions (e.g., a protrusion of the upper charge trapping pattern 185a) and a second portion of the outer sidewall of the lower charge trapping pattern 185b between the upper and lower portions (e.g., a protrusion of the lower charge trapping pattern 185b) in the third direction. Fig.28 In the illustrated exemplary embodiment, the outer sidewall of the tunnel insulating pattern 205 protrudes to substantially the same point in the third direction as the protrusions of the upper charge trapping pattern 185 a and the lower charge trapping pattern 185 b .

[0149] In an exemplary embodiment, the outer sidewall of the charge trapping pattern structure 185 may have a slope that is not vertical (eg, at a right angle) but varies (eg, is inclined to different degrees) with respect to the upper surface of the substrate 100 .

[0150] In an exemplary embodiment, the thickness of the upper charge trapping pattern 185a in the third direction may be greatest at a first portion of the upper charge trapping pattern 185a, and the thickness of the lower charge trapping pattern 185b in the third direction may be greatest at a second portion of the lower charge trapping pattern 185b.

[0151] Reference Fig.29 , can be executed with Figures 18 to 21 and Figures 1 to 3 The processes described in the accompanying drawings are substantially the same as or similar to those described in the accompanying drawings to complete the manufacture of the vertical memory device.

[0152] Sidewalls of the second barrier pattern 285 adjacent to the channel 225 and sidewalls of each of the second and third gate electrodes 295 and 297 adjacent to the channel 225 may have shapes corresponding to outer sidewalls of the tunnel insulating pattern 205 and the charge trapping pattern structure 185 .

[0153] For example, the sidewall of the second barrier pattern 285 and the sidewall of each of the second and third gate electrodes 295 and 297 may respectively have a slope that is not vertical (eg, at a right angle) but varies (eg, is inclined to different degrees) with respect to the upper surface of the substrate 100 .

[0154] In exemplary embodiments, a sidewall of each of the second and third gate electrodes 295 and 297 adjacent to the channel 225 in the third direction may have a wavy shape as a whole toward the channel 225 .

[0155] As noted above, although the invention has been described with reference to exemplary embodiments, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present inventive concept.

[0156] This application claims the benefit of Korean Patent Application No. 10-2019-0067767 filed on June 10, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A vertical memory device, comprising: gate electrodes on a substrate, the gate electrodes being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a channel penetrating the gate electrode and extending in the vertical direction; a tunnel insulation pattern formed on an outer sidewall of the trench; a charge trapping pattern structure formed on an outer sidewall of the tunnel insulating pattern adjacent to the gate electrode in a horizontal direction parallel to the upper surface of the substrate, the charge trapping pattern structure comprising an upper charge trapping pattern and a lower charge trapping pattern, the upper charge trapping pattern and the lower charge trapping pattern at least partially overlapping with the corresponding gate electrode in the horizontal direction; as well as a blocking pattern formed between each of the gate electrodes adjacent to the charge trapping pattern structure and the charge trapping pattern structure; wherein the upper surface of the upper charge trapping pattern is higher than the upper surface of the gate electrode adjacent to the charge trapping pattern structure, and The lower surface of the lower charge trapping pattern is lower than the lower surface of the gate electrode adjacent to the charge trapping pattern structure. 2 . The vertical memory device of claim 1 , wherein a thickness of the upper charge trapping pattern in the horizontal direction decreases from a top portion toward a bottom portion, and a thickness of the lower charge trapping pattern in the horizontal direction increases from a top portion toward a bottom portion. 3 . The vertical memory device of claim 1 , wherein the barrier pattern covers the upper surface and the lower surface of each of the gate electrodes.

4. The vertical memory device according to claim 1, wherein: The blocking pattern is a second blocking pattern; and The vertical memory device further includes a first barrier pattern covering the upper surface of the upper charge trap pattern and the lower surface of the lower charge trap pattern. 5 . The vertical memory device of claim 4 , wherein the second barrier pattern has a thickness in the vertical direction greater than a thickness of the first barrier pattern.

6. The vertical memory device according to claim 1, wherein: the upper charge trapping pattern and the lower charge trapping pattern are spaced apart from each other in the vertical direction by a portion of the tunnel insulating pattern; as well as The tunnel insulating pattern includes a protrusion protruding away from the channel in the horizontal direction. 7 . The vertical memory device of claim 6 , wherein a sidewall of the barrier pattern contacts the protrusion of the tunnel insulating pattern and has a convex shape toward each of the gate electrodes. 8 . The vertical memory device according to claim 1 , wherein a sidewall of each of the gate electrodes adjacent to the channel in the horizontal direction has a concave or convex shape toward the channel. 9 . The vertical memory device of claim 1 , wherein a sidewall of each of the gate electrodes adjacent to the channel in the horizontal direction has a wavy shape toward the channel.

10. A vertical memory device comprising: gate electrodes on a substrate, the gate electrodes being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a channel penetrating the gate electrode and extending in the vertical direction; a tunnel insulation pattern formed on an outer sidewall of the trench; a charge trapping pattern structure formed on an outer sidewall of the tunnel insulating pattern adjacent to the gate electrode in a horizontal direction parallel to the upper surface of the substrate, the charge trapping pattern structure comprising an upper charge trapping pattern and a lower charge trapping pattern, the upper charge trapping pattern and the lower charge trapping pattern at least partially overlapping with the corresponding gate electrode in the horizontal direction; as well as A blocking pattern is formed between each of the gate electrodes adjacent to the charge trapping pattern structure and the charge trapping pattern structure, wherein the blocking pattern covers an upper surface and a lower surface of each of the gate electrodes. 11 . The vertical memory device of claim 10 , wherein the blocking pattern covers an upper surface of the upper charge trap pattern and a lower surface of the lower charge trap pattern.

12. The vertical memory device of claim 11, wherein portions of the blocking pattern covering the upper surface and the lower surface of each of the gate electrodes have a thickness greater than a thickness of portions of the blocking pattern covering the upper surface of the upper charge trapping pattern and the lower surface of the lower charge trapping pattern. 13 . The vertical memory device of claim 10 , wherein a thickness of the upper charge trapping pattern in the horizontal direction decreases from a top portion toward a bottom portion, and a thickness of the lower charge trapping pattern in the horizontal direction increases from a top portion toward a bottom portion. 14 . The vertical memory device of claim 10 , wherein the tunnel insulating pattern comprises a protrusion protruding in the horizontal direction, wherein the upper and lower charge trap patterns are spaced apart from each other in the vertical direction by the protrusion. 15 . The vertical memory device of claim 14 , wherein a sidewall of the barrier pattern contacts the protrusion of the tunnel insulating pattern and has a convex shape toward each of the gate electrodes.

16. A vertical memory device comprising: gate electrodes on a substrate, the gate electrodes being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a channel penetrating the gate electrode and extending in the vertical direction; a tunnel insulating pattern formed on an outer sidewall of the trench, the tunnel insulating pattern comprising a protrusion protruding in a horizontal direction parallel to the upper surface of the substrate; a charge trapping pattern structure formed on an outer sidewall of the tunnel insulating pattern adjacent to the gate electrode in the horizontal direction, the charge trapping pattern structure comprising an upper charge trapping pattern and a lower charge trapping pattern spaced apart from each other in the vertical direction by the protrusion of the tunnel insulating pattern, the upper charge trapping pattern and the lower charge trapping pattern at least partially overlapping with the corresponding gate electrode in the horizontal direction; as well as A barrier pattern has a sidewall having a convex shape toward each of the gate electrodes, the convex shape corresponding to the protrusion of the tunnel insulating pattern. 17 . The vertical memory device of claim 16 , wherein a thickness of the upper charge trapping pattern in the horizontal direction decreases from a top portion toward a bottom portion, and a thickness of the lower charge trapping pattern in the horizontal direction increases from a top portion toward a bottom portion. 18 . The vertical memory device of claim 16 , wherein the barrier pattern covers an upper surface and a lower surface of each of the gate electrodes. 19 . The vertical memory device of claim 18 , wherein the blocking pattern covers an upper surface of the upper charge trap pattern and a lower surface of the lower charge trap pattern.

20. The vertical memory device of claim 19, wherein portions of the blocking pattern covering the upper surface and the lower surface of each of the gate electrodes have a thickness greater than a thickness of portions of the blocking pattern covering the upper surface of the upper charge trapping pattern and the lower surface of the lower charge trapping pattern.

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