Semiconductor package and method of manufacturing the same

Abstract

Disclosed is a semiconductor package comprising: a redistribution structure including a redistribution insulating layer and a redistribution pattern; a first semiconductor chip disposed on a first surface of the redistribution insulating layer and electrically connected to the redistribution pattern; and a lower electrode pad disposed on a second surface of the redistribution insulating layer opposite to the first surface, the lower electrode pad comprising a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0078341 filed on June 28, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present inventive concept relates to a semiconductor package and a method of manufacturing the semiconductor package, and more particularly, to a fan-out semiconductor package and a method of manufacturing the fan-out semiconductor package. For example, the present disclosure relates to a method and device of a fan-out wafer level package (FOWLP). Background Art

[0004] Recently, due to the rapid growth in demand for portable devices in the electronic product market, there has been a need for miniaturization and lightweighting of electronic components installed in these electronic products. For the miniaturization and lightweighting of electronic components, it is advantageous that the semiconductor package mounted thereon has a smaller volume while being able to process a large amount of data. In particular, in a highly integrated semiconductor chip with an increased number of input and output (I / O) terminals, the spacing between the input and output terminals can be reduced, and thus interference may occur between the input and output terminals. In order to eliminate such interference between the input and output terminals, a fan-out semiconductor package with an increased spacing between the input and output terminals is beneficial. Summary of the invention

[0005] The inventive concept provides a semiconductor package having improved reliability and a method of manufacturing the semiconductor package.

[0006] According to one aspect of the inventive concept, a semiconductor package is provided, comprising: a redistribution structure including a redistribution insulating layer and a redistribution pattern; a first semiconductor chip disposed on a first surface of the redistribution insulating layer and electrically connected to the redistribution pattern; and a lower electrode pad disposed on a second surface of the redistribution insulating layer opposite to the first surface, the lower electrode pad comprising a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

[0007] According to one aspect of the inventive concept, a semiconductor package is provided, comprising: a redistribution insulating layer, comprising a first surface and a second surface opposite to each other; a first conductive line pattern in the redistribution insulating layer; a second conductive line pattern on the first surface of the redistribution insulating layer; a lower electrode pad, comprising a first portion embedded in the redistribution insulating layer, and a second portion protruding from the second surface of the redistribution insulating layer; a first conductive via pattern extending between the first conductive line pattern and the lower electrode pad and contacting the lower electrode pad; a second conductive via pattern extending between the second conductive line pattern and the first conductive line pattern; and a semiconductor chip disposed on the redistribution insulating layer and electrically connected to the second conductive line pattern.

[0008] According to one aspect of the inventive concept, a semiconductor package is proposed, comprising: a redistribution structure comprising a plurality of insulating layers, a plurality of conductive line patterns disposed on an upper surface of each of the plurality of insulating layers, and a plurality of conductive through-hole patterns, the plurality of conductive through-hole patterns penetrating at least one of the plurality of insulating layers and connected to at least one of the plurality of conductive line patterns; a semiconductor chip on an upper surface of the redistribution structure; a chip connection terminal between the semiconductor chip and the uppermost conductive line pattern of the plurality of conductive line patterns; a bottom filling material layer surrounding the chip connection terminal between the semiconductor chip and the redistribution structure; a molding layer covering at least a portion of the semiconductor chip; a lower electrode pad on a bottom surface of the redistribution structure; and an external connection terminal on the lower electrode pad, wherein the lower electrode pad comprises a first portion embedded in a lowermost insulating layer of the plurality of insulating layers, and a second portion protruding from the lowermost insulating layer, and a thickness of the second portion of the lower electrode pad is less than a thickness of the first portion of the lower electrode pad.

[0009] According to one aspect of the inventive concept, there is provided a method for manufacturing a semiconductor package, the method comprising: forming a covering insulating layer on a carrier substrate; forming a lower electrode pad on the covering insulating layer; forming a redistribution structure, the redistribution structure comprising a redistribution insulating layer covering the lower electrode pad and a redistribution pattern electrically connected to the lower electrode pad; arranging a semiconductor chip on the redistribution structure; removing the carrier substrate and removing the covering insulating layer; and removing a portion of the redistribution insulating layer to expose a portion of a side wall of the lower electrode pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concept;

[0012] Figure 2According to an exemplary embodiment of the present invention Figure 1 An enlarged cross-sectional view of region "II" in FIG.

[0013] Figure 3 is a flowchart illustrating a method of manufacturing a semiconductor package according to an example embodiment of the inventive concept;

[0014] FIG. 4A to FIG. 4L are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an example embodiment of the inventive concept;

[0015] FIG. 5A to FIG. 5E are cross-sectional views sequentially illustrating a method of forming a first redistribution pattern according to an example embodiment of the inventive concept;

[0016] Figure 6 is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concept; and

[0017] Figure 7 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0018] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same elements, and redundant descriptions thereof will be omitted.

[0019] Figure 1 is a cross-sectional view illustrating a semiconductor package 10 according to an example embodiment of the inventive concepts. Figure 2 According to an exemplary embodiment of the present invention Figure 1 An enlarged cross-sectional view of region “II”.

[0020] Reference Figure 1 and Figure 2 , the semiconductor package 10 may include a redistribution structure 100 , a semiconductor chip 200 disposed on an upper side of the redistribution structure 100 , and a lower electrode pad 150 disposed on a lower side of the redistribution structure 100 .

[0021] The redistribution structure 100 may include a redistribution insulation layer 110 and a plurality of redistribution patterns 120 , 130 , and 140 .

[0022] The redistribution insulating layer 110 may include a plurality of insulating layers 111, 113, and 115. Each of the plurality of insulating layers 111, 113, and 115 may include, for example, a material film including an organic compound. In example embodiments, each of the plurality of insulating layers 111, 113, and 115 may include a material film including an organic polymer material. In example embodiments, each of the plurality of insulating layers 111, 113, and 115 may include an insulating material, wherein the insulating material may include a photoimageable dielectric (PID) material that can be used in a photolithography process. For example, each of the plurality of insulating layers 111, 113, and 115 may include photosensitive polyimide (PSPI). In example embodiments, each of the plurality of insulating layers 111, 113, and 115 may include an oxide or a nitride.

[0023] The plurality of redistribution patterns 120, 130, and 140 may include a plurality of conductive line patterns 121, 131, and 141 and a plurality of conductive via patterns 123, 133, and 143. The plurality of conductive line patterns 121, 131, and 141 may be disposed on at least one of the upper and lower surfaces of each of the plurality of insulating layers 111, 113, and 115. The plurality of conductive via patterns 123, 133, and 143 may penetrate at least one of the plurality of insulating layers 111, 113, and 115. The plurality of conductive via patterns 123, 133, and 143 may be connected to at least one of the plurality of conductive line patterns 121, 131, and 141, and / or may be connected to the lower electrode pad 150.

[0024] The plurality of seed layers 125, 135, and 145 may be interposed between the plurality of insulating layers 111, 113, and 115 and the plurality of conductive line patterns 121, 131, and 141, respectively, and may be interposed between the plurality of insulating layers 111, 113, and 115 and the plurality of conductive via patterns 123, 133, and 143, respectively. In example embodiments, the plurality of seed layers 125, 135, and 145 may be formed by performing physical vapor deposition, and the plurality of conductive line patterns 121, 131, and 141 and the plurality of conductive via patterns 123, 133, and 143 may be formed using an electroless plating process such as a chemical plating process or an autocatalytic plating process.

[0025] For example, the plurality of seed layers 125, 135, and 145 may be selected from a group consisting of copper (Cu), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), aluminum (Al), etc. However, the plurality of seed layers 125, 135, and 145 are not limited to these materials. In example embodiments, the plurality of seed layers 125, 135, and 145 may include Cu / Ti with copper stacked on titanium, or Cu / TiW with copper stacked on titanium tungsten.

[0026] The plurality of conductive line patterns 121, 131, and 141 and the plurality of conductive via patterns 123, 133, and 143 may include metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), and tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), or alloys thereof, but are not limited thereto. In example embodiments, when the plurality of conductive line patterns 121, 131, and 141 and the plurality of conductive via patterns 123, 133, and 143 include copper (Cu), at least a portion of the plurality of seed layers 125, 135, and 145 may serve as a diffusion barrier layer. For example, the diffusion barrier layer may prevent / reduce the diffusion of materials of the conductive line patterns 121, 131, and 141 and / or the conductive via patterns 123, 133, and 143 into the insulating layers 111, 113, and 115.

[0027] A portion of the plurality of conductive thread patterns 121, 131, and 141 may form a single body with a portion of the plurality of conductive via patterns 123, 133, and 143. For example, a portion of the plurality of conductive thread patterns 121, 131, and 141 may form a single body with a portion of the plurality of conductive via patterns 123, 133, and 143, and a portion of the plurality of conductive via patterns 123, 133, and 143 contacts a lower side of a portion of the plurality of conductive thread patterns 121, 131, and 141. Alternatively, a portion of the plurality of conductive thread patterns 121, 131, and 141 may form a single body with a portion of the plurality of conductive via patterns 123, 133, and 143, and a portion of the plurality of conductive via patterns 123, 133, and 143 contacts an upper side of a portion of the plurality of conductive thread patterns 121, 131, and 141. In some embodiments, each of the conductive via patterns 123, 133, and 143 may be integrated with a corresponding one of the conductive line patterns 121, 131, and 141 disposed thereover to form a Figure 1 In some embodiments, each conductive via pattern 123, 133, and 143 may be integrated with a corresponding conductive line pattern 121, 131, or 141 disposed thereunder to form a continuous body, which is different from Figure 1 .

[0028] It will be understood that when an element is referred to as being “connected” or “coupled” “to” or “on” another element, the element may be directly connected or coupled to or directly on the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to or “contacting” or “in contact with” another element, there are no intervening elements.

[0029] The configuration of the redistribution structure 100 will be described in more detail below.

[0030] The redistribution insulating layer 110 may include a first insulating layer 111, a second insulating layer 113, and a third insulating layer 115 sequentially stacked. The first redistribution pattern 120 may include a first conductive line pattern 121, a first conductive via pattern 123, and a first seed layer 125. The second redistribution pattern 130 may include a second conductive line pattern 131, a second conductive via pattern 133, and a second seed layer 135. The third redistribution pattern 140 may include a third conductive line pattern 141, a third conductive via pattern 143, and a third seed layer 145.

[0031] The first insulating layer 111 may include a first through hole opening VO1 that exposes a portion of 150. The first seed layer 125 may be disposed on a portion of the upper surface of the first insulating layer 111, a sidewall of the first through hole opening VO1, and a portion of the upper surface of the lower electrode pad 150 exposed through the first through hole opening VO1. A portion of the first seed layer 125 may be interposed between the first conductive line pattern 121 and the upper surface of the first insulating layer 111, another portion of the first seed layer 125 may be formed to surround the sidewall of the first conductive via pattern 123, and another portion of the first seed layer 125 may be interposed between the first conductive via pattern 123 and the lower electrode pad 150.

[0032] Unless the context indicates otherwise, the terms first, second, third, etc. are used as labels to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section (which may or may not be similar). Thus, an element, component, region, layer, or section discussed below in one part of the specification (or a claim) may be referred to as a second element, component, region, layer, or section in another part of the specification (or another claim).

[0033] The first conductive line pattern 121 and the first conductive via pattern 123 may be disposed on the first seed layer 125. The first conductive line pattern 121 and the first conductive via pattern 123 may be formed together by a plating process and may be integrated with each other as a single body. The first conductive line pattern 121 may be disposed on a portion of the first seed layer 125 formed on the upper surface of the first insulating layer 111, and the first conductive line pattern 121 may also be disposed on the first conductive via pattern 123. The first conductive via pattern 123 may cover a portion of the first seed layer 125 in the first via opening VO1 and may fill the first via opening VO1. For example, the top of the first conductive via pattern 123 may have the same level as the upper surface of the first insulating layer 111 (e.g., at the same vertical level). For example, the first conductive via pattern 123 and a portion of the first seed layer 125 may fill the first via opening VO1 from the bottom to the top of the first via opening VO1. The first conductive via pattern 123 may penetrate the first insulating layer 111 to connect the first conductive line pattern 121 to the lower electrode pad 150. For example, the first conductive via pattern 123 may electrically connect the first conductive wire pattern 121 to the lower electrode pad 150 .

[0034] The embodiments herein may be shown with idealized views (although relative dimensions may be exaggerated for clarity). It should be understood that actual implementations may differ from these exemplary views, depending on manufacturing techniques and / or tolerances. Therefore, when referring to orientation, layout, position, shape, size, quantity or other metrics, the description of certain features using terms such as "same", "equal" and geometric descriptions such as "parallel", "uniform", "planar", "coplanar", "cylindrical", "square", etc. as used herein includes acceptable variations from being exactly the same, including nearly identical layouts, positions, shapes, sizes, quantities or other metrics within acceptable variations that occur, for example, due to manufacturing processes. Unless otherwise indicated by the context or other statements, the term "substantially" may be used herein to emphasize this meaning.

[0035] In example embodiments, the first conductive via pattern 123 may have a shape that gradually decreases in a direction from the first surface 118 to the second surface 119 of the redistribution insulation layer 110. For example, a cross-sectional area of ​​the first conductive via pattern 123 parallel to the upper surface of the first insulation layer 111 may gradually decrease from the upper surface of the first insulation layer 111 to the lower surface of the first insulation layer 111. Figure 1 and Figure 2 As shown, the width of the first conductive via pattern 123 may gradually decrease from the top to the bottom of the first conductive via pattern 123 in the cross-sectional view.

[0036] The second insulating layer 113 may be stacked on the first insulating layer 111, the second insulating layer 113 covering a portion of the first conductive line pattern 121 and having a second through hole opening VO2 exposing the remaining portion of the first conductive line pattern 121. For example, a portion of the first conductive line pattern 121 may be covered by the second insulating layer 113, and a portion of the first conductive line pattern 121 may be exposed through the second through hole opening VO2 formed in the second insulating layer 113.

[0037] The second seed layer 135 may be disposed on a portion of the upper surface of the second insulating layer 113, the sidewall of the second via opening VO2, and a portion of the upper surface of the first conductive line pattern 121 exposed through the second conductive via opening VO2. A portion of the second seed layer 135 may be interposed between the second conductive line pattern 131 and the upper surface of the second insulating layer 113, another portion of the second seed layer 135 may be formed to surround the sidewall of the second conductive via pattern 133, and another portion of the second seed layer 135 may be interposed between the second conductive via pattern 133 and the first conductive line pattern 121.

[0038] The second conductive via pattern 133 and the second conductive line pattern 131 may be disposed on the second seed layer 135. The second conductive via pattern 133 and the second conductive line pattern 131 may be formed by a plating process and may be integrated with each other as a single body. The second conductive line pattern 131 may be disposed on a portion of the second seed layer 135 on the upper surface of the second insulating layer 113, and the second conductive line pattern 131 may also be disposed on the second conductive via pattern 133. The second conductive via pattern 133 may cover a portion of the second seed layer 135 in the second via opening VO2 and may fill the second via opening VO2. For example, the top of the second conductive via pattern 133 may have the same level as the upper surface of the second insulating layer 113 (e.g., at the same vertical level). For example, the second conductive via pattern 133 and a portion of the second seed layer 135 may fill the second via opening VO2 from the bottom to the top of the second via opening VO1. The second conductive via pattern 133 may penetrate the second insulating layer 113 to connect the second conductive line pattern 131 to the first conductive line pattern 121. For example, the second conductive via pattern 133 may electrically connect the second conductive thread pattern 131 to the first conductive thread pattern 121 .

[0039] In example embodiments, the second conductive via pattern 133 may have a shape that gradually decreases in a direction from the first surface 118 to the second surface 119 of the redistribution insulation layer 110. For example, a cross-sectional area of ​​the second conductive via pattern 133 parallel to the upper surface of the second insulation layer 113 may gradually decrease from the upper surface of the second insulation layer 113 to the lower surface of the second insulation layer 113. Figure 1 and Figure 2 As shown, the width of the second conductive via pattern 133 may gradually decrease from the top to the bottom of the second conductive via pattern 133 in the cross-sectional view.

[0040] The third insulating layer 115 may be stacked on the second insulating layer 113, the second insulating layer 115 covering a portion of the second conductive line pattern 131 and having a third through hole opening VO3 exposing the remaining portion of the second conductive line pattern 131. For example, a portion of the second conductive line pattern 131 may be covered by the third insulating layer 115, and a portion of the second conductive line pattern 131 may be exposed through the third through hole opening VO3 formed in the third insulating layer 115.

[0041] The third seed layer 145 may be disposed on a portion of the upper surface of the third insulating layer 115, the sidewall of the third via opening VO3, and a portion of the upper surface of the second conductive line pattern 131 exposed through the third conductive via opening VO3. A portion of the third seed layer 145 may be interposed between the third conductive line pattern 141 and the upper surface of the third insulating layer 115, another portion of the third seed layer 145 may be formed to surround the sidewall of the third conductive via pattern 143, and another portion of the third seed layer 145 may be interposed between the third conductive via pattern 143 and the second conductive line pattern 131.

[0042] The third conductive via pattern 143 and the third conductive line pattern 141 may be disposed on the third seed layer 145. The third conductive via pattern 143 and the third conductive line pattern 141 may be formed by a plating process and may be integrated with each other as a single body. The third conductive line pattern 141 may be disposed on a portion of the third seed layer 145 on the upper surface of the third insulating layer 115, and the third conductive line pattern 141 may also be disposed on the third conductive via pattern 143. The third conductive via pattern 143 may cover a portion of the third seed layer 145 in the third through hole opening VO2 and may fill the third through hole opening VO3. For example, the top of the third conductive via pattern 143 may have the same level as the upper surface of the third insulating layer 115 (e.g., at the same vertical level). For example, the third conductive via pattern 143 and a portion of the second seed layer 145 may fill the second through hole opening VO2 from the bottom to the top of the second through hole opening VO1. The third conductive via pattern 143 may penetrate the third insulating layer 115 to connect the third conductive line pattern 141 to the second conductive line pattern 131. For example, the third conductive via pattern 143 may electrically connect the third conductive thread pattern 141 to the second conductive thread pattern 131 .

[0043] In example embodiments, the third conductive via pattern 143 may have a shape that gradually decreases in a direction from the first surface 118 to the second surface 119 of the redistribution insulation layer 110. For example, a cross-sectional area of ​​the third conductive via pattern 143 parallel to the upper surface of the third insulation layer 115 may gradually decrease from the upper surface of the third insulation layer 115 to the lower surface of the third insulation layer 115. Figure 1 and Figure 2 As shown, the width of the third conductive via pattern 143 may gradually decrease from the top to the bottom of the third conductive via pattern 143 in the cross-sectional view.

[0044] In example embodiments, the third conductive wire pattern 141 may be disposed on the first surface 118 of the redistribution insulation layer 110 , and may serve as an upper electrode pad that may be attached to the semiconductor chip 200 .

[0045] exist Figure 1 , the redistribution structure 100 is shown to include three insulating layers 111, 113, and 115, three conductive line patterns 121, 131, and 141, and three conductive via patterns 123, 133, and 143, but is not limited thereto. The number of insulating layers, the number of conductive line patterns, and the number of conductive via patterns may be variously modified according to the design of circuit interconnections in the redistribution structure 100.

[0046] The semiconductor chip 200 may be attached to the redistribution structure 100. For example, the semiconductor chip 200 may be mounted on the redistribution structure 100 in a flip-chip manner. For example, the semiconductor chip 200 may be inverted so that the chip pads 220 are lowered onto the chip connection terminals 230 and / or lowered toward the third conductor pattern 141.

[0047] The semiconductor chip 200 may include, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. The semiconductor chip 200 may include, for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable programmable read-only memory (EPROM) chip, a phase change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, or a resistive random access memory (RRAM) chip.

[0048] The semiconductor chip 200 may include a semiconductor substrate 210 and a chip pad 220 disposed on one surface of the semiconductor substrate 210 .

[0049] The semiconductor substrate 210 may include, for example, silicon (Si). Alternatively, the semiconductor substrate 210 may include a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP). The semiconductor substrate 210 may have an active surface and an inactive surface opposite to the active surface. In example embodiments, the active surface of the semiconductor substrate 210 may face the redistribution structure 100.

[0050] The semiconductor chip 200 may include a plurality of various individual devices on an active surface of a semiconductor substrate 210 .

[0051] The chip connection terminal 230 may be disposed between the chip pad 220 of the semiconductor chip 200 and the third conductive wire pattern 141 serving as an upper electrode pad of the redistribution structure 100. The chip connection terminal 230 may electrically connect the chip pad 220 of the semiconductor chip 200 with the third conductive wire pattern 141. The chip connection terminal 230 may include, for example, at least one of a columnar structure, a solder bump, a solder ball, and a solder layer.

[0052] Through the chip connection terminal 230, the path from the first redistribution pattern to the third redistribution pattern 120, 130 and 140 of the redistribution structure 100, the lower electrode pad 150 and the external connection terminal 400, the semiconductor chip 200 can receive at least one of a control signal, a power signal and a ground signal from the outside for the operation of the semiconductor chip 200, and the semiconductor chip 200 can also receive a data signal to be stored in the semiconductor chip 200 from the outside, or can provide the data signal stored in the semiconductor chip 200 to the outside.

[0053] An underfill material layer 240 surrounding the chip connection terminals 230 may be filled between the semiconductor chip 200 and the redistribution structure 100. The underfill material layer 240 may include, for example, an epoxy resin formed by a capillary underfill method. In example embodiments, the underfill material layer 240 may include a non-conductive film (NCF), such as an insulator.

[0054] The lower electrode pad 150 may be disposed on the lower side of the redistribution structure 100. The external connection terminal 400 may be disposed on the lower electrode pad 150. The semiconductor package 10 may be electrically connected to and mounted on a module substrate or a system board of an electronic product / device through the external connection terminal 400. The lower electrode pad 150 may be used as an under bump metal (UBM) provided with the external connection terminal 400.

[0055] For example, the lower electrode pad 150 and other pads described herein may have a uniform thickness. The bottom surface of the lower electrode pad 150 provided with the external connection terminal 400 may include a flat surface. The top surface of the lower electrode pad 150 may also have a flat surface, which may be parallel to the bottom surface. For example, the lower electrode pad 150 may include a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga) or ruthenium (Ru) or an alloy thereof, but is not limited thereto.

[0056] In example embodiments, a portion of the lower electrode pad 150 may be embedded in the redistribution insulating layer 110, and another portion of the lower electrode pad 150 may protrude from the redistribution insulating layer 110. For example, the embedded portion of the lower electrode pad 150 may be a portion that is recessed into the redistribution insulating layer 110 relative to the surface level of the redistribution insulating layer 110. For example, the redistribution insulating layer 110 may cover a portion of the sidewall of the lower electrode pad 150, but may not cover another portion of the sidewall of the lower electrode pad 150. In some embodiments, a portion of the lower electrode pad 150 may be embedded in the redistribution insulating layer 110, and another portion of the lower electrode pad 150 may protrude from the redistribution insulating layer 110, such as Figure 1 and Figure 2 For example, the top surface of the lower electrode pad 150 may be at a level higher than the second surface 119 of the redistribution insulation layer 110. Figure 1 and Figure 2 For example, a top surface of the lower electrode pad 150 may contact the redistribution insulation layer 110 .

[0057] According to example embodiments of the inventive concepts, another portion of the lower electrode pad 150 may protrude from the second surface 119 of the redistribution insulation layer 110, and thus stress along the second surface 119 of the redistribution insulation layer 110 may be reduced at the sidewall of the lower electrode pad 150. Therefore, damage to the lower electrode pad 150 and the redistribution structure 100 around the electrode pad 150 due to stress on the semiconductor package 10 may be prevented, and ultimately the reliability of the semiconductor package 10 may be improved.

[0058] For example, a portion of the lower electrode pad 150 embedded in the redistribution insulating layer 110 (or surrounded by the redistribution insulating layer 110) may be defined as a first portion 151 of the lower electrode pad 150, and another portion of the lower electrode pad 150 protruding from the second surface 119 of the redistribution insulating layer 110 may be defined as a second portion 153 of the lower electrode pad 150. In this case, the sidewall of the first portion 151 of the lower electrode pad 150 may be covered by the redistribution insulating layer 110, and the sidewall of the second portion 153 of the lower electrode pad 150 may not be covered by the redistribution insulating layer 110. The sidewall of the second portion 153 of the lower electrode pad 150 may be exposed to the outside. For example, the second portion 153 of the electrode pad 150 may be exposed to the outside of the redistribution insulating layer 110. For example, when the semiconductor package 10 is mounted on / connected to another device / structure, the second portion 153 may be covered by another structure (e.g., by the external connection terminal 400 and / or another structure).

[0059] In example embodiments, a thickness 151t of a first portion 151 of the lower electrode pad 150 may be greater than a thickness 153t of a second portion 153 of the lower electrode pad 150. For example, a height of a sidewall of the first portion 151 of the lower electrode pad 150 may be greater than a height of a sidewall of the second portion 153 of the lower electrode pad 150. When a thickness 153t of the second portion 153 of the lower electrode pad 150 protruding from the redistribution insulating layer 110 is too small, a stress relaxation effect at a sidewall of the lower electrode pad 150 may be reduced. When a thickness 153t of the second portion 153 of the lower electrode pad 150 protruding from the redistribution insulating layer 110 is too large compared to the total thickness of the lower electrode pad 150, a thickness 151t of the first portion 151 of the lower electrode pad 150 embedded in the redistribution insulating layer 110 may be too small, so that adhesion between the redistribution insulating layer 110 and the lower electrode pad 150 may be reduced.

[0060] In example embodiments, a thickness 153t of the second portion 153 of the lower electrode pad 150 may be between about 10% and about 30% of the total thickness of the lower electrode pad 150. For example, when the thickness of the lower electrode pad 150 is 10 μm, a thickness 153t of the second portion 153 of the lower electrode pad 150 protruding from the second surface 119 of the redistribution insulating layer 110 may be between about 1 μm and about 3 μm. For example, when the thickness of the lower electrode pad 150 is 10 μm, a thickness 151t of the first portion 151 of the lower electrode pad 150 embedded in the redistribution insulating layer 110 may be between about 7 μm and about 9 μm. A height direction of the sidewalls of the first portion 151 and the second portion 153 and a thickness direction of the lower electrode pad 150 including the first portion 151 and the second portion 153 may be perpendicular to the first surface 118 and / or the second surface 119 of the redistribution insulating layer 110.

[0061] Terms such as "about" or "approximately" may reflect that the amount, size, orientation, or arrangement varies only in a minor relative manner and / or in a manner that does not significantly change the operation, function, or structure of certain elements. For example, a range from "about 0.1 to about 10" may include ranges such as 0% to 5% deviation around 0.1 and 0% to 5% deviation around 10, particularly where such deviations maintain the same effect as the listed range.

[0062] The semiconductor package 10 may further include a mold layer 300 that covers at least a portion of the semiconductor chip 200 on the redistribution structure 100. The mold layer 300 may include, for example, an epoxy mold compound (EMC). The mold layer 300 may cover a portion of the first surface 118 of the redistribution insulation layer 110, and may cover the side surface of the semiconductor chip 200. In this case, the upper surface of the semiconductor chip 200 may be exposed to the outside, for example, to the outside of the mold layer 300 or to the outside of the semiconductor package 10. In other example embodiments, the mold layer 300 may also cover the upper surface of the semiconductor chip 200.

[0063] Although not shown in the drawings, a heat dissipation member may be attached to the upper surface of the semiconductor chip 200. The heat dissipation member may include, for example, a heat sink or a heat sink. In an example embodiment, a thermal interface material (TIM) may be disposed between the heat dissipation member and the upper surface of the semiconductor chip 200. The thermal interface material may include, for example, mineral oil, grease, gap filling putty, phase change gel, phase change material pad, particle filled epoxy resin.

[0064] The footprint of the semiconductor chip 200 may be smaller than the footprint of the redistribution structure 100. For example, in a plan view, the area of ​​the semiconductor chip 200 may be smaller than the area of ​​the redistribution structure 100. For example, the horizontal width of the semiconductor chip 200 may be smaller than the horizontal width of the redistribution structure 100. In example embodiments, a portion of the plurality of conductive line patterns 121, 131, and 141 may extend to further protrude from the side surface of the semiconductor chip 200 in a horizontal direction. For example, a portion of the first conductive line pattern 121 and a portion of the second conductive line pattern 131 may further protrude from the side surface of the semiconductor chip 200 in a horizontal direction. For example, in a plan view, a portion of the first conductive pattern 121 and / or a portion of the second conductive pattern 131 may protrude from the side surface of the semiconductor chip 200. In some embodiments, in a plan view, at least one of the plurality of lower electrode pads 150 may, for example, be disposed at a position spaced apart (e.g., outward) from the side surface of the semiconductor chip 200.

[0065] Figure 3 is a flowchart illustrating a method of manufacturing a semiconductor package according to an example embodiment of the inventive concepts.

[0066] Reference Figure 3 , the method for manufacturing a semiconductor package may include: a first step S110, forming a cover insulating layer on a carrier substrate; a second step S120, forming a lower electrode pad on the cover insulating layer; a third step S130, forming a redistribution structure; a fourth step S140, attaching a semiconductor chip to the redistribution structure and forming a molding layer; a fifth step S150, removing the carrier substrate; a sixth step S160, removing the cover insulating layer to expose the lower electrode pad; a seventh step S170, removing a portion of the redistribution insulating layer to expose a portion of the side wall of the lower electrode pad; and an eighth step S180, forming an external connection terminal on the lower electrode pad.

[0067] The method for manufacturing a semiconductor package may include the process steps S110 to S180 described above. In other embodiments, some process steps may be performed in a different order than described above. For example, two steps of a process described in succession may be performed substantially simultaneously or in a reverse order. FIG. 4A to FIG. 4L The technical features of each of the first step S110 to the eighth step S180 are described in more detail.

[0068] FIG. 4A to FIG. 4L are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package 10 according to example embodiments of the inventive concepts.

[0069] Reference Figure 4AThe cover insulating layer 320 may be formed on the carrier substrate 310 to which the release film 311 is attached. The cover insulating layer 320 may include Figure 1 The capping insulating layer 320 may include the same insulating material as the redistribution insulating layer 110, or may include an insulating material different from the redistribution structure insulating layer 110. For example, the capping insulating layer 320 may include a material film including an organic compound. In example embodiments, the capping insulating layer 320 may include photosensitive polyimide. Alternatively, for example, the capping insulating layer 320 may include an oxide or a nitride.

[0070] The carrier substrate 310 may support the cover insulating layer 320, and may include any material having process stability in a baking process and an etching process. For example, the carrier substrate 310 may be removed by heating and / or laser in a subsequent process. When the carrier substrate 310 is subsequently separated and removed by laser ablation, the carrier substrate 310 may include a transparent substrate. When the carrier substrate 310 is separated and subsequently removed by heating, the carrier substrate 310 may be a heat-resistant substrate. In example embodiments, the carrier substrate 310 may include a glass substrate. Alternatively, in other example embodiments, the carrier substrate 310 may include a heat-resistant organic polymer material, such as polyimide (PI), polyetheretherketone (PEEK), polyethersulfone (PES), polyphenylene sulfide (PPS), etc., but is not limited thereto.

[0071] The release film 311 may include, for example, a laser reactive layer capable of making the carrier substrate 310 separable by vaporizing in response to laser irradiation. The release film 311 may include a carbon-based material layer. For example, the release film 311 may include an amorphous carbon layer (ACL). For example, the release film 311 may include a spin-on hard mask (SOH) having a hydrocarbon compound or a derivative thereof having a relatively high carbon content of about 85 wt % to about 99 wt % based on the total weight.

[0072] Reference Figure 4B , the lower electrode pad 150 may be formed on the cover insulating layer 320. In order to form the lower electrode pad 150, a conductive material film may be formed on the cover insulating layer 320, and then the conductive material film may be patterned. The lower electrode pad 150 may be formed to have a uniform thickness as a whole on the upper surface of the cover insulating layer 320, and the lower surface of the lower electrode pad 150 in contact with the upper surface of the cover insulating layer 320 may have a flat shape.

[0073] In example embodiments, the lower electrode pad 150 may include a single metal material. Alternatively, the lower electrode pad 150 may have a multi-layer structure in which each layer includes a different metal material from other layers.

[0074] Reference Figure 4CAfter forming the lower electrode pad 150, a first insulating layer 111a including a first through hole opening VO1 may be formed, wherein the first through hole opening VO1 exposes a portion of the lower electrode pad 150. For example, to form the first insulating layer 111a, an insulating material film covering the lower electrode pad 150 and the cover insulating layer 320 may be formed, and then the first through hole opening VO1 may be formed by removing a portion of the insulating material film through an exposure and development process. A portion of the lower electrode pad 150 may be exposed by the first through hole opening VO1.

[0075] Reference Figure 4D , you can Figure 4C A first seed layer 125, a first conductive line pattern 121, and a first conductive via pattern 123 are formed on the resulting structure. For example, the first seed layer 125 may be formed to cover the upper surface of the first insulating layer 111a, the inner sidewall of the first insulating layer 111a provided by the first via opening VO1 (e.g., the sidewall of the first via opening VO1), and the lower electrode pad 150 exposed through the first via opening VO1. The inner sidewall of the first insulating layer 111a may be a surface of the first insulating layer 111a formed by the first via opening VO1, e.g., the inner side surface. The first conductive line pattern 121 may extend along the upper surface of the first insulating layer 111a, and the first conductive via pattern 123 may fill the first via opening VO1, for example, together with a portion of the first seed layer 125. The first seed layer 125, the first conductive line pattern 121, and the first conductive via pattern 123 may constitute a first redistribution pattern 120. Reference will be made later FIG. 5A to FIG. 5E The method of forming the first redistribution pattern 120 is described in more detail.

[0076] Reference Figure 4E ,exist Figure 4D The obtained structure is obtained by referring to Figure 4C and Figure 4D The processes are substantially the same or similar to the above processes, and the second insulating layer 113 including the second through hole opening VO2, the second redistribution pattern 130, the third insulating layer 115 including the third through hole opening VO3, and the third redistribution pattern 140 may be sequentially formed. The first to third insulating layers 111, 113, and 115 and the first to third redistribution patterns 120, 130, and 140 may constitute the redistribution structure 100.

[0077] For example, the second seed layer 135 may be formed to cover the upper surface of the second insulating layer 113, the inner sidewall of the second insulating layer 113 provided by the second through hole opening VO2 (e.g., the sidewall of the second through hole opening VO2), and the portion of the first conductive line pattern 121 exposed through the second through hole opening VO2. The second conductive line pattern 131 may extend along the upper surface of the second insulating layer 113, and the second conductive via pattern 133 may, for example, fill the second through hole opening VO2 together with a portion of the second seed layer 135. The second seed layer 135, the second conductive line pattern 131, and the second conductive via pattern 133 may constitute a second redistribution pattern 130.

[0078] The third seed layer 145 may be formed to cover the upper surface of the third insulating layer 115, the inner sidewall of the third insulating layer 115 provided by the third via opening VO3 (e.g., the sidewall of the third via opening VO3), and the portion of the second conductive line pattern 131 exposed through the third via opening VO3. The third conductive line pattern 141 may extend along the upper surface of the third insulating layer 115, and the third conductive via pattern 143 may fill the third via opening VO3, for example, together with a portion of the third seed layer 145. The third seed layer 145, the third conductive line pattern 141, and the third conductive via pattern 143 may constitute a third redistribution pattern 140.

[0079] Reference Figure 4F , the semiconductor chip 200 may be attached to the redistribution structure 100. The semiconductor chip 200 may be attached to the redistribution structure 100 so that the chip pad 220 faces the redistribution structure 100. The chip pad 220 of the semiconductor chip 200 may be electrically connected to the third conductive line pattern 141 of the redistribution structure 100 through the chip connection terminal 230. In this case, the third conductive line pattern 141 may be used as an upper electrode pad of the redistribution structure 100 in which the chip connection terminal 230 is disposed.

[0080] After the semiconductor chip 200 is attached to the redistribution structure 100, an underfill material layer 240 may be formed to fill the space between the semiconductor chip 200 and the redistribution structure 100. The underfill material layer 240 may surround the chip connection terminal 230. For example, after the semiconductor chip 200 is attached to the redistribution structure 100, the underfill material layer 240 may be formed by a capillary underfill method. In some example embodiments, the underfill material layer 240 may be formed by attaching a non-conductive film on the chip pad 220 of the semiconductor chip 200 and then attaching the semiconductor chip 200 on the redistribution structure 100.

[0081] Reference Figure 4G, after forming the underfill material layer 240, a mold layer 300 for molding the semiconductor chip 200 may be formed. The mold layer 300 may cover the side surface of the semiconductor chip 200 and expose the upper surface of the semiconductor chip 200. The mold layer 300 may cover a portion of the first surface 118 of the redistribution insulation layer 110. In other example embodiments, the mold layer 300 may be formed to further cover the upper surface of the semiconductor chip 200.

[0082] Will Figure 4H and Figure 4G Referring together, after forming the mold layer 300, the carrier substrate 310 may be removed. Figure 4G In the resulting structure, the carrier substrate 310 to which the release film 311 is attached may be separated from other structures. For example, in order to separate the carrier substrate 310, the release film 311 may be irradiated with laser or heated. Due to the separation of the carrier substrate 310, the cover insulating layer 320 may be exposed.

[0083] Reference Fig. 4I , in reverse Figure 4H After the resulting product is formed, the capping insulating layer 320 may be removed to expose the lower electrode pad 150. For example, an etching process may be performed to remove the capping insulating layer 320. With the removal of the capping insulating layer 320, the lower surface of the lower electrode pad 150 may be exposed.

[0084] Reference Figure 4J and Fig. 4I After removing the cover insulating layer 320, the Fig. 4I The first insulating layer 111a is removed to expose a portion of the sidewall of the lower electrode pad 150. For example, a dry etching process may be performed to remove the Fig. 4I As a part of the first insulating layer 111a is removed Fig. 4I As a result of a portion of the first insulating layer 111a, Figure 2 The first portion 151 of the lower electrode pad 150 may be embedded in the first insulating layer 111, and the Figure 2 The second portion 153 may protrude from the first insulating layer 111 .

[0085] In this case, by controlling the etching speed and the etching time, the thickness of the lower electrode pad 150 protruding from the first insulating layer 111 may be adjusted. In example embodiments, as a result of the etching process on the first insulating layer 111, the thickness of the second portion 153 of the lower electrode pad 150 protruding from the first insulating layer 111 may be less than the thickness of the first portion 151 of the lower electrode pad 150 embedded in the first insulating layer 111.

[0086] In an example embodiment, Fig. 4IA portion of the first insulating layer 111a and the capping insulating layer 320 may be removed in the same etching process. For example, an etching process may be performed to remove Fig. 4I The first insulating layer 111a and the cover insulating layer 320. In this case, the cover insulating layer 320 may include Fig. 4I The first insulating layer 111a is made of the same material.

[0087] Alternatively, in other example embodiments, the Fig. 4I A portion of the first insulating layer 111 a and the cover insulating layer 320 .

[0088] Reference Figure 4K , the external connection terminal 400 may be attached to the lower electrode pad 150. The external connection terminal 400 may include, for example, a solder ball or a bump.

[0089] Reference Figure 4L After forming the external connection terminals 400, the external connection terminals 400 may be cut along the scribe lines SL. Figure 4K The sawing process of the resulting product is completed as Figure 1 The sawn semiconductor package 10 is shown.

[0090] Generally, in a method of manufacturing a semiconductor package in a chip-last manner, redistribution structure formation, chip attachment, UBM formation, and solder ball attachment may be performed in sequence. However, according to a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept, since the lower electrode pad 150 serving as the UBM may be first formed before forming the redistribution structure 100, the process may be simplified and the production cost may be reduced.

[0091] FIG. 5A to FIG. 5E are cross-sectional views sequentially illustrating a method of forming the first redistribution pattern 120 according to example embodiments of the inventive concepts.

[0092] Reference Figure 5A An insulating material layer may be formed on the capping insulating layer 320, and an etching process may be performed on the insulating material layer to form a first insulating layer 111a including a first via opening VO1. For example, a reactive ion etching (RIE) process using plasma, laser drilling, etc. may be performed to form the first via opening VO1.

[0093] In example embodiments, the first via opening VO1 may have a shape in which the width of the first via opening VO1 gradually narrows downward (or closer to the lower electrode pad 150), for example, as shown in FIG. Figure 5AIn the cross-sectional view shown. The inner sidewall of the first insulating layer 111a provided by the first through hole opening VO1 (e.g., the sidewall of the first through hole opening Vo1) may have an inclined sidewall portion. For example, the angle formed by the lower surface of the first insulating layer 111a and the inclined sidewall portion may be adjusted by controlling a combination of etching gas, gas supply amount, and etching rate in the etching process. For example, the angle formed by the lower surface of the first insulating layer 111a and the inclined sidewall portion may be between about 75 degrees and about 85 degrees, for example, in a range similar to Figure 5A In the cross-sectional view.

[0094] Reference Figure 5B , the first preliminary seed layer 125a may be formed to cover the upper surface of the first insulating layer 111a, the inner sidewall of the first insulating layer 111a provided by the first via opening VO1 (e.g., the sidewall of the first via opening VO1), and the portion of the lower electrode pad 150 exposed through the first via opening VO1. The first preliminary seed layer 125a may conformally extend on the upper surface of the first insulating layer 111a, the inner sidewall of the first insulating layer 111a provided by the first via opening VO1, and the portion of the lower electrode pad 150 exposed through the first via opening VO1.

[0095] Reference Figure 5C A mask pattern MP including an opening OP may be formed on the first preliminary seed layer 125a. The opening OP of the mask pattern MP may expose a portion of the first preliminary seed layer 125a and define a region where the first conductive line pattern 121 and the first conductive via pattern 123 are formed in a subsequent process.

[0096] Reference Figure 5D , the first conductive line pattern 121 and the first conductive via pattern 123 may be formed on a portion of the first preliminary seed layer 125a exposed by the opening OP of the mask pattern MP. The first conductive line pattern 121 may extend on the upper surface of the first insulating layer 111a, and the first conductive via pattern 123 may, for example, fill the first via opening VO1 together with a portion of the first preliminary seed layer 125. For example, the first conductive line pattern 121 and the first conductive via pattern 123 may be formed together by a plating process using the first preliminary seed layer 125a as a seed. The first conductive line pattern 121 and the first conductive via pattern 123 may be integrally formed as a single body.

[0097] In this case, since the first conductive via pattern 123 may be formed to fill the first via opening VO1 in the first insulating layer 111a, the first conductive via pattern 123 may have a shape corresponding to the shape of the first via opening VO1. For example, the first conductive via pattern 123 may be formed in the first via opening VO1 in which the first preliminary seed layer 125a is conformally formed. For example, the first conductive via pattern 123 may have a shape such as Figure 5D The cross-sectional view shows a shape in which the width gradually decreases downward (or closer to the lower electrode pad 150).

[0098] Reference Figure 5E and Figure 5D After forming the first conductive line pattern 121 and the first conductive via pattern 123, the mask pattern MP may be removed, and then the portion of the first preliminary seed layer 125a exposed by removing the mask pattern MP may be removed. As a result of removing the portion of the first preliminary seed layer 125a exposed by removing the mask pattern MP, a first seed layer 125 may be formed. The first seed layer 125 may be interposed between the first conductive line pattern 121 and the first insulating layer 111a, between the first conductive via pattern 123 and the inner sidewall of the first insulating layer 111a, and between the conductive via pattern 123 and the lower electrode pad 150.

[0099] and form a reference FIG. 5A to FIG. 5E The same or similar method as shown in the first redistribution pattern 120 can be used to form Figure 4E The second redistribution pattern 130 and Figure 4E Each of the third redistribution patterns 140 in .

[0100] Figure 6 1 is a cross-sectional view showing a semiconductor package 10a according to some embodiments of the inventive concept. In addition to the semiconductor package 10a including a plurality of semiconductor chips 200a, Figure 6 The semiconductor package 10a shown can be used with reference Figure 1 and Figure 2 The semiconductor packages 10 described are substantially the same or similar.

[0101] Reference Figure 6, the semiconductor package 10a may include a redistribution structure 100 and a plurality of semiconductor chips 200a on the redistribution structure 100. The plurality of semiconductor chips 200a may include a first semiconductor chip 201 and a second semiconductor chip 203 spaced apart from each other. The first semiconductor chip 201 may include a semiconductor substrate 211 and a chip pad 221, and the chip pad 221 of the first semiconductor chip 201 may be electrically connected to the third redistribution pattern 140 through a chip connection terminal 230. The second semiconductor chip 203 may include a semiconductor substrate 213 and a chip pad 223, and the chip pad 223 of the second semiconductor chip 203 may be electrically connected to the third redistribution pattern 140 through a chip connection terminal 230.

[0102] In example embodiments, the first semiconductor chip 201 and the second semiconductor chip 203 may include semiconductor chips of different types. For example, when the first semiconductor chip 201 is a non-memory chip, the second semiconductor chip 203 may be a memory chip. For example, the first semiconductor chip 201 may include a logic chip. The first semiconductor chip 201 may include, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. In some embodiments, the second semiconductor chip 203 may include, for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable programmable read-only memory (EPROM) chip, a phase change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, or a resistive random access memory (RRAM) chip. In some embodiments, the second semiconductor chip 203 may include a high bandwidth memory (HBM) DRAM semiconductor chip. Alternatively, in example embodiments, the first semiconductor chip 201 and the second semiconductor chip 203 may include the same type of semiconductor chips. In example embodiments, the semiconductor package 10 a may include a system-in-package (SIP) in which different kinds of semiconductor chips are electrically connected to each other to operate as one system.

[0103] In this case, the footprint occupied by the plurality of semiconductor chips 200a may be smaller than the horizontal area of ​​the redistribution structure 100. The footprint occupied by the plurality of semiconductor chips 200a may completely overlap the redistribution structure 100 in the vertical direction. For example, in a plan view, the area of ​​the plurality of semiconductor chips 200a may be smaller than the area of ​​the redistribution structure 100. In some embodiments, the plurality of semiconductor chips 200a may be vertically stacked to form a stacked chip.

[0104] Figure 7 is a cross-sectional view illustrating a semiconductor package 10 b according to an embodiment of the inventive concept.

[0105] Reference Figure 7 , the semiconductor package 10b may include a lower package 11L and an upper package 11U on the lower package 11L. The semiconductor package 10b may include a semiconductor package in a package-on-package (POP) form in which the upper package 11U is attached to the lower package 11L.

[0106] The lower package 11L may include a first redistribution structure 100L, a first semiconductor chip 200L, a first lower electrode pad 150L, ​​a first chip connection terminal 230L, a first bottom filling material layer 240L, a first mold layer 300L, and a first conductive pillar 160. The first redistribution structure 100L includes a redistribution insulating layer 110L, and redistribution patterns 120L, 130L, and 140L. The first redistribution structure 100L, the first semiconductor chip 200L, the first lower electrode pad 150L, ​​the first chip connection terminal 230L, the first bottom filling material layer 240L, and the first mold layer 300L of the lower package 11L may be respectively the same as those described above with reference to the drawings. Figure 1 and Figure 2 The redistribution structure 100 , the semiconductor chip 200 , the lower electrode pads 150 , the chip connection terminals 230 , the underfill material layer 240 , and the mold layer 300 of the described semiconductor package 10 are substantially the same or similar.

[0107] The first conductive pillar 160 may penetrate the first mold layer 300L. A portion of the third conductive line pattern 140L of the first redistribution structure 100L may be connected to the lower end of the first mold layer 300L. The upper end of the first mold layer 300L may be connected to the inter-package connection terminal 410. The third conductive line pattern 140L of the first redistribution structure 100L may contact and / or be electrically connected to the lower end of the first conductive pillar 160. The upper end of the first conductive pillar 160 may contact and / or be electrically connected to the inter-package connection terminal 410.

[0108] The upper package 11U may include a second redistribution structure 100U, a second semiconductor chip 200U, a second lower electrode pad 150U, a second chip connection terminal 230U, a second bottom filling material layer 240U, and a second mold layer 300U, wherein the second redistribution structure 100U includes a second redistribution insulating layer 110U and second redistribution patterns 120U and 140U. The second redistribution structure 100U, the second semiconductor chip 200U, the second lower electrode pad 150U, the second chip connection terminal 230U, the second bottom filling material layer 240U, and the second mold layer 300U of the upper package 11U may be respectively the same as those described above with reference to the drawings. Figure 1 and Figure 2The redistribution structure 100 , the semiconductor chip 200 , the lower electrode pads 150 , the chip connection terminals 230 , the underfill material layer 240 , and the mold layer 300 of the described semiconductor package 10 are substantially the same or similar.

[0109] The upper package 11U may be electrically and physically connected to the lower package 11L through the inter-package connection terminal 410 interposed therebetween. The inter-package connection terminal 410 may contact the bottom surface of the second lower electrode pad 150U of the upper package 11U and may contact the first conductive pillar 160 of the lower package 11L.

[0110] In an exemplary embodiment, similar to reference Figure 1 and Figure 2 As described with respect to the lower electrode pad 150, a portion of the second lower electrode pad 150U of the upper package 11U may protrude from the second redistribution insulating layer 110U. For example, the thickness of the portion of the second lower electrode pad 150U embedded in the second redistribution insulating layer 110U may be greater than the thickness of another portion of the second lower electrode pad 150U protruding from the second redistribution insulating layer 110U.

[0111] In example embodiments, the first semiconductor chip 200L and the second semiconductor chip 200U may include semiconductor chips of different types. Alternatively, in other example embodiments, the first semiconductor chip 200L and the second semiconductor chip 200U may include semiconductor chips of the same type.

[0112] The second semiconductor chip 200U can be electrically connected to the first semiconductor chip 200L and / or the outside via the following components: a plurality of conductive line patterns 121U and 141U and a plurality of conductive via patterns 123U and 143U included in the second redistribution structure 100U; a second lower electrode pad 150U; an inter-package connecting terminal 410; a first conductive pillar 160; and a plurality of conductive line patterns 121L, 131L and 141L and a plurality of conductive via patterns 123L, 133L and 143L included in the first redistribution structure 100L.

[0113] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: A redistribution structure, comprising a redistribution insulating layer and a redistribution pattern, wherein the redistribution insulating layer comprises a first insulating layer; a first semiconductor chip disposed on a first surface of the redistribution insulating layer and electrically connected to the redistribution pattern; as well as a lower electrode pad disposed on a second surface of the redistribution insulating layer opposite to the first surface, the lower electrode pad comprising a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, Wherein, the thickness of the first portion of the lower electrode pad is greater than the thickness of the second portion of the lower electrode pad, wherein the redistribution pattern is formed on the top surface of the first insulating layer, the lower electrode pad is formed on the bottom surface of the first insulating layer, and The redistribution pattern includes a seed layer, and the seed layer contacts a top surface of the first insulating layer and a top surface of the lower electrode pad.

2. The semiconductor package according to claim 1, in, The thickness of the second portion of the lower electrode pad is between 10% and 30% of the total thickness of the lower electrode pad.

3. The semiconductor package according to claim 1, in, A sidewall of the second portion of the lower electrode pad is exposed to the outside of the redistribution insulating layer.

4. The semiconductor package according to claim 1, in, The redistribution structure further includes a conductive via pattern passing through a portion of the redistribution insulation layer to be electrically connected to the lower electrode pad.

5. The semiconductor package according to claim 4, in, A width of the conductive via pattern gradually narrows in a first direction, wherein the first direction is directed from a first surface of the redistribution insulation layer to a second surface of the redistribution insulation layer.

6. The semiconductor package according to claim 4, in, The seed layer surrounds sidewalls of the conductive via pattern.

7. The semiconductor package according to claim 1, in, The first semiconductor chip includes: a chip pad disposed on a surface facing the first surface of the redistribution insulation layer, and The semiconductor package further includes a chip connection terminal disposed between a portion of the redistribution pattern on the first surface of the redistribution insulation layer and the chip pad of the first semiconductor chip.

8. The semiconductor package according to claim 7, Also includes: An underfill material layer is disposed between the first semiconductor chip and the first surface of the redistribution insulation layer and surrounds the chip connection terminals.

9. The semiconductor package according to claim 1, Also included is an external connection terminal on a bottom surface of the lower electrode pad.

10. The semiconductor package according to claim 9, in, The bottom surface of the lower electrode pad is flat.

11. The semiconductor package according to claim 1, further comprising: a molding layer covering a side surface of the first semiconductor chip; as well as A conductive pillar penetrates the mold layer and is electrically connected to the redistribution pattern.

12. The semiconductor package according to claim 1, further comprising: a second semiconductor chip spaced apart from the first semiconductor chip, The first semiconductor chip is a logic chip, and the second semiconductor chip is a memory chip.

13. A semiconductor package, comprising: a redistribution insulating layer, comprising a first surface and a second surface opposite to each other, wherein the redistribution insulating layer comprises a first insulating layer; a first conductive line pattern in the redistribution insulating layer; a second conductive line pattern on the first surface of the redistribution insulation layer; a lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from a second surface of the redistribution insulating layer; a first conductive via pattern extending between the first conductive line pattern and the lower electrode pad and contacting the lower electrode pad; a second conductive via pattern extending between the second conductive line pattern and the first conductive line pattern; as well as a semiconductor chip disposed on the redistribution insulating layer and electrically connected to the second conductive line pattern, wherein the first conductive line pattern is formed on the top surface of the first insulating layer, the lower electrode pad is formed on the bottom surface of the first insulating layer, and The semiconductor package further includes a first seed layer, wherein the first seed layer contacts a top surface of the first insulating layer and a top surface of the lower electrode pad.

14. The semiconductor package according to claim 13, in, The second portion of the lower electrode pad has a thickness between 1 μm and 3 μm.

15. The semiconductor package according to claim 13, in, Widths of the first conductive via pattern and the second conductive via pattern are each gradually narrowed in a first direction, wherein the first direction is from a first surface of the redistribution insulation layer toward a second surface of the redistribution insulation layer.

16. The semiconductor package according to claim 13, in, A side wall of the second portion of the lower electrode pad is exposed to the outside of the redistribution insulating layer, and A height of a sidewall of the first portion of the lower electrode pad is greater than a height of a sidewall of the second portion of the lower electrode pad.

17. The semiconductor package according to claim 13, wherein the first seed layer surrounds a sidewall of the first conductive via pattern; and The semiconductor package further comprises: The second seed layer surrounds the sidewall of the second conductive via pattern and is disposed between the second conductive via pattern and the first conductive via pattern.

18. The semiconductor package according to claim 13, further comprising: a chip connection terminal, disposed between the second conductive line pattern and the semiconductor chip; as well as The bottom filling material layer is disposed between the semiconductor chip and the first surface of the redistribution insulation layer and surrounds the chip connection terminals.

19. The semiconductor package according to claim 13, further comprising: an external connection terminal on a bottom surface of the second portion of the lower electrode pad, Wherein, a bottom surface of the second portion of the lower electrode pad is flat.

20. A semiconductor package, comprising: a redistribution structure comprising a plurality of insulating layers, a plurality of conductive line patterns disposed on an upper surface of each of the plurality of insulating layers, and a plurality of conductive via patterns penetrating at least one of the plurality of insulating layers and connected to at least one of the plurality of conductive line patterns; a semiconductor chip on an upper surface of the redistribution structure; a chip connection terminal disposed between the semiconductor chip and the uppermost conductive line pattern among the plurality of conductive line patterns; a bottom filling material layer, between the semiconductor chip and the redistribution structure, surrounding the chip connection terminals; a molding layer covering at least a portion of the semiconductor chip; a lower electrode pad on a bottom surface of the redistribution structure; as well as external connection terminals, on the lower electrode pad, wherein the lower electrode pad includes a first portion embedded in a lowermost insulating layer among the plurality of insulating layers, and a second portion protruding from the lowermost insulating layer, and a thickness of the second portion of the lower electrode pad is less than a thickness of the first portion of the lower electrode pad, The redistribution structure further comprises: a plurality of seed layers disposed between the upper surface of each of the plurality of insulating layers and the plurality of conductive line patterns, and between each of the plurality of insulating layers and the plurality of conductive via patterns, and Wherein, a first seed layer among the plurality of seed layers contacts a top surface of a first insulating layer among the plurality of insulating layers and a top surface of the lower electrode pad.

21. The semiconductor package according to claim 20, in, Each of the plurality of conductive via patterns has a shape that gradually narrows in a direction from an upper surface of the redistribution structure toward a lower surface of the redistribution structure.

22. The semiconductor package according to claim 20, in, A portion of the plurality of conductive via patterns contacts the lower electrode pad.

23. The semiconductor package according to claim 20, in, The lower electrode pad has a uniform thickness, and a sidewall of a second portion of the lower electrode pad is exposed to the outside of the lowermost insulating layer.

24. The semiconductor package according to claim 20, further comprising: A plurality of lower electrode pads, Wherein, in a plan view, at least one of the plurality of lower electrode pads is spaced outwardly from a side surface of the semiconductor chip.

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